1 /* $NetBSD: if_ath_pci.c,v 1.30 2008/03/12 18:02:21 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 3. Neither the names of the above-listed copyright holders nor the names 18 * of any contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * NO WARRANTY 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGES. 37 */ 38 39 #include <sys/cdefs.h> 40 #ifdef __FreeBSD__ 41 __FBSDID("$FreeBSD: src/sys/dev/ath/if_ath_pci.c,v 1.11 2005/01/18 18:08:16 sam Exp $"); 42 #endif 43 #ifdef __NetBSD__ 44 __KERNEL_RCSID(0, "$NetBSD: if_ath_pci.c,v 1.30 2008/03/12 18:02:21 dyoung Exp $"); 45 #endif 46 47 /* 48 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 49 */ 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/mbuf.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/socket.h> 57 #include <sys/errno.h> 58 #include <sys/device.h> 59 60 #include <net/if.h> 61 #include <net/if_media.h> 62 #include <net/if_ether.h> 63 64 #include <net80211/ieee80211_netbsd.h> 65 #include <net80211/ieee80211_var.h> 66 67 #ifdef INET 68 #include <netinet/in.h> 69 #endif 70 71 #include <dev/ic/ath_netbsd.h> 72 #include <dev/ic/athvar.h> 73 #include <contrib/dev/ath/ah.h> 74 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcidevs.h> 78 79 /* 80 * PCI glue. 81 */ 82 83 struct ath_pci_softc { 84 struct ath_softc sc_sc; 85 pci_chipset_tag_t sc_pc; 86 pcitag_t sc_pcitag; 87 pci_intr_handle_t sc_pih; 88 void *sc_ih; /* interrupt handler */ 89 bus_space_tag_t sc_iot; 90 bus_space_handle_t sc_ioh; 91 bus_size_t sc_mapsz; 92 }; 93 94 #define BS_BAR 0x10 95 96 static void ath_pci_attach(device_t, device_t, void *); 97 static int ath_pci_detach(device_t, int); 98 static int ath_pci_match(device_t, struct cfdata *, void *); 99 static int ath_pci_detach(device_t, int); 100 101 CFATTACH_DECL(ath_pci, 102 sizeof(struct ath_pci_softc), 103 ath_pci_match, 104 ath_pci_attach, 105 ath_pci_detach, 106 NULL); 107 108 static int 109 ath_pci_match(device_t parent, struct cfdata *match, void *aux) 110 { 111 const char* devname; 112 struct pci_attach_args *pa = aux; 113 114 devname = ath_hal_probe(PCI_VENDOR(pa->pa_id), PCI_PRODUCT(pa->pa_id)); 115 if (devname != NULL) 116 return 1; 117 return 0; 118 } 119 120 static bool 121 ath_pci_suspend(device_t self PMF_FN_ARGS) 122 { 123 struct ath_pci_softc *sc = device_private(self); 124 125 ath_suspend(&sc->sc_sc); 126 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 127 sc->sc_ih = NULL; 128 129 return true; 130 } 131 132 static bool 133 ath_pci_resume(device_t self PMF_FN_ARGS) 134 { 135 struct ath_pci_softc *sc = device_private(self); 136 137 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pih, IPL_NET, ath_intr, 138 &sc->sc_sc); 139 if (sc->sc_ih == NULL) { 140 aprint_error_dev(self, "couldn't map interrupt\n"); 141 return false; 142 } 143 ath_resume(&sc->sc_sc); 144 145 return true; 146 } 147 148 static int 149 ath_pci_setup(struct ath_pci_softc *sc) 150 { 151 pcireg_t bhlc, csr, icr, lattimer; 152 /* 153 * Enable memory mapping and bus mastering. 154 */ 155 csr = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 156 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 157 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, csr); 158 csr = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 159 160 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 161 aprint_error("couldn't enable memory mapping\n"); 162 return 0; 163 } 164 if ((csr & PCI_COMMAND_MASTER_ENABLE) == 0) { 165 aprint_error("couldn't enable bus mastering\n"); 166 return 0; 167 } 168 169 /* 170 * XXX Both this comment and code are replicated in 171 * XXX cardbus_rescan(). 172 * 173 * Make sure the latency timer is set to some reasonable 174 * value. 175 * 176 * I will set the initial value of the Latency Timer here. 177 * 178 * While a PCI device owns the bus, its Latency Timer counts 179 * down bus cycles from its initial value to 0. Minimum 180 * Grant tells for how long the device wants to own the 181 * bus once it gets access, in units of 250ns. 182 * 183 * On a 33 MHz bus, there are 8 cycles per 250ns. So I 184 * multiply the Minimum Grant by 8 to find out the initial 185 * value of the Latency Timer. 186 * 187 * I never set a Latency Timer less than 0x10, since that 188 * is what the old code did. 189 */ 190 bhlc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_BHLC_REG); 191 icr = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_INTERRUPT_REG); 192 lattimer = MAX(0x10, MIN(0xf8, 8 * PCI_MIN_GNT(icr))); 193 if (PCI_LATTIMER(bhlc) < lattimer) { 194 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 195 bhlc |= (lattimer << PCI_LATTIMER_SHIFT); 196 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_BHLC_REG, bhlc); 197 } 198 return 1; 199 } 200 201 static void 202 ath_pci_attach(device_t parent, device_t self, void *aux) 203 { 204 struct ath_pci_softc *psc = device_private(self); 205 struct ath_softc *sc = &psc->sc_sc; 206 struct pci_attach_args *pa = aux; 207 pci_chipset_tag_t pc = pa->pa_pc; 208 pcireg_t mem_type; 209 const char *intrstr = NULL; 210 211 psc->sc_pc = pc; 212 213 psc->sc_pcitag = pa->pa_tag; 214 215 if (!ath_pci_setup(psc)) 216 goto bad; 217 218 /* 219 * Setup memory-mapping of PCI registers. 220 */ 221 mem_type = pci_mapreg_type(pc, pa->pa_tag, BS_BAR); 222 if (mem_type != PCI_MAPREG_TYPE_MEM && 223 mem_type != PCI_MAPREG_MEM_TYPE_64BIT) { 224 aprint_error("bad pci register type %d\n", (int)mem_type); 225 goto bad; 226 } 227 if (pci_mapreg_map(pa, BS_BAR, mem_type, 0, &psc->sc_iot, 228 &psc->sc_ioh, NULL, &psc->sc_mapsz)) { 229 aprint_error("cannot map register space\n"); 230 goto bad; 231 } 232 233 sc->sc_st = HALTAG(psc->sc_iot); 234 sc->sc_sh = HALHANDLE(psc->sc_ioh); 235 236 /* 237 * Arrange interrupt line. 238 */ 239 if (pci_intr_map(pa, &psc->sc_pih)) { 240 aprint_error("couldn't map interrupt\n"); 241 goto bad1; 242 } 243 244 intrstr = pci_intr_string(pc, psc->sc_pih); 245 psc->sc_ih = pci_intr_establish(pc, psc->sc_pih, IPL_NET, ath_intr, sc); 246 if (psc->sc_ih == NULL) { 247 aprint_error("couldn't map interrupt\n"); 248 goto bad2; 249 } 250 251 aprint_normal("\n"); 252 aprint_verbose_dev(self, "interrupting at %s\n", intrstr); 253 254 sc->sc_dmat = pa->pa_dmat; 255 256 ATH_LOCK_INIT(sc); 257 258 if (ath_attach(PCI_PRODUCT(pa->pa_id), sc) != 0) 259 goto bad3; 260 261 if (!pmf_device_register(self, ath_pci_suspend, ath_pci_resume)) 262 aprint_error_dev(self, "couldn't establish power handler\n"); 263 else { 264 pmf_class_network_register(self, &sc->sc_if); 265 pmf_device_suspend_self(self); 266 } 267 return; 268 bad3: 269 ATH_LOCK_DESTROY(sc); 270 271 pci_intr_disestablish(pc, psc->sc_ih); 272 bad2: /* XXX */ 273 bad1: 274 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 275 bad: /* XXX */ 276 return; 277 } 278 279 static int 280 ath_pci_detach(device_t self, int flags) 281 { 282 struct ath_pci_softc *psc = device_private(self); 283 284 ath_detach(&psc->sc_sc); 285 pmf_device_deregister(self); 286 if (psc->sc_ih != NULL) 287 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 288 bus_space_unmap(psc->sc_iot, psc->sc_ioh, psc->sc_mapsz); 289 290 ATH_LOCK_DESTROY(&psc->sc_sc); 291 292 return (0); 293 } 294