1 /* $NetBSD: if_aq.c,v 1.45 2023/05/29 08:00:05 rin Exp $ */ 2 3 /** 4 * aQuantia Corporation Network Driver 5 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * (1) Redistributions of source code must retain the above 12 * copyright notice, this list of conditions and the following 13 * disclaimer. 14 * 15 * (2) Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 20 * (3) The name of the author may not be used to endorse or promote 21 * products derived from this software without specific prior 22 * written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 25 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 28 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 30 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 */ 37 38 /*- 39 * Copyright (c) 2020 Ryo Shimizu <ryo@nerv.org> 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 53 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 54 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 55 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 56 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 57 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 59 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 60 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 61 * POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #include <sys/cdefs.h> 65 __KERNEL_RCSID(0, "$NetBSD: if_aq.c,v 1.45 2023/05/29 08:00:05 rin Exp $"); 66 67 #ifdef _KERNEL_OPT 68 #include "opt_if_aq.h" 69 #include "sysmon_envsys.h" 70 #endif 71 72 #include <sys/param.h> 73 #include <sys/types.h> 74 #include <sys/bitops.h> 75 #include <sys/cprng.h> 76 #include <sys/cpu.h> 77 #include <sys/interrupt.h> 78 #include <sys/module.h> 79 #include <sys/pcq.h> 80 81 #include <net/bpf.h> 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 #include <net/if_media.h> 85 #include <net/if_ether.h> 86 #include <net/rss_config.h> 87 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcireg.h> 90 #include <dev/pci/pcidevs.h> 91 #include <dev/sysmon/sysmonvar.h> 92 93 /* driver configuration */ 94 #define CONFIG_INTR_MODERATION_ENABLE true /* delayed interrupt */ 95 #undef CONFIG_LRO_SUPPORT /* no LRO not supported */ 96 #undef CONFIG_NO_TXRX_INDEPENDENT /* share TX/RX interrupts */ 97 98 #define AQ_NINTR_MAX (AQ_RSSQUEUE_MAX + AQ_RSSQUEUE_MAX + 1) 99 /* TX + RX + LINK. must be <= 32 */ 100 #define AQ_LINKSTAT_IRQ 31 /* for legacy mode */ 101 102 #define AQ_TXD_NUM 2048 /* per ring. 8*n && 32~8184 */ 103 #define AQ_RXD_NUM 2048 /* per ring. 8*n && 32~8184 */ 104 /* minimum required to send a packet (vlan needs additional TX descriptor) */ 105 #define AQ_TXD_MIN (1 + 1) 106 107 108 /* hardware specification */ 109 #define AQ_RINGS_NUM 32 110 #define AQ_RSSQUEUE_MAX 8 111 #define AQ_RX_DESCRIPTOR_MIN 32 112 #define AQ_TX_DESCRIPTOR_MIN 32 113 #define AQ_RX_DESCRIPTOR_MAX 8184 114 #define AQ_TX_DESCRIPTOR_MAX 8184 115 #define AQ_TRAFFICCLASS_NUM 8 116 #define AQ_RSS_HASHKEY_SIZE 40 117 #define AQ_RSS_INDIRECTION_TABLE_MAX 64 118 119 #define AQ1_JUMBO_MTU_REV_A 9000 120 #define AQ1_JUMBO_MTU_REV_B 16338 121 #define AQ2_JUMBO_MTU 16338 122 123 /* 124 * TERMINOLOGY 125 * ATL (AQ1) = Atlantic. AQC100,107-109,111,112. 126 * ATL2 (AQ2) = Atlantic2. AQC113-116. 127 * MPI = MAC PHY INTERFACE? 128 * RPO = RX Protocol Offloading 129 * TPO = TX Protocol Offloading 130 * RPF = RX Packet Filter 131 * TPB = TX Packet buffer 132 * RPB = RX Packet buffer 133 * ART = Action Resolver Table 134 * TC = Traffic Class 135 */ 136 137 enum aq_hwtype { 138 HWTYPE_AQ1, 139 HWTYPE_AQ2 140 }; 141 142 /* registers */ 143 #define AQ_FW_SOFTRESET_REG 0x0000 144 #define AQ_FW_SOFTRESET_RESET __BIT(15) /* soft reset bit */ 145 #define AQ_FW_SOFTRESET_DIS __BIT(14) /* reset disable */ 146 147 #define AQ_FW_VERSION_REG 0x0018 148 #define AQ_HW_REVISION_REG 0x001c 149 #define AQ2_HW_FPGA_VERSION_REG 0x00f4 /* AQ2 */ 150 #define AQ_GLB_NVR_INTERFACE1_REG 0x0100 151 152 #define AQ_FW_MBOX_CMD_REG 0x0200 153 #define AQ_FW_MBOX_CMD_EXECUTE 0x00008000 154 #define AQ_FW_MBOX_CMD_BUSY 0x00000100 155 #define AQ_FW_MBOX_ADDR_REG 0x0208 156 #define AQ_FW_MBOX_VAL_REG 0x020c 157 158 #define FW2X_LED_MIN_VERSION 0x03010026 /* >= 3.1.38 */ 159 #define FW2X_LED_REG 0x031c 160 #define FW2X_LED_DEFAULT 0x00000000 161 #define FW2X_LED_NONE 0x0000003f 162 #define FW2X_LINKLED __BITS(0,1) 163 #define FW2X_LINKLED_ACTIVE 0 164 #define FW2X_LINKLED_ON 1 165 #define FW2X_LINKLED_BLINK 2 166 #define FW2X_LINKLED_OFF 3 167 #define FW2X_STATUSLED __BITS(2,5) 168 #define FW2X_STATUSLED_ORANGE 0 169 #define FW2X_STATUSLED_ORANGE_BLINK 2 170 #define FW2X_STATUSLED_OFF 3 171 #define FW2X_STATUSLED_GREEN 4 172 #define FW2X_STATUSLED_ORANGE_GREEN_BLINK 8 173 #define FW2X_STATUSLED_GREEN_BLINK 10 174 175 #define FW_MPI_MBOX_ADDR_REG 0x0360 176 #define FW1X_MPI_INIT1_REG 0x0364 177 #define FW1X_MPI_CONTROL_REG 0x0368 178 #define FW1X_MPI_STATE_REG 0x036c 179 #define FW1X_MPI_STATE_MODE __BITS(7,0) 180 #define FW1X_MPI_STATE_SPEED __BITS(32,16) 181 #define FW1X_MPI_STATE_DISABLE_DIRTYWAKE __BITS(25) 182 #define FW1X_MPI_STATE_DOWNSHIFT __BITS(31,28) 183 #define FW1X_MPI_INIT2_REG 0x0370 184 #define FW1X_MPI_EFUSEADDR_REG 0x0374 185 186 #define FW2X_MPI_EFUSEADDR_REG 0x0364 187 #define FW2X_MPI_CONTROL_REG 0x0368 /* 64bit */ 188 #define FW2X_MPI_STATE_REG 0x0370 /* 64bit */ 189 #define FW_BOOT_EXIT_CODE_REG 0x0388 190 #define RBL_STATUS_DEAD 0x0000dead 191 #define RBL_STATUS_SUCCESS 0x0000abba 192 #define RBL_STATUS_FAILURE 0x00000bad 193 #define RBL_STATUS_HOST_BOOT 0x0000f1a7 194 195 #define AQ_FW_GLB_CPU_SEM_REG(i) (0x03a0 + (i) * 4) 196 #define AQ1_FW_SEM_RAM_REG AQ_FW_GLB_CPU_SEM_REG(2) 197 #define AQ2_ART_SEM_REG AQ_FW_GLB_CPU_SEM_REG(3) 198 199 #define AQ_FW_GLB_CTL2_REG 0x0404 200 #define AQ_FW_GLB_CTL2_MCP_UP_FORCE_INTERRUPT __BIT(1) 201 202 #define AQ_GLB_GENERAL_PROVISIONING9_REG 0x0520 203 #define AQ_GLB_NVR_PROVISIONING2_REG 0x0534 204 205 #define FW_MPI_DAISY_CHAIN_STATUS_REG 0x0704 206 207 #define AQ_PCI_REG_CONTROL_6_REG 0x1014 208 209 /* msix bitmap */ 210 #define AQ_INTR_STATUS_REG 0x2000 /* intr status */ 211 #define AQ_INTR_STATUS_CLR_REG 0x2050 /* intr status clear */ 212 #define AQ_INTR_MASK_REG 0x2060 /* intr mask set */ 213 #define AQ_INTR_MASK_CLR_REG 0x2070 /* intr mask clear */ 214 #define AQ_INTR_AUTOMASK_REG 0x2090 215 216 /* AQ_INTR_IRQ_MAP_TXRX_REG[AQ_RINGS_NUM] 0x2100-0x2140 */ 217 #define AQ_INTR_IRQ_MAP_TXRX_REG(i) (0x2100 + ((i) / 2) * 4) 218 #define AQ_INTR_IRQ_MAP_TX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i) 219 #define AQ_INTR_IRQ_MAP_TX_IRQMAP(i) (__BITS(28,24) >> (((i) & 1)*8)) 220 #define AQ_INTR_IRQ_MAP_TX_EN(i) (__BIT(31) >> (((i) & 1)*8)) 221 #define AQ_INTR_IRQ_MAP_RX_REG(i) AQ_INTR_IRQ_MAP_TXRX_REG(i) 222 #define AQ_INTR_IRQ_MAP_RX_IRQMAP(i) (__BITS(12,8) >> (((i) & 1)*8)) 223 #define AQ_INTR_IRQ_MAP_RX_EN(i) (__BIT(15) >> (((i) & 1)*8)) 224 225 /* AQ_GEN_INTR_MAP_REG[AQ_RINGS_NUM] 0x2180-0x2200 */ 226 #define AQ_GEN_INTR_MAP_REG(i) (0x2180 + (i) * 4) 227 #define AQ_B0_ERR_INT 8 228 229 #define AQ_INTR_CTRL_REG 0x2300 230 #define AQ_INTR_CTRL_IRQMODE __BITS(1,0) 231 #define AQ_INTR_CTRL_IRQMODE_LEGACY 0 232 #define AQ_INTR_CTRL_IRQMODE_MSI 1 233 #define AQ_INTR_CTRL_IRQMODE_MSIX 2 234 #define AQ_INTR_CTRL_MULTIVEC __BIT(2) 235 #define AQ_INTR_CTRL_AUTO_MASK __BIT(5) 236 #define AQ_INTR_CTRL_CLR_ON_READ __BIT(7) 237 #define AQ_INTR_CTRL_RESET_DIS __BIT(29) 238 #define AQ_INTR_CTRL_RESET_IRQ __BIT(31) 239 240 #define AQ_MBOXIF_POWER_GATING_CONTROL_REG 0x32a8 241 242 #define FW_MPI_RESETCTRL_REG 0x4000 243 #define FW_MPI_RESETCTRL_RESET_DIS __BIT(29) 244 245 #define RX_SYSCONTROL_REG 0x5000 246 #define RX_SYSCONTROL_RPF_TPO_SYS_LOOPBACK __BIT(8) 247 #define RX_SYSCONTROL_RPB_DMA_SYS_LOOPBACK __BIT(6) 248 #define RX_SYSCONTROL_RPB_DMA_NET_LOOPBACK __BIT(4) 249 #define RX_SYSCONTROL_RESET_DIS __BIT(29) 250 251 #define RX_TCP_RSS_HASH_REG 0x5040 252 #define RX_TCP_RSS_HASH_RPF2 __BITS(19,16) 253 #define RX_TCP_RSS_HASH_TYPE __BITS(15,0) 254 255 /* for RPF_*_REG.ACTION */ 256 #define RPF_ACTION_DISCARD 0 257 #define RPF_ACTION_HOST 1 258 #define RPF_ACTION_MANAGEMENT 2 259 #define RPF_ACTION_HOST_MANAGEMENT 3 260 #define RPF_ACTION_WOL 4 261 262 #define RPF_L2BC_REG 0x5100 263 #define RPF_L2BC_EN __BIT(0) 264 #define RPF_L2BC_PROMISC __BIT(3) 265 #define RPF_L2BC_ACTION __BITS(12,14) 266 #define RPF_L2BC_THRESHOLD __BITS(31,16) 267 268 /* RPF_L2UC_*_REG[34] (AQ2 has [38]) */ 269 #define RPF_L2UC_LSW_REG(i) (0x5110 + (i) * 8) 270 #define RPF_L2UC_MSW_REG(i) (0x5114 + (i) * 8) 271 #define RPF_L2UC_MSW_MACADDR_HI __BITS(15,0) 272 #define RPF_L2UC_MSW_ACTION __BITS(18,16) 273 #define RPF_L2UC_MSW_TAG __BITS(27,22) /* AQ2 */ 274 #define RPF_L2UC_MSW_EN __BIT(31) 275 276 #define AQ_HW_MAC_OWN 0 /* index of own address */ 277 #define AQ1_HW_MAC_NUM 34 278 #define AQ2_HW_MAC_NUM 38 279 #define AQ_HW_MAC_NUM(sc) \ 280 (HWTYPE_AQ2_P((sc)) ? AQ2_HW_MAC_NUM : AQ1_HW_MAC_NUM) 281 282 /* RPF_MCAST_FILTER_REG[8] 0x5250-0x5270 */ 283 #define RPF_MCAST_FILTER_REG(i) (0x5250 + (i) * 4) 284 #define RPF_MCAST_FILTER_EN __BIT(31) 285 #define RPF_MCAST_FILTER_MASK_REG 0x5270 286 #define RPF_MCAST_FILTER_MASK_ALLMULTI __BIT(14) 287 288 #define RPF_VLAN_MODE_REG 0x5280 289 #define RPF_VLAN_MODE_PROMISC __BIT(1) 290 #define RPF_VLAN_MODE_ACCEPT_UNTAGGED __BIT(2) 291 #define RPF_VLAN_MODE_UNTAGGED_ACTION __BITS(5,3) 292 293 #define RPF_VLAN_TPID_REG 0x5284 294 #define RPF_VLAN_TPID_OUTER __BITS(31,16) 295 #define RPF_VLAN_TPID_INNER __BITS(15,0) 296 297 /* RPF_VLAN_FILTER_REG[RPF_VLAN_MAX_FILTERS] 0x5290-0x52d0 */ 298 #define RPF_VLAN_MAX_FILTERS 16 299 #define RPF_VLAN_FILTER_REG(i) (0x5290 + (i) * 4) 300 #define RPF_VLAN_FILTER_EN __BIT(31) 301 #define RPF_VLAN_FILTER_RXQ_EN __BIT(28) 302 #define RPF_VLAN_FILTER_RXQ __BITS(24,20) 303 #define RPF_VLAN_FILTER_ACTION __BITS(18,16) 304 #define RPF_VLAN_FILTER_TAG __BITS(15,12) /* AQ2 */ 305 #define RPF_VLAN_FILTER_ID __BITS(11,0) 306 307 /* RPF_ETHERTYPE_FILTER_REG[AQ_RINGS_NUM] 0x5300-0x5380 */ 308 #define RPF_ETHERTYPE_FILTER_REG(i) (0x5300 + (i) * 4) 309 #define RPF_ETHERTYPE_FILTER_EN __BIT(31) 310 #define RPF_ETHERTYPE_FILTER_PRIO_EN __BIT(30) 311 #define RPF_ETHERTYPE_FILTER_RXQF_EN __BIT(29) 312 #define RPF_ETHERTYPE_FILTER_PRIO __BITS(28,26) 313 #define RPF_ETHERTYPE_FILTER_RXQF __BITS(24,20) 314 #define RPF_ETHERTYPE_FILTER_MNG_RXQF __BIT(19) 315 #define RPF_ETHERTYPE_FILTER_ACTION __BITS(18,16) 316 #define RPF_ETHERTYPE_FILTER_VAL __BITS(15,0) 317 318 /* RPF_L3_FILTER_REG[8] 0x5380-0x53a0 */ 319 #define RPF_L3_FILTER_REG(i) (0x5380 + (i) * 4) 320 #define RPF_L3_FILTER_L4_EN __BIT(31) 321 #define RPF_L3_FILTER_IPV6_EN __BIT(30) 322 #define RPF_L3_FILTER_SRCADDR_EN __BIT(29) 323 #define RPF_L3_FILTER_DSTADDR_EN __BIT(28) 324 #define RPF_L3_FILTER_L4_SRCPORT_EN __BIT(27) 325 #define RPF_L3_FILTER_L4_DSTPORT_EN __BIT(26) 326 #define RPF_L3_FILTER_L4_PROTO_EN __BIT(25) 327 #define RPF_L3_FILTER_ARP_EN __BIT(24) 328 #define RPF_L3_FILTER_L4_RXQUEUE_EN __BIT(23) 329 #define RPF_L3_FILTER_L4_RXQUEUE_MANAGEMENT_EN __BIT(22) 330 #define RPF_L3_FILTER_L4_ACTION __BITS(16,18) 331 #define RPF_L3_FILTER_L4_RXQUEUE __BITS(12,8) 332 #define RPF_L3_FILTER_L4_PROTO __BITS(2,0) 333 #define RPF_L3_FILTER_L4_PROTO_TCP 0 334 #define RPF_L3_FILTER_L4_PROTO_UDP 1 335 #define RPF_L3_FILTER_L4_PROTO_SCTP 2 336 #define RPF_L3_FILTER_L4_PROTO_ICMP 3 337 /* parameters of RPF_L3_FILTER_REG[8] */ 338 #define RPF_L3_FILTER_SRCADDR_REG(i) (0x53b0 + (i) * 4) 339 #define RPF_L3_FILTER_DSTADDR_REG(i) (0x53d0 + (i) * 4) 340 #define RPF_L3_FILTER_L4_SRCPORT_REG(i) (0x5400 + (i) * 4) 341 #define RPF_L3_FILTER_L4_DSTPORT_REG(i) (0x5420 + (i) * 4) 342 343 #define RX_FLR_RSS_CONTROL1_REG 0x54c0 344 #define RX_FLR_RSS_CONTROL1_EN __BIT(31) 345 346 #define RPF_RPB_RX_TC_UPT_REG 0x54c4 347 #define RPF_RPB_RX_TC_UPT_MASK(i) (0x00000007 << ((i) * 4)) 348 349 #define RPF_RSS_KEY_ADDR_REG 0x54d0 350 #define RPF_RSS_KEY_ADDR __BITS(4,0) 351 #define RPF_RSS_KEY_WR_EN __BIT(5) 352 #define RPF_RSS_KEY_WR_DATA_REG 0x54d4 353 #define RPF_RSS_KEY_RD_DATA_REG 0x54d8 354 355 #define RPF_RSS_REDIR_ADDR_REG 0x54e0 356 #define RPF_RSS_REDIR_ADDR __BITS(3,0) 357 #define RPF_RSS_REDIR_WR_EN __BIT(4) 358 359 #define RPF_RSS_REDIR_WR_DATA_REG 0x54e4 360 #define RPF_RSS_REDIR_WR_DATA __BITS(15,0) 361 362 #define RPO_HWCSUM_REG 0x5580 363 #define RPO_HWCSUM_IP4CSUM_EN __BIT(1) 364 #define RPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */ 365 366 #define RPO_LRO_ENABLE_REG 0x5590 367 368 #define RPO_LRO_CONF_REG 0x5594 369 #define RPO_LRO_CONF_QSESSION_LIMIT __BITS(13,12) 370 #define RPO_LRO_CONF_TOTAL_DESC_LIMIT __BITS(6,5) 371 #define RPO_LRO_CONF_PATCHOPTIMIZATION_EN __BIT(15) 372 #define RPO_LRO_CONF_MIN_PAYLOAD_OF_FIRST_PKT __BITS(4,0) 373 #define RPO_LRO_RSC_MAX_REG 0x5598 374 375 /* RPO_LRO_LDES_MAX_REG[32/8] 0x55a0-0x55b0 */ 376 #define RPO_LRO_LDES_MAX_REG(i) (0x55a0 + (i / 8) * 4) 377 #define RPO_LRO_LDES_MAX_MASK(i) (0x00000003 << ((i & 7) * 4)) 378 #define RPO_LRO_TB_DIV_REG 0x5620 379 #define RPO_LRO_TB_DIV __BITS(20,31) 380 #define RPO_LRO_INACTIVE_IVAL_REG 0x5620 381 #define RPO_LRO_INACTIVE_IVAL __BITS(10,19) 382 #define RPO_LRO_MAX_COALESCING_IVAL_REG 0x5620 383 #define RPO_LRO_MAX_COALESCING_IVAL __BITS(9,0) 384 385 #define RPB_RPF_RX_REG 0x5700 386 #define RPB_RPF_RX_TC_MODE __BIT(8) 387 #define RPB_RPF_RX_FC_MODE __BITS(5,4) 388 #define RPB_RPF_RX_BUF_EN __BIT(0) 389 390 /* RPB_RXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x5710-0x5790 */ 391 #define RPB_RXB_BUFSIZE_REG(i) (0x5710 + (i) * 0x10) 392 #define RPB_RXB_BUFSIZE __BITS(8,0) 393 #define RPB_RXB_XOFF_REG(i) (0x5714 + (i) * 0x10) 394 #define RPB_RXB_XOFF_EN __BIT(31) 395 #define RPB_RXB_XOFF_THRESH_HI __BITS(29,16) 396 #define RPB_RXB_XOFF_THRESH_LO __BITS(13,0) 397 398 #define RX_DMA_DESC_CACHE_INIT_REG 0x5a00 399 #define RX_DMA_DESC_CACHE_INIT __BIT(0) 400 401 #define RX_DMA_INT_DESC_WRWB_EN_REG 0x05a30 402 #define RX_DMA_INT_DESC_WRWB_EN __BIT(2) 403 #define RX_DMA_INT_DESC_MODERATE_EN __BIT(3) 404 405 /* RX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x5a40-0x5ac0 */ 406 #define RX_INTR_MODERATION_CTL_REG(i) (0x5a40 + (i) * 4) 407 #define RX_INTR_MODERATION_CTL_EN __BIT(1) 408 #define RX_INTR_MODERATION_CTL_MIN __BITS(15,8) 409 #define RX_INTR_MODERATION_CTL_MAX __BITS(24,16) 410 411 /* RX_DMA_DESC_*[AQ_RINGS_NUM] 0x5b00-0x5f00 */ 412 #define RX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x5b00 + (i) * 0x20) 413 #define RX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x5b04 + (i) * 0x20) 414 #define RX_DMA_DESC_REG(i) (0x5b08 + (i) * 0x20) 415 #define RX_DMA_DESC_LEN __BITS(12,3) /* RXD_NUM/8 */ 416 #define RX_DMA_DESC_RESET __BIT(25) 417 #define RX_DMA_DESC_HEADER_SPLIT __BIT(28) 418 #define RX_DMA_DESC_VLAN_STRIP __BIT(29) 419 #define RX_DMA_DESC_EN __BIT(31) 420 #define RX_DMA_DESC_HEAD_PTR_REG(i) (0x5b0c + (i) * 0x20) 421 #define RX_DMA_DESC_HEAD_PTR __BITS(12,0) 422 #define RX_DMA_DESC_TAIL_PTR_REG(i) (0x5b10 + (i) * 0x20) 423 #define RX_DMA_DESC_BUFSIZE_REG(i) (0x5b18 + (i) * 0x20) 424 #define RX_DMA_DESC_BUFSIZE_DATA __BITS(4,0) 425 #define RX_DMA_DESC_BUFSIZE_HDR __BITS(12,8) 426 427 /* RX_DMA_DCAD_REG[AQ_RINGS_NUM] 0x6100-0x6180 */ 428 #define RX_DMA_DCAD_REG(i) (0x6100 + (i) * 4) 429 #define RX_DMA_DCAD_CPUID __BITS(7,0) 430 #define RX_DMA_DCAD_PAYLOAD_EN __BIT(29) 431 #define RX_DMA_DCAD_HEADER_EN __BIT(30) 432 #define RX_DMA_DCAD_DESC_EN __BIT(31) 433 434 #define RX_DMA_DCA_REG 0x6180 435 #define RX_DMA_DCA_EN __BIT(31) 436 #define RX_DMA_DCA_MODE __BITS(3,0) 437 438 /* counters */ 439 #define RX_DMA_GOOD_PKT_COUNTERLSW 0x6800 440 #define RX_DMA_GOOD_OCTET_COUNTERLSW 0x6808 441 #define RX_DMA_DROP_PKT_CNT_REG 0x6818 442 #define RX_DMA_COALESCED_PKT_CNT_REG 0x6820 443 444 #define TX_SYSCONTROL_REG 0x7000 445 #define TX_SYSCONTROL_TPO_PKT_SYS_LOOPBACK __BIT(7) 446 #define TX_SYSCONTROL_TPB_DMA_SYS_LOOPBACK __BIT(6) 447 #define TX_SYSCONTROL_TPB_DMA_NET_LOOPBACK __BIT(4) 448 #define TX_SYSCONTROL_RESET_DIS __BIT(29) 449 450 #define TX_TPO2_REG 0x7040 451 #define TX_TPO2_EN __BIT(16) 452 453 #define TPS_DESC_VM_ARB_MODE_REG 0x7300 454 #define TPS_DESC_VM_ARB_MODE __BIT(0) 455 #define TPS_DESC_RATE_REG 0x7310 456 #define TPS_DESC_RATE_TA_RST __BIT(31) 457 #define TPS_DESC_RATE_LIM __BITS(10,0) 458 #define TPS_DESC_TC_ARB_MODE_REG 0x7200 459 #define TPS_DESC_TC_ARB_MODE __BITS(1,0) 460 #define TPS_DATA_TC_ARB_MODE_REG 0x7100 461 #define TPS_DATA_TC_ARB_MODE __BIT(0) 462 463 /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7110-0x7130 */ 464 #define TPS_DATA_TCT_REG(i) (0x7110 + (i) * 4) 465 #define TPS_DATA_TCT_CREDIT_MAX __BITS(16,27) 466 #define TPS_DATA_TCT_WEIGHT __BITS(8,0) 467 /* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7210-0x7230 */ 468 #define TPS_DESC_TCT_REG(i) (0x7210 + (i) * 4) 469 #define TPS_DESC_TCT_CREDIT_MAX __BITS(16,27) 470 #define TPS_DESC_TCT_WEIGHT __BITS(8,0) 471 472 #define AQ1_HW_TXBUF_MAX 160 473 #define AQ1_HW_RXBUF_MAX 320 474 #define AQ2_HW_TXBUF_MAX 128 475 #define AQ2_HW_RXBUF_MAX 192 476 477 #define TPO_HWCSUM_REG 0x7800 478 #define TPO_HWCSUM_IP4CSUM_EN __BIT(1) 479 #define TPO_HWCSUM_L4CSUM_EN __BIT(0) /* TCP/UDP/SCTP */ 480 481 #define TDM_LSO_EN_REG 0x7810 482 483 #define THM_LSO_TCP_FLAG1_REG 0x7820 484 #define THM_LSO_TCP_FLAG1_FIRST __BITS(11,0) 485 #define THM_LSO_TCP_FLAG1_MID __BITS(27,16) 486 #define THM_LSO_TCP_FLAG2_REG 0x7824 487 #define THM_LSO_TCP_FLAG2_LAST __BITS(11,0) 488 489 #define TPB_TX_BUF_REG 0x7900 490 #define TPB_TX_BUF_EN __BIT(0) 491 #define TPB_TX_BUF_SCP_INS_EN __BIT(2) 492 #define TPB_TX_BUF_CLK_GATE_EN __BIT(5) 493 #define TPB_TX_BUF_TC_MODE __BIT(8) 494 #define TPB_TX_BUF_TC_Q_RAND_MAP_EN __BIT(9) /* AQ2 */ 495 496 /* TPB_TXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x7910-7990 */ 497 #define TPB_TXB_BUFSIZE_REG(i) (0x7910 + (i) * 0x10) 498 #define TPB_TXB_BUFSIZE __BITS(7,0) 499 #define TPB_TXB_THRESH_REG(i) (0x7914 + (i) * 0x10) 500 #define TPB_TXB_THRESH_HI __BITS(16,28) 501 #define TPB_TXB_THRESH_LO __BITS(12,0) 502 503 #define AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG 0x7b20 504 #define TX_DMA_INT_DESC_WRWB_EN_REG 0x7b40 505 #define TX_DMA_INT_DESC_WRWB_EN __BIT(1) 506 #define TX_DMA_INT_DESC_MODERATE_EN __BIT(4) 507 508 /* TX_DMA_DESC_*[AQ_RINGS_NUM] 0x7c00-0x8400 */ 509 #define TX_DMA_DESC_BASE_ADDRLSW_REG(i) (0x7c00 + (i) * 0x40) 510 #define TX_DMA_DESC_BASE_ADDRMSW_REG(i) (0x7c04 + (i) * 0x40) 511 #define TX_DMA_DESC_REG(i) (0x7c08 + (i) * 0x40) 512 #define TX_DMA_DESC_LEN __BITS(12, 3) /* TXD_NUM/8 */ 513 #define TX_DMA_DESC_EN __BIT(31) 514 #define TX_DMA_DESC_HEAD_PTR_REG(i) (0x7c0c + (i) * 0x40) 515 #define TX_DMA_DESC_HEAD_PTR __BITS(12,0) 516 #define TX_DMA_DESC_TAIL_PTR_REG(i) (0x7c10 + (i) * 0x40) 517 #define TX_DMA_DESC_WRWB_THRESH_REG(i) (0x7c18 + (i) * 0x40) 518 #define TX_DMA_DESC_WRWB_THRESH __BITS(14,8) 519 520 /* TDM_DCAD_REG[AQ_RINGS_NUM] 0x8400-0x8480 */ 521 #define TDM_DCAD_REG(i) (0x8400 + (i) * 4) 522 #define TDM_DCAD_CPUID __BITS(7,0) 523 #define TDM_DCAD_CPUID_EN __BIT(31) 524 525 #define TDM_DCA_REG 0x8480 526 #define TDM_DCA_EN __BIT(31) 527 #define TDM_DCA_MODE __BITS(3,0) 528 529 /* TX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x8980-0x8a00 */ 530 #define TX_INTR_MODERATION_CTL_REG(i) (0x8980 + (i) * 4) 531 #define TX_INTR_MODERATION_CTL_EN __BIT(1) 532 #define TX_INTR_MODERATION_CTL_MIN __BITS(15,8) 533 #define TX_INTR_MODERATION_CTL_MAX __BITS(24,16) 534 535 /* AQ2 (ATL2) registers */ 536 #define AQ2_QUEUE_MODE 0x0c9c 537 538 #define AQ2_MIF_HOST_FINISHED_STATUS_WRITE_REG 0x0e00 539 #define AQ2_MIF_HOST_FINISHED_STATUS_READ_REG 0x0e04 540 #define AQ2_MIF_HOST_FINISHED_STATUS_ACK __BIT(0) 541 542 #define AQ2_MCP_HOST_REQ_INT_REG 0x0f00 543 #define AQ2_MCP_HOST_REQ_INT_READY __BIT(0) 544 #define AQ2_MCP_HOST_REQ_INT_SET_REG 0x0f04 545 #define AQ2_MCP_HOST_REQ_INT_CLR_REG 0x0f08 546 547 #define AQ2_PHI_EXT_TAG_REG 0x1000 548 #define AQ2_PHI_EXT_TAG_ENABLE __BIT(5) 549 550 #define AQ2_MIF_BOOT_REG 0x3040 551 #define AQ2_MIF_BOOT_HOST_DATA_LOADED __BIT(16) 552 #define AQ2_MIF_BOOT_BOOT_STARTED __BIT(24) 553 #define AQ2_MIF_BOOT_CRASH_INIT __BIT(27) 554 #define AQ2_MIF_BOOT_BOOT_CODE_FAILED __BIT(28) 555 #define AQ2_MIF_BOOT_FW_INIT_FAILED __BIT(29) 556 #define AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS __BIT(31) 557 558 /* ART(Action Resolver Table) */ 559 #define AQ2_ART_ACTION_ACT_MASK __BITS(9,8) 560 #define AQ2_ART_ACTION_RSS_MASK __BIT(7) 561 #define AQ2_ART_ACTION_INDEX_MASK __BITS(6,2) 562 #define AQ2_ART_ACTION_ENABLE_MASK __BIT(0) 563 #define AQ2_ART_ACTION(act, rss, idx, en) \ 564 (__SHIFTIN((act), AQ2_ART_ACTION_ACT_MASK) | \ 565 __SHIFTIN((rss), AQ2_ART_ACTION_RSS_MASK) | \ 566 __SHIFTIN((idx), AQ2_ART_ACTION_INDEX_MASK) | \ 567 __SHIFTIN((en), AQ2_ART_ACTION_ENABLE_MASK)) 568 #define AQ2_ART_ACTION_DROP AQ2_ART_ACTION(0, 0, 0, 1) 569 #define AQ2_ART_ACTION_DISABLE AQ2_ART_ACTION(0, 0, 0, 0) 570 #define AQ2_ART_ACTION_ASSIGN_QUEUE(q) AQ2_ART_ACTION(1, 0, (q), 1) 571 #define AQ2_ART_ACTION_ASSIGN_TC(tc) AQ2_ART_ACTION(1, 1, (tc), 1) 572 573 #define AQ2_RPF_TAG_PCP_MASK __BITS(31,29) 574 #define AQ2_RPF_TAG_FLEX_MASK __BITS(28,27) 575 #define AQ2_RPF_TAG_UNKNOWN_MASK __BITS(26,24) 576 #define AQ2_RPF_TAG_L4_MASK __BITS(23,21) 577 #define AQ2_RPF_TAG_L3_V6_MASK __BITS(20,18) 578 #define AQ2_RPF_TAG_L3_V4_MASK __BITS(17,15) 579 #define AQ2_RPF_TAG_UNTAG_MASK __BIT(14) 580 #define AQ2_RPF_TAG_VLAN_MASK __BITS(13,10) 581 #define AQ2_RPF_TAG_ET_MASK __BITS(9,7) 582 #define AQ2_RPF_TAG_ALLMC_MASK __BIT(6) 583 #define AQ2_RPF_TAG_UC_MASK __BITS(5,0) 584 585 /* index of aq2_filter_art_set() */ 586 #define AQ2_RPF_INDEX_L2_PROMISC_OFF 0 587 #define AQ2_RPF_INDEX_VLAN_PROMISC_OFF 1 588 #define AQ2_RPF_INDEX_L3L4_USER 8 589 #define AQ2_RPF_INDEX_ET_PCP_USER 24 590 #define AQ2_RPF_INDEX_VLAN_USER 40 591 #define AQ2_RPF_INDEX_PCP_TO_TC 56 592 593 #define AQ2_RPF_L2BC_TAG_REG 0x50f0 594 #define AQ2_RPF_L2BC_TAG_MASK __BITS(5,0) 595 596 #define AQ2_RPF_NEW_CTRL_REG 0x5104 597 #define AQ2_RPF_NEW_CTRL_ENABLE __BIT(11) 598 599 #define AQ2_RPF_L2UC_TAG_REG(i) (0x5110 + (i) * 8) 600 #define AQ2_RPF_L2UC_TAG_MASK __BITS(27,22) 601 602 #define AQ2_RPF_REDIR2_REG 0x54c8 603 #define AQ2_RPF_REDIR2_INDEX __BIT(12) 604 #define AQ2_RPF_REDIR2_HASHTYPE __BITS(8,0) 605 #define AQ2_RPF_REDIR2_HASHTYPE_NONE 0 606 #define AQ2_RPF_REDIR2_HASHTYPE_IP __BIT(0) 607 #define AQ2_RPF_REDIR2_HASHTYPE_TCP4 __BIT(1) 608 #define AQ2_RPF_REDIR2_HASHTYPE_UDP4 __BIT(2) 609 #define AQ2_RPF_REDIR2_HASHTYPE_IP6 __BIT(3) 610 #define AQ2_RPF_REDIR2_HASHTYPE_TCP6 __BIT(4) 611 #define AQ2_RPF_REDIR2_HASHTYPE_UDP6 __BIT(5) 612 #define AQ2_RPF_REDIR2_HASHTYPE_IP6EX __BIT(6) 613 #define AQ2_RPF_REDIR2_HASHTYPE_TCP6EX __BIT(7) 614 #define AQ2_RPF_REDIR2_HASHTYPE_UDP6EX __BIT(8) 615 #define AQ2_RPF_REDIR2_HASHTYPE_ALL __BITS(8,0) 616 617 #define AQ2_RX_Q_TC_MAP_REG(i) (0x5900 + (i) * 4) 618 619 #define AQ2_RDM_RX_DESC_RD_REQ_LIMIT_REG 0x5a04 620 621 #define AQ2_RPF_RSS_REDIR_REG(tc, i) \ 622 (0x6200 + (0x100 * ((tc) >> 2)) + (i) * 4) 623 #define AQ2_RPF_RSS_REDIR_TC_MASK(tc) \ 624 (__BITS(4,0) << (5 * ((tc) & 3))) 625 626 #define AQ2_RPF_L3_V6_V4_SELECT_REG 0x6500 627 #define AQ2_RPF_L3_V6_V4_SELECT_EN __BIT(23) 628 629 #define AQ2_RPF_REC_TAB_ENABLE_REG 0x6ff0 630 #define AQ2_RPF_REC_TAB_ENABLE_MASK __BITS(15,0) 631 632 #define AQ2_TX_Q_TC_MAP_REG(i) (0x799c + (i) * 4) 633 634 #define AQ2_LAUNCHTIME_CTRL_REG 0x7a1c 635 #define AQ2_LAUNCHTIME_CTRL_RATIO __BITS(15,8) 636 #define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_QUATER 4 637 #define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_HALF 2 638 #define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_FULL 1 639 640 /* AT2_TX_INTR_MODERATION_CTL_REG[AQ_RINGS_NUM] 0x7c28-0x8428 */ 641 #define AQ2_TX_INTR_MODERATION_CTL_REG(i) (0x7c28 + (i) * 0x40) 642 #define AQ2_TX_INTR_MODERATION_CTL_EN __BIT(1) 643 #define AQ2_TX_INTR_MODERATION_CTL_MIN __BITS(15,8) 644 #define AQ2_TX_INTR_MODERATION_CTL_MAX __BITS(24,16) 645 646 /* RW shared buffer */ 647 #define AQ2_FW_INTERFACE_IN_MTU_REG 0x12000 648 #define AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG 0x12008 649 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG 0x12010 650 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_PROMISCUOUS_MODE __BIT(13) 651 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_FRAME_PADDING_REMOVAL_RX __BIT(12) 652 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_CRC_FORWARDING __BIT(11) 653 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_TX_PADDING __BIT(10) 654 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_CONTROL_FRAME __BIT(9) 655 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISCARD_ERROR_FRAME __BIT(8) 656 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISABLE_LENGTH_CHECK __BIT(7) 657 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_FLOW_CONTROL_MODE __BIT(6) 658 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISCARD_SHORT_FRAMES __BIT(5) 659 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_DISABLE_CRC_CORRUPTION __BIT(4) 660 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE __BITS(3,0) 661 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_INVALID 0 662 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE 1 663 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SLEEP_PROXY 2 664 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_LOWPOWER 3 665 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SHUTDOWN 4 666 667 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG 0x12018 668 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_DOWNSHIFT_RETRY __BITS(31,28) 669 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_DOWNSHIFT __BIT(27) 670 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX __BIT(25) 671 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX __BIT(24) 672 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_10G __BIT(20) 673 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_5G __BIT(19) 674 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_2G5 __BIT(18) 675 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_1G __BIT(17) 676 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_100M __BIT(16) 677 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G __BIT(15) 678 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G __BIT(14) 679 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G __BIT(13) 680 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5 __BIT(12) 681 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5 __BIT(11) 682 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G __BIT(10) 683 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M __BIT(9) 684 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M __BIT(8) 685 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD __BIT(7) 686 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD __BIT(6) 687 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD __BIT(5) 688 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EXTERNAL_LOOPBACK __BIT(4) 689 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_INTERNAL_LOOPBACK __BIT(3) 690 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_MINIMAL_LINK_SPEED __BIT(2) 691 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_RENEGOTIATE __BIT(1) 692 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP __BIT(0) 693 694 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_REG 0x12020 695 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_WARN_TEMP __BITS(24,31) 696 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_COLD_TEMP __BITS(16,23) 697 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_SHUTDOWN_TEMP __BITS(15,8) 698 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_WARNING_ENABLE __BIT(1) 699 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_ENABLE __BIT(0) 700 701 #define AQ2_FW_INTERFACE_IN_SLEEP_PROXY 0x12028 702 #define AQ2_FW_INTERFACE_IN_PAUSE_QUANTA 0x12984 703 704 #define AQ2_FW_INTERFACE_IN_CABLE_DIAG_CONTROL_REG 0x12a44 705 #define AQ2_FW_INTERFACE_IN_DATA_BUFFER_STATUS_OFF_REG 0x12a4c 706 #define AQ2_FW_INTERFACE_IN_DATA_BUFFER_STATUS_LEN_REG 0x12a50 707 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG 0x12a58 708 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_QUEUE_OR_TC __BIT(23) 709 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_RX_QUEUE_TC_INDEX __BITS(22,18) 710 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_ACCEPT __BIT(16) 711 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_QUEUE_OR_TC __BIT(15) 712 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_RX_QUEUE_TC_INDEX __BITS(14,10) 713 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_ACCEPT __BIT(8) 714 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_QUEUE_OR_TC __BIT(7) 715 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_RX_QUEUE_TX_INDEX __BITS(6,2) 716 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_MCAST __BIT(1) 717 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_ALL __BIT(0) 718 719 /* RO shared buffer */ 720 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG 0x13000 721 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B __BITS(31,16) 722 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A __BITS(15,0) 723 #define AQ2_FW_INTERFACE_OUT_VERSION_BUNDLE_REG 0x13004 724 #define AQ2_FW_INTERFACE_OUT_VERSION_MAC_REG 0x13008 725 #define AQ2_FW_INTERFACE_OUT_VERSION_PHY_REG 0x1300c 726 #define AQ2_FW_INTERFACE_OUT_VERSION_BUILD __BITS(31,16) 727 #define AQ2_FW_INTERFACE_OUT_VERSION_MINOR __BITS(8,15) 728 #define AQ2_FW_INTERFACE_OUT_VERSION_MAJOR __BITS(7,0) 729 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_REG 0x13010 730 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER __BITS(3,0) 731 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_A0 0 732 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_B0 1 733 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_REG 0x13014 734 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_DUPLEX __BIT(11) 735 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_EEE __BIT(10) 736 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_RX __BIT(9) 737 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_TX __BIT(8) 738 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE __BITS(7,4) 739 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10G 6 740 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_5G 5 741 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_2G5 4 742 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_1G 3 743 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_100M 2 744 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10M 1 745 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_INVALID 0 746 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_STATE __BITS(3,0) 747 #define AQ2_FW_INTERFACE_OUT_WOL_STATUS_REG 0x13018 748 749 #define AQ2_FW_INTERFACE_OUT_MAC_HEALTH_MONITOR 0x13610 750 #define AQ2_FW_INTERFACE_OUT_PHY_HEALTH_MONITOR 0x13620 751 typedef struct aq2_health_monitor { 752 uint32_t data1; 753 #define HEALTH_MONITOR_DATA1_READY __BIT(0) 754 #define HEALTH_MONITOR_DATA1_FAULT __BIT(1) 755 #define HEALTH_MONITOR_DATA1_FLASHLESS_FINISHED __BIT(2) 756 #define HEALTH_MONITOR_DATA1_HOT_WARNING __BIT(2) 757 #define HEALTH_MONITOR_DATA1_TEMPERATURE __BITS(15,8) 758 #define HEALTH_MONITOR_DATA1_HEARTBEAT __BITS(31,16) 759 uint32_t data2; 760 #define HEALTH_MONITOR_DATA2_FAULTCODE __BITS(15,0) 761 } aq2_health_monitor_t; 762 763 #define AQ2_FW_INTERFACE_OUT_CABLE_DIAG_STATUS_LANE_REG(i) (0x13630 + (i) * 4) 764 #define AQ2_FW_INTERFACE_OUT_CABLE_DIAG_STATUS_IDSTAT_REG 0x13640 765 #define AQ2_FW_INTERFACE_OUT_CABLE_DIAG_STATUS_IDSTAT_ID __BITS(7,0) 766 #define AQ2_FW_INTERFACE_OUT_CABLE_DIAG_STATUS_IDSTAT_STATUS __BITS(8,11) 767 768 #define AQ2_FW_INTERFACE_OUT_DEVICE_LINK_CAPS_REG 0x13648 769 #define AQ2_FW_INTERFACE_OUT_SLEEP_PROXY_CAPS_REG 0x13650 770 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_REG 0x13660 771 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_PAUSE_TX __BIT(25) 772 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_PAUSE_RX __BIT(24) 773 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_10G __BIT(23) 774 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_5G __BIT(21) 775 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_2G5 __BIT(19) 776 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_1G __BIT(18) 777 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_EEE_100M __BIT(17) 778 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_10G __BIT(15) 779 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_N5G __BIT(14) 780 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_5G __BIT(13) 781 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_N2G5 __BIT(12) 782 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_2G5 __BIT(11) 783 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_1G __BIT(10) 784 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_100M __BIT(9) 785 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_10M __BIT(8) 786 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_1G_HD __BIT(7) 787 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_100M_HD __BIT(6) 788 #define AQ2_FW_INTERFACE_OUT_LKP_LINK_CAPS_RATE_10M_HD __BIT(5) 789 790 #define AQ2_FW_INTERFACE_OUT_CORE_DUMP_REG 0x13668 791 #define AQ2_FW_INTERFACE_OUT_STATS_REG 0x13700 792 struct aq2_statistics_a0 { 793 uint32_t link_up; 794 uint32_t link_down; 795 uint64_t tx_unicast_octets; 796 uint64_t tx_multicast_octets; 797 uint64_t tx_broadcast_octets; 798 uint64_t rx_unicast_octets; 799 uint64_t rx_multicast_octets; 800 uint64_t rx_broadcast_octets; 801 uint32_t tx_unicast_frames; 802 uint32_t tx_multicast_frames; 803 uint32_t tx_broadcast_frames; 804 uint32_t tx_errors; 805 uint32_t rx_unicast_frames; 806 uint32_t rx_multicast_frames; 807 uint32_t rx_broadcast_frames; 808 uint32_t rx_dropped_frames; 809 uint32_t rx_errors; 810 uint32_t tx_good_frames; 811 uint32_t rx_good_frames; 812 uint32_t reserved1; 813 uint32_t main_loop_cycles; 814 uint32_t reserved2; 815 }; 816 817 struct aq2_statistics_b0 { 818 uint64_t rx_good_octets; 819 uint64_t rx_pause_frames; 820 uint64_t rx_good_frames; 821 uint64_t rx_errors; 822 uint64_t rx_unicast_frames; 823 uint64_t rx_multicast_frames; 824 uint64_t rx_broadcast_frames; 825 uint64_t tx_good_octets; 826 uint64_t tx_pause_frames; 827 uint64_t tx_good_frames; 828 uint64_t tx_errors; 829 uint64_t tx_unicast_frames; 830 uint64_t tx_multicast_frames; 831 uint64_t tx_broadcast_frames; 832 uint32_t main_loop_cycles; 833 } __packed; 834 835 typedef struct aq2_statistics { 836 union { 837 struct aq2_statistics_a0 a0; 838 struct aq2_statistics_b0 b0; 839 }; 840 } aq2_statistics_t; 841 842 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS_REG 0x13774 843 typedef struct aq2_filter_caps { 844 uint32_t caps1; 845 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_ETHTYPE_FILTER_COUNT __BITS(24,31) 846 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_ETHTYPE_FILTER_BASE_INDEX __BITS(16,23) 847 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_L2_FILTER_COUNT __BITS(8,15) 848 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_FLEXIBLE_FILTER_MASK __BITS(6,7) 849 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS1_L2_FILTER_BASE_INDEX __BITS(0,5) 850 uint32_t caps2; 851 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_L3_IP6_FILTER_COUNT __BITS(28,31) 852 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_L3_IP6_FILTER_BASE_INDEX __BITS(24,27) 853 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_L3_IP4_FILTER_COUNT __BITS(20,23) 854 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_L3_IP4_FILTER_BASE_INDEX __BITS(16,19) 855 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_VLAN_FILTER_COUNT __BITS(8,15) 856 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS2_VLAN_FILTER_BASE_INDEX __BITS(0,7) 857 uint32_t caps3; 858 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_TABLE_COUNT __BITS(24,31) 859 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX __BITS(16,23) 860 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_L4_FLEX_FILTER_COUNT __BITS(12,15) 861 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_L4_FLEX_FILTER_BASE_INDEX __BITS(8,11) 862 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_L4_FILTER_COUNT __BITS(4,7) 863 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_L4_FILTER_BASE_INDEX __BITS(0,3) 864 } aq2_filter_caps_t; 865 866 #define AQ2_FW_INTERFACE_OUT_DEVICE_CAPS_REG 0x13780 867 #define AQ2_FW_INTERFACE_OUT_MANAGEMENT_STATUS_REG 0x1378c 868 #define AQ2_FW_INTERFACE_OUT_TRACE_REG 0x13800 869 870 #define AQ2_RPF_ACT_ART_REQ_TAG_REG(i) (0x14000 + (i) * 0x10) 871 #define AQ2_RPF_ACT_ART_REQ_MASK_REG(i) (0x14004 + (i) * 0x10) 872 #define AQ2_RPF_ACT_ART_REQ_ACTION_REG(i) (0x14008 + (i) * 0x10) 873 874 #define FW1X_CTRL_10G __BIT(0) 875 #define FW1X_CTRL_5G __BIT(1) 876 #define FW1X_CTRL_5GSR __BIT(2) 877 #define FW1X_CTRL_2G5 __BIT(3) 878 #define FW1X_CTRL_1G __BIT(4) 879 #define FW1X_CTRL_100M __BIT(5) 880 881 #define FW2X_CTRL_10BASET_HD __BIT(0) 882 #define FW2X_CTRL_10BASET_FD __BIT(1) 883 #define FW2X_CTRL_100BASETX_HD __BIT(2) 884 #define FW2X_CTRL_100BASET4_HD __BIT(3) 885 #define FW2X_CTRL_100BASET2_HD __BIT(4) 886 #define FW2X_CTRL_100BASETX_FD __BIT(5) 887 #define FW2X_CTRL_100BASET2_FD __BIT(6) 888 #define FW2X_CTRL_1000BASET_HD __BIT(7) 889 #define FW2X_CTRL_1000BASET_FD __BIT(8) 890 #define FW2X_CTRL_2P5GBASET_FD __BIT(9) 891 #define FW2X_CTRL_5GBASET_FD __BIT(10) 892 #define FW2X_CTRL_10GBASET_FD __BIT(11) 893 #define FW2X_CTRL_RESERVED1 __BIT(32) 894 #define FW2X_CTRL_10BASET_EEE __BIT(33) 895 #define FW2X_CTRL_RESERVED2 __BIT(34) 896 #define FW2X_CTRL_PAUSE __BIT(35) 897 #define FW2X_CTRL_ASYMMETRIC_PAUSE __BIT(36) 898 #define FW2X_CTRL_100BASETX_EEE __BIT(37) 899 #define FW2X_CTRL_RESERVED3 __BIT(38) 900 #define FW2X_CTRL_RESERVED4 __BIT(39) 901 #define FW2X_CTRL_1000BASET_FD_EEE __BIT(40) 902 #define FW2X_CTRL_2P5GBASET_FD_EEE __BIT(41) 903 #define FW2X_CTRL_5GBASET_FD_EEE __BIT(42) 904 #define FW2X_CTRL_10GBASET_FD_EEE __BIT(43) 905 #define FW2X_CTRL_RESERVED5 __BIT(44) 906 #define FW2X_CTRL_RESERVED6 __BIT(45) 907 #define FW2X_CTRL_RESERVED7 __BIT(46) 908 #define FW2X_CTRL_RESERVED8 __BIT(47) 909 #define FW2X_CTRL_RESERVED9 __BIT(48) 910 #define FW2X_CTRL_CABLE_DIAG __BIT(49) 911 #define FW2X_CTRL_TEMPERATURE __BIT(50) 912 #define FW2X_CTRL_DOWNSHIFT __BIT(51) 913 #define FW2X_CTRL_PTP_AVB_EN __BIT(52) 914 #define FW2X_CTRL_MEDIA_DETECT __BIT(53) 915 #define FW2X_CTRL_LINK_DROP __BIT(54) 916 #define FW2X_CTRL_SLEEP_PROXY __BIT(55) 917 #define FW2X_CTRL_WOL __BIT(56) 918 #define FW2X_CTRL_MAC_STOP __BIT(57) 919 #define FW2X_CTRL_EXT_LOOPBACK __BIT(58) 920 #define FW2X_CTRL_INT_LOOPBACK __BIT(59) 921 #define FW2X_CTRL_EFUSE_AGENT __BIT(60) 922 #define FW2X_CTRL_WOL_TIMER __BIT(61) 923 #define FW2X_CTRL_STATISTICS __BIT(62) 924 #define FW2X_CTRL_TRANSACTION_ID __BIT(63) 925 926 #define FW2X_SNPRINTB \ 927 "\177\020" \ 928 "b\x23" "PAUSE\0" \ 929 "b\x24" "ASYMMETRIC-PAUSE\0" \ 930 "b\x31" "CABLE-DIAG\0" \ 931 "b\x32" "TEMPERATURE\0" \ 932 "b\x33" "DOWNSHIFT\0" \ 933 "b\x34" "PTP-AVB\0" \ 934 "b\x35" "MEDIA-DETECT\0" \ 935 "b\x36" "LINK-DROP\0" \ 936 "b\x37" "SLEEP-PROXY\0" \ 937 "b\x38" "WOL\0" \ 938 "b\x39" "MAC-STOP\0" \ 939 "b\x3a" "EXT-LOOPBACK\0" \ 940 "b\x3b" "INT-LOOPBACK\0" \ 941 "b\x3c" "EFUSE-AGENT\0" \ 942 "b\x3d" "WOL-TIMER\0" \ 943 "b\x3e" "STATISTICS\0" \ 944 "b\x3f" "TRANSACTION-ID\0" \ 945 "\0" 946 947 #define FW2X_CTRL_RATE_100M FW2X_CTRL_100BASETX_FD 948 #define FW2X_CTRL_RATE_1G FW2X_CTRL_1000BASET_FD 949 #define FW2X_CTRL_RATE_2G5 FW2X_CTRL_2P5GBASET_FD 950 #define FW2X_CTRL_RATE_5G FW2X_CTRL_5GBASET_FD 951 #define FW2X_CTRL_RATE_10G FW2X_CTRL_10GBASET_FD 952 #define FW2X_CTRL_RATE_MASK \ 953 (FW2X_CTRL_RATE_100M | \ 954 FW2X_CTRL_RATE_1G | \ 955 FW2X_CTRL_RATE_2G5 | \ 956 FW2X_CTRL_RATE_5G | \ 957 FW2X_CTRL_RATE_10G) 958 #define FW2X_CTRL_EEE_MASK \ 959 (FW2X_CTRL_10BASET_EEE | \ 960 FW2X_CTRL_100BASETX_EEE | \ 961 FW2X_CTRL_1000BASET_FD_EEE | \ 962 FW2X_CTRL_2P5GBASET_FD_EEE | \ 963 FW2X_CTRL_5GBASET_FD_EEE | \ 964 FW2X_CTRL_10GBASET_FD_EEE) 965 966 typedef enum aq_fw_bootloader_mode { 967 FW_BOOT_MODE_UNKNOWN = 0, 968 FW_BOOT_MODE_FLB, 969 FW_BOOT_MODE_RBL_FLASH, 970 FW_BOOT_MODE_RBL_HOST_BOOTLOAD 971 } aq_fw_bootloader_mode_t; 972 973 #define AQ_WRITE_REG(sc, reg, val) \ 974 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 975 976 #define AQ_READ_REG(sc, reg) \ 977 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 978 979 #define AQ_READ_REGS(sc, reg, p, cnt) \ 980 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (p), (cnt)) 981 982 #define AQ_READ64_REG(sc, reg) \ 983 ((uint64_t)AQ_READ_REG(sc, reg) | \ 984 (((uint64_t)AQ_READ_REG(sc, (reg) + 4)) << 32)) 985 986 #define AQ_WRITE64_REG(sc, reg, val) \ 987 do { \ 988 AQ_WRITE_REG(sc, reg, (uint32_t)val); \ 989 AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32)); \ 990 } while (/* CONSTCOND */0) 991 992 #define AQ_READ_REG_BIT(sc, reg, mask) \ 993 __SHIFTOUT(AQ_READ_REG(sc, reg), mask) 994 995 #define AQ_WRITE_REG_BIT(sc, reg, mask, val) \ 996 do { \ 997 uint32_t _v; \ 998 _v = AQ_READ_REG((sc), (reg)); \ 999 _v &= ~(mask); \ 1000 if ((val) != 0) \ 1001 _v |= __SHIFTIN((val), (mask)); \ 1002 AQ_WRITE_REG((sc), (reg), _v); \ 1003 } while (/* CONSTCOND */ 0) 1004 1005 #define WAIT_FOR(expr, us, n, errp) \ 1006 do { \ 1007 unsigned int _n; \ 1008 for (_n = n; (!(expr)) && _n != 0; --_n) { \ 1009 delay((us)); \ 1010 } \ 1011 if ((errp != NULL)) { \ 1012 if (_n == 0) \ 1013 *(errp) = ETIMEDOUT; \ 1014 else \ 1015 *(errp) = 0; \ 1016 } \ 1017 } while (/* CONSTCOND */ 0) 1018 1019 #define msec_delay(x) DELAY(1000 * (x)) 1020 1021 typedef struct aq_mailbox_header { 1022 uint32_t version; 1023 uint32_t transaction_id; 1024 int32_t error; 1025 } __packed __aligned(4) aq_mailbox_header_t; 1026 1027 typedef struct aq_hw_stats_s { 1028 uint32_t uprc; 1029 uint32_t mprc; 1030 uint32_t bprc; 1031 uint32_t erpt; 1032 uint32_t uptc; 1033 uint32_t mptc; 1034 uint32_t bptc; 1035 uint32_t erpr; 1036 uint32_t mbtc; 1037 uint32_t bbtc; 1038 uint32_t mbrc; 1039 uint32_t bbrc; 1040 uint32_t ubrc; 1041 uint32_t ubtc; 1042 uint32_t ptc; 1043 uint32_t prc; 1044 uint32_t dpc; /* not exists in fw2x_msm_statistics */ 1045 uint32_t cprc; /* not exists in fw2x_msm_statistics */ 1046 } __packed __aligned(4) aq_hw_stats_s_t; 1047 1048 typedef struct fw1x_mailbox { 1049 aq_mailbox_header_t header; 1050 aq_hw_stats_s_t msm; 1051 } __packed __aligned(4) fw1x_mailbox_t; 1052 1053 typedef struct fw2x_msm_statistics { 1054 uint32_t uprc; 1055 uint32_t mprc; 1056 uint32_t bprc; 1057 uint32_t erpt; 1058 uint32_t uptc; 1059 uint32_t mptc; 1060 uint32_t bptc; 1061 uint32_t erpr; 1062 uint32_t mbtc; 1063 uint32_t bbtc; 1064 uint32_t mbrc; 1065 uint32_t bbrc; 1066 uint32_t ubrc; 1067 uint32_t ubtc; 1068 uint32_t ptc; 1069 uint32_t prc; 1070 } __packed __aligned(4) fw2x_msm_statistics_t; 1071 1072 typedef struct fw2x_phy_cable_diag_data { 1073 uint32_t lane_data[4]; 1074 } __packed __aligned(4) fw2x_phy_cable_diag_data_t; 1075 1076 typedef struct fw2x_capabilities { 1077 uint32_t caps_lo; 1078 uint32_t caps_hi; 1079 } __packed __aligned(4) fw2x_capabilities_t; 1080 1081 typedef struct fw2x_mailbox { /* struct fwHostInterface */ 1082 aq_mailbox_header_t header; 1083 fw2x_msm_statistics_t msm; /* msmStatistics_t msm; */ 1084 1085 uint32_t phy_info1; 1086 #define PHYINFO1_FAULT_CODE __BITS(31,16) 1087 #define PHYINFO1_PHY_H_BIT __BITS(0,15) 1088 uint32_t phy_info2; 1089 #define PHYINFO2_TEMPERATURE __BITS(15,0) 1090 #define PHYINFO2_CABLE_LEN __BITS(23,16) 1091 1092 fw2x_phy_cable_diag_data_t diag_data; 1093 uint32_t reserved[8]; 1094 1095 fw2x_capabilities_t caps; 1096 1097 /* ... */ 1098 } __packed __aligned(4) fw2x_mailbox_t; 1099 1100 typedef enum aq_link_speed { 1101 AQ_LINK_NONE = 0, 1102 AQ_LINK_10G = __BIT(0), 1103 AQ_LINK_5G = __BIT(1), 1104 AQ_LINK_2G5 = __BIT(2), 1105 AQ_LINK_1G = __BIT(3), 1106 AQ_LINK_100M = __BIT(4), 1107 AQ_LINK_10M = __BIT(5) 1108 } aq_link_speed_t; 1109 #define AQ_LINK_ALL (AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | \ 1110 AQ_LINK_5G | AQ_LINK_10G ) 1111 #define AQ_LINK_AUTO __BITS(31, 0) 1112 1113 typedef enum aq_link_fc { 1114 AQ_FC_NONE = 0, 1115 AQ_FC_RX = __BIT(0), 1116 AQ_FC_TX = __BIT(1), 1117 AQ_FC_ALL = (AQ_FC_RX | AQ_FC_TX) 1118 } aq_link_fc_t; 1119 1120 typedef enum aq_link_eee { 1121 AQ_EEE_DISABLE = 0, 1122 AQ_EEE_ENABLE = 1 1123 } aq_link_eee_t; 1124 1125 typedef enum aq_hw_fw_mpi_state { 1126 MPI_DEINIT = 0, 1127 MPI_RESET = 1, 1128 MPI_INIT = 2, 1129 MPI_POWER = 4 1130 } aq_hw_fw_mpi_state_t; 1131 1132 enum aq_media_type { 1133 AQ_MEDIA_TYPE_UNKNOWN = 0, 1134 AQ_MEDIA_TYPE_FIBRE, 1135 AQ_MEDIA_TYPE_TP 1136 }; 1137 1138 struct aq_rx_desc_read { 1139 uint64_t buf_addr; 1140 uint64_t hdr_addr; 1141 } __packed __aligned(8); 1142 1143 struct aq_rx_desc_wb { 1144 uint32_t type; 1145 #define RXDESC_TYPE_RSSTYPE __BITS(3,0) 1146 #define RXDESC_TYPE_RSSTYPE_NONE 0 1147 #define RXDESC_TYPE_RSSTYPE_IPV4 2 1148 #define RXDESC_TYPE_RSSTYPE_IPV6 3 1149 #define RXDESC_TYPE_RSSTYPE_IPV4_TCP 4 1150 #define RXDESC_TYPE_RSSTYPE_IPV6_TCP 5 1151 #define RXDESC_TYPE_RSSTYPE_IPV4_UDP 6 1152 #define RXDESC_TYPE_RSSTYPE_IPV6_UDP 7 1153 #define RXDESC_TYPE_PKTTYPE_ETHER __BITS(5,4) 1154 #define RXDESC_TYPE_PKTTYPE_ETHER_IPV4 0 1155 #define RXDESC_TYPE_PKTTYPE_ETHER_IPV6 1 1156 #define RXDESC_TYPE_PKTTYPE_ETHER_OTHERS 2 1157 #define RXDESC_TYPE_PKTTYPE_ETHER_ARP 3 1158 #define RXDESC_TYPE_PKTTYPE_PROTO __BITS(8,6) 1159 #define RXDESC_TYPE_PKTTYPE_PROTO_TCP 0 1160 #define RXDESC_TYPE_PKTTYPE_PROTO_UDP 1 1161 #define RXDESC_TYPE_PKTTYPE_PROTO_SCTP 2 1162 #define RXDESC_TYPE_PKTTYPE_PROTO_ICMP 3 1163 #define RXDESC_TYPE_PKTTYPE_PROTO_OTHERS 4 1164 #define RXDESC_TYPE_PKTTYPE_VLAN __BIT(9) 1165 #define RXDESC_TYPE_PKTTYPE_VLAN_DOUBLE __BIT(10) 1166 #define RXDESC_TYPE_MAC_DMA_ERR __BIT(12) 1167 #define RXDESC_TYPE_RESERVED __BITS(18,13) 1168 #define RXDESC_TYPE_IPV4_CSUM_CHECKED __BIT(19) /* PKTTYPE_ETHER_IPV4 */ 1169 #define RXDESC_TYPE_TCPUDP_CSUM_CHECKED __BIT(20) 1170 #define RXDESC_TYPE_SPH __BIT(21) 1171 #define RXDESC_TYPE_HDR_LEN __BITS(31,22) 1172 uint32_t rss_hash; 1173 uint16_t status; 1174 #define RXDESC_STATUS_DD __BIT(0) 1175 #define RXDESC_STATUS_EOP __BIT(1) 1176 #define RXDESC_STATUS_MACERR __BIT(2) 1177 #define RXDESC_STATUS_IPV4_CSUM_NG __BIT(3) 1178 #define RXDESC_STATUS_TCPUDP_CSUM_ERROR __BIT(4) 1179 #define RXDESC_STATUS_TCPUDP_CSUM_OK __BIT(5) 1180 1181 #define RXDESC_STATUS_STAT __BITS(2,5) 1182 #define RXDESC_STATUS_ESTAT __BITS(6,11) 1183 #define RXDESC_STATUS_RSC_CNT __BITS(12,15) 1184 uint16_t pkt_len; 1185 uint16_t next_desc_ptr; 1186 uint16_t vlan; 1187 } __packed __aligned(4); 1188 1189 typedef union aq_rx_desc { 1190 struct aq_rx_desc_read read; 1191 struct aq_rx_desc_wb wb; 1192 } __packed __aligned(8) aq_rx_desc_t; 1193 1194 typedef struct aq_tx_desc { 1195 uint64_t buf_addr; 1196 uint32_t ctl1; 1197 #define AQ_TXDESC_CTL1_TYPE_MASK 0x00000003 1198 #define AQ_TXDESC_CTL1_TYPE_TXD 0x00000001 1199 #define AQ_TXDESC_CTL1_TYPE_TXC 0x00000002 1200 #define AQ_TXDESC_CTL1_BLEN __BITS(19,4) /* TXD */ 1201 #define AQ_TXDESC_CTL1_DD __BIT(20) /* TXD */ 1202 #define AQ_TXDESC_CTL1_EOP __BIT(21) /* TXD */ 1203 #define AQ_TXDESC_CTL1_CMD_VLAN __BIT(22) /* TXD */ 1204 #define AQ_TXDESC_CTL1_CMD_FCS __BIT(23) /* TXD */ 1205 #define AQ_TXDESC_CTL1_CMD_IP4CSUM __BIT(24) /* TXD */ 1206 #define AQ_TXDESC_CTL1_CMD_L4CSUM __BIT(25) /* TXD */ 1207 #define AQ_TXDESC_CTL1_CMD_LSO __BIT(26) /* TXD */ 1208 #define AQ_TXDESC_CTL1_CMD_WB __BIT(27) /* TXD */ 1209 #define AQ_TXDESC_CTL1_CMD_VXLAN __BIT(28) /* TXD */ 1210 #define AQ_TXDESC_CTL1_VID __BITS(15,4) /* TXC */ 1211 #define AQ_TXDESC_CTL1_LSO_IPV6 __BIT(21) /* TXC */ 1212 #define AQ_TXDESC_CTL1_LSO_TCP __BIT(22) /* TXC */ 1213 uint32_t ctl2; 1214 #define AQ_TXDESC_CTL2_LEN __BITS(31,14) 1215 #define AQ_TXDESC_CTL2_CTX_EN __BIT(13) 1216 #define AQ_TXDESC_CTL2_CTX_IDX __BIT(12) 1217 } __packed __aligned(8) aq_tx_desc_t; 1218 1219 struct aq_txring { 1220 struct aq_softc *txr_sc; 1221 int txr_index; 1222 kmutex_t txr_mutex; 1223 bool txr_active; 1224 bool txr_stopping; 1225 bool txr_sending; 1226 time_t txr_lastsent; 1227 1228 pcq_t *txr_pcq; 1229 void *txr_softint; 1230 1231 aq_tx_desc_t *txr_txdesc; /* aq_tx_desc_t[AQ_TXD_NUM] */ 1232 bus_dmamap_t txr_txdesc_dmamap; 1233 bus_dma_segment_t txr_txdesc_seg[1]; 1234 bus_size_t txr_txdesc_size; 1235 1236 struct { 1237 struct mbuf *m; 1238 bus_dmamap_t dmamap; 1239 } txr_mbufs[AQ_TXD_NUM]; 1240 unsigned int txr_prodidx; 1241 unsigned int txr_considx; 1242 int txr_nfree; 1243 }; 1244 1245 struct aq_rxring { 1246 struct aq_softc *rxr_sc; 1247 int rxr_index; 1248 kmutex_t rxr_mutex; 1249 bool rxr_active; 1250 bool rxr_discarding; 1251 bool rxr_stopping; 1252 struct mbuf *rxr_receiving_m; /* receiving jumboframe */ 1253 struct mbuf *rxr_receiving_m_last; /* last mbuf of jumboframe */ 1254 1255 aq_rx_desc_t *rxr_rxdesc; /* aq_rx_desc_t[AQ_RXD_NUM] */ 1256 bus_dmamap_t rxr_rxdesc_dmamap; 1257 bus_dma_segment_t rxr_rxdesc_seg[1]; 1258 bus_size_t rxr_rxdesc_size; 1259 struct { 1260 struct mbuf *m; 1261 bus_dmamap_t dmamap; 1262 } rxr_mbufs[AQ_RXD_NUM]; 1263 unsigned int rxr_readidx; 1264 }; 1265 1266 struct aq_queue { 1267 struct aq_softc *sc; 1268 struct aq_txring txring; 1269 struct aq_rxring rxring; 1270 }; 1271 1272 struct aq_softc; 1273 struct aq_firmware_ops { 1274 int (*reset)(struct aq_softc *); 1275 int (*get_mac_addr)(struct aq_softc *); 1276 int (*set_mode)(struct aq_softc *, aq_hw_fw_mpi_state_t, 1277 aq_link_speed_t, aq_link_fc_t, aq_link_eee_t); 1278 int (*get_mode)(struct aq_softc *, aq_hw_fw_mpi_state_t *, 1279 aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *); 1280 int (*get_stats)(struct aq_softc *, aq_hw_stats_s_t *); 1281 #if NSYSMON_ENVSYS > 0 1282 int (*get_temperature)(struct aq_softc *, uint32_t *); 1283 #endif 1284 }; 1285 1286 #ifdef AQ_EVENT_COUNTERS 1287 #define AQ_EVCNT_DECL(name) \ 1288 char sc_evcount_##name##_name[32]; \ 1289 struct evcnt sc_evcount_##name##_ev; 1290 #define AQ_EVCNT_ATTACH(sc, name, desc, evtype) \ 1291 do { \ 1292 snprintf((sc)->sc_evcount_##name##_name, \ 1293 sizeof((sc)->sc_evcount_##name##_name), \ 1294 "%s", desc); \ 1295 evcnt_attach_dynamic(&(sc)->sc_evcount_##name##_ev, \ 1296 (evtype), NULL, device_xname((sc)->sc_dev), \ 1297 (sc)->sc_evcount_##name##_name); \ 1298 } while (/*CONSTCOND*/0) 1299 #define AQ_EVCNT_ATTACH_MISC(sc, name, desc) \ 1300 AQ_EVCNT_ATTACH(sc, name, desc, EVCNT_TYPE_MISC) 1301 #define AQ_EVCNT_DETACH(sc, name) \ 1302 if ((sc)->sc_evcount_##name##_name[0] != '\0') \ 1303 evcnt_detach(&(sc)->sc_evcount_##name##_ev) 1304 #define AQ_EVCNT_ADD(sc, name, val) \ 1305 ((sc)->sc_evcount_##name##_ev.ev_count += (val)) 1306 #endif /* AQ_EVENT_COUNTERS */ 1307 1308 #define AQ_LOCK(sc) mutex_enter(&(sc)->sc_mutex); 1309 #define AQ_UNLOCK(sc) mutex_exit(&(sc)->sc_mutex); 1310 #define AQ_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_mutex)); 1311 1312 /* lock for firmware interface */ 1313 #define AQ_MPI_LOCK(sc) mutex_enter(&(sc)->sc_mpi_mutex); 1314 #define AQ_MPI_UNLOCK(sc) mutex_exit(&(sc)->sc_mpi_mutex); 1315 #define AQ_MPI_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_mpi_mutex)); 1316 1317 1318 struct aq_softc { 1319 device_t sc_dev; 1320 1321 bus_space_tag_t sc_iot; 1322 bus_space_handle_t sc_ioh; 1323 bus_size_t sc_iosize; 1324 bus_dma_tag_t sc_dmat; 1325 1326 void *sc_ihs[AQ_NINTR_MAX]; 1327 pci_intr_handle_t *sc_intrs; 1328 1329 int sc_tx_irq[AQ_RSSQUEUE_MAX]; 1330 int sc_rx_irq[AQ_RSSQUEUE_MAX]; 1331 int sc_linkstat_irq; 1332 bool sc_use_txrx_independent_intr; 1333 bool sc_poll_linkstat; 1334 bool sc_detect_linkstat; 1335 1336 #if NSYSMON_ENVSYS > 0 1337 struct sysmon_envsys *sc_sme; 1338 envsys_data_t sc_sensor_temp; 1339 #endif 1340 1341 callout_t sc_tick_ch; 1342 1343 int sc_nintrs; 1344 bool sc_msix; 1345 1346 struct aq_queue sc_queue[AQ_RSSQUEUE_MAX]; 1347 int sc_nqueues; 1348 uint32_t sc_tc_mode; /* traffic class mode (4 or 8) */ 1349 uint32_t sc_tcs; /* traffic class num */ 1350 1351 pci_chipset_tag_t sc_pc; 1352 pcitag_t sc_pcitag; 1353 uint16_t sc_product; 1354 uint16_t sc_revision; 1355 1356 kmutex_t sc_mutex; 1357 kmutex_t sc_mpi_mutex; 1358 1359 const struct aq_firmware_ops *sc_fw_ops; 1360 uint64_t sc_fw_caps; /* AQ1 */ 1361 aq2_filter_caps_t sc_filter_caps; /* AQ2 */ 1362 uint32_t sc_filter_art_base_index; /* AQ2 */ 1363 enum aq_media_type sc_media_type; 1364 aq_link_speed_t sc_available_rates; 1365 1366 aq_link_speed_t sc_link_rate; 1367 aq_link_fc_t sc_link_fc; 1368 aq_link_eee_t sc_link_eee; 1369 1370 uint32_t sc_fw_version; 1371 #define FW_VERSION_MAJOR(sc) (((sc)->sc_fw_version >> 24) & 0xff) 1372 #define FW_VERSION_MINOR(sc) (((sc)->sc_fw_version >> 16) & 0xff) 1373 #define FW_VERSION_BUILD(sc) ((sc)->sc_fw_version & 0xffff) 1374 uint32_t sc_features; 1375 #define FEATURES_MIPS 0x00000001 1376 #define FEATURES_TPO2 0x00000002 1377 #define FEATURES_RPF2 0x00000004 1378 #define FEATURES_MPI_AQ 0x00000008 1379 #define FEATURES_AQ1_REV_A0 0x01000000 1380 #define FEATURES_AQ1_REV_A (FEATURES_AQ1_REV_A0) 1381 #define FEATURES_AQ1_REV_B0 0x02000000 1382 #define FEATURES_AQ1_REV_B1 0x04000000 1383 #define FEATURES_AQ1_REV_B (FEATURES_AQ1_REV_B0 | FEATURES_AQ1_REV_B1) 1384 #define FEATURES_AQ1 (FEATURES_AQ1_REV_A | FEATURES_AQ1_REV_B) 1385 #define FEATURES_AQ2 0x10000000 1386 #define FEATURES_AQ2_IFACE_A0 0x20000000 1387 #define FEATURES_AQ2_IFACE_B0 0x40000000 1388 #define HWTYPE_AQ1_P(sc) (((sc)->sc_features & FEATURES_AQ1) != 0) 1389 #define HWTYPE_AQ2_P(sc) (((sc)->sc_features & FEATURES_AQ2) != 0) 1390 1391 int sc_max_mtu; 1392 uint32_t sc_mbox_addr; 1393 1394 bool sc_rbl_enabled; 1395 bool sc_fast_start_enabled; 1396 bool sc_flash_present; 1397 1398 bool sc_intr_moderation_enable; 1399 bool sc_rss_enable; 1400 1401 struct ethercom sc_ethercom; 1402 struct ether_addr sc_enaddr; 1403 struct ifmedia sc_media; 1404 int sc_ec_capenable; /* last ec_capenable */ 1405 unsigned short sc_if_flags; /* last if_flags */ 1406 1407 bool sc_tx_sending; 1408 bool sc_stopping; 1409 1410 struct workqueue *sc_reset_wq; 1411 struct work sc_reset_work; 1412 volatile unsigned sc_reset_pending; 1413 1414 bool sc_trigger_reset; 1415 1416 #ifdef AQ_EVENT_COUNTERS 1417 aq_hw_stats_s_t sc_statistics[2]; 1418 int sc_statistics_idx; 1419 bool sc_poll_statistics; 1420 1421 AQ_EVCNT_DECL(uprc); 1422 AQ_EVCNT_DECL(mprc); 1423 AQ_EVCNT_DECL(bprc); 1424 AQ_EVCNT_DECL(erpt); 1425 AQ_EVCNT_DECL(uptc); 1426 AQ_EVCNT_DECL(mptc); 1427 AQ_EVCNT_DECL(bptc); 1428 AQ_EVCNT_DECL(erpr); 1429 AQ_EVCNT_DECL(mbtc); 1430 AQ_EVCNT_DECL(bbtc); 1431 AQ_EVCNT_DECL(mbrc); 1432 AQ_EVCNT_DECL(bbrc); 1433 AQ_EVCNT_DECL(ubrc); 1434 AQ_EVCNT_DECL(ubtc); 1435 AQ_EVCNT_DECL(ptc); 1436 AQ_EVCNT_DECL(prc); 1437 AQ_EVCNT_DECL(dpc); 1438 AQ_EVCNT_DECL(cprc); 1439 #endif 1440 }; 1441 1442 static int aq_match(device_t, cfdata_t, void *); 1443 static void aq_attach(device_t, device_t, void *); 1444 static int aq_detach(device_t, int); 1445 1446 static int aq_setup_msix(struct aq_softc *, struct pci_attach_args *, int, 1447 bool, bool); 1448 static int aq_setup_legacy(struct aq_softc *, struct pci_attach_args *, 1449 pci_intr_type_t); 1450 static int aq_establish_msix_intr(struct aq_softc *, bool, bool); 1451 1452 static int aq_ifmedia_change(struct ifnet * const); 1453 static void aq_ifmedia_status(struct ifnet * const, struct ifmediareq *); 1454 static int aq_vlan_cb(struct ethercom *ec, uint16_t vid, bool set); 1455 static int aq_ifflags_cb(struct ethercom *); 1456 static int aq_init(struct ifnet *); 1457 static int aq_init_locked(struct ifnet *); 1458 static void aq_send_common_locked(struct ifnet *, struct aq_softc *, 1459 struct aq_txring *, bool); 1460 static int aq_transmit(struct ifnet *, struct mbuf *); 1461 static void aq_deferred_transmit(void *); 1462 static void aq_start(struct ifnet *); 1463 static void aq_stop(struct ifnet *, int); 1464 static void aq_stop_locked(struct ifnet *, bool); 1465 static int aq_ioctl(struct ifnet *, unsigned long, void *); 1466 1467 static int aq_txrx_rings_alloc(struct aq_softc *); 1468 static void aq_txrx_rings_free(struct aq_softc *); 1469 static int aq_tx_pcq_alloc(struct aq_softc *, struct aq_txring *); 1470 static void aq_tx_pcq_free(struct aq_softc *, struct aq_txring *); 1471 1472 static void aq_initmedia(struct aq_softc *); 1473 static void aq_enable_intr(struct aq_softc *, bool, bool); 1474 1475 static void aq_handle_reset_work(struct work *, void *); 1476 static void aq_unset_stopping_flags(struct aq_softc *); 1477 static void aq_set_stopping_flags(struct aq_softc *); 1478 1479 #if NSYSMON_ENVSYS > 0 1480 static void aq_temp_refresh(struct sysmon_envsys *, envsys_data_t *); 1481 #endif 1482 static void aq_tick(void *); 1483 static int aq_legacy_intr(void *); 1484 static int aq_link_intr(void *); 1485 static int aq_txrx_intr(void *); 1486 static int aq_tx_intr(void *); 1487 static int aq_rx_intr(void *); 1488 1489 static int aq_set_linkmode(struct aq_softc *, aq_link_speed_t, aq_link_fc_t, 1490 aq_link_eee_t); 1491 static int aq_get_linkmode(struct aq_softc *, aq_link_speed_t *, aq_link_fc_t *, 1492 aq_link_eee_t *); 1493 1494 static int aq1_fw_reboot(struct aq_softc *); 1495 static int aq1_fw_version_init(struct aq_softc *); 1496 static int aq_hw_init(struct aq_softc *); 1497 static int aq1_hw_init_ucp(struct aq_softc *); 1498 static int aq_hw_reset(struct aq_softc *); 1499 static int aq1_fw_downld_dwords(struct aq_softc *, uint32_t, uint32_t *, 1500 uint32_t); 1501 static int aq1_get_mac_addr(struct aq_softc *); 1502 static int aq_init_rss(struct aq_softc *); 1503 static int aq_set_capability(struct aq_softc *); 1504 1505 static int fw1x_reset(struct aq_softc *); 1506 static int fw1x_set_mode(struct aq_softc *, aq_hw_fw_mpi_state_t, 1507 aq_link_speed_t, aq_link_fc_t, aq_link_eee_t); 1508 static int fw1x_get_mode(struct aq_softc *, aq_hw_fw_mpi_state_t *, 1509 aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *); 1510 static int fw1x_get_stats(struct aq_softc *, aq_hw_stats_s_t *); 1511 1512 static int fw2x_reset(struct aq_softc *); 1513 static int fw2x_set_mode(struct aq_softc *, aq_hw_fw_mpi_state_t, 1514 aq_link_speed_t, aq_link_fc_t, aq_link_eee_t); 1515 static int fw2x_get_mode(struct aq_softc *, aq_hw_fw_mpi_state_t *, 1516 aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *); 1517 static int fw2x_get_stats(struct aq_softc *, aq_hw_stats_s_t *); 1518 #if NSYSMON_ENVSYS > 0 1519 static int fw2x_get_temperature(struct aq_softc *, uint32_t *); 1520 #endif 1521 1522 #ifndef AQ_WATCHDOG_TIMEOUT 1523 #define AQ_WATCHDOG_TIMEOUT 5 1524 #endif 1525 static int aq_watchdog_timeout = AQ_WATCHDOG_TIMEOUT; 1526 1527 static int aq2_fw_reboot(struct aq_softc *); 1528 static int aq2_fw_reset(struct aq_softc *); 1529 static int aq2_get_mac_addr(struct aq_softc *); 1530 static int aq2_fw_set_mode(struct aq_softc *, aq_hw_fw_mpi_state_t, 1531 aq_link_speed_t, aq_link_fc_t, aq_link_eee_t); 1532 static int aq2_fw_get_mode(struct aq_softc *, aq_hw_fw_mpi_state_t *, 1533 aq_link_speed_t *, aq_link_fc_t *, aq_link_eee_t *); 1534 static int aq2_init_filter(struct aq_softc *); 1535 static int aq2_filter_art_set(struct aq_softc *, uint32_t, uint32_t, uint32_t, 1536 uint32_t); 1537 static int aq2_fw_get_stats(struct aq_softc *, aq_hw_stats_s_t *); 1538 #if NSYSMON_ENVSYS > 0 1539 static int aq2_fw_get_temperature(struct aq_softc *, uint32_t *); 1540 #endif 1541 1542 static const struct aq_firmware_ops aq_fw1x_ops = { 1543 .reset = fw1x_reset, 1544 .get_mac_addr = aq1_get_mac_addr, 1545 .set_mode = fw1x_set_mode, 1546 .get_mode = fw1x_get_mode, 1547 .get_stats = fw1x_get_stats, 1548 #if NSYSMON_ENVSYS > 0 1549 .get_temperature = NULL 1550 #endif 1551 }; 1552 1553 static const struct aq_firmware_ops aq_fw2x_ops = { 1554 .reset = fw2x_reset, 1555 .get_mac_addr = aq1_get_mac_addr, 1556 .set_mode = fw2x_set_mode, 1557 .get_mode = fw2x_get_mode, 1558 .get_stats = fw2x_get_stats, 1559 #if NSYSMON_ENVSYS > 0 1560 .get_temperature = fw2x_get_temperature 1561 #endif 1562 }; 1563 1564 static const struct aq_firmware_ops aq2_fw_ops = { 1565 .reset = aq2_fw_reset, 1566 .get_mac_addr = aq2_get_mac_addr, 1567 .set_mode = aq2_fw_set_mode, 1568 .get_mode = aq2_fw_get_mode, 1569 .get_stats = aq2_fw_get_stats, 1570 #if NSYSMON_ENVSYS > 0 1571 .get_temperature = aq2_fw_get_temperature 1572 #endif 1573 }; 1574 1575 CFATTACH_DECL3_NEW(aq, sizeof(struct aq_softc), 1576 aq_match, aq_attach, aq_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 1577 1578 static const struct aq_product { 1579 pci_vendor_id_t aq_vendor; 1580 pci_product_id_t aq_product; 1581 const char *aq_name; 1582 enum aq_hwtype aq_hwtype; 1583 enum aq_media_type aq_media_type; 1584 aq_link_speed_t aq_available_rates; 1585 } aq_products[] = { 1586 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100, 1587 "Aquantia AQC100 10 Gigabit Network Adapter", HWTYPE_AQ1, 1588 AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL 1589 }, 1590 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107, 1591 "Aquantia AQC107 10 Gigabit Network Adapter", HWTYPE_AQ1, 1592 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL 1593 }, 1594 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108, 1595 "Aquantia AQC108 5 Gigabit Network Adapter", HWTYPE_AQ1, 1596 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1597 }, 1598 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109, 1599 "Aquantia AQC109 2.5 Gigabit Network Adapter", HWTYPE_AQ1, 1600 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1601 }, 1602 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111, 1603 "Aquantia AQC111 5 Gigabit Network Adapter", HWTYPE_AQ1, 1604 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1605 }, 1606 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112, 1607 "Aquantia AQC112 2.5 Gigabit Network Adapter", HWTYPE_AQ1, 1608 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1609 }, 1610 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC100S, 1611 "Aquantia AQC100S 10 Gigabit Network Adapter", HWTYPE_AQ1, 1612 AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL 1613 }, 1614 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC107S, 1615 "Aquantia AQC107S 10 Gigabit Network Adapter", HWTYPE_AQ1, 1616 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL 1617 }, 1618 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC108S, 1619 "Aquantia AQC108S 5 Gigabit Network Adapter", HWTYPE_AQ1, 1620 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1621 }, 1622 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC109S, 1623 "Aquantia AQC109S 2.5 Gigabit Network Adapter", HWTYPE_AQ1, 1624 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1625 }, 1626 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC111S, 1627 "Aquantia AQC111S 5 Gigabit Network Adapter", HWTYPE_AQ1, 1628 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1629 }, 1630 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC112S, 1631 "Aquantia AQC112S 2.5 Gigabit Network Adapter", HWTYPE_AQ1, 1632 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1633 }, 1634 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D100, 1635 "Aquantia D100 10 Gigabit Network Adapter", HWTYPE_AQ1, 1636 AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL 1637 }, 1638 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D107, 1639 "Aquantia D107 10 Gigabit Network Adapter", HWTYPE_AQ1, 1640 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL 1641 }, 1642 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D108, 1643 "Aquantia D108 5 Gigabit Network Adapter", HWTYPE_AQ1, 1644 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1645 }, 1646 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_D109, 1647 "Aquantia D109 2.5 Gigabit Network Adapter", HWTYPE_AQ1, 1648 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1649 }, 1650 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113DEV, 1651 "Aquantia AQC113DEV 10 Gigabit Network Adapter", HWTYPE_AQ2, 1652 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL | AQ_LINK_10M 1653 }, 1654 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113, 1655 "Aquantia AQC113 10 Gigabit Network Adapter", HWTYPE_AQ2, 1656 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL | AQ_LINK_10M 1657 }, 1658 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113C, 1659 "Aquantia AQC113C 10 Gigabit Network Adapter", HWTYPE_AQ2, 1660 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL | AQ_LINK_10M 1661 }, 1662 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113CA, 1663 "Aquantia AQC113CA 10 Gigabit Network Adapter", HWTYPE_AQ2, 1664 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL | AQ_LINK_10M 1665 }, 1666 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC113CS, 1667 "Aquantia AQC113CS 10 Gigabit Network Adapter", HWTYPE_AQ2, 1668 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL | AQ_LINK_10M 1669 }, 1670 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC114CS, 1671 "Aquantia AQC114CS 5 Gigabit Network Adapter", HWTYPE_AQ2, 1672 AQ_MEDIA_TYPE_TP, 1673 AQ_LINK_10M | AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G 1674 }, 1675 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC115C, 1676 "Aquantia AQC115C 2.5 Gigabit Network Adapter", HWTYPE_AQ2, 1677 AQ_MEDIA_TYPE_TP, 1678 AQ_LINK_10M | AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 1679 }, 1680 { PCI_VENDOR_AQUANTIA, PCI_PRODUCT_AQUANTIA_AQC116C, 1681 "Aquantia AQC116C Gigabit Network Adapter", HWTYPE_AQ2, 1682 AQ_MEDIA_TYPE_TP, AQ_LINK_10M | AQ_LINK_100M | AQ_LINK_1G 1683 } 1684 }; 1685 1686 static const struct aq_product * 1687 aq_lookup(const struct pci_attach_args *pa) 1688 { 1689 unsigned int i; 1690 1691 for (i = 0; i < __arraycount(aq_products); i++) { 1692 if (PCI_VENDOR(pa->pa_id) == aq_products[i].aq_vendor && 1693 PCI_PRODUCT(pa->pa_id) == aq_products[i].aq_product) 1694 return &aq_products[i]; 1695 } 1696 return NULL; 1697 } 1698 1699 static int 1700 aq_match(device_t parent, cfdata_t cf, void *aux) 1701 { 1702 struct pci_attach_args * const pa = aux; 1703 1704 if (aq_lookup(pa) != NULL) 1705 return 1; 1706 1707 return 0; 1708 } 1709 1710 static void 1711 aq_attach(device_t parent, device_t self, void *aux) 1712 { 1713 struct aq_softc * const sc = device_private(self); 1714 struct pci_attach_args * const pa = aux; 1715 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 1716 pci_chipset_tag_t pc; 1717 pcitag_t tag; 1718 pcireg_t command, memtype, bar; 1719 const struct aq_product *aqp; 1720 int error; 1721 1722 sc->sc_dev = self; 1723 mutex_init(&sc->sc_mutex, MUTEX_DEFAULT, IPL_NET); 1724 mutex_init(&sc->sc_mpi_mutex, MUTEX_DEFAULT, IPL_NET); 1725 1726 sc->sc_pc = pc = pa->pa_pc; 1727 sc->sc_pcitag = tag = pa->pa_tag; 1728 sc->sc_dmat = pci_dma64_available(pa) ? pa->pa_dmat64 : pa->pa_dmat; 1729 1730 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1731 command |= PCI_COMMAND_MASTER_ENABLE; 1732 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1733 1734 sc->sc_product = PCI_PRODUCT(pa->pa_id); 1735 sc->sc_revision = PCI_REVISION(pa->pa_class); 1736 1737 aqp = aq_lookup(pa); 1738 KASSERT(aqp != NULL); 1739 1740 pci_aprint_devinfo_fancy(pa, "Ethernet controller", aqp->aq_name, 1); 1741 1742 bar = pci_conf_read(pc, tag, PCI_BAR(0)); 1743 if ((PCI_MAPREG_MEM_ADDR(bar) == 0) || 1744 (PCI_MAPREG_TYPE(bar) != PCI_MAPREG_TYPE_MEM)) { 1745 aprint_error_dev(sc->sc_dev, "wrong BAR type\n"); 1746 return; 1747 } 1748 memtype = pci_mapreg_type(pc, tag, PCI_BAR(0)); 1749 if (pci_mapreg_map(pa, PCI_BAR(0), memtype, 0, &sc->sc_iot, &sc->sc_ioh, 1750 NULL, &sc->sc_iosize) != 0) { 1751 aprint_error_dev(sc->sc_dev, "unable to map register\n"); 1752 return; 1753 } 1754 1755 switch (aqp->aq_hwtype) { 1756 case HWTYPE_AQ1: 1757 error = aq1_fw_reboot(sc); 1758 break; 1759 case HWTYPE_AQ2: 1760 error = aq2_fw_reboot(sc); 1761 break; 1762 default: 1763 error = ENOTSUP; 1764 break; 1765 } 1766 if (error != 0) 1767 goto attach_failure; 1768 1769 /* max queue num is 8, and must be 2^n */ 1770 if (ncpu >= 8) 1771 sc->sc_nqueues = 8; 1772 else if (ncpu >= 4) 1773 sc->sc_nqueues = 4; 1774 else if (ncpu >= 2) 1775 sc->sc_nqueues = 2; 1776 else 1777 sc->sc_nqueues = 1; 1778 1779 sc->sc_tc_mode = (sc->sc_nqueues <= 4) ? 8 : 4; 1780 sc->sc_tcs = 1; 1781 1782 int msixcount = pci_msix_count(pa->pa_pc, pa->pa_tag); 1783 #ifndef CONFIG_NO_TXRX_INDEPENDENT 1784 if (msixcount >= (sc->sc_nqueues * 2 + 1)) { 1785 /* TX intrs + RX intrs + LINKSTAT intrs */ 1786 sc->sc_use_txrx_independent_intr = true; 1787 sc->sc_poll_linkstat = false; 1788 sc->sc_msix = true; 1789 } else if (msixcount >= (sc->sc_nqueues * 2)) { 1790 /* TX intrs + RX intrs */ 1791 sc->sc_use_txrx_independent_intr = true; 1792 sc->sc_poll_linkstat = true; 1793 sc->sc_msix = true; 1794 } else 1795 #endif 1796 if (msixcount >= (sc->sc_nqueues + 1)) { 1797 /* TX/RX intrs LINKSTAT intrs */ 1798 sc->sc_use_txrx_independent_intr = false; 1799 sc->sc_poll_linkstat = false; 1800 sc->sc_msix = true; 1801 } else if (msixcount >= sc->sc_nqueues) { 1802 /* TX/RX intrs */ 1803 sc->sc_use_txrx_independent_intr = false; 1804 sc->sc_poll_linkstat = true; 1805 sc->sc_msix = true; 1806 } else { 1807 /* giving up using MSI-X */ 1808 sc->sc_msix = false; 1809 } 1810 1811 /* on AQ1a0, AQ2, or FIBRE, linkstat interrupt doesn't work? */ 1812 if (aqp->aq_media_type == AQ_MEDIA_TYPE_FIBRE || 1813 (HWTYPE_AQ1_P(sc) && FW_VERSION_MAJOR(sc) == 1) || 1814 HWTYPE_AQ2_P(sc)) 1815 sc->sc_poll_linkstat = true; 1816 1817 #ifdef AQ_FORCE_POLL_LINKSTAT 1818 sc->sc_poll_linkstat = true; 1819 #endif 1820 1821 aprint_debug_dev(sc->sc_dev, 1822 "ncpu=%d, pci_msix_count=%d." 1823 " allocate %d interrupts for %d%s queues%s\n", 1824 ncpu, msixcount, 1825 (sc->sc_use_txrx_independent_intr ? 1826 (sc->sc_nqueues * 2) : sc->sc_nqueues) + 1827 (sc->sc_poll_linkstat ? 0 : 1), 1828 sc->sc_nqueues, 1829 sc->sc_use_txrx_independent_intr ? "*2" : "", 1830 sc->sc_poll_linkstat ? "" : ", and link status"); 1831 1832 if (sc->sc_msix) 1833 error = aq_setup_msix(sc, pa, sc->sc_nqueues, 1834 sc->sc_use_txrx_independent_intr, !sc->sc_poll_linkstat); 1835 else 1836 error = ENODEV; 1837 1838 if (error != 0) { 1839 /* if MSI-X failed, fallback to MSI with single queue */ 1840 sc->sc_use_txrx_independent_intr = false; 1841 sc->sc_poll_linkstat = false; 1842 sc->sc_msix = false; 1843 sc->sc_nqueues = 1; 1844 error = aq_setup_legacy(sc, pa, PCI_INTR_TYPE_MSI); 1845 } 1846 if (error != 0) { 1847 /* if MSI failed, fallback to INTx */ 1848 error = aq_setup_legacy(sc, pa, PCI_INTR_TYPE_INTX); 1849 } 1850 if (error != 0) 1851 goto attach_failure; 1852 1853 callout_init(&sc->sc_tick_ch, CALLOUT_MPSAFE); 1854 callout_setfunc(&sc->sc_tick_ch, aq_tick, sc); 1855 1856 char wqname[MAXCOMLEN]; 1857 snprintf(wqname, sizeof(wqname), "%sReset", device_xname(sc->sc_dev)); 1858 error = workqueue_create(&sc->sc_reset_wq, wqname, 1859 aq_handle_reset_work, sc, PRI_SOFTNET, IPL_SOFTCLOCK, 1860 WQ_MPSAFE); 1861 if (error) { 1862 aprint_error_dev(sc->sc_dev, 1863 "unable to create reset workqueue\n"); 1864 goto attach_failure; 1865 } 1866 1867 sc->sc_intr_moderation_enable = CONFIG_INTR_MODERATION_ENABLE; 1868 1869 if (sc->sc_msix && (sc->sc_nqueues > 1)) 1870 sc->sc_rss_enable = true; 1871 else 1872 sc->sc_rss_enable = false; 1873 1874 error = aq_txrx_rings_alloc(sc); 1875 if (error != 0) 1876 goto attach_failure; 1877 1878 error = aq_hw_reset(sc); 1879 if (error != 0) 1880 goto attach_failure; 1881 1882 error = sc->sc_fw_ops->get_mac_addr(sc); 1883 if (error != 0) 1884 goto attach_failure; 1885 1886 aq_init_rss(sc); 1887 1888 error = aq_hw_init(sc); /* initialize and interrupts */ 1889 if (error != 0) 1890 goto attach_failure; 1891 1892 sc->sc_media_type = aqp->aq_media_type; 1893 sc->sc_available_rates = aqp->aq_available_rates; 1894 1895 sc->sc_ethercom.ec_ifmedia = &sc->sc_media; 1896 ifmedia_init(&sc->sc_media, IFM_IMASK, 1897 aq_ifmedia_change, aq_ifmedia_status); 1898 aq_initmedia(sc); 1899 1900 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1901 ifp->if_softc = sc; 1902 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1903 ifp->if_extflags = IFEF_MPSAFE; 1904 ifp->if_baudrate = IF_Gbps(10); 1905 ifp->if_init = aq_init; 1906 ifp->if_ioctl = aq_ioctl; 1907 if (sc->sc_msix && (sc->sc_nqueues > 1)) 1908 ifp->if_transmit = aq_transmit; 1909 ifp->if_start = aq_start; 1910 ifp->if_stop = aq_stop; 1911 ifp->if_watchdog = NULL; 1912 IFQ_SET_READY(&ifp->if_snd); 1913 1914 /* initialize capabilities */ 1915 sc->sc_ethercom.ec_capabilities = 0; 1916 sc->sc_ethercom.ec_capenable = 0; 1917 #if notyet 1918 /* TODO */ 1919 sc->sc_ethercom.ec_capabilities |= ETHERCAP_EEE; 1920 #endif 1921 sc->sc_ethercom.ec_capabilities |= 1922 ETHERCAP_JUMBO_MTU | 1923 ETHERCAP_VLAN_MTU | 1924 ETHERCAP_VLAN_HWTAGGING | 1925 ETHERCAP_VLAN_HWFILTER; 1926 sc->sc_ethercom.ec_capenable |= 1927 ETHERCAP_VLAN_HWTAGGING | 1928 ETHERCAP_VLAN_HWFILTER; 1929 1930 ifp->if_capabilities = 0; 1931 ifp->if_capenable = 0; 1932 #ifdef CONFIG_LRO_SUPPORT 1933 ifp->if_capabilities |= IFCAP_LRO; 1934 ifp->if_capenable |= IFCAP_LRO; 1935 #endif 1936 #if notyet 1937 /* TSO */ 1938 ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6; 1939 #endif 1940 1941 /* TX hardware checksum offloading */ 1942 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx; 1943 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv6_Tx; 1944 ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv6_Tx; 1945 /* RX hardware checksum offloading */ 1946 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx; 1947 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_TCPv6_Rx; 1948 ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Rx | IFCAP_CSUM_UDPv6_Rx; 1949 1950 if_initialize(ifp); 1951 ifp->if_percpuq = if_percpuq_create(ifp); 1952 if_deferred_start_init(ifp, NULL); 1953 ether_ifattach(ifp, sc->sc_enaddr.ether_addr_octet); 1954 ether_set_vlan_cb(&sc->sc_ethercom, aq_vlan_cb); 1955 ether_set_ifflags_cb(&sc->sc_ethercom, aq_ifflags_cb); 1956 if_register(ifp); 1957 1958 /* only intr about link */ 1959 aq_enable_intr(sc, /*link*/true, /*txrx*/false); 1960 1961 /* update media */ 1962 aq_ifmedia_change(ifp); 1963 1964 #if NSYSMON_ENVSYS > 0 1965 /* temperature monitoring */ 1966 if (sc->sc_fw_ops != NULL && sc->sc_fw_ops->get_temperature != NULL && 1967 (((sc->sc_fw_caps & FW2X_CTRL_TEMPERATURE) != 0) || 1968 HWTYPE_AQ2_P(sc))) { 1969 sc->sc_sme = sysmon_envsys_create(); 1970 sc->sc_sme->sme_name = device_xname(self); 1971 sc->sc_sme->sme_cookie = sc; 1972 sc->sc_sme->sme_flags = 0; 1973 sc->sc_sme->sme_refresh = aq_temp_refresh; 1974 sc->sc_sensor_temp.units = ENVSYS_STEMP; 1975 sc->sc_sensor_temp.state = ENVSYS_SINVALID; 1976 snprintf(sc->sc_sensor_temp.desc, ENVSYS_DESCLEN, "PHY"); 1977 1978 sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor_temp); 1979 if (sysmon_envsys_register(sc->sc_sme)) { 1980 sysmon_envsys_destroy(sc->sc_sme); 1981 sc->sc_sme = NULL; 1982 goto attach_failure; 1983 } 1984 1985 /* 1986 * for unknown reasons, the first call of fw2x_get_temperature() 1987 * will always fail (firmware matter?), so run once now. 1988 */ 1989 aq_temp_refresh(sc->sc_sme, &sc->sc_sensor_temp); 1990 } 1991 #endif 1992 1993 #ifdef AQ_EVENT_COUNTERS 1994 /* get starting statistics values */ 1995 if (sc->sc_fw_ops != NULL && sc->sc_fw_ops->get_stats != NULL && 1996 sc->sc_fw_ops->get_stats(sc, &sc->sc_statistics[0]) == 0) { 1997 sc->sc_poll_statistics = true; 1998 } 1999 2000 AQ_EVCNT_ATTACH_MISC(sc, uprc, "RX unicast packet"); 2001 AQ_EVCNT_ATTACH_MISC(sc, bprc, "RX broadcast packet"); 2002 AQ_EVCNT_ATTACH_MISC(sc, mprc, "RX multicast packet"); 2003 AQ_EVCNT_ATTACH_MISC(sc, erpr, "RX error packet"); 2004 AQ_EVCNT_ATTACH_MISC(sc, ubrc, "RX unicast bytes"); 2005 AQ_EVCNT_ATTACH_MISC(sc, bbrc, "RX broadcast bytes"); 2006 AQ_EVCNT_ATTACH_MISC(sc, mbrc, "RX multicast bytes"); 2007 AQ_EVCNT_ATTACH_MISC(sc, prc, "RX good packet"); 2008 AQ_EVCNT_ATTACH_MISC(sc, uptc, "TX unicast packet"); 2009 AQ_EVCNT_ATTACH_MISC(sc, bptc, "TX broadcast packet"); 2010 AQ_EVCNT_ATTACH_MISC(sc, mptc, "TX multicast packet"); 2011 AQ_EVCNT_ATTACH_MISC(sc, erpt, "TX error packet"); 2012 AQ_EVCNT_ATTACH_MISC(sc, ubtc, "TX unicast bytes"); 2013 AQ_EVCNT_ATTACH_MISC(sc, bbtc, "TX broadcast bytes"); 2014 AQ_EVCNT_ATTACH_MISC(sc, mbtc, "TX multicast bytes"); 2015 AQ_EVCNT_ATTACH_MISC(sc, ptc, "TX good packet"); 2016 AQ_EVCNT_ATTACH_MISC(sc, dpc, "DMA drop packet"); 2017 AQ_EVCNT_ATTACH_MISC(sc, cprc, "RX coalesced packet"); 2018 #endif 2019 2020 if (pmf_device_register(self, NULL, NULL)) 2021 pmf_class_network_register(self, ifp); 2022 else 2023 aprint_error_dev(self, "couldn't establish power handler\n"); 2024 2025 return; 2026 2027 attach_failure: 2028 aq_detach(self, 0); 2029 } 2030 2031 static int 2032 aq_detach(device_t self, int flags __unused) 2033 { 2034 struct aq_softc * const sc = device_private(self); 2035 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 2036 int i; 2037 2038 if (sc->sc_dev == NULL) 2039 return 0; 2040 2041 if (sc->sc_iosize != 0) { 2042 if (ifp->if_softc != NULL) { 2043 IFNET_LOCK(ifp); 2044 aq_stop(ifp, 1); 2045 IFNET_UNLOCK(ifp); 2046 } 2047 2048 for (i = 0; i < AQ_NINTR_MAX; i++) { 2049 if (sc->sc_ihs[i] != NULL) { 2050 pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]); 2051 sc->sc_ihs[i] = NULL; 2052 } 2053 } 2054 if (sc->sc_nintrs > 0) { 2055 callout_stop(&sc->sc_tick_ch); 2056 2057 pci_intr_release(sc->sc_pc, sc->sc_intrs, 2058 sc->sc_nintrs); 2059 sc->sc_intrs = NULL; 2060 sc->sc_nintrs = 0; 2061 } 2062 2063 if (sc->sc_reset_wq != NULL) { 2064 workqueue_destroy(sc->sc_reset_wq); 2065 sc->sc_reset_wq = NULL; 2066 } 2067 2068 aq_txrx_rings_free(sc); 2069 2070 if (ifp->if_softc != NULL) { 2071 ether_ifdetach(ifp); 2072 if_detach(ifp); 2073 } 2074 2075 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize); 2076 sc->sc_iosize = 0; 2077 } 2078 2079 #if NSYSMON_ENVSYS > 0 2080 if (sc->sc_sme != NULL) { 2081 /* all sensors associated with this will also be detached */ 2082 sysmon_envsys_unregister(sc->sc_sme); 2083 } 2084 #endif 2085 2086 #ifdef AQ_EVENT_COUNTERS 2087 AQ_EVCNT_DETACH(sc, uprc); 2088 AQ_EVCNT_DETACH(sc, mprc); 2089 AQ_EVCNT_DETACH(sc, bprc); 2090 AQ_EVCNT_DETACH(sc, erpt); 2091 AQ_EVCNT_DETACH(sc, uptc); 2092 AQ_EVCNT_DETACH(sc, mptc); 2093 AQ_EVCNT_DETACH(sc, bptc); 2094 AQ_EVCNT_DETACH(sc, erpr); 2095 AQ_EVCNT_DETACH(sc, mbtc); 2096 AQ_EVCNT_DETACH(sc, bbtc); 2097 AQ_EVCNT_DETACH(sc, mbrc); 2098 AQ_EVCNT_DETACH(sc, bbrc); 2099 AQ_EVCNT_DETACH(sc, ubrc); 2100 AQ_EVCNT_DETACH(sc, ubtc); 2101 AQ_EVCNT_DETACH(sc, ptc); 2102 AQ_EVCNT_DETACH(sc, prc); 2103 AQ_EVCNT_DETACH(sc, dpc); 2104 AQ_EVCNT_DETACH(sc, cprc); 2105 #endif 2106 2107 if (sc->sc_ethercom.ec_ifmedia != NULL) { 2108 ifmedia_fini(&sc->sc_media); 2109 sc->sc_ethercom.ec_ifmedia = NULL; 2110 } 2111 2112 mutex_destroy(&sc->sc_mpi_mutex); 2113 mutex_destroy(&sc->sc_mutex); 2114 sc->sc_dev = NULL; 2115 2116 return 0; 2117 } 2118 2119 static int 2120 aq_establish_intr(struct aq_softc *sc, int intno, kcpuset_t *affinity, 2121 int (*func)(void *), void *arg, const char *xname) 2122 { 2123 char intrbuf[PCI_INTRSTR_LEN]; 2124 pci_chipset_tag_t pc = sc->sc_pc; 2125 void *vih; 2126 const char *intrstr = NULL; 2127 2128 intrstr = pci_intr_string(pc, sc->sc_intrs[intno], intrbuf, 2129 sizeof(intrbuf)); 2130 2131 pci_intr_setattr(pc, &sc->sc_intrs[intno], PCI_INTR_MPSAFE, true); 2132 2133 vih = pci_intr_establish_xname(pc, sc->sc_intrs[intno], 2134 IPL_NET, func, arg, xname); 2135 if (vih == NULL) { 2136 aprint_error_dev(sc->sc_dev, 2137 "unable to establish MSI-X%s%s for %s\n", 2138 intrstr ? " at " : "", 2139 intrstr ? intrstr : "", xname); 2140 return EIO; 2141 } 2142 sc->sc_ihs[intno] = vih; 2143 2144 if (affinity != NULL) { 2145 /* Round-robin affinity */ 2146 kcpuset_zero(affinity); 2147 kcpuset_set(affinity, intno % ncpu); 2148 interrupt_distribute(vih, affinity, NULL); 2149 } 2150 2151 return 0; 2152 } 2153 2154 static int 2155 aq_establish_msix_intr(struct aq_softc *sc, bool txrx_independent, 2156 bool linkintr) 2157 { 2158 kcpuset_t *affinity; 2159 int error, intno, i; 2160 char intr_xname[INTRDEVNAMEBUF]; 2161 2162 kcpuset_create(&affinity, false); 2163 2164 intno = 0; 2165 2166 if (txrx_independent) { 2167 for (i = 0; i < sc->sc_nqueues; i++) { 2168 snprintf(intr_xname, sizeof(intr_xname), "%s RX%d", 2169 device_xname(sc->sc_dev), i); 2170 sc->sc_rx_irq[i] = intno; 2171 error = aq_establish_intr(sc, intno++, affinity, 2172 aq_rx_intr, &sc->sc_queue[i].rxring, intr_xname); 2173 if (error != 0) 2174 goto fail; 2175 } 2176 for (i = 0; i < sc->sc_nqueues; i++) { 2177 snprintf(intr_xname, sizeof(intr_xname), "%s TX%d", 2178 device_xname(sc->sc_dev), i); 2179 sc->sc_tx_irq[i] = intno; 2180 error = aq_establish_intr(sc, intno++, affinity, 2181 aq_tx_intr, &sc->sc_queue[i].txring, intr_xname); 2182 if (error != 0) 2183 goto fail; 2184 } 2185 } else { 2186 for (i = 0; i < sc->sc_nqueues; i++) { 2187 snprintf(intr_xname, sizeof(intr_xname), "%s TXRX%d", 2188 device_xname(sc->sc_dev), i); 2189 sc->sc_rx_irq[i] = intno; 2190 sc->sc_tx_irq[i] = intno; 2191 error = aq_establish_intr(sc, intno++, affinity, 2192 aq_txrx_intr, &sc->sc_queue[i], intr_xname); 2193 if (error != 0) 2194 goto fail; 2195 } 2196 } 2197 2198 if (linkintr) { 2199 snprintf(intr_xname, sizeof(intr_xname), "%s LINK", 2200 device_xname(sc->sc_dev)); 2201 sc->sc_linkstat_irq = intno; 2202 error = aq_establish_intr(sc, intno++, affinity, 2203 aq_link_intr, sc, intr_xname); 2204 if (error != 0) 2205 goto fail; 2206 } 2207 2208 kcpuset_destroy(affinity); 2209 return 0; 2210 2211 fail: 2212 for (i = 0; i < AQ_NINTR_MAX; i++) { 2213 if (sc->sc_ihs[i] != NULL) { 2214 pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[i]); 2215 sc->sc_ihs[i] = NULL; 2216 } 2217 } 2218 2219 kcpuset_destroy(affinity); 2220 return ENOMEM; 2221 } 2222 2223 static int 2224 aq_setup_msix(struct aq_softc *sc, struct pci_attach_args *pa, int nqueue, 2225 bool txrx_independent, bool linkintr) 2226 { 2227 int error, nintr; 2228 2229 if (txrx_independent) 2230 nintr = nqueue * 2; 2231 else 2232 nintr = nqueue; 2233 2234 if (linkintr) 2235 nintr++; 2236 2237 error = pci_msix_alloc_exact(pa, &sc->sc_intrs, nintr); 2238 if (error != 0) { 2239 aprint_error_dev(sc->sc_dev, 2240 "failed to allocate MSI-X interrupts\n"); 2241 goto fail; 2242 } 2243 2244 error = aq_establish_msix_intr(sc, txrx_independent, linkintr); 2245 if (error == 0) { 2246 sc->sc_nintrs = nintr; 2247 } else { 2248 pci_intr_release(sc->sc_pc, sc->sc_intrs, nintr); 2249 sc->sc_nintrs = 0; 2250 } 2251 fail: 2252 return error; 2253 2254 } 2255 2256 static int 2257 aq_setup_legacy(struct aq_softc *sc, struct pci_attach_args *pa, 2258 pci_intr_type_t inttype) 2259 { 2260 int counts[PCI_INTR_TYPE_SIZE]; 2261 int error, nintr; 2262 2263 nintr = 1; 2264 2265 memset(counts, 0, sizeof(counts)); 2266 counts[inttype] = nintr; 2267 2268 error = pci_intr_alloc(pa, &sc->sc_intrs, counts, inttype); 2269 if (error != 0) { 2270 aprint_error_dev(sc->sc_dev, 2271 "failed to allocate%s interrupts\n", 2272 (inttype == PCI_INTR_TYPE_MSI) ? " MSI" : ""); 2273 return error; 2274 } 2275 error = aq_establish_intr(sc, 0, NULL, aq_legacy_intr, sc, 2276 device_xname(sc->sc_dev)); 2277 if (error == 0) { 2278 sc->sc_nintrs = nintr; 2279 } else { 2280 pci_intr_release(sc->sc_pc, sc->sc_intrs, nintr); 2281 sc->sc_nintrs = 0; 2282 } 2283 return error; 2284 } 2285 2286 static void 2287 aq1_global_software_reset(struct aq_softc *sc) 2288 { 2289 uint32_t v; 2290 2291 AQ_WRITE_REG_BIT(sc, RX_SYSCONTROL_REG, RX_SYSCONTROL_RESET_DIS, 0); 2292 AQ_WRITE_REG_BIT(sc, TX_SYSCONTROL_REG, TX_SYSCONTROL_RESET_DIS, 0); 2293 AQ_WRITE_REG_BIT(sc, FW_MPI_RESETCTRL_REG, 2294 FW_MPI_RESETCTRL_RESET_DIS, 0); 2295 2296 v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG); 2297 v &= ~AQ_FW_SOFTRESET_DIS; 2298 v |= AQ_FW_SOFTRESET_RESET; 2299 AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v); 2300 } 2301 2302 static int 2303 aq1_mac_soft_reset_rbl(struct aq_softc *sc, aq_fw_bootloader_mode_t *mode) 2304 { 2305 int timo; 2306 2307 aprint_debug_dev(sc->sc_dev, "RBL> MAC reset STARTED!\n"); 2308 2309 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1); 2310 AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1); 2311 AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0); 2312 2313 /* MAC FW will reload PHY FW if 1E.1000.3 was cleaned - #undone */ 2314 AQ_WRITE_REG(sc, FW_BOOT_EXIT_CODE_REG, RBL_STATUS_DEAD); 2315 2316 aq1_global_software_reset(sc); 2317 2318 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e0); 2319 2320 /* Wait for RBL to finish boot process. */ 2321 #define RBL_TIMEOUT_MS 10000 2322 uint16_t rbl_status; 2323 for (timo = RBL_TIMEOUT_MS; timo > 0; timo--) { 2324 rbl_status = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG) & 0xffff; 2325 if (rbl_status != 0 && rbl_status != RBL_STATUS_DEAD) 2326 break; 2327 msec_delay(1); 2328 } 2329 if (timo <= 0) { 2330 aprint_error_dev(sc->sc_dev, 2331 "RBL> RBL restart failed: timeout\n"); 2332 return EBUSY; 2333 } 2334 switch (rbl_status) { 2335 case RBL_STATUS_SUCCESS: 2336 if (mode != NULL) 2337 *mode = FW_BOOT_MODE_RBL_FLASH; 2338 aprint_debug_dev(sc->sc_dev, "RBL> reset complete! [Flash]\n"); 2339 break; 2340 case RBL_STATUS_HOST_BOOT: 2341 if (mode != NULL) 2342 *mode = FW_BOOT_MODE_RBL_HOST_BOOTLOAD; 2343 aprint_debug_dev(sc->sc_dev, 2344 "RBL> reset complete! [Host Bootload]\n"); 2345 break; 2346 case RBL_STATUS_FAILURE: 2347 default: 2348 aprint_error_dev(sc->sc_dev, 2349 "unknown RBL status 0x%x\n", rbl_status); 2350 return EBUSY; 2351 } 2352 2353 return 0; 2354 } 2355 2356 static int 2357 aq1_mac_soft_reset_flb(struct aq_softc *sc) 2358 { 2359 uint32_t v; 2360 int timo; 2361 2362 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1); 2363 /* 2364 * Let Felicity hardware to complete SMBUS transaction before 2365 * Global software reset. 2366 */ 2367 msec_delay(50); 2368 2369 /* 2370 * If SPI burst transaction was interrupted(before running the script), 2371 * global software reset may not clear SPI interface. 2372 * Clean it up manually before global reset. 2373 */ 2374 AQ_WRITE_REG(sc, AQ_GLB_NVR_PROVISIONING2_REG, 0x00a0); 2375 AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x009f); 2376 AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x809f); 2377 msec_delay(50); 2378 2379 v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG); 2380 v &= ~AQ_FW_SOFTRESET_DIS; 2381 v |= AQ_FW_SOFTRESET_RESET; 2382 AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v); 2383 2384 /* Kickstart. */ 2385 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0); 2386 AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0); 2387 if (!sc->sc_fast_start_enabled) 2388 AQ_WRITE_REG(sc, AQ_GLB_GENERAL_PROVISIONING9_REG, 1); 2389 2390 /* 2391 * For the case SPI burst transaction was interrupted (by MCP reset 2392 * above), wait until it is completed by hardware. 2393 */ 2394 msec_delay(50); 2395 2396 /* MAC Kickstart */ 2397 if (!sc->sc_fast_start_enabled) { 2398 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x180e0); 2399 2400 uint32_t flb_status; 2401 for (timo = 0; timo < 1000; timo++) { 2402 flb_status = AQ_READ_REG(sc, 2403 FW_MPI_DAISY_CHAIN_STATUS_REG) & 0x10; 2404 if (flb_status != 0) 2405 break; 2406 msec_delay(1); 2407 } 2408 if (flb_status == 0) { 2409 aprint_error_dev(sc->sc_dev, 2410 "FLB> MAC kickstart failed: timed out\n"); 2411 return ETIMEDOUT; 2412 } 2413 aprint_debug_dev(sc->sc_dev, 2414 "FLB> MAC kickstart done, %d ms\n", timo); 2415 /* FW reset */ 2416 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0); 2417 /* 2418 * Let Felicity hardware complete SMBUS transaction before 2419 * Global software reset. 2420 */ 2421 msec_delay(50); 2422 sc->sc_fast_start_enabled = true; 2423 } 2424 AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1); 2425 2426 /* PHY Kickstart: #undone */ 2427 aq1_global_software_reset(sc); 2428 2429 for (timo = 0; timo < 1000; timo++) { 2430 if (AQ_READ_REG(sc, AQ_FW_VERSION_REG) != 0) 2431 break; 2432 msec_delay(10); 2433 } 2434 if (timo >= 1000) { 2435 aprint_error_dev(sc->sc_dev, "FLB> Global Soft Reset failed\n"); 2436 return ETIMEDOUT; 2437 } 2438 aprint_debug_dev(sc->sc_dev, "FLB> F/W restart: %d ms\n", timo * 10); 2439 return 0; 2440 2441 } 2442 2443 static int 2444 aq1_mac_soft_reset(struct aq_softc *sc, aq_fw_bootloader_mode_t *mode) 2445 { 2446 if (sc->sc_rbl_enabled) 2447 return aq1_mac_soft_reset_rbl(sc, mode); 2448 2449 if (mode != NULL) 2450 *mode = FW_BOOT_MODE_FLB; 2451 return aq1_mac_soft_reset_flb(sc); 2452 } 2453 2454 static int 2455 aq1_fw_read_version(struct aq_softc *sc) 2456 { 2457 int i, error = EBUSY; 2458 #define MAC_FW_START_TIMEOUT_MS 10000 2459 for (i = 0; i < MAC_FW_START_TIMEOUT_MS; i++) { 2460 sc->sc_fw_version = AQ_READ_REG(sc, AQ_FW_VERSION_REG); 2461 if (sc->sc_fw_version != 0) { 2462 error = 0; 2463 break; 2464 } 2465 delay(1000); 2466 } 2467 return error; 2468 } 2469 2470 static int 2471 aq1_fw_reboot(struct aq_softc *sc) 2472 { 2473 uint32_t ver, v, bootExitCode; 2474 int i, error; 2475 2476 ver = AQ_READ_REG(sc, AQ_FW_VERSION_REG); 2477 2478 for (i = 1000; i > 0; i--) { 2479 v = AQ_READ_REG(sc, FW_MPI_DAISY_CHAIN_STATUS_REG); 2480 bootExitCode = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG); 2481 if (v != 0x06000000 || bootExitCode != 0) 2482 break; 2483 } 2484 if (i <= 0) { 2485 aprint_error_dev(sc->sc_dev, 2486 "F/W reset failed. Neither RBL nor FLB started\n"); 2487 return ETIMEDOUT; 2488 } 2489 sc->sc_rbl_enabled = (bootExitCode != 0); 2490 2491 /* 2492 * Having FW version 0 is an indicator that cold start 2493 * is in progress. This means two things: 2494 * 1) Driver have to wait for FW/HW to finish boot (500ms giveup) 2495 * 2) Driver may skip reset sequence and save time. 2496 */ 2497 if (sc->sc_fast_start_enabled && (ver != 0)) { 2498 error = aq1_fw_read_version(sc); 2499 /* Skip reset as it just completed */ 2500 if (error == 0) 2501 return 0; 2502 } 2503 2504 aq_fw_bootloader_mode_t mode = FW_BOOT_MODE_UNKNOWN; 2505 error = aq1_mac_soft_reset(sc, &mode); 2506 if (error != 0) { 2507 aprint_error_dev(sc->sc_dev, "MAC reset failed: %d\n", error); 2508 return ENXIO; 2509 } 2510 2511 switch (mode) { 2512 case FW_BOOT_MODE_FLB: 2513 aprint_debug_dev(sc->sc_dev, 2514 "FLB> F/W successfully loaded from flash.\n"); 2515 sc->sc_flash_present = true; 2516 break; 2517 case FW_BOOT_MODE_RBL_FLASH: 2518 aprint_debug_dev(sc->sc_dev, 2519 "RBL> F/W loaded from flash. Host Bootload disabled.\n"); 2520 sc->sc_flash_present = true; 2521 break; 2522 case FW_BOOT_MODE_UNKNOWN: 2523 aprint_error_dev(sc->sc_dev, 2524 "F/W bootload error: unknown bootloader type\n"); 2525 return ENOTSUP; 2526 case FW_BOOT_MODE_RBL_HOST_BOOTLOAD: 2527 aprint_debug_dev(sc->sc_dev, "RBL> Host Bootload mode\n"); 2528 aprint_error_dev(sc->sc_dev, 2529 "RBL> F/W Host Bootload not implemented\n"); 2530 return ENOTSUP; 2531 } 2532 2533 error = aq1_fw_read_version(sc); 2534 if (error != 0) 2535 return error; 2536 2537 error = aq1_fw_version_init(sc); 2538 if (error != 0) 2539 return error; 2540 2541 error = aq1_hw_init_ucp(sc); 2542 if (error < 0) 2543 return error; 2544 2545 KASSERT(sc->sc_mbox_addr != 0); 2546 return 0; 2547 } 2548 2549 static int 2550 aq_hw_reset(struct aq_softc *sc) 2551 { 2552 int error; 2553 2554 /* disable irq */ 2555 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS, 0); 2556 2557 /* apply */ 2558 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_IRQ, 1); 2559 2560 /* wait ack 10 times by 1ms */ 2561 WAIT_FOR( 2562 (AQ_READ_REG(sc, AQ_INTR_CTRL_REG) & AQ_INTR_CTRL_RESET_IRQ) == 0, 2563 1000, 10, &error); 2564 if (error != 0) { 2565 aprint_error_dev(sc->sc_dev, 2566 "atlantic: IRQ reset failed: %d\n", error); 2567 return error; 2568 } 2569 2570 return sc->sc_fw_ops->reset(sc); 2571 } 2572 2573 static int 2574 aq1_hw_init_ucp(struct aq_softc *sc) 2575 { 2576 int timo; 2577 2578 if (FW_VERSION_MAJOR(sc) == 1) { 2579 if (AQ_READ_REG(sc, FW1X_MPI_INIT2_REG) == 0) 2580 AQ_WRITE_REG(sc, FW1X_MPI_INIT2_REG, 0xfefefefe); 2581 AQ_WRITE_REG(sc, FW1X_MPI_INIT1_REG, 0); 2582 } 2583 2584 /* Wait a maximum of 10sec. It usually takes about 5sec. */ 2585 for (timo = 10000; timo > 0; timo--) { 2586 sc->sc_mbox_addr = AQ_READ_REG(sc, FW_MPI_MBOX_ADDR_REG); 2587 if (sc->sc_mbox_addr != 0) 2588 break; 2589 delay(1000); 2590 } 2591 if (sc->sc_mbox_addr == 0) { 2592 aprint_error_dev(sc->sc_dev, "cannot get mbox addr\n"); 2593 return ETIMEDOUT; 2594 } 2595 2596 #define AQ_FW_MIN_VERSION 0x01050006 2597 #define AQ_FW_MIN_VERSION_STR "1.5.6" 2598 if (sc->sc_fw_version < AQ_FW_MIN_VERSION) { 2599 aprint_error_dev(sc->sc_dev, 2600 "atlantic: wrong FW version: " AQ_FW_MIN_VERSION_STR 2601 " or later required, this is %d.%d.%d\n", 2602 FW_VERSION_MAJOR(sc), 2603 FW_VERSION_MINOR(sc), 2604 FW_VERSION_BUILD(sc)); 2605 return ENOTSUP; 2606 } 2607 2608 return 0; 2609 } 2610 2611 static int 2612 aq1_fw_version_init(struct aq_softc *sc) 2613 { 2614 int error = 0; 2615 char fw_vers[sizeof("F/W version xxxxx.xxxxx.xxxxx")]; 2616 2617 if (FW_VERSION_MAJOR(sc) == 1) { 2618 sc->sc_fw_ops = &aq_fw1x_ops; 2619 } else if ((FW_VERSION_MAJOR(sc) == 2) || (FW_VERSION_MAJOR(sc) == 3)) { 2620 sc->sc_fw_ops = &aq_fw2x_ops; 2621 } else { 2622 aprint_error_dev(sc->sc_dev, 2623 "Unsupported F/W version %d.%d.%d\n", 2624 FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), 2625 FW_VERSION_BUILD(sc)); 2626 return ENOTSUP; 2627 } 2628 snprintf(fw_vers, sizeof(fw_vers), "F/W version %d.%d.%d", 2629 FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), FW_VERSION_BUILD(sc)); 2630 2631 /* detect revision */ 2632 uint32_t hwrev = AQ_READ_REG(sc, AQ_HW_REVISION_REG); 2633 switch (hwrev & 0x0000000f) { 2634 case 0x01: 2635 aprint_normal_dev(sc->sc_dev, "Atlantic revision A0, %s\n", 2636 fw_vers); 2637 sc->sc_features |= FEATURES_AQ1_REV_A0 | 2638 FEATURES_MPI_AQ | FEATURES_MIPS; 2639 sc->sc_max_mtu = AQ1_JUMBO_MTU_REV_A; 2640 break; 2641 case 0x02: 2642 aprint_normal_dev(sc->sc_dev, "Atlantic revision B0, %s\n", 2643 fw_vers); 2644 sc->sc_features |= FEATURES_AQ1_REV_B0 | 2645 FEATURES_MPI_AQ | FEATURES_MIPS | 2646 FEATURES_TPO2 | FEATURES_RPF2; 2647 sc->sc_max_mtu = AQ1_JUMBO_MTU_REV_B; 2648 break; 2649 case 0x0A: 2650 aprint_normal_dev(sc->sc_dev, "Atlantic revision B1, %s\n", 2651 fw_vers); 2652 sc->sc_features |= FEATURES_AQ1_REV_B1 | 2653 FEATURES_MPI_AQ | FEATURES_MIPS | 2654 FEATURES_TPO2 | FEATURES_RPF2; 2655 sc->sc_max_mtu = AQ1_JUMBO_MTU_REV_B; 2656 break; 2657 default: 2658 aprint_error_dev(sc->sc_dev, 2659 "Unknown revision (0x%08x)\n", hwrev); 2660 sc->sc_features = 0; 2661 sc->sc_max_mtu = ETHERMTU; 2662 error = ENOTSUP; 2663 break; 2664 } 2665 return error; 2666 } 2667 2668 static int 2669 fw1x_reset(struct aq_softc *sc) 2670 { 2671 struct aq_mailbox_header mbox; 2672 const int retryCount = 1000; 2673 uint32_t tid0; 2674 int i; 2675 2676 tid0 = ~0; /*< Initial value of MBOX transactionId. */ 2677 2678 for (i = 0; i < retryCount; ++i) { 2679 /* 2680 * Read the beginning of Statistics structure to capture 2681 * the Transaction ID. 2682 */ 2683 aq1_fw_downld_dwords(sc, sc->sc_mbox_addr, 2684 (uint32_t *)&mbox, sizeof(mbox) / sizeof(uint32_t)); 2685 2686 /* Successfully read the stats. */ 2687 if (tid0 == ~0U) { 2688 /* We have read the initial value. */ 2689 tid0 = mbox.transaction_id; 2690 continue; 2691 } else if (mbox.transaction_id != tid0) { 2692 /* 2693 * Compare transaction ID to initial value. 2694 * If it's different means f/w is alive. 2695 * We're done. 2696 */ 2697 return 0; 2698 } 2699 2700 /* 2701 * Transaction ID value haven't changed since last time. 2702 * Try reading the stats again. 2703 */ 2704 delay(10); 2705 } 2706 aprint_error_dev(sc->sc_dev, "F/W 1.x reset finalize timeout\n"); 2707 return EBUSY; 2708 } 2709 2710 static int 2711 fw1x_set_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t mode, 2712 aq_link_speed_t speed, aq_link_fc_t fc, aq_link_eee_t eee) 2713 { 2714 uint32_t mpictrl = 0; 2715 uint32_t mpispeed = 0; 2716 2717 if (speed & AQ_LINK_10G) 2718 mpispeed |= FW1X_CTRL_10G; 2719 if (speed & AQ_LINK_5G) 2720 mpispeed |= (FW1X_CTRL_5G | FW1X_CTRL_5GSR); 2721 if (speed & AQ_LINK_2G5) 2722 mpispeed |= FW1X_CTRL_2G5; 2723 if (speed & AQ_LINK_1G) 2724 mpispeed |= FW1X_CTRL_1G; 2725 if (speed & AQ_LINK_100M) 2726 mpispeed |= FW1X_CTRL_100M; 2727 2728 mpictrl |= __SHIFTIN(mode, FW1X_MPI_STATE_MODE); 2729 mpictrl |= __SHIFTIN(mpispeed, FW1X_MPI_STATE_SPEED); 2730 AQ_WRITE_REG(sc, FW1X_MPI_CONTROL_REG, mpictrl); 2731 return 0; 2732 } 2733 2734 static int 2735 fw1x_get_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t *modep, 2736 aq_link_speed_t *speedp, aq_link_fc_t *fcp, aq_link_eee_t *eeep) 2737 { 2738 uint32_t mpistate, mpi_speed; 2739 aq_link_speed_t speed = AQ_LINK_NONE; 2740 2741 mpistate = AQ_READ_REG(sc, FW1X_MPI_STATE_REG); 2742 2743 if (modep != NULL) 2744 *modep = __SHIFTOUT(mpistate, FW1X_MPI_STATE_MODE); 2745 2746 mpi_speed = __SHIFTOUT(mpistate, FW1X_MPI_STATE_SPEED); 2747 if (mpi_speed & FW1X_CTRL_10G) 2748 speed = AQ_LINK_10G; 2749 else if (mpi_speed & (FW1X_CTRL_5G|FW1X_CTRL_5GSR)) 2750 speed = AQ_LINK_5G; 2751 else if (mpi_speed & FW1X_CTRL_2G5) 2752 speed = AQ_LINK_2G5; 2753 else if (mpi_speed & FW1X_CTRL_1G) 2754 speed = AQ_LINK_1G; 2755 else if (mpi_speed & FW1X_CTRL_100M) 2756 speed = AQ_LINK_100M; 2757 2758 if (speedp != NULL) 2759 *speedp = speed; 2760 2761 if (fcp != NULL) 2762 *fcp = AQ_FC_NONE; 2763 2764 if (eeep != NULL) 2765 *eeep = AQ_EEE_DISABLE; 2766 2767 return 0; 2768 } 2769 2770 static int 2771 fw1x_get_stats(struct aq_softc *sc, aq_hw_stats_s_t *stats) 2772 { 2773 int error; 2774 2775 error = aq1_fw_downld_dwords(sc, 2776 sc->sc_mbox_addr + offsetof(fw1x_mailbox_t, msm), (uint32_t *)stats, 2777 sizeof(aq_hw_stats_s_t) / sizeof(uint32_t)); 2778 if (error < 0) { 2779 device_printf(sc->sc_dev, 2780 "fw1x> download statistics data FAILED, error %d", error); 2781 return error; 2782 } 2783 2784 stats->dpc = AQ_READ_REG(sc, RX_DMA_DROP_PKT_CNT_REG); 2785 stats->cprc = AQ_READ_REG(sc, RX_DMA_COALESCED_PKT_CNT_REG); 2786 return 0; 2787 } 2788 2789 static int 2790 fw2x_reset(struct aq_softc *sc) 2791 { 2792 fw2x_capabilities_t caps = { 0 }; 2793 int error; 2794 2795 error = aq1_fw_downld_dwords(sc, 2796 sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, caps), 2797 (uint32_t *)&caps, sizeof caps / sizeof(uint32_t)); 2798 if (error != 0) { 2799 aprint_error_dev(sc->sc_dev, 2800 "fw2x> can't get F/W capabilities mask, error %d\n", 2801 error); 2802 return error; 2803 } 2804 sc->sc_fw_caps = caps.caps_lo | ((uint64_t)caps.caps_hi << 32); 2805 2806 char buf[256]; 2807 snprintb(buf, sizeof(buf), FW2X_SNPRINTB, sc->sc_fw_caps); 2808 aprint_verbose_dev(sc->sc_dev, "fw2x> F/W capabilities=%s\n", buf); 2809 2810 return 0; 2811 } 2812 2813 static int 2814 fw2x_set_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t mode, 2815 aq_link_speed_t speed, aq_link_fc_t fc, aq_link_eee_t eee) 2816 { 2817 uint64_t mpi_ctrl; 2818 int error = 0; 2819 2820 AQ_MPI_LOCK(sc); 2821 2822 mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG); 2823 2824 switch (mode) { 2825 case MPI_INIT: 2826 mpi_ctrl &= ~FW2X_CTRL_RATE_MASK; 2827 if (speed & AQ_LINK_10G) 2828 mpi_ctrl |= FW2X_CTRL_RATE_10G; 2829 if (speed & AQ_LINK_5G) 2830 mpi_ctrl |= FW2X_CTRL_RATE_5G; 2831 if (speed & AQ_LINK_2G5) 2832 mpi_ctrl |= FW2X_CTRL_RATE_2G5; 2833 if (speed & AQ_LINK_1G) 2834 mpi_ctrl |= FW2X_CTRL_RATE_1G; 2835 if (speed & AQ_LINK_100M) 2836 mpi_ctrl |= FW2X_CTRL_RATE_100M; 2837 2838 mpi_ctrl &= ~FW2X_CTRL_LINK_DROP; 2839 2840 mpi_ctrl &= ~FW2X_CTRL_EEE_MASK; 2841 if (eee == AQ_EEE_ENABLE) 2842 mpi_ctrl |= FW2X_CTRL_EEE_MASK; 2843 2844 mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE); 2845 if (fc & AQ_FC_RX) 2846 mpi_ctrl |= FW2X_CTRL_PAUSE; 2847 if (fc & AQ_FC_TX) 2848 mpi_ctrl |= FW2X_CTRL_ASYMMETRIC_PAUSE; 2849 break; 2850 case MPI_DEINIT: 2851 mpi_ctrl &= ~(FW2X_CTRL_RATE_MASK | FW2X_CTRL_EEE_MASK); 2852 mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE); 2853 break; 2854 default: 2855 device_printf(sc->sc_dev, "fw2x> unknown MPI state %d\n", mode); 2856 error = EINVAL; 2857 goto failure; 2858 } 2859 AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl); 2860 2861 failure: 2862 AQ_MPI_UNLOCK(sc); 2863 return error; 2864 } 2865 2866 static int 2867 fw2x_get_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t *modep, 2868 aq_link_speed_t *speedp, aq_link_fc_t *fcp, aq_link_eee_t *eeep) 2869 { 2870 uint64_t mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG); 2871 2872 if (modep != NULL) { 2873 uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG); 2874 if (mpi_ctrl & FW2X_CTRL_RATE_MASK) 2875 *modep = MPI_INIT; 2876 else 2877 *modep = MPI_DEINIT; 2878 } 2879 2880 aq_link_speed_t speed = AQ_LINK_NONE; 2881 if (mpi_state & FW2X_CTRL_RATE_10G) 2882 speed = AQ_LINK_10G; 2883 else if (mpi_state & FW2X_CTRL_RATE_5G) 2884 speed = AQ_LINK_5G; 2885 else if (mpi_state & FW2X_CTRL_RATE_2G5) 2886 speed = AQ_LINK_2G5; 2887 else if (mpi_state & FW2X_CTRL_RATE_1G) 2888 speed = AQ_LINK_1G; 2889 else if (mpi_state & FW2X_CTRL_RATE_100M) 2890 speed = AQ_LINK_100M; 2891 2892 if (speedp != NULL) 2893 *speedp = speed; 2894 2895 aq_link_fc_t fc = AQ_FC_NONE; 2896 if (mpi_state & FW2X_CTRL_PAUSE) 2897 fc |= AQ_FC_RX; 2898 if (mpi_state & FW2X_CTRL_ASYMMETRIC_PAUSE) 2899 fc |= AQ_FC_TX; 2900 if (fcp != NULL) 2901 *fcp = fc; 2902 2903 /* XXX: TODO: EEE */ 2904 if (eeep != NULL) 2905 *eeep = AQ_EEE_DISABLE; 2906 2907 return 0; 2908 } 2909 2910 static int 2911 toggle_mpi_ctrl_and_wait(struct aq_softc *sc, uint64_t mask, 2912 uint32_t timeout_ms, uint32_t try_count) 2913 { 2914 uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG); 2915 uint64_t mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG); 2916 int error; 2917 2918 /* First, check that control and state values are consistent */ 2919 if ((mpi_ctrl & mask) != (mpi_state & mask)) { 2920 device_printf(sc->sc_dev, 2921 "fw2x> MPI control (%#llx) and state (%#llx)" 2922 " are not consistent for mask %#llx!\n", 2923 (unsigned long long)mpi_ctrl, (unsigned long long)mpi_state, 2924 (unsigned long long)mask); 2925 return EINVAL; 2926 } 2927 2928 /* Invert bits (toggle) in control register */ 2929 mpi_ctrl ^= mask; 2930 AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl); 2931 2932 /* Clear all bits except masked */ 2933 mpi_ctrl &= mask; 2934 2935 /* Wait for FW reflecting change in state register */ 2936 WAIT_FOR((AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG) & mask) == mpi_ctrl, 2937 1000 * timeout_ms, try_count, &error); 2938 if (error != 0) { 2939 device_printf(sc->sc_dev, 2940 "f/w2x> timeout while waiting for response" 2941 " in state register for bit %#llx!", 2942 (unsigned long long)mask); 2943 return error; 2944 } 2945 return 0; 2946 } 2947 2948 static int 2949 fw2x_get_stats(struct aq_softc *sc, aq_hw_stats_s_t *stats) 2950 { 2951 int error; 2952 2953 AQ_MPI_LOCK(sc); 2954 /* Say to F/W to update the statistics */ 2955 error = toggle_mpi_ctrl_and_wait(sc, FW2X_CTRL_STATISTICS, 1, 25); 2956 if (error != 0) { 2957 device_printf(sc->sc_dev, 2958 "fw2x> statistics update error %d\n", error); 2959 goto failure; 2960 } 2961 2962 CTASSERT(sizeof(fw2x_msm_statistics_t) <= sizeof(struct aq_hw_stats_s)); 2963 error = aq1_fw_downld_dwords(sc, 2964 sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, msm), (uint32_t *)stats, 2965 sizeof(fw2x_msm_statistics_t) / sizeof(uint32_t)); 2966 if (error != 0) { 2967 device_printf(sc->sc_dev, 2968 "fw2x> download statistics data FAILED, error %d", error); 2969 goto failure; 2970 } 2971 stats->dpc = AQ_READ_REG(sc, RX_DMA_DROP_PKT_CNT_REG); 2972 stats->cprc = AQ_READ_REG(sc, RX_DMA_COALESCED_PKT_CNT_REG); 2973 2974 failure: 2975 AQ_MPI_UNLOCK(sc); 2976 return error; 2977 } 2978 2979 #if NSYSMON_ENVSYS > 0 2980 static int 2981 fw2x_get_temperature(struct aq_softc *sc, uint32_t *temp) 2982 { 2983 int error; 2984 uint32_t value, celsius; 2985 2986 AQ_MPI_LOCK(sc); 2987 2988 /* Say to F/W to update the temperature */ 2989 error = toggle_mpi_ctrl_and_wait(sc, FW2X_CTRL_TEMPERATURE, 1, 25); 2990 if (error != 0) 2991 goto failure; 2992 2993 error = aq1_fw_downld_dwords(sc, 2994 sc->sc_mbox_addr + offsetof(fw2x_mailbox_t, phy_info2), 2995 &value, sizeof(value) / sizeof(uint32_t)); 2996 if (error != 0) 2997 goto failure; 2998 2999 /* 1/256 decrees C to microkelvin */ 3000 celsius = __SHIFTOUT(value, PHYINFO2_TEMPERATURE); 3001 if (celsius == 0) { 3002 error = EIO; 3003 goto failure; 3004 } 3005 *temp = celsius * (1000000 / 256) + 273150000; 3006 3007 failure: 3008 AQ_MPI_UNLOCK(sc); 3009 return 0; 3010 } 3011 #endif 3012 3013 static int 3014 aq1_fw_downld_dwords(struct aq_softc *sc, uint32_t addr, uint32_t *p, 3015 uint32_t cnt) 3016 { 3017 uint32_t v; 3018 int error = 0; 3019 3020 WAIT_FOR(AQ_READ_REG(sc, AQ1_FW_SEM_RAM_REG) == 1, 1, 10000, &error); 3021 if (error != 0) { 3022 AQ_WRITE_REG(sc, AQ1_FW_SEM_RAM_REG, 1); 3023 v = AQ_READ_REG(sc, AQ1_FW_SEM_RAM_REG); 3024 if (v == 0) { 3025 device_printf(sc->sc_dev, 3026 "%s:%d: timeout\n", __func__, __LINE__); 3027 return ETIMEDOUT; 3028 } 3029 } 3030 3031 AQ_WRITE_REG(sc, AQ_FW_MBOX_ADDR_REG, addr); 3032 3033 error = 0; 3034 for (; cnt > 0 && error == 0; cnt--) { 3035 /* execute mailbox interface */ 3036 AQ_WRITE_REG_BIT(sc, AQ_FW_MBOX_CMD_REG, 3037 AQ_FW_MBOX_CMD_EXECUTE, 1); 3038 if (sc->sc_features & FEATURES_AQ1_REV_B1) { 3039 WAIT_FOR(AQ_READ_REG(sc, AQ_FW_MBOX_ADDR_REG) != addr, 3040 1, 1000, &error); 3041 } else { 3042 WAIT_FOR((AQ_READ_REG(sc, AQ_FW_MBOX_CMD_REG) & 3043 AQ_FW_MBOX_CMD_BUSY) == 0, 3044 1, 1000, &error); 3045 } 3046 *p++ = AQ_READ_REG(sc, AQ_FW_MBOX_VAL_REG); 3047 addr += sizeof(uint32_t); 3048 } 3049 AQ_WRITE_REG(sc, AQ1_FW_SEM_RAM_REG, 1); 3050 3051 if (error != 0) 3052 device_printf(sc->sc_dev, 3053 "%s:%d: timeout\n", __func__, __LINE__); 3054 3055 return error; 3056 } 3057 3058 /* read my mac address */ 3059 static int 3060 aq1_get_mac_addr(struct aq_softc *sc) 3061 { 3062 uint32_t mac_addr[2]; 3063 uint32_t efuse_shadow_addr; 3064 int err; 3065 3066 efuse_shadow_addr = 0; 3067 if (FW_VERSION_MAJOR(sc) >= 2) 3068 efuse_shadow_addr = AQ_READ_REG(sc, FW2X_MPI_EFUSEADDR_REG); 3069 else 3070 efuse_shadow_addr = AQ_READ_REG(sc, FW1X_MPI_EFUSEADDR_REG); 3071 3072 if (efuse_shadow_addr == 0) { 3073 aprint_error_dev(sc->sc_dev, "cannot get efuse addr\n"); 3074 return ENXIO; 3075 } 3076 3077 memset(mac_addr, 0, sizeof(mac_addr)); 3078 err = aq1_fw_downld_dwords(sc, efuse_shadow_addr + (40 * 4), 3079 mac_addr, __arraycount(mac_addr)); 3080 if (err < 0) 3081 return err; 3082 3083 if (mac_addr[0] == 0 && mac_addr[1] == 0) { 3084 aprint_error_dev(sc->sc_dev, "mac address not found\n"); 3085 return ENXIO; 3086 } 3087 3088 mac_addr[0] = htobe32(mac_addr[0]); 3089 mac_addr[1] = htobe32(mac_addr[1]); 3090 3091 memcpy(sc->sc_enaddr.ether_addr_octet, 3092 (uint8_t *)mac_addr, ETHER_ADDR_LEN); 3093 aprint_normal_dev(sc->sc_dev, "Etheraddr: %s\n", 3094 ether_sprintf(sc->sc_enaddr.ether_addr_octet)); 3095 3096 return 0; 3097 } 3098 3099 /* set multicast filter. index 0 for own address */ 3100 static int 3101 aq_set_mac_addr(struct aq_softc *sc, int index, uint8_t *enaddr) 3102 { 3103 uint32_t h, l; 3104 3105 if (index >= AQ_HW_MAC_NUM(sc)) 3106 return EINVAL; 3107 3108 if (enaddr == NULL) { 3109 /* disable */ 3110 AQ_WRITE_REG_BIT(sc, 3111 RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0); 3112 return 0; 3113 } 3114 3115 h = (enaddr[0] << 8) | (enaddr[1]); 3116 l = ((uint32_t)enaddr[2] << 24) | (enaddr[3] << 16) | 3117 (enaddr[4] << 8) | (enaddr[5]); 3118 3119 /* disable, set, and enable */ 3120 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0); 3121 AQ_WRITE_REG(sc, RPF_L2UC_LSW_REG(index), l); 3122 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), 3123 RPF_L2UC_MSW_MACADDR_HI, h); 3124 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), 3125 RPF_L2UC_MSW_ACTION, RPF_ACTION_HOST); 3126 if (HWTYPE_AQ2_P(sc)) { 3127 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), 3128 RPF_L2UC_MSW_TAG, __SHIFTIN(1, AQ2_RPF_TAG_UC_MASK)); 3129 } 3130 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 1); 3131 3132 return 0; 3133 } 3134 3135 static int 3136 aq_set_capability(struct aq_softc *sc) 3137 { 3138 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 3139 int ip4csum_tx = 3140 ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) == 0) ? 0 : 1; 3141 int ip4csum_rx = 3142 ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) == 0) ? 0 : 1; 3143 int l4csum_tx = ((ifp->if_capenable & 3144 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 3145 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx)) == 0) ? 0 : 1; 3146 int l4csum_rx = 3147 ((ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 3148 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) == 0) ? 0 : 1; 3149 uint32_t lso = 3150 ((ifp->if_capenable & (IFCAP_TSOv4 | IFCAP_TSOv6)) == 0) ? 3151 0 : 0xffffffff; 3152 uint32_t lro = ((ifp->if_capenable & IFCAP_LRO) == 0) ? 3153 0 : 0xffffffff; 3154 uint32_t i, v; 3155 3156 /* TX checksums offloads*/ 3157 AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_IP4CSUM_EN, ip4csum_tx); 3158 AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_L4CSUM_EN, l4csum_tx); 3159 3160 /* RX checksums offloads*/ 3161 AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_IP4CSUM_EN, ip4csum_rx); 3162 AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_L4CSUM_EN, l4csum_rx); 3163 3164 /* LSO offloads*/ 3165 AQ_WRITE_REG(sc, TDM_LSO_EN_REG, lso); 3166 3167 #define AQ_B0_LRO_RXD_MAX 16 3168 v = (8 < AQ_B0_LRO_RXD_MAX) ? 3 : 3169 (4 < AQ_B0_LRO_RXD_MAX) ? 2 : 3170 (2 < AQ_B0_LRO_RXD_MAX) ? 1 : 0; 3171 for (i = 0; i < AQ_RINGS_NUM; i++) { 3172 AQ_WRITE_REG_BIT(sc, RPO_LRO_LDES_MAX_REG(i), 3173 RPO_LRO_LDES_MAX_MASK(i), v); 3174 } 3175 3176 AQ_WRITE_REG_BIT(sc, RPO_LRO_TB_DIV_REG, RPO_LRO_TB_DIV, 0x61a); 3177 AQ_WRITE_REG_BIT(sc, RPO_LRO_INACTIVE_IVAL_REG, 3178 RPO_LRO_INACTIVE_IVAL, 0); 3179 /* 3180 * the LRO timebase divider is 5 uS (0x61a), 3181 * to get a maximum coalescing interval of 250 uS, 3182 * we need to multiply by 50(0x32) to get 3183 * the default value 250 uS 3184 */ 3185 AQ_WRITE_REG_BIT(sc, RPO_LRO_MAX_COALESCING_IVAL_REG, 3186 RPO_LRO_MAX_COALESCING_IVAL, 50); 3187 AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG, 3188 RPO_LRO_CONF_QSESSION_LIMIT, 1); 3189 AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG, 3190 RPO_LRO_CONF_TOTAL_DESC_LIMIT, 2); 3191 AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG, 3192 RPO_LRO_CONF_PATCHOPTIMIZATION_EN, 0); 3193 AQ_WRITE_REG_BIT(sc, RPO_LRO_CONF_REG, 3194 RPO_LRO_CONF_MIN_PAYLOAD_OF_FIRST_PKT, 10); 3195 AQ_WRITE_REG(sc, RPO_LRO_RSC_MAX_REG, 1); 3196 AQ_WRITE_REG(sc, RPO_LRO_ENABLE_REG, lro); 3197 3198 return 0; 3199 } 3200 3201 static int 3202 aq_set_filter(struct aq_softc *sc) 3203 { 3204 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 3205 struct ethercom * const ec = &sc->sc_ethercom; 3206 struct ether_multi *enm; 3207 struct ether_multistep step; 3208 int idx, error = 0; 3209 3210 if (HWTYPE_AQ2_P(sc)) { 3211 uint32_t action = (ifp->if_flags & IFF_PROMISC) ? 3212 AQ2_ART_ACTION_DISABLE : AQ2_ART_ACTION_DROP; 3213 aq2_filter_art_set(sc, AQ2_RPF_INDEX_L2_PROMISC_OFF, 0, 3214 AQ2_RPF_TAG_UC_MASK | AQ2_RPF_TAG_ALLMC_MASK, action); 3215 aq2_filter_art_set(sc, AQ2_RPF_INDEX_VLAN_PROMISC_OFF, 0, 3216 AQ2_RPF_TAG_VLAN_MASK | AQ2_RPF_TAG_UNTAG_MASK, action); 3217 } 3218 3219 if (ifp->if_flags & IFF_PROMISC) { 3220 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC, 3221 (ifp->if_flags & IFF_PROMISC) ? 1 : 0); 3222 ec->ec_flags |= ETHER_F_ALLMULTI; 3223 goto done; 3224 } 3225 3226 /* clear all table */ 3227 for (idx = 0; idx < AQ_HW_MAC_NUM(sc); idx++) { 3228 if (idx == AQ_HW_MAC_OWN) /* already used for own */ 3229 continue; 3230 aq_set_mac_addr(sc, idx, NULL); 3231 } 3232 3233 /* don't accept all multicast */ 3234 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG, 3235 RPF_MCAST_FILTER_MASK_ALLMULTI, 0); 3236 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0), 3237 RPF_MCAST_FILTER_EN, 0); 3238 3239 idx = 0; 3240 ETHER_LOCK(ec); 3241 ETHER_FIRST_MULTI(step, ec, enm); 3242 while (enm != NULL) { 3243 if (idx == AQ_HW_MAC_OWN) 3244 idx++; 3245 3246 if ((idx >= AQ_HW_MAC_NUM(sc)) || 3247 memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3248 /* 3249 * too many filters. 3250 * fallback to accept all multicast addresses. 3251 */ 3252 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG, 3253 RPF_MCAST_FILTER_MASK_ALLMULTI, 1); 3254 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0), 3255 RPF_MCAST_FILTER_EN, 1); 3256 ec->ec_flags |= ETHER_F_ALLMULTI; 3257 ETHER_UNLOCK(ec); 3258 goto done; 3259 } 3260 3261 /* add a filter */ 3262 aq_set_mac_addr(sc, idx++, enm->enm_addrlo); 3263 3264 ETHER_NEXT_MULTI(step, enm); 3265 } 3266 ec->ec_flags &= ~ETHER_F_ALLMULTI; 3267 ETHER_UNLOCK(ec); 3268 3269 done: 3270 return error; 3271 } 3272 3273 static int 3274 aq2_filter_art_set(struct aq_softc *sc, uint32_t idx, 3275 uint32_t tag, uint32_t mask, uint32_t action) 3276 { 3277 int error; 3278 3279 AQ_MPI_LOCK(sc); 3280 3281 WAIT_FOR(AQ_READ_REG(sc, AQ2_ART_SEM_REG) == 1, 10, 10000, &error); 3282 if (error != 0) { 3283 device_printf(sc->sc_dev, "%s: timeout\n", __func__); 3284 goto done; 3285 } 3286 3287 idx += sc->sc_filter_art_base_index; 3288 AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_TAG_REG(idx), tag); 3289 AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_MASK_REG(idx), mask); 3290 AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_ACTION_REG(idx), action); 3291 3292 AQ_WRITE_REG(sc, AQ2_ART_SEM_REG, 1); 3293 3294 done: 3295 AQ_MPI_UNLOCK(sc); 3296 return 0; 3297 } 3298 3299 static int 3300 aq2_init_filter(struct aq_softc *sc) 3301 { 3302 AQ_WRITE_REG_BIT(sc, AQ2_RPF_REC_TAB_ENABLE_REG, 3303 AQ2_RPF_REC_TAB_ENABLE_MASK, 0xffff); 3304 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(0), 3305 RPF_L2UC_MSW_TAG, __SHIFTIN(1, AQ2_RPF_TAG_UC_MASK)); 3306 AQ_WRITE_REG_BIT(sc, AQ2_RPF_L2BC_TAG_REG, 3307 AQ2_RPF_L2BC_TAG_MASK, __SHIFTIN(1, AQ2_RPF_TAG_UC_MASK)); 3308 3309 aq2_filter_art_set(sc, AQ2_RPF_INDEX_L2_PROMISC_OFF, 3310 0, AQ2_RPF_TAG_UC_MASK | AQ2_RPF_TAG_ALLMC_MASK, 3311 AQ2_ART_ACTION_DROP); 3312 aq2_filter_art_set(sc, AQ2_RPF_INDEX_VLAN_PROMISC_OFF, 3313 0, AQ2_RPF_TAG_VLAN_MASK | AQ2_RPF_TAG_UNTAG_MASK, 3314 AQ2_ART_ACTION_DROP); 3315 3316 for (int i = 0; i < 8; i++) { 3317 aq2_filter_art_set(sc, AQ2_RPF_INDEX_PCP_TO_TC + i, 3318 __SHIFTIN(i, AQ2_RPF_TAG_PCP_MASK), AQ2_RPF_TAG_PCP_MASK, 3319 AQ2_ART_ACTION_ASSIGN_TC(i % sc->sc_nqueues)); 3320 } 3321 3322 return 0; 3323 } 3324 3325 static int 3326 aq2_interface_buffer_read(struct aq_softc *sc, uint32_t reg0, uint32_t *data0, 3327 uint32_t size0) 3328 { 3329 uint32_t tid0, tid1, reg, *data, size; 3330 int timo; 3331 3332 for (timo = 10000; timo > 0; timo--) { 3333 tid0 = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG); 3334 if (__SHIFTOUT(tid0, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A) != 3335 __SHIFTOUT(tid0, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B)) { 3336 delay(10); 3337 continue; 3338 } 3339 3340 for (reg = reg0, data = data0, size = size0; 3341 size >= 4; reg += 4, data++, size -= 4) { 3342 *data = AQ_READ_REG(sc, reg); 3343 } 3344 3345 tid1 = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG); 3346 if (tid0 == tid1) 3347 break; 3348 } 3349 if (timo == 0) { 3350 device_printf(sc->sc_dev, "%s: timeout\n", __func__); 3351 return ETIMEDOUT; 3352 } 3353 return 0; 3354 } 3355 3356 static int 3357 aq2_fw_reboot(struct aq_softc *sc) 3358 { 3359 uint32_t v; 3360 int timo; 3361 char buf[32]; 3362 3363 /* It seems that there is still only one type of firmware ABI in aq2 */ 3364 sc->sc_fw_ops = &aq2_fw_ops; 3365 sc->sc_features |= FEATURES_AQ2; 3366 sc->sc_max_mtu = AQ2_JUMBO_MTU; 3367 3368 AQ_WRITE_REG(sc, AQ2_MCP_HOST_REQ_INT_CLR_REG, 1); 3369 AQ_WRITE_REG(sc, AQ2_MIF_BOOT_REG, 1); /* reboot request */ 3370 for (timo = 200000; timo > 0; timo--) { 3371 v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG); 3372 if ((v & AQ2_MIF_BOOT_BOOT_STARTED) && v != 0xffffffff) 3373 break; 3374 delay(10); 3375 } 3376 if (timo <= 0) { 3377 aprint_error_dev(sc->sc_dev, "FW reboot timeout\n"); 3378 return ETIMEDOUT; 3379 } 3380 3381 for (timo = 2000000; timo > 0; timo--) { 3382 v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG); 3383 if ((v & AQ2_MIF_BOOT_FW_INIT_FAILED) || 3384 (v & AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS)) 3385 break; 3386 v = AQ_READ_REG(sc, AQ2_MCP_HOST_REQ_INT_REG); 3387 if (v & AQ2_MCP_HOST_REQ_INT_READY) 3388 break; 3389 delay(10); 3390 } 3391 if (timo <= 0) { 3392 aprint_error_dev(sc->sc_dev, "FW restart timeout\n"); 3393 return ETIMEDOUT; 3394 } 3395 3396 v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG); 3397 if (v & AQ2_MIF_BOOT_FW_INIT_FAILED) { 3398 aprint_error_dev(sc->sc_dev, "FW restart failed\n"); 3399 return ETIMEDOUT; 3400 } 3401 3402 v = AQ_READ_REG(sc, AQ2_MCP_HOST_REQ_INT_REG); 3403 if (v & AQ2_MCP_HOST_REQ_INT_READY) { 3404 aprint_error_dev(sc->sc_dev, "firmware required\n"); 3405 return ENXIO; 3406 } 3407 3408 /* 3409 * Get aq2 firmware version. 3410 * Note that the bit layout and its meaning are different from aq1. 3411 */ 3412 aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_VERSION_BUNDLE_REG, 3413 (uint32_t *)&v, sizeof(v)); 3414 sc->sc_fw_version = 3415 __SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MAJOR) << 24 | 3416 __SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MINOR) << 16 | 3417 __SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_BUILD); 3418 3419 aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_VERSION_IFACE_REG, 3420 (uint32_t *)&v, sizeof(v)); 3421 switch (__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER)) { 3422 case AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_A0: 3423 sc->sc_features |= FEATURES_AQ2_IFACE_A0; 3424 strncpy(buf, "A0", sizeof(buf)); 3425 break; 3426 case AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_B0: 3427 sc->sc_features |= FEATURES_AQ2_IFACE_B0; 3428 strncpy(buf, "B0", sizeof(buf)); 3429 break; 3430 default: 3431 snprintf(buf, sizeof(buf), "(unknown 0x%08x)", v); 3432 break; 3433 } 3434 aprint_normal_dev(sc->sc_dev, 3435 "Atlantic2 %s, F/W version %d.%d.%d\n", buf, 3436 FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), FW_VERSION_BUILD(sc)); 3437 3438 aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_FILTER_CAPS_REG, 3439 (uint32_t *)&sc->sc_filter_caps, sizeof(sc->sc_filter_caps)); 3440 sc->sc_filter_art_base_index = __SHIFTOUT(sc->sc_filter_caps.caps3, 3441 AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX) * 8; 3442 3443 /* debug info */ 3444 v = AQ_READ_REG(sc, AQ_HW_REVISION_REG); 3445 aprint_debug_dev(sc->sc_dev, "HW Rev: 0x%08x\n", v); 3446 3447 aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_VERSION_MAC_REG, 3448 (uint32_t *)&v, sizeof(v)); 3449 aprint_debug_dev(sc->sc_dev, "MAC Version %d.%d.%d\n", 3450 (int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MAJOR), 3451 (int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MINOR), 3452 (int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_BUILD)); 3453 3454 aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_VERSION_PHY_REG, 3455 (uint32_t *)&v, sizeof(v)); 3456 aprint_debug_dev(sc->sc_dev, "PHY Version %d.%d.%d\n", 3457 (int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MAJOR), 3458 (int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_MINOR), 3459 (int)__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_VERSION_BUILD)); 3460 3461 v = AQ_READ_REG(sc, AQ2_HW_FPGA_VERSION_REG); 3462 aprint_debug_dev(sc->sc_dev, "AQ2 FPGA Version: %d.%d.%d.%d\n", 3463 (int)__SHIFTOUT(v, __BITS(31, 24)), 3464 (int)__SHIFTOUT(v, __BITS(23, 16)), 3465 (int)__SHIFTOUT(v, __BITS(15, 8)), 3466 (int)__SHIFTOUT(v, __BITS(7, 0))); 3467 3468 aprint_debug_dev(sc->sc_dev, "FILTER CAPS: 0x%08x,0x%08x,0x%08x\n", 3469 sc->sc_filter_caps.caps1, sc->sc_filter_caps.caps2, 3470 sc->sc_filter_caps.caps3); 3471 3472 return 0; 3473 } 3474 3475 static int 3476 aq2_fw_wait_shared_ack(struct aq_softc *sc) 3477 { 3478 int error; 3479 3480 AQ_WRITE_REG(sc, AQ2_MIF_HOST_FINISHED_STATUS_WRITE_REG, 3481 AQ2_MIF_HOST_FINISHED_STATUS_ACK); 3482 WAIT_FOR((AQ_READ_REG(sc, AQ2_MIF_HOST_FINISHED_STATUS_READ_REG) & 3483 AQ2_MIF_HOST_FINISHED_STATUS_ACK) == 0, 100, 100000, &error); 3484 3485 return error; 3486 } 3487 3488 static int 3489 aq2_fw_reset(struct aq_softc *sc) 3490 { 3491 AQ_WRITE_REG_BIT(sc, AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG, 3492 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE, 3493 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE); 3494 3495 AQ_WRITE_REG(sc, AQ2_FW_INTERFACE_IN_MTU_REG, 3496 AQ2_JUMBO_MTU + sizeof(struct ether_header)); 3497 3498 uint32_t v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG); 3499 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_QUEUE_OR_TC; 3500 v &= ~AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_RX_QUEUE_TC_INDEX; 3501 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_ACCEPT; 3502 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_QUEUE_OR_TC; 3503 v &= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_RX_QUEUE_TC_INDEX; 3504 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_ACCEPT; 3505 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_QUEUE_OR_TC; 3506 v &= ~AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_RX_QUEUE_TX_INDEX; 3507 AQ_WRITE_REG(sc, AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG, v); 3508 3509 return aq2_fw_wait_shared_ack(sc); 3510 } 3511 3512 static int 3513 aq2_fw_set_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t mode, 3514 aq_link_speed_t speed, aq_link_fc_t fc, aq_link_eee_t eee) 3515 { 3516 uint32_t v; 3517 int error; 3518 3519 AQ_MPI_LOCK(sc); 3520 3521 v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG); 3522 v &= ~( 3523 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G | 3524 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G | 3525 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G | 3526 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5 | 3527 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5 | 3528 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G | 3529 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M | 3530 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M | 3531 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD | 3532 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD | 3533 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD); 3534 3535 v &= ~AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP; 3536 3537 if (speed & AQ_LINK_10G) 3538 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G; 3539 if (speed & AQ_LINK_5G) 3540 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G | 3541 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G; 3542 if (speed & AQ_LINK_2G5) 3543 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5 | 3544 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5; 3545 if (speed & AQ_LINK_1G) 3546 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G | 3547 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD; 3548 if (speed & AQ_LINK_100M) 3549 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M | 3550 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD; 3551 if (speed & AQ_LINK_10M) { 3552 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M | 3553 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD; 3554 } 3555 3556 /* flow control */ 3557 v &= ~(AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX | 3558 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX); 3559 if (fc & AQ_FC_TX) 3560 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX; 3561 if (fc & AQ_FC_RX) 3562 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX; 3563 3564 if (speed == AQ_LINK_NONE) { 3565 AQ_WRITE_REG_BIT(sc, AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG, 3566 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE, 3567 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SHUTDOWN); 3568 } else { 3569 AQ_WRITE_REG_BIT(sc, AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG, 3570 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE, 3571 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE); 3572 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP; 3573 } 3574 3575 AQ_WRITE_REG(sc, AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG, v); 3576 error = aq2_fw_wait_shared_ack(sc); 3577 3578 AQ_MPI_UNLOCK(sc); 3579 return error; 3580 } 3581 3582 static int 3583 aq2_fw_get_mode(struct aq_softc *sc, aq_hw_fw_mpi_state_t *modep, 3584 aq_link_speed_t *speedp, aq_link_fc_t *fcp, aq_link_eee_t *eeep) 3585 { 3586 aq_link_speed_t speed; 3587 uint32_t v; 3588 3589 v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_LINK_STATUS_REG); 3590 switch (__SHIFTOUT(v, AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE)) { 3591 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10G: 3592 speed = AQ_LINK_10G; 3593 break; 3594 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_5G: 3595 speed = AQ_LINK_5G; 3596 break; 3597 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_2G5: 3598 speed = AQ_LINK_2G5; 3599 break; 3600 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_1G: 3601 speed = AQ_LINK_1G; 3602 break; 3603 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_100M: 3604 speed = AQ_LINK_100M; 3605 break; 3606 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10M: 3607 speed = AQ_LINK_10M; 3608 break; 3609 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_INVALID: 3610 default: 3611 speed = AQ_LINK_NONE; 3612 break; 3613 } 3614 if (speedp != NULL) 3615 *speedp = speed; 3616 3617 aq_link_fc_t fc = 0; 3618 if (v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_TX) 3619 fc |= AQ_FC_TX; 3620 if (v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_RX) 3621 fc |= AQ_FC_RX; 3622 if (fcp != NULL) 3623 *fcp = fc; 3624 3625 aq_link_eee_t eee; 3626 eee = (v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_EEE) ? 3627 AQ_EEE_ENABLE : AQ_EEE_DISABLE; 3628 if (eeep != NULL) 3629 *eeep = eee; 3630 3631 return -1; 3632 } 3633 3634 static int 3635 aq2_fw_get_stats(struct aq_softc *sc, aq_hw_stats_s_t *stats) 3636 { 3637 aq2_statistics_t aq2stat; 3638 int error; 3639 3640 AQ_MPI_LOCK(sc); 3641 error = aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_STATS_REG, 3642 (uint32_t *)&aq2stat, sizeof(aq2stat)); 3643 AQ_MPI_UNLOCK(sc); 3644 if (error != 0) 3645 return error; 3646 3647 if (sc->sc_features & FEATURES_AQ2_IFACE_A0) { 3648 /* RX */ 3649 stats->uprc = aq2stat.a0.rx_unicast_frames; 3650 stats->mprc = aq2stat.a0.rx_multicast_frames; 3651 stats->bprc = aq2stat.a0.rx_broadcast_frames; 3652 stats->erpr = aq2stat.a0.rx_errors; 3653 stats->ubrc = aq2stat.a0.rx_unicast_octets; 3654 stats->bbrc = aq2stat.a0.rx_broadcast_octets; 3655 stats->mbrc = aq2stat.a0.rx_multicast_octets; 3656 stats->prc = aq2stat.a0.rx_good_frames; 3657 /* TX */ 3658 stats->uptc = aq2stat.a0.tx_unicast_frames; 3659 stats->bptc = aq2stat.a0.tx_broadcast_frames; 3660 stats->mptc = aq2stat.a0.tx_multicast_frames; 3661 stats->erpt = aq2stat.a0.tx_errors; 3662 stats->ubtc = aq2stat.a0.tx_unicast_octets; 3663 stats->bbtc = aq2stat.a0.tx_broadcast_octets; 3664 stats->mbtc = aq2stat.a0.tx_multicast_octets; 3665 stats->ptc = aq2stat.a0.tx_good_frames; 3666 } else if (sc->sc_features & FEATURES_AQ2_IFACE_B0) { 3667 /* RX */ 3668 stats->uprc = aq2stat.b0.rx_unicast_frames; 3669 stats->mprc = aq2stat.b0.rx_multicast_frames; 3670 stats->bprc = aq2stat.b0.rx_broadcast_frames; 3671 stats->erpr = aq2stat.b0.rx_errors; 3672 stats->ubrc = 0; 3673 stats->bbrc = 0; 3674 stats->mbrc = 0; 3675 stats->prc = aq2stat.b0.rx_good_frames; 3676 /* TX */ 3677 stats->uptc = aq2stat.b0.tx_unicast_frames; 3678 stats->bptc = aq2stat.b0.tx_multicast_frames; 3679 stats->mptc = aq2stat.b0.tx_broadcast_frames; 3680 stats->erpt = aq2stat.b0.tx_errors; 3681 stats->ubtc = 0; 3682 stats->bbtc = 0; 3683 stats->mbtc = 0; 3684 stats->ptc = aq2stat.b0.tx_good_frames; 3685 } else { 3686 return ENOTSUP; 3687 } 3688 stats->dpc = AQ_READ64_REG(sc, RX_DMA_DROP_PKT_CNT_REG); 3689 stats->cprc = AQ_READ64_REG(sc, RX_DMA_COALESCED_PKT_CNT_REG); 3690 3691 return error; 3692 } 3693 3694 #if NSYSMON_ENVSYS > 0 3695 static int 3696 aq2_fw_get_temperature(struct aq_softc *sc, uint32_t *temp) 3697 { 3698 aq2_health_monitor_t health; 3699 uint32_t data; 3700 3701 AQ_MPI_LOCK(sc); 3702 3703 aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_PHY_HEALTH_MONITOR, 3704 (uint32_t *)&health, sizeof(health)); 3705 3706 AQ_MPI_UNLOCK(sc); 3707 3708 data = __SHIFTOUT(health.data1, HEALTH_MONITOR_DATA1_TEMPERATURE); 3709 if (data == 0) 3710 return EIO; 3711 3712 *temp = data * 1000000 + 273150000; 3713 return 0; 3714 } 3715 #endif 3716 3717 static int 3718 aq2_get_mac_addr(struct aq_softc *sc) 3719 { 3720 uint32_t mac_addr[2]; 3721 3722 memset(mac_addr, 0, sizeof(mac_addr)); 3723 AQ_READ_REGS(sc, AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG, 3724 mac_addr, __arraycount(mac_addr)); 3725 3726 if (mac_addr[0] == 0 && mac_addr[1] == 0) { 3727 aprint_error_dev(sc->sc_dev, "mac address not found\n"); 3728 return ENXIO; 3729 } 3730 3731 HTOLE32(mac_addr[0]); 3732 HTOLE32(mac_addr[1]); 3733 3734 memcpy(sc->sc_enaddr.ether_addr_octet, 3735 (uint8_t *)mac_addr, ETHER_ADDR_LEN); 3736 aprint_normal_dev(sc->sc_dev, "Etheraddr: %s\n", 3737 ether_sprintf(sc->sc_enaddr.ether_addr_octet)); 3738 3739 return 0; 3740 } 3741 3742 static int 3743 aq_ifmedia_change(struct ifnet * const ifp) 3744 { 3745 struct aq_softc * const sc = ifp->if_softc; 3746 3747 aq_link_speed_t rate = AQ_LINK_NONE; 3748 aq_link_fc_t fc = AQ_FC_NONE; 3749 aq_link_eee_t eee = AQ_EEE_DISABLE; 3750 3751 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 3752 return EINVAL; 3753 3754 switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) { 3755 case IFM_AUTO: 3756 rate = AQ_LINK_AUTO; 3757 break; 3758 case IFM_NONE: 3759 rate = AQ_LINK_NONE; 3760 break; 3761 case IFM_10_T: 3762 rate = AQ_LINK_10M; 3763 break; 3764 case IFM_100_TX: 3765 rate = AQ_LINK_100M; 3766 break; 3767 case IFM_1000_T: 3768 rate = AQ_LINK_1G; 3769 break; 3770 case IFM_2500_T: 3771 rate = AQ_LINK_2G5; 3772 break; 3773 case IFM_5000_T: 3774 rate = AQ_LINK_5G; 3775 break; 3776 case IFM_10G_T: 3777 rate = AQ_LINK_10G; 3778 break; 3779 default: 3780 device_printf(sc->sc_dev, "unknown media: 0x%X\n", 3781 IFM_SUBTYPE(sc->sc_media.ifm_media)); 3782 return ENODEV; 3783 } 3784 3785 if (sc->sc_media.ifm_media & IFM_FLOW) 3786 fc = AQ_FC_ALL; 3787 3788 /* XXX: todo EEE */ 3789 3790 /* re-initialize hardware with new parameters */ 3791 aq_set_linkmode(sc, rate, fc, eee); 3792 3793 return 0; 3794 } 3795 3796 static void 3797 aq_ifmedia_status(struct ifnet * const ifp, struct ifmediareq *ifmr) 3798 { 3799 struct aq_softc * const sc = ifp->if_softc; 3800 3801 /* update ifm_active */ 3802 ifmr->ifm_active = IFM_ETHER; 3803 if (sc->sc_link_fc & AQ_FC_RX) 3804 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 3805 if (sc->sc_link_fc & AQ_FC_TX) 3806 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 3807 3808 /* XXX: need to detect fulldup or halfdup */ 3809 switch (sc->sc_link_rate) { 3810 case AQ_LINK_10M: 3811 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 3812 break; 3813 case AQ_LINK_100M: 3814 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 3815 break; 3816 case AQ_LINK_1G: 3817 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 3818 break; 3819 case AQ_LINK_2G5: 3820 ifmr->ifm_active |= IFM_2500_T | IFM_FDX; 3821 break; 3822 case AQ_LINK_5G: 3823 ifmr->ifm_active |= IFM_5000_T | IFM_FDX; 3824 break; 3825 case AQ_LINK_10G: 3826 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 3827 break; 3828 default: 3829 ifmr->ifm_active |= IFM_NONE; 3830 break; 3831 } 3832 3833 /* update ifm_status */ 3834 ifmr->ifm_status = IFM_AVALID; 3835 if (sc->sc_link_rate != AQ_LINK_NONE) 3836 ifmr->ifm_status |= IFM_ACTIVE; 3837 } 3838 3839 static void 3840 aq_initmedia(struct aq_softc *sc) 3841 { 3842 #define IFMEDIA_ETHER_ADD(sc, media) \ 3843 ifmedia_add(&(sc)->sc_media, IFM_ETHER | media, 0, NULL); 3844 3845 IFMEDIA_ETHER_ADD(sc, IFM_NONE); 3846 3847 if (sc->sc_available_rates & AQ_LINK_10M) { 3848 IFMEDIA_ETHER_ADD(sc, IFM_10_T); 3849 IFMEDIA_ETHER_ADD(sc, IFM_10_T | IFM_FDX); 3850 } 3851 if (sc->sc_available_rates & AQ_LINK_100M) { 3852 IFMEDIA_ETHER_ADD(sc, IFM_100_TX); 3853 IFMEDIA_ETHER_ADD(sc, IFM_100_TX | IFM_FLOW); 3854 IFMEDIA_ETHER_ADD(sc, IFM_100_TX | IFM_FDX | IFM_FLOW); 3855 } 3856 if (sc->sc_available_rates & AQ_LINK_1G) { 3857 IFMEDIA_ETHER_ADD(sc, IFM_1000_T | IFM_FDX); 3858 IFMEDIA_ETHER_ADD(sc, IFM_1000_T | IFM_FDX | IFM_FLOW); 3859 } 3860 if (sc->sc_available_rates & AQ_LINK_2G5) { 3861 IFMEDIA_ETHER_ADD(sc, IFM_2500_T | IFM_FDX); 3862 IFMEDIA_ETHER_ADD(sc, IFM_2500_T | IFM_FDX | IFM_FLOW); 3863 } 3864 if (sc->sc_available_rates & AQ_LINK_5G) { 3865 IFMEDIA_ETHER_ADD(sc, IFM_5000_T | IFM_FDX); 3866 IFMEDIA_ETHER_ADD(sc, IFM_5000_T | IFM_FDX | IFM_FLOW); 3867 } 3868 if (sc->sc_available_rates & AQ_LINK_10G) { 3869 IFMEDIA_ETHER_ADD(sc, IFM_10G_T | IFM_FDX); 3870 IFMEDIA_ETHER_ADD(sc, IFM_10G_T | IFM_FDX | IFM_FLOW); 3871 } 3872 IFMEDIA_ETHER_ADD(sc, IFM_AUTO); 3873 IFMEDIA_ETHER_ADD(sc, IFM_AUTO | IFM_FLOW); 3874 3875 /* default: auto without flowcontrol */ 3876 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 3877 aq_set_linkmode(sc, AQ_LINK_AUTO, AQ_FC_NONE, AQ_EEE_DISABLE); 3878 } 3879 3880 static int 3881 aq_set_linkmode(struct aq_softc *sc, aq_link_speed_t speed, aq_link_fc_t fc, 3882 aq_link_eee_t eee) 3883 { 3884 return sc->sc_fw_ops->set_mode(sc, MPI_INIT, speed, fc, eee); 3885 } 3886 3887 static int 3888 aq_get_linkmode(struct aq_softc *sc, aq_link_speed_t *speed, aq_link_fc_t *fc, 3889 aq_link_eee_t *eee) 3890 { 3891 aq_hw_fw_mpi_state_t mode; 3892 int error; 3893 3894 error = sc->sc_fw_ops->get_mode(sc, &mode, speed, fc, eee); 3895 if (error != 0) 3896 return error; 3897 if (mode != MPI_INIT) 3898 return ENXIO; 3899 3900 return 0; 3901 } 3902 3903 static void 3904 aq_hw_init_tx_path(struct aq_softc *sc) 3905 { 3906 /* Tx TC/RSS number config */ 3907 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_TC_MODE, 3908 (sc->sc_tc_mode == 4) ? 1 : 0); 3909 3910 AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG, 3911 THM_LSO_TCP_FLAG1_FIRST, 0x0ff6); 3912 AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG, 3913 THM_LSO_TCP_FLAG1_MID, 0x0ff6); 3914 AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG2_REG, 3915 THM_LSO_TCP_FLAG2_LAST, 0x0f7f); 3916 3917 /* misc */ 3918 AQ_WRITE_REG(sc, TX_TPO2_REG, 3919 (sc->sc_features & FEATURES_TPO2) ? TX_TPO2_EN : 0); 3920 AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_EN, 0); 3921 AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_MODE, 0); 3922 3923 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_SCP_INS_EN, 1); 3924 3925 if ((sc->sc_features & FEATURES_AQ1_REV_B) || HWTYPE_AQ2_P(sc)) { 3926 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_CLK_GATE_EN, 0); 3927 } 3928 } 3929 3930 static void 3931 aq_hw_init_rx_path(struct aq_softc *sc) 3932 { 3933 int i; 3934 3935 /* Rx TC/RSS number config */ 3936 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 3937 (sc->sc_tc_mode == 4) ? 1 : 0); 3938 3939 /* Rx flow control */ 3940 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 0); 3941 3942 if (HWTYPE_AQ2_P(sc)) { 3943 AQ_WRITE_REG_BIT(sc, AQ2_RPF_REDIR2_REG, 3944 AQ2_RPF_REDIR2_HASHTYPE, AQ2_RPF_REDIR2_HASHTYPE_ALL); 3945 } 3946 3947 if (sc->sc_rss_enable) { 3948 /* RSS Ring selection */ 3949 switch (sc->sc_nqueues) { 3950 case 2: 3951 AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 3952 RX_FLR_RSS_CONTROL1_EN | 0x11111111); 3953 break; 3954 case 4: 3955 AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 3956 RX_FLR_RSS_CONTROL1_EN | 0x22222222); 3957 break; 3958 case 8: 3959 AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 3960 RX_FLR_RSS_CONTROL1_EN | 0x33333333); 3961 break; 3962 } 3963 } else { 3964 /* disable RSS */ 3965 AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 0); 3966 } 3967 3968 if (HWTYPE_AQ1_P(sc)) { 3969 /* multicast filter */ 3970 for (i = 0; i < 32; i++) { 3971 AQ_WRITE_REG_BIT(sc, RPF_ETHERTYPE_FILTER_REG(i), 3972 RPF_ETHERTYPE_FILTER_EN, 0); 3973 } 3974 } 3975 3976 /* L2 and Multicast filters */ 3977 for (i = 0; i < AQ_HW_MAC_NUM(sc); i++) { 3978 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_EN, 0); 3979 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_ACTION, 3980 RPF_ACTION_HOST); 3981 } 3982 AQ_WRITE_REG(sc, RPF_MCAST_FILTER_MASK_REG, 0); 3983 AQ_WRITE_REG(sc, RPF_MCAST_FILTER_REG(0), 0x00010fff); 3984 3985 /* Vlan filters */ 3986 AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_OUTER, 3987 ETHERTYPE_QINQ); 3988 AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_INNER, 3989 ETHERTYPE_VLAN); 3990 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 0); 3991 3992 if ((sc->sc_features & FEATURES_AQ1_REV_B) || HWTYPE_AQ2_P(sc)) { 3993 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, 3994 RPF_VLAN_MODE_ACCEPT_UNTAGGED, 1); 3995 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, 3996 RPF_VLAN_MODE_UNTAGGED_ACTION, RPF_ACTION_HOST); 3997 } 3998 3999 if (HWTYPE_AQ2_P(sc)) { 4000 aq2_init_filter(sc); 4001 } 4002 4003 AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG, 4004 RX_DMA_INT_DESC_WRWB_EN, 1); 4005 4006 if (HWTYPE_AQ1_P(sc)) { 4007 if (sc->sc_features & FEATURES_RPF2) { 4008 AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, 4009 RX_TCP_RSS_HASH_RPF2); 4010 } else { 4011 AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, 0); 4012 } 4013 /* 4014 * XXX: RX_TCP_RSS_HASH_REG: 4015 * linux set 0x000f0000 4016 * freebsd set 0x000f001e 4017 */ 4018 /* RSS hash type set for IP/TCP */ 4019 AQ_WRITE_REG_BIT(sc, RX_TCP_RSS_HASH_REG, 4020 RX_TCP_RSS_HASH_TYPE, 0x001e); 4021 } 4022 4023 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_EN, 1); 4024 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_ACTION, RPF_ACTION_HOST); 4025 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_THRESHOLD, 0xffff); 4026 4027 AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_EN, 0); 4028 AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_MODE, 0); 4029 } 4030 4031 static void 4032 aq_hw_interrupt_moderation_set(struct aq_softc *sc) 4033 { 4034 uint32_t v; 4035 int i; 4036 4037 if (sc->sc_intr_moderation_enable) { 4038 unsigned int tx_min, rx_min; /* 0-255 */ 4039 unsigned int tx_max, rx_max; /* 0-511? */ 4040 4041 switch (sc->sc_link_rate) { 4042 case AQ_LINK_10M: 4043 case AQ_LINK_100M: 4044 tx_min = 0x4f; 4045 tx_max = 0xff; 4046 rx_min = 0x04; 4047 rx_max = 0x50; 4048 break; 4049 case AQ_LINK_1G: 4050 default: 4051 tx_min = 0x4f; 4052 tx_max = 0xff; 4053 rx_min = 0x30; 4054 rx_max = 0x80; 4055 break; 4056 case AQ_LINK_2G5: 4057 tx_min = 0x4f; 4058 tx_max = 0xff; 4059 rx_min = 0x18; 4060 rx_max = 0xe0; 4061 break; 4062 case AQ_LINK_5G: 4063 tx_min = 0x4f; 4064 tx_max = 0xff; 4065 rx_min = 0x0c; 4066 rx_max = 0x70; 4067 break; 4068 case AQ_LINK_10G: 4069 tx_min = 0x4f; 4070 tx_max = 0x1ff; 4071 rx_min = 0x06; /* freebsd use 80 */ 4072 rx_max = 0x38; /* freebsd use 120 */ 4073 break; 4074 } 4075 4076 AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG, 4077 TX_DMA_INT_DESC_WRWB_EN, 0); 4078 AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG, 4079 TX_DMA_INT_DESC_MODERATE_EN, 1); 4080 AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG, 4081 RX_DMA_INT_DESC_WRWB_EN, 0); 4082 AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG, 4083 RX_DMA_INT_DESC_MODERATE_EN, 1); 4084 4085 if (HWTYPE_AQ2_P(sc)) { 4086 v = __SHIFTIN(tx_min, AQ2_TX_INTR_MODERATION_CTL_MIN) | 4087 __SHIFTIN(tx_max, AQ2_TX_INTR_MODERATION_CTL_MAX) | 4088 AQ2_TX_INTR_MODERATION_CTL_EN; 4089 for (i = 0; i < AQ_RINGS_NUM; i++) { 4090 AQ_WRITE_REG(sc, 4091 AQ2_TX_INTR_MODERATION_CTL_REG(i), v); 4092 } 4093 } else { 4094 v = __SHIFTIN(tx_min, TX_INTR_MODERATION_CTL_MIN) | 4095 __SHIFTIN(tx_max, TX_INTR_MODERATION_CTL_MAX) | 4096 TX_INTR_MODERATION_CTL_EN; 4097 for (i = 0; i < AQ_RINGS_NUM; i++) { 4098 AQ_WRITE_REG(sc, 4099 TX_INTR_MODERATION_CTL_REG(i), v); 4100 } 4101 } 4102 4103 for (i = 0; i < AQ_RINGS_NUM; i++) { 4104 AQ_WRITE_REG(sc, RX_INTR_MODERATION_CTL_REG(i), 4105 __SHIFTIN(rx_min, RX_INTR_MODERATION_CTL_MIN) | 4106 __SHIFTIN(rx_max, RX_INTR_MODERATION_CTL_MAX) | 4107 RX_INTR_MODERATION_CTL_EN); 4108 } 4109 4110 } else { 4111 AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG, 4112 TX_DMA_INT_DESC_WRWB_EN, 1); 4113 AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG, 4114 TX_DMA_INT_DESC_MODERATE_EN, 0); 4115 AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG, 4116 RX_DMA_INT_DESC_WRWB_EN, 1); 4117 AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG, 4118 RX_DMA_INT_DESC_MODERATE_EN, 0); 4119 4120 if (HWTYPE_AQ2_P(sc)) { 4121 for (i = 0; i < AQ_RINGS_NUM; i++) { 4122 AQ_WRITE_REG(sc, 4123 AQ2_TX_INTR_MODERATION_CTL_REG(i), 0); 4124 } 4125 } else { 4126 for (i = 0; i < AQ_RINGS_NUM; i++) { 4127 AQ_WRITE_REG(sc, 4128 TX_INTR_MODERATION_CTL_REG(i), 0); 4129 } 4130 } 4131 4132 for (i = 0; i < AQ_RINGS_NUM; i++) { 4133 AQ_WRITE_REG(sc, RX_INTR_MODERATION_CTL_REG(i), 0); 4134 } 4135 } 4136 } 4137 4138 static void 4139 aq_hw_qos_set(struct aq_softc *sc) 4140 { 4141 uint32_t tc, tx_bufsize, rx_bufsize; 4142 4143 /* TPS Descriptor rate init */ 4144 AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_TA_RST, 0); 4145 AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_LIM, 0xa); 4146 4147 /* TPS VM init */ 4148 AQ_WRITE_REG_BIT(sc, TPS_DESC_VM_ARB_MODE_REG, TPS_DESC_VM_ARB_MODE, 0); 4149 4150 /* TPS TC credits init */ 4151 AQ_WRITE_REG_BIT(sc, TPS_DESC_TC_ARB_MODE_REG, TPS_DESC_TC_ARB_MODE, 0); 4152 AQ_WRITE_REG_BIT(sc, TPS_DATA_TC_ARB_MODE_REG, TPS_DATA_TC_ARB_MODE, 0); 4153 4154 if (HWTYPE_AQ1_P(sc)) { 4155 tx_bufsize = AQ1_HW_TXBUF_MAX / sc->sc_tcs; 4156 rx_bufsize = AQ1_HW_RXBUF_MAX / sc->sc_tcs; 4157 } else { 4158 tx_bufsize = AQ2_HW_TXBUF_MAX / sc->sc_tcs; 4159 rx_bufsize = AQ2_HW_RXBUF_MAX / sc->sc_tcs; 4160 } 4161 4162 for (tc = 0; tc < sc->sc_tcs; tc++) { 4163 AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc), 4164 TPS_DATA_TCT_CREDIT_MAX, 0xfff); 4165 AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc), 4166 TPS_DATA_TCT_WEIGHT, 0x64); 4167 AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc), 4168 TPS_DESC_TCT_CREDIT_MAX, 0x50); 4169 AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc), 4170 TPS_DESC_TCT_WEIGHT, 0x1e); 4171 4172 /* Tx buf size */ 4173 AQ_WRITE_REG_BIT(sc, TPB_TXB_BUFSIZE_REG(tc), TPB_TXB_BUFSIZE, 4174 tx_bufsize); 4175 AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_HI, 4176 (tx_bufsize * (1024 / 32) * 66) / 100); 4177 AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_LO, 4178 (tx_bufsize * (1024 / 32) * 50) / 100); 4179 4180 /* QoS Rx buf size per TC */ 4181 AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_EN, 0); 4182 AQ_WRITE_REG_BIT(sc, RPB_RXB_BUFSIZE_REG(tc), RPB_RXB_BUFSIZE, 4183 rx_bufsize); 4184 AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), 4185 RPB_RXB_XOFF_THRESH_HI, 4186 (rx_bufsize * (1024 / 32) * 66) / 100); 4187 AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), 4188 RPB_RXB_XOFF_THRESH_LO, 4189 (rx_bufsize * (1024 / 32) * 50) / 100); 4190 } 4191 4192 /* QoS 802.1p priority -> TC mapping */ 4193 for (int pri = 0; pri < 8; pri++) { 4194 AQ_WRITE_REG_BIT(sc, RPF_RPB_RX_TC_UPT_REG, 4195 RPF_RPB_RX_TC_UPT_MASK(pri), sc->sc_tcs * pri / 8); 4196 } 4197 4198 /* ring to TC mapping */ 4199 if (HWTYPE_AQ2_P(sc)) { 4200 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, 4201 TPB_TX_BUF_TC_Q_RAND_MAP_EN, 1); 4202 switch (sc->sc_tc_mode) { 4203 case 4: 4204 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(0), 0x00000000); 4205 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(1), 0x00000000); 4206 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(2), 0x01010101); 4207 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(3), 0x01010101); 4208 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(4), 0x02020202); 4209 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(5), 0x02020202); 4210 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(6), 0x03030303); 4211 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(7), 0x03030303); 4212 4213 AQ_WRITE_REG(sc, AQ2_RX_Q_TC_MAP_REG(0), 0x00000000); 4214 AQ_WRITE_REG(sc, AQ2_RX_Q_TC_MAP_REG(1), 0x11111111); 4215 AQ_WRITE_REG(sc, AQ2_RX_Q_TC_MAP_REG(2), 0x22222222); 4216 AQ_WRITE_REG(sc, AQ2_RX_Q_TC_MAP_REG(3), 0x33333333); 4217 break; 4218 case 8: 4219 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(0), 0x00000000); 4220 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(1), 0x01010101); 4221 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(2), 0x02020202); 4222 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(3), 0x03030303); 4223 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(4), 0x04040404); 4224 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(5), 0x05050505); 4225 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(6), 0x06060606); 4226 AQ_WRITE_REG(sc, AQ2_TX_Q_TC_MAP_REG(7), 0x07070707); 4227 4228 AQ_WRITE_REG(sc, AQ2_RX_Q_TC_MAP_REG(0), 0x11110000); 4229 AQ_WRITE_REG(sc, AQ2_RX_Q_TC_MAP_REG(1), 0x33332222); 4230 AQ_WRITE_REG(sc, AQ2_RX_Q_TC_MAP_REG(2), 0x55554444); 4231 AQ_WRITE_REG(sc, AQ2_RX_Q_TC_MAP_REG(3), 0x77776666); 4232 break; 4233 } 4234 } 4235 } 4236 4237 static int 4238 aq_init_rss(struct aq_softc *sc) 4239 { 4240 CTASSERT(AQ_RSS_HASHKEY_SIZE == RSS_KEYSIZE); 4241 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4242 uint8_t rss_table[AQ_RSS_INDIRECTION_TABLE_MAX]; 4243 unsigned int i; 4244 int error; 4245 4246 if (HWTYPE_AQ2_P(sc)) { 4247 uint32_t q_per_tc = (sc->sc_tc_mode == 8) ? 4 : 8; 4248 uint32_t tc; 4249 4250 AQ_WRITE_REG_BIT(sc, AQ2_RPF_REDIR2_REG, 4251 AQ2_RPF_REDIR2_INDEX, (sc->sc_tc_mode == 8) ? 1 : 0); 4252 for (i = 0; i < AQ_RSS_INDIRECTION_TABLE_MAX; i++) { 4253 for (tc = 0; tc < sc->sc_tc_mode; tc++) { 4254 uint32_t q = tc * q_per_tc + (i % sc->sc_nqueues); 4255 AQ_WRITE_REG_BIT(sc, AQ2_RPF_RSS_REDIR_REG(tc, i), 4256 AQ2_RPF_RSS_REDIR_TC_MASK(tc), q); 4257 } 4258 } 4259 } 4260 4261 /* initialize rss key */ 4262 rss_getkey((uint8_t *)rss_key); 4263 4264 /* hash to ring table */ 4265 for (i = 0; i < AQ_RSS_INDIRECTION_TABLE_MAX; i++) { 4266 rss_table[i] = i % sc->sc_nqueues; 4267 } 4268 4269 /* 4270 * set rss key 4271 */ 4272 for (i = 0; i < __arraycount(rss_key); i++) { 4273 uint32_t key_data = sc->sc_rss_enable ? ntohl(rss_key[i]) : 0; 4274 AQ_WRITE_REG(sc, RPF_RSS_KEY_WR_DATA_REG, key_data); 4275 AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG, 4276 RPF_RSS_KEY_ADDR, __arraycount(rss_key) - 1 - i); 4277 AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG, 4278 RPF_RSS_KEY_WR_EN, 1); 4279 WAIT_FOR(AQ_READ_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG, 4280 RPF_RSS_KEY_WR_EN) == 0, 1000, 10, &error); 4281 if (error != 0) { 4282 device_printf(sc->sc_dev, "%s: rss key write timeout\n", 4283 __func__); 4284 goto rss_set_timeout; 4285 } 4286 } 4287 4288 /* 4289 * set rss indirection table 4290 * 4291 * AQ's rss redirect table is consist of 3bit*64 (192bit) packed array. 4292 * we'll make it by __BITMAP(3) macros. 4293 */ 4294 __BITMAP_TYPE(, uint16_t, 3 * AQ_RSS_INDIRECTION_TABLE_MAX) bit3x64; 4295 __BITMAP_ZERO(&bit3x64); 4296 4297 #define AQ_3BIT_PACKED_ARRAY_SET(bitmap, idx, val) \ 4298 do { \ 4299 if (val & 1) { \ 4300 __BITMAP_SET((idx) * 3, (bitmap)); \ 4301 } else { \ 4302 __BITMAP_CLR((idx) * 3, (bitmap)); \ 4303 } \ 4304 if (val & 2) { \ 4305 __BITMAP_SET((idx) * 3 + 1, (bitmap)); \ 4306 } else { \ 4307 __BITMAP_CLR((idx) * 3 + 1, (bitmap)); \ 4308 } \ 4309 if (val & 4) { \ 4310 __BITMAP_SET((idx) * 3 + 2, (bitmap)); \ 4311 } else { \ 4312 __BITMAP_CLR((idx) * 3 + 2, (bitmap)); \ 4313 } \ 4314 } while (0 /* CONSTCOND */) 4315 4316 for (i = 0; i < AQ_RSS_INDIRECTION_TABLE_MAX; i++) { 4317 AQ_3BIT_PACKED_ARRAY_SET(&bit3x64, i, rss_table[i]); 4318 } 4319 4320 /* write 192bit data in steps of 16bit */ 4321 for (i = 0; i < (int)__arraycount(bit3x64._b); i++) { 4322 AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_WR_DATA_REG, 4323 RPF_RSS_REDIR_WR_DATA, bit3x64._b[i]); 4324 AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG, 4325 RPF_RSS_REDIR_ADDR, i); 4326 AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG, 4327 RPF_RSS_REDIR_WR_EN, 1); 4328 4329 WAIT_FOR(AQ_READ_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG, 4330 RPF_RSS_REDIR_WR_EN) == 0, 1000, 10, &error); 4331 if (error != 0) 4332 break; 4333 } 4334 4335 rss_set_timeout: 4336 return error; 4337 } 4338 4339 static void 4340 aq1_hw_l3_filter_set(struct aq_softc *sc) 4341 { 4342 int i; 4343 4344 /* clear all filter */ 4345 for (i = 0; i < 8; i++) { 4346 AQ_WRITE_REG_BIT(sc, RPF_L3_FILTER_REG(i), 4347 RPF_L3_FILTER_L4_EN, 0); 4348 } 4349 } 4350 4351 static void 4352 aq_set_vlan_filters(struct aq_softc *sc) 4353 { 4354 struct ethercom * const ec = &sc->sc_ethercom; 4355 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 4356 struct vlanid_list *vlanidp; 4357 int i; 4358 4359 ETHER_LOCK(ec); 4360 4361 /* disable all vlan filters */ 4362 for (i = 0; i < RPF_VLAN_MAX_FILTERS; i++) { 4363 AQ_WRITE_REG(sc, RPF_VLAN_FILTER_REG(i), 0); 4364 if (HWTYPE_AQ2_P(sc)) { 4365 aq2_filter_art_set(sc, AQ2_RPF_INDEX_VLAN_USER + i, 4366 0, 0, AQ2_ART_ACTION_DISABLE); 4367 AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i), 4368 RPF_VLAN_FILTER_TAG, 1); 4369 } 4370 } 4371 4372 /* count VID */ 4373 i = 0; 4374 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) 4375 i++; 4376 4377 if (((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_HWFILTER) == 0) || 4378 (ifp->if_flags & IFF_PROMISC) || 4379 (i > RPF_VLAN_MAX_FILTERS)) { 4380 /* 4381 * no vlan hwfilter, in promiscuous mode, or too many VID? 4382 * must receive all VID 4383 */ 4384 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, 4385 RPF_VLAN_MODE_PROMISC, 1); 4386 goto done; 4387 } 4388 4389 /* receive only selected VID */ 4390 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 0); 4391 i = 0; 4392 SIMPLEQ_FOREACH(vlanidp, &ec->ec_vids, vid_list) { 4393 AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i), 4394 RPF_VLAN_FILTER_EN, 1); 4395 AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i), 4396 RPF_VLAN_FILTER_RXQ_EN, 0); 4397 AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i), 4398 RPF_VLAN_FILTER_RXQ, 0); 4399 AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i), 4400 RPF_VLAN_FILTER_ACTION, RPF_ACTION_HOST); 4401 AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i), 4402 RPF_VLAN_FILTER_ID, vlanidp->vid); 4403 4404 if (HWTYPE_AQ2_P(sc)) { 4405 /* 4406 * If you want to fix the ring (CPU) for each VLAN ID, 4407 * Use AQ2_ART_ACTION_ASSIGN_QUEUE(i % sc->sc_nqueues) 4408 * instead of AQ2_ART_ACTION_ASSIGN_TC(). 4409 */ 4410 uint32_t action = 4411 AQ2_ART_ACTION_ASSIGN_TC(i % sc->sc_nqueues); 4412 4413 AQ_WRITE_REG_BIT(sc, RPF_VLAN_FILTER_REG(i), 4414 RPF_VLAN_FILTER_TAG, i + 2); 4415 aq2_filter_art_set(sc, AQ2_RPF_INDEX_VLAN_USER + i, 4416 __SHIFTIN(i + 2, AQ2_RPF_TAG_VLAN_MASK), 4417 AQ2_RPF_TAG_VLAN_MASK, action); 4418 } 4419 i++; 4420 } 4421 4422 done: 4423 ETHER_UNLOCK(ec); 4424 } 4425 4426 static int 4427 aq_hw_init(struct aq_softc *sc) 4428 { 4429 uint32_t v; 4430 4431 if (HWTYPE_AQ1_P(sc)) { 4432 /* Force limit MRRS on RDM/TDM to 2K */ 4433 v = AQ_READ_REG(sc, AQ_PCI_REG_CONTROL_6_REG); 4434 AQ_WRITE_REG(sc, AQ_PCI_REG_CONTROL_6_REG, 4435 (v & ~0x0707) | 0x0404); 4436 4437 /* 4438 * TX DMA total request limit. B0 hardware is not capable to 4439 * handle more than (8K-MRRS) incoming DMA data. 4440 * Value 24 in 256byte units 4441 */ 4442 AQ_WRITE_REG(sc, AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG, 24); 4443 } 4444 4445 if (HWTYPE_AQ2_P(sc)) { 4446 uint32_t fpgaver, speed; 4447 fpgaver = AQ_READ_REG(sc, AQ2_HW_FPGA_VERSION_REG); 4448 if (fpgaver < 0x01000000) 4449 speed = AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_FULL; 4450 else if (fpgaver >= 0x01008502) 4451 speed = AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_HALF; 4452 else 4453 speed = AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_QUATER; 4454 AQ_WRITE_REG_BIT(sc, AQ2_LAUNCHTIME_CTRL_REG, 4455 AQ2_LAUNCHTIME_CTRL_RATIO, speed); 4456 } 4457 4458 aq_hw_init_tx_path(sc); 4459 aq_hw_init_rx_path(sc); 4460 4461 aq_hw_interrupt_moderation_set(sc); 4462 4463 aq_set_mac_addr(sc, AQ_HW_MAC_OWN, sc->sc_enaddr.ether_addr_octet); 4464 aq_set_linkmode(sc, AQ_LINK_NONE, AQ_FC_NONE, AQ_EEE_DISABLE); 4465 4466 aq_hw_qos_set(sc); 4467 4468 if (HWTYPE_AQ2_P(sc)) { 4469 AQ_WRITE_REG_BIT(sc, AQ2_RPF_NEW_CTRL_REG, 4470 AQ2_RPF_NEW_CTRL_ENABLE, 1); 4471 } 4472 4473 /* Enable interrupt */ 4474 int irqmode; 4475 if (sc->sc_msix) 4476 irqmode = AQ_INTR_CTRL_IRQMODE_MSIX; 4477 else 4478 irqmode = AQ_INTR_CTRL_IRQMODE_MSI; 4479 4480 AQ_WRITE_REG(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS); 4481 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_MULTIVEC, 4482 sc->sc_msix ? 1 : 0); 4483 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_IRQMODE, irqmode); 4484 4485 AQ_WRITE_REG(sc, AQ_INTR_AUTOMASK_REG, 0xffffffff); 4486 4487 AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(0), 4488 ((AQ_B0_ERR_INT << 24) | (1 << 31)) | 4489 ((AQ_B0_ERR_INT << 16) | (1 << 23)) 4490 ); 4491 4492 /* link interrupt */ 4493 if (!sc->sc_msix) 4494 sc->sc_linkstat_irq = AQ_LINKSTAT_IRQ; 4495 AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(3), 4496 __BIT(7) | sc->sc_linkstat_irq); 4497 4498 return 0; 4499 } 4500 4501 static int 4502 aq_update_link_status(struct aq_softc *sc) 4503 { 4504 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 4505 aq_link_speed_t rate = AQ_LINK_NONE; 4506 aq_link_fc_t fc = AQ_FC_NONE; 4507 aq_link_eee_t eee = AQ_EEE_DISABLE; 4508 unsigned int speed; 4509 int changed = 0; 4510 4511 aq_get_linkmode(sc, &rate, &fc, &eee); 4512 4513 if (sc->sc_link_rate != rate) 4514 changed = 1; 4515 if (sc->sc_link_fc != fc) 4516 changed = 1; 4517 if (sc->sc_link_eee != eee) 4518 changed = 1; 4519 4520 if (changed) { 4521 switch (rate) { 4522 case AQ_LINK_10M: 4523 speed = 10; 4524 break; 4525 case AQ_LINK_100M: 4526 speed = 100; 4527 break; 4528 case AQ_LINK_1G: 4529 speed = 1000; 4530 break; 4531 case AQ_LINK_2G5: 4532 speed = 2500; 4533 break; 4534 case AQ_LINK_5G: 4535 speed = 5000; 4536 break; 4537 case AQ_LINK_10G: 4538 speed = 10000; 4539 break; 4540 case AQ_LINK_NONE: 4541 default: 4542 speed = 0; 4543 break; 4544 } 4545 4546 if (sc->sc_link_rate == AQ_LINK_NONE && rate != AQ_LINK_NONE) { 4547 /* link DOWN -> UP */ 4548 device_printf(sc->sc_dev, "link is UP: speed=%u\n", 4549 speed); 4550 if_link_state_change(ifp, LINK_STATE_UP); 4551 } else if (rate == AQ_LINK_NONE) { 4552 /* link UP -> DOWN */ 4553 device_printf(sc->sc_dev, "link is DOWN\n"); 4554 if_link_state_change(ifp, LINK_STATE_DOWN); 4555 } else { 4556 device_printf(sc->sc_dev, 4557 "link mode changed: speed=%u, fc=0x%x, eee=%x\n", 4558 speed, fc, eee); 4559 } 4560 4561 sc->sc_link_rate = rate; 4562 sc->sc_link_fc = fc; 4563 sc->sc_link_eee = eee; 4564 4565 /* update interrupt timing according to new link speed */ 4566 aq_hw_interrupt_moderation_set(sc); 4567 } 4568 4569 return changed; 4570 } 4571 4572 #ifdef AQ_EVENT_COUNTERS 4573 static void 4574 aq_update_statistics(struct aq_softc *sc) 4575 { 4576 int prev = sc->sc_statistics_idx; 4577 int cur = prev ^ 1; 4578 4579 if (sc->sc_fw_ops->get_stats(sc, &sc->sc_statistics[cur]) != 0) 4580 return; 4581 4582 /* 4583 * some aq's internal statistics counters are 32bit. 4584 * cauculate delta, and add to evcount 4585 */ 4586 #define ADD_DELTA(cur, prev, name) \ 4587 do { \ 4588 uint32_t n; \ 4589 n = (uint32_t)(sc->sc_statistics[cur].name - \ 4590 sc->sc_statistics[prev].name); \ 4591 if (n != 0) { \ 4592 AQ_EVCNT_ADD(sc, name, n); \ 4593 } \ 4594 } while (/*CONSTCOND*/0); 4595 4596 ADD_DELTA(cur, prev, uprc); 4597 ADD_DELTA(cur, prev, mprc); 4598 ADD_DELTA(cur, prev, bprc); 4599 ADD_DELTA(cur, prev, prc); 4600 ADD_DELTA(cur, prev, erpr); 4601 ADD_DELTA(cur, prev, uptc); 4602 ADD_DELTA(cur, prev, mptc); 4603 ADD_DELTA(cur, prev, bptc); 4604 ADD_DELTA(cur, prev, ptc); 4605 ADD_DELTA(cur, prev, erpt); 4606 ADD_DELTA(cur, prev, mbtc); 4607 ADD_DELTA(cur, prev, bbtc); 4608 ADD_DELTA(cur, prev, mbrc); 4609 ADD_DELTA(cur, prev, bbrc); 4610 ADD_DELTA(cur, prev, ubrc); 4611 ADD_DELTA(cur, prev, ubtc); 4612 ADD_DELTA(cur, prev, dpc); 4613 ADD_DELTA(cur, prev, cprc); 4614 4615 sc->sc_statistics_idx = cur; 4616 } 4617 #endif /* AQ_EVENT_COUNTERS */ 4618 4619 /* allocate and map one DMA block */ 4620 static int 4621 _alloc_dma(struct aq_softc *sc, bus_size_t size, bus_size_t *sizep, 4622 void **addrp, bus_dmamap_t *mapp, bus_dma_segment_t *seg) 4623 { 4624 int nsegs, error; 4625 4626 if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, seg, 4627 1, &nsegs, 0)) != 0) { 4628 aprint_error_dev(sc->sc_dev, 4629 "unable to allocate DMA buffer, error=%d\n", error); 4630 goto fail_alloc; 4631 } 4632 4633 if ((error = bus_dmamem_map(sc->sc_dmat, seg, 1, size, addrp, 4634 BUS_DMA_COHERENT)) != 0) { 4635 aprint_error_dev(sc->sc_dev, 4636 "unable to map DMA buffer, error=%d\n", error); 4637 goto fail_map; 4638 } 4639 4640 if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 4641 0, mapp)) != 0) { 4642 aprint_error_dev(sc->sc_dev, 4643 "unable to create DMA map, error=%d\n", error); 4644 goto fail_create; 4645 } 4646 4647 if ((error = bus_dmamap_load(sc->sc_dmat, *mapp, *addrp, size, NULL, 4648 0)) != 0) { 4649 aprint_error_dev(sc->sc_dev, 4650 "unable to load DMA map, error=%d\n", error); 4651 goto fail_load; 4652 } 4653 4654 *sizep = size; 4655 return 0; 4656 4657 fail_load: 4658 bus_dmamap_destroy(sc->sc_dmat, *mapp); 4659 *mapp = NULL; 4660 fail_create: 4661 bus_dmamem_unmap(sc->sc_dmat, *addrp, size); 4662 *addrp = NULL; 4663 fail_map: 4664 bus_dmamem_free(sc->sc_dmat, seg, 1); 4665 memset(seg, 0, sizeof(*seg)); 4666 fail_alloc: 4667 *sizep = 0; 4668 return error; 4669 } 4670 4671 static void 4672 _free_dma(struct aq_softc *sc, bus_size_t *sizep, void **addrp, 4673 bus_dmamap_t *mapp, bus_dma_segment_t *seg) 4674 { 4675 if (*mapp != NULL) { 4676 bus_dmamap_destroy(sc->sc_dmat, *mapp); 4677 *mapp = NULL; 4678 } 4679 if (*addrp != NULL) { 4680 bus_dmamem_unmap(sc->sc_dmat, *addrp, *sizep); 4681 *addrp = NULL; 4682 } 4683 if (*sizep != 0) { 4684 bus_dmamem_free(sc->sc_dmat, seg, 1); 4685 memset(seg, 0, sizeof(*seg)); 4686 *sizep = 0; 4687 } 4688 } 4689 4690 static int 4691 aq_txring_alloc(struct aq_softc *sc, struct aq_txring *txring) 4692 { 4693 int i, error; 4694 4695 /* allocate tx descriptors */ 4696 error = _alloc_dma(sc, sizeof(aq_tx_desc_t) * AQ_TXD_NUM, 4697 &txring->txr_txdesc_size, (void **)&txring->txr_txdesc, 4698 &txring->txr_txdesc_dmamap, txring->txr_txdesc_seg); 4699 if (error != 0) 4700 return error; 4701 4702 memset(txring->txr_txdesc, 0, sizeof(aq_tx_desc_t) * AQ_TXD_NUM); 4703 4704 /* fill tx ring with dmamap */ 4705 for (i = 0; i < AQ_TXD_NUM; i++) { 4706 #define AQ_MAXDMASIZE (16 * 1024) 4707 #define AQ_NTXSEGS 32 4708 /* XXX: TODO: error check */ 4709 bus_dmamap_create(sc->sc_dmat, AQ_MAXDMASIZE, AQ_NTXSEGS, 4710 AQ_MAXDMASIZE, 0, 0, &txring->txr_mbufs[i].dmamap); 4711 } 4712 return 0; 4713 } 4714 4715 static void 4716 aq_txring_free(struct aq_softc *sc, struct aq_txring *txring) 4717 { 4718 int i; 4719 4720 _free_dma(sc, &txring->txr_txdesc_size, (void **)&txring->txr_txdesc, 4721 &txring->txr_txdesc_dmamap, txring->txr_txdesc_seg); 4722 4723 for (i = 0; i < AQ_TXD_NUM; i++) { 4724 if (txring->txr_mbufs[i].dmamap != NULL) { 4725 if (txring->txr_mbufs[i].m != NULL) { 4726 bus_dmamap_unload(sc->sc_dmat, 4727 txring->txr_mbufs[i].dmamap); 4728 m_freem(txring->txr_mbufs[i].m); 4729 txring->txr_mbufs[i].m = NULL; 4730 } 4731 bus_dmamap_destroy(sc->sc_dmat, 4732 txring->txr_mbufs[i].dmamap); 4733 txring->txr_mbufs[i].dmamap = NULL; 4734 } 4735 } 4736 } 4737 4738 static int 4739 aq_rxring_alloc(struct aq_softc *sc, struct aq_rxring *rxring) 4740 { 4741 int i, error; 4742 4743 /* allocate rx descriptors */ 4744 error = _alloc_dma(sc, sizeof(aq_rx_desc_t) * AQ_RXD_NUM, 4745 &rxring->rxr_rxdesc_size, (void **)&rxring->rxr_rxdesc, 4746 &rxring->rxr_rxdesc_dmamap, rxring->rxr_rxdesc_seg); 4747 if (error != 0) 4748 return error; 4749 4750 memset(rxring->rxr_rxdesc, 0, sizeof(aq_rx_desc_t) * AQ_RXD_NUM); 4751 4752 /* fill rxring with dmamaps */ 4753 for (i = 0; i < AQ_RXD_NUM; i++) { 4754 rxring->rxr_mbufs[i].m = NULL; 4755 /* XXX: TODO: error check */ 4756 bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 0, 4757 &rxring->rxr_mbufs[i].dmamap); 4758 } 4759 return 0; 4760 } 4761 4762 static void 4763 aq_rxdrain(struct aq_softc *sc, struct aq_rxring *rxring) 4764 { 4765 int i; 4766 4767 /* free all mbufs allocated for RX */ 4768 for (i = 0; i < AQ_RXD_NUM; i++) { 4769 if (rxring->rxr_mbufs[i].m != NULL) { 4770 bus_dmamap_unload(sc->sc_dmat, 4771 rxring->rxr_mbufs[i].dmamap); 4772 m_freem(rxring->rxr_mbufs[i].m); 4773 rxring->rxr_mbufs[i].m = NULL; 4774 } 4775 } 4776 } 4777 4778 static void 4779 aq_rxring_free(struct aq_softc *sc, struct aq_rxring *rxring) 4780 { 4781 int i; 4782 4783 /* free all mbufs and dmamaps */ 4784 aq_rxdrain(sc, rxring); 4785 for (i = 0; i < AQ_RXD_NUM; i++) { 4786 if (rxring->rxr_mbufs[i].dmamap != NULL) { 4787 bus_dmamap_destroy(sc->sc_dmat, 4788 rxring->rxr_mbufs[i].dmamap); 4789 rxring->rxr_mbufs[i].dmamap = NULL; 4790 } 4791 } 4792 4793 /* free RX descriptor */ 4794 _free_dma(sc, &rxring->rxr_rxdesc_size, (void **)&rxring->rxr_rxdesc, 4795 &rxring->rxr_rxdesc_dmamap, rxring->rxr_rxdesc_seg); 4796 } 4797 4798 static void 4799 aq_rxring_setmbuf(struct aq_softc *sc, struct aq_rxring *rxring, int idx, 4800 struct mbuf *m) 4801 { 4802 int error; 4803 4804 /* if mbuf already exists, unload and free */ 4805 if (rxring->rxr_mbufs[idx].m != NULL) { 4806 bus_dmamap_unload(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap); 4807 m_freem(rxring->rxr_mbufs[idx].m); 4808 rxring->rxr_mbufs[idx].m = NULL; 4809 } 4810 4811 rxring->rxr_mbufs[idx].m = m; 4812 4813 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 4814 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap, 4815 m, BUS_DMA_READ | BUS_DMA_NOWAIT); 4816 if (error) { 4817 device_printf(sc->sc_dev, 4818 "unable to load rx DMA map %d, error = %d\n", idx, error); 4819 panic("%s: unable to load rx DMA map. error=%d", 4820 __func__, error); 4821 } 4822 bus_dmamap_sync(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap, 0, 4823 rxring->rxr_mbufs[idx].dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 4824 } 4825 4826 static inline void 4827 aq_rxring_reset_desc(struct aq_softc *sc, struct aq_rxring *rxring, int idx) 4828 { 4829 /* refill rxdesc, and sync */ 4830 rxring->rxr_rxdesc[idx].read.buf_addr = 4831 htole64(rxring->rxr_mbufs[idx].dmamap->dm_segs[0].ds_addr); 4832 rxring->rxr_rxdesc[idx].read.hdr_addr = 0; 4833 bus_dmamap_sync(sc->sc_dmat, rxring->rxr_rxdesc_dmamap, 4834 sizeof(aq_rx_desc_t) * idx, sizeof(aq_rx_desc_t), 4835 BUS_DMASYNC_PREWRITE); 4836 } 4837 4838 static struct mbuf * 4839 aq_alloc_mbuf(void) 4840 { 4841 struct mbuf *m; 4842 4843 MGETHDR(m, M_DONTWAIT, MT_DATA); 4844 if (m == NULL) 4845 return NULL; 4846 4847 MCLGET(m, M_DONTWAIT); 4848 if ((m->m_flags & M_EXT) == 0) { 4849 m_freem(m); 4850 return NULL; 4851 } 4852 4853 return m; 4854 } 4855 4856 /* allocate mbuf and unload dmamap */ 4857 static int 4858 aq_rxring_add(struct aq_softc *sc, struct aq_rxring *rxring, int idx) 4859 { 4860 struct mbuf *m; 4861 4862 m = aq_alloc_mbuf(); 4863 if (m == NULL) 4864 return ENOBUFS; 4865 4866 aq_rxring_setmbuf(sc, rxring, idx, m); 4867 return 0; 4868 } 4869 4870 static int 4871 aq_txrx_rings_alloc(struct aq_softc *sc) 4872 { 4873 int n, error; 4874 4875 for (n = 0; n < sc->sc_nqueues; n++) { 4876 sc->sc_queue[n].sc = sc; 4877 sc->sc_queue[n].txring.txr_sc = sc; 4878 sc->sc_queue[n].txring.txr_index = n; 4879 mutex_init(&sc->sc_queue[n].txring.txr_mutex, MUTEX_DEFAULT, 4880 IPL_NET); 4881 error = aq_txring_alloc(sc, &sc->sc_queue[n].txring); 4882 if (error != 0) 4883 goto failure; 4884 4885 error = aq_tx_pcq_alloc(sc, &sc->sc_queue[n].txring); 4886 if (error != 0) 4887 goto failure; 4888 4889 sc->sc_queue[n].rxring.rxr_sc = sc; 4890 sc->sc_queue[n].rxring.rxr_index = n; 4891 mutex_init(&sc->sc_queue[n].rxring.rxr_mutex, MUTEX_DEFAULT, 4892 IPL_NET); 4893 error = aq_rxring_alloc(sc, &sc->sc_queue[n].rxring); 4894 if (error != 0) 4895 break; 4896 } 4897 4898 failure: 4899 return error; 4900 } 4901 4902 static void 4903 aq_txrx_rings_free(struct aq_softc *sc) 4904 { 4905 int n; 4906 4907 for (n = 0; n < sc->sc_nqueues; n++) { 4908 aq_txring_free(sc, &sc->sc_queue[n].txring); 4909 mutex_destroy(&sc->sc_queue[n].txring.txr_mutex); 4910 4911 aq_tx_pcq_free(sc, &sc->sc_queue[n].txring); 4912 4913 aq_rxring_free(sc, &sc->sc_queue[n].rxring); 4914 mutex_destroy(&sc->sc_queue[n].rxring.rxr_mutex); 4915 } 4916 } 4917 4918 static int 4919 aq_tx_pcq_alloc(struct aq_softc *sc, struct aq_txring *txring) 4920 { 4921 int error = 0; 4922 txring->txr_softint = NULL; 4923 4924 txring->txr_pcq = pcq_create(AQ_TXD_NUM, KM_NOSLEEP); 4925 if (txring->txr_pcq == NULL) { 4926 aprint_error_dev(sc->sc_dev, 4927 "unable to allocate pcq for TXring[%d]\n", 4928 txring->txr_index); 4929 error = ENOMEM; 4930 goto done; 4931 } 4932 4933 txring->txr_softint = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 4934 aq_deferred_transmit, txring); 4935 if (txring->txr_softint == NULL) { 4936 aprint_error_dev(sc->sc_dev, 4937 "unable to establish softint for TXring[%d]\n", 4938 txring->txr_index); 4939 error = ENOENT; 4940 } 4941 4942 done: 4943 return error; 4944 } 4945 4946 static void 4947 aq_tx_pcq_free(struct aq_softc *sc, struct aq_txring *txring) 4948 { 4949 struct mbuf *m; 4950 4951 if (txring->txr_softint != NULL) { 4952 softint_disestablish(txring->txr_softint); 4953 txring->txr_softint = NULL; 4954 } 4955 4956 if (txring->txr_pcq != NULL) { 4957 while ((m = pcq_get(txring->txr_pcq)) != NULL) 4958 m_freem(m); 4959 pcq_destroy(txring->txr_pcq); 4960 txring->txr_pcq = NULL; 4961 } 4962 } 4963 4964 #if NSYSMON_ENVSYS > 0 4965 static void 4966 aq_temp_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 4967 { 4968 struct aq_softc *sc; 4969 uint32_t temp; 4970 int error; 4971 4972 sc = sme->sme_cookie; 4973 4974 error = sc->sc_fw_ops->get_temperature(sc, &temp); 4975 if (error == 0) { 4976 edata->value_cur = temp; 4977 edata->state = ENVSYS_SVALID; 4978 } else { 4979 edata->state = ENVSYS_SINVALID; 4980 } 4981 } 4982 #endif 4983 4984 4985 4986 static bool 4987 aq_watchdog_check(struct aq_softc * const sc) 4988 { 4989 4990 AQ_LOCKED(sc); 4991 4992 bool ok = true; 4993 for (int n = 0; n < sc->sc_nqueues; n++) { 4994 struct aq_txring *txring = &sc->sc_queue[n].txring; 4995 4996 mutex_enter(&txring->txr_mutex); 4997 if (txring->txr_sending && 4998 time_uptime - txring->txr_lastsent > aq_watchdog_timeout) 4999 ok = false; 5000 5001 mutex_exit(&txring->txr_mutex); 5002 5003 if (!ok) 5004 return false; 5005 } 5006 5007 if (sc->sc_trigger_reset) { 5008 /* debug operation, no need for atomicity or reliability */ 5009 sc->sc_trigger_reset = 0; 5010 return false; 5011 } 5012 5013 return true; 5014 } 5015 5016 5017 5018 static bool 5019 aq_watchdog_tick(struct ifnet *ifp) 5020 { 5021 struct aq_softc * const sc = ifp->if_softc; 5022 5023 AQ_LOCKED(sc); 5024 5025 if (!sc->sc_trigger_reset && aq_watchdog_check(sc)) 5026 return true; 5027 5028 if (atomic_swap_uint(&sc->sc_reset_pending, 1) == 0) { 5029 workqueue_enqueue(sc->sc_reset_wq, &sc->sc_reset_work, NULL); 5030 } 5031 5032 return false; 5033 } 5034 5035 static void 5036 aq_tick(void *arg) 5037 { 5038 struct aq_softc * const sc = arg; 5039 5040 AQ_LOCK(sc); 5041 if (sc->sc_stopping) { 5042 AQ_UNLOCK(sc); 5043 return; 5044 } 5045 5046 if (sc->sc_poll_linkstat || sc->sc_detect_linkstat) { 5047 sc->sc_detect_linkstat = false; 5048 aq_update_link_status(sc); 5049 } 5050 5051 #ifdef AQ_EVENT_COUNTERS 5052 if (sc->sc_poll_statistics) 5053 aq_update_statistics(sc); 5054 #endif 5055 5056 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 5057 const bool ok = aq_watchdog_tick(ifp); 5058 if (ok) 5059 callout_schedule(&sc->sc_tick_ch, hz); 5060 5061 AQ_UNLOCK(sc); 5062 } 5063 5064 /* interrupt enable/disable */ 5065 static void 5066 aq_enable_intr(struct aq_softc *sc, bool link, bool txrx) 5067 { 5068 uint32_t imask = 0; 5069 int i; 5070 5071 if (txrx) { 5072 for (i = 0; i < sc->sc_nqueues; i++) { 5073 imask |= __BIT(sc->sc_tx_irq[i]); 5074 imask |= __BIT(sc->sc_rx_irq[i]); 5075 } 5076 } 5077 5078 if (link) 5079 imask |= __BIT(sc->sc_linkstat_irq); 5080 5081 AQ_WRITE_REG(sc, AQ_INTR_MASK_REG, imask); 5082 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff); 5083 } 5084 5085 static int 5086 aq_legacy_intr(void *arg) 5087 { 5088 struct aq_softc *sc = arg; 5089 uint32_t status; 5090 int nintr = 0; 5091 5092 status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG); 5093 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff); 5094 5095 if (status & __BIT(sc->sc_linkstat_irq)) { 5096 AQ_LOCK(sc); 5097 sc->sc_detect_linkstat = true; 5098 if (!sc->sc_stopping) 5099 callout_schedule(&sc->sc_tick_ch, 0); 5100 AQ_UNLOCK(sc); 5101 nintr++; 5102 } 5103 5104 if (status & __BIT(sc->sc_rx_irq[0])) { 5105 nintr += aq_rx_intr(&sc->sc_queue[0].rxring); 5106 } 5107 5108 if (status & __BIT(sc->sc_tx_irq[0])) { 5109 nintr += aq_tx_intr(&sc->sc_queue[0].txring); 5110 } 5111 5112 return nintr; 5113 } 5114 5115 static int 5116 aq_txrx_intr(void *arg) 5117 { 5118 struct aq_queue *queue = arg; 5119 struct aq_softc *sc = queue->sc; 5120 struct aq_txring *txring = &queue->txring; 5121 struct aq_rxring *rxring = &queue->rxring; 5122 uint32_t status; 5123 int nintr = 0; 5124 int txringidx, rxringidx, txirq, rxirq; 5125 5126 txringidx = txring->txr_index; 5127 rxringidx = rxring->rxr_index; 5128 txirq = sc->sc_tx_irq[txringidx]; 5129 rxirq = sc->sc_rx_irq[rxringidx]; 5130 5131 status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG); 5132 if ((status & (__BIT(txirq) | __BIT(rxirq))) == 0) { 5133 /* stray interrupt? */ 5134 return 0; 5135 } 5136 5137 nintr += aq_rx_intr(rxring); 5138 nintr += aq_tx_intr(txring); 5139 5140 return nintr; 5141 } 5142 5143 static int 5144 aq_link_intr(void *arg) 5145 { 5146 struct aq_softc * const sc = arg; 5147 uint32_t status; 5148 int nintr = 0; 5149 5150 status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG); 5151 if (status & __BIT(sc->sc_linkstat_irq)) { 5152 AQ_LOCK(sc); 5153 sc->sc_detect_linkstat = true; 5154 if (!sc->sc_stopping) 5155 callout_schedule(&sc->sc_tick_ch, 0); 5156 AQ_UNLOCK(sc); 5157 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 5158 __BIT(sc->sc_linkstat_irq)); 5159 nintr++; 5160 } 5161 5162 return nintr; 5163 } 5164 5165 static void 5166 aq_txring_reset(struct aq_softc *sc, struct aq_txring *txring, bool start) 5167 { 5168 const int ringidx = txring->txr_index; 5169 int i; 5170 5171 mutex_enter(&txring->txr_mutex); 5172 5173 txring->txr_prodidx = 0; 5174 txring->txr_considx = 0; 5175 txring->txr_nfree = AQ_TXD_NUM; 5176 txring->txr_active = false; 5177 5178 /* free mbufs untransmitted */ 5179 for (i = 0; i < AQ_TXD_NUM; i++) { 5180 if (txring->txr_mbufs[i].m != NULL) { 5181 m_freem(txring->txr_mbufs[i].m); 5182 txring->txr_mbufs[i].m = NULL; 5183 } 5184 } 5185 5186 /* disable DMA */ 5187 AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_EN, 0); 5188 5189 if (start) { 5190 /* TX descriptor physical address */ 5191 paddr_t paddr = txring->txr_txdesc_dmamap->dm_segs[0].ds_addr; 5192 AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr); 5193 AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRMSW_REG(ringidx), 5194 (uint32_t)((uint64_t)paddr >> 32)); 5195 5196 /* TX descriptor size */ 5197 AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_LEN, 5198 AQ_TXD_NUM / 8); 5199 5200 /* reload TAIL pointer */ 5201 txring->txr_prodidx = txring->txr_considx = 5202 AQ_READ_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(ringidx)); 5203 AQ_WRITE_REG(sc, TX_DMA_DESC_WRWB_THRESH_REG(ringidx), 0); 5204 5205 /* Mapping interrupt vector */ 5206 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx), 5207 AQ_INTR_IRQ_MAP_TX_IRQMAP(ringidx), sc->sc_tx_irq[ringidx]); 5208 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx), 5209 AQ_INTR_IRQ_MAP_TX_EN(ringidx), true); 5210 5211 /* enable DMA */ 5212 AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), 5213 TX_DMA_DESC_EN, 1); 5214 5215 const int cpuid = 0; /* XXX? */ 5216 AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx), 5217 TDM_DCAD_CPUID, cpuid); 5218 AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx), 5219 TDM_DCAD_CPUID_EN, 0); 5220 5221 txring->txr_active = true; 5222 } 5223 5224 mutex_exit(&txring->txr_mutex); 5225 } 5226 5227 static int 5228 aq_rxring_reset(struct aq_softc *sc, struct aq_rxring *rxring, bool start) 5229 { 5230 const int ringidx = rxring->rxr_index; 5231 int i; 5232 int error = 0; 5233 5234 mutex_enter(&rxring->rxr_mutex); 5235 rxring->rxr_active = false; 5236 rxring->rxr_discarding = false; 5237 if (rxring->rxr_receiving_m != NULL) { 5238 m_freem(rxring->rxr_receiving_m); 5239 rxring->rxr_receiving_m = NULL; 5240 rxring->rxr_receiving_m_last = NULL; 5241 } 5242 5243 /* disable DMA */ 5244 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_EN, 0); 5245 5246 /* free all RX mbufs */ 5247 aq_rxdrain(sc, rxring); 5248 5249 if (start) { 5250 for (i = 0; i < AQ_RXD_NUM; i++) { 5251 error = aq_rxring_add(sc, rxring, i); 5252 if (error != 0) { 5253 aq_rxdrain(sc, rxring); 5254 return error; 5255 } 5256 aq_rxring_reset_desc(sc, rxring, i); 5257 } 5258 5259 /* RX descriptor physical address */ 5260 paddr_t paddr = rxring->rxr_rxdesc_dmamap->dm_segs[0].ds_addr; 5261 AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr); 5262 AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRMSW_REG(ringidx), 5263 (uint32_t)((uint64_t)paddr >> 32)); 5264 5265 /* RX descriptor size */ 5266 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_LEN, 5267 AQ_RXD_NUM / 8); 5268 5269 /* maximum receive frame size */ 5270 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx), 5271 RX_DMA_DESC_BUFSIZE_DATA, MCLBYTES / 1024); 5272 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx), 5273 RX_DMA_DESC_BUFSIZE_HDR, 0 / 1024); 5274 5275 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), 5276 RX_DMA_DESC_HEADER_SPLIT, 0); 5277 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), 5278 RX_DMA_DESC_VLAN_STRIP, 5279 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) ? 5280 1 : 0); 5281 5282 /* 5283 * reload TAIL pointer, and update readidx 5284 * (HEAD pointer cannot write) 5285 */ 5286 rxring->rxr_readidx = AQ_READ_REG_BIT(sc, 5287 RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR); 5288 AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx), 5289 (rxring->rxr_readidx + AQ_RXD_NUM - 1) % AQ_RXD_NUM); 5290 5291 /* Rx ring set mode */ 5292 5293 /* Mapping interrupt vector */ 5294 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx), 5295 AQ_INTR_IRQ_MAP_RX_IRQMAP(ringidx), sc->sc_rx_irq[ringidx]); 5296 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx), 5297 AQ_INTR_IRQ_MAP_RX_EN(ringidx), 1); 5298 5299 const int cpuid = 0; /* XXX? */ 5300 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx), 5301 RX_DMA_DCAD_CPUID, cpuid); 5302 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx), 5303 RX_DMA_DCAD_DESC_EN, 0); 5304 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx), 5305 RX_DMA_DCAD_HEADER_EN, 0); 5306 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx), 5307 RX_DMA_DCAD_PAYLOAD_EN, 0); 5308 5309 /* enable DMA. start receiving */ 5310 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), 5311 RX_DMA_DESC_EN, 1); 5312 5313 rxring->rxr_active = true; 5314 } 5315 5316 mutex_exit(&rxring->rxr_mutex); 5317 return error; 5318 } 5319 5320 #define TXRING_NEXTIDX(idx) \ 5321 (((idx) >= (AQ_TXD_NUM - 1)) ? 0 : ((idx) + 1)) 5322 #define RXRING_NEXTIDX(idx) \ 5323 (((idx) >= (AQ_RXD_NUM - 1)) ? 0 : ((idx) + 1)) 5324 5325 static int 5326 aq_encap_txring(struct aq_softc *sc, struct aq_txring *txring, struct mbuf *m) 5327 { 5328 bus_dmamap_t map; 5329 uint32_t ctl1, ctl1_ctx, ctl2; 5330 int idx, i, error; 5331 5332 idx = txring->txr_prodidx; 5333 map = txring->txr_mbufs[idx].dmamap; 5334 5335 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 5336 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 5337 if (error == EFBIG) { 5338 struct mbuf *n; 5339 n = m_defrag(m, M_DONTWAIT); 5340 if (n == NULL) 5341 return EFBIG; 5342 /* m_defrag() preserve m */ 5343 KASSERT(n == m); 5344 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 5345 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 5346 } 5347 if (error != 0) 5348 return error; 5349 5350 /* 5351 * check spaces of free descriptors. 5352 * +1 is additional descriptor for context (vlan, etc,.) 5353 */ 5354 if ((map->dm_nsegs + 1) > txring->txr_nfree) { 5355 bus_dmamap_unload(sc->sc_dmat, map); 5356 return EAGAIN; 5357 } 5358 5359 /* sync dma for mbuf */ 5360 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 5361 BUS_DMASYNC_PREWRITE); 5362 5363 ctl1_ctx = 0; 5364 ctl2 = __SHIFTIN(m->m_pkthdr.len, AQ_TXDESC_CTL2_LEN); 5365 5366 if (vlan_has_tag(m)) { 5367 ctl1 = AQ_TXDESC_CTL1_TYPE_TXC; 5368 ctl1 |= __SHIFTIN(vlan_get_tag(m), AQ_TXDESC_CTL1_VID); 5369 5370 ctl1_ctx |= AQ_TXDESC_CTL1_CMD_VLAN; 5371 ctl2 |= AQ_TXDESC_CTL2_CTX_EN; 5372 5373 /* fill context descriptor and forward index */ 5374 txring->txr_txdesc[idx].buf_addr = 0; 5375 txring->txr_txdesc[idx].ctl1 = htole32(ctl1); 5376 txring->txr_txdesc[idx].ctl2 = 0; 5377 5378 idx = TXRING_NEXTIDX(idx); 5379 txring->txr_nfree--; 5380 } 5381 5382 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 5383 ctl1_ctx |= AQ_TXDESC_CTL1_CMD_IP4CSUM; 5384 if (m->m_pkthdr.csum_flags & 5385 (M_CSUM_TCPv4 | M_CSUM_UDPv4 | M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 5386 ctl1_ctx |= AQ_TXDESC_CTL1_CMD_L4CSUM; 5387 } 5388 5389 /* fill descriptor(s) */ 5390 for (i = 0; i < map->dm_nsegs; i++) { 5391 ctl1 = ctl1_ctx | AQ_TXDESC_CTL1_TYPE_TXD | 5392 __SHIFTIN(map->dm_segs[i].ds_len, AQ_TXDESC_CTL1_BLEN); 5393 ctl1 |= AQ_TXDESC_CTL1_CMD_FCS; 5394 5395 if (i == 0) { 5396 /* remember mbuf of these descriptors */ 5397 txring->txr_mbufs[idx].m = m; 5398 } else { 5399 txring->txr_mbufs[idx].m = NULL; 5400 } 5401 5402 if (i == map->dm_nsegs - 1) { 5403 /* last segment, mark an EndOfPacket, and cause intr */ 5404 ctl1 |= AQ_TXDESC_CTL1_EOP | AQ_TXDESC_CTL1_CMD_WB; 5405 } 5406 5407 txring->txr_txdesc[idx].buf_addr = 5408 htole64(map->dm_segs[i].ds_addr); 5409 txring->txr_txdesc[idx].ctl1 = htole32(ctl1); 5410 txring->txr_txdesc[idx].ctl2 = htole32(ctl2); 5411 5412 bus_dmamap_sync(sc->sc_dmat, txring->txr_txdesc_dmamap, 5413 sizeof(aq_tx_desc_t) * idx, sizeof(aq_tx_desc_t), 5414 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5415 5416 idx = TXRING_NEXTIDX(idx); 5417 txring->txr_nfree--; 5418 } 5419 5420 txring->txr_prodidx = idx; 5421 5422 return 0; 5423 } 5424 5425 static int 5426 aq_tx_intr(void *arg) 5427 { 5428 struct aq_txring * const txring = arg; 5429 struct aq_softc * const sc = txring->txr_sc; 5430 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 5431 struct mbuf *m; 5432 const int ringidx = txring->txr_index; 5433 unsigned int idx, hw_head, n = 0; 5434 5435 mutex_enter(&txring->txr_mutex); 5436 5437 if (!txring->txr_active) 5438 goto tx_intr_done; 5439 5440 hw_head = AQ_READ_REG_BIT(sc, TX_DMA_DESC_HEAD_PTR_REG(ringidx), 5441 TX_DMA_DESC_HEAD_PTR); 5442 if (hw_head == txring->txr_considx) { 5443 txring->txr_sending = false; 5444 goto tx_intr_done; 5445 } 5446 5447 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 5448 5449 for (idx = txring->txr_considx; idx != hw_head; 5450 idx = TXRING_NEXTIDX(idx), n++) { 5451 5452 if ((m = txring->txr_mbufs[idx].m) != NULL) { 5453 bus_dmamap_unload(sc->sc_dmat, 5454 txring->txr_mbufs[idx].dmamap); 5455 5456 if_statinc_ref(nsr, if_opackets); 5457 if_statadd_ref(nsr, if_obytes, m->m_pkthdr.len); 5458 if (m->m_flags & M_MCAST) 5459 if_statinc_ref(nsr, if_omcasts); 5460 5461 m_freem(m); 5462 txring->txr_mbufs[idx].m = NULL; 5463 } 5464 5465 txring->txr_nfree++; 5466 } 5467 txring->txr_considx = idx; 5468 5469 IF_STAT_PUTREF(ifp); 5470 5471 /* no more pending TX packet, cancel watchdog */ 5472 if (txring->txr_nfree >= AQ_TXD_NUM) 5473 txring->txr_sending = false; 5474 5475 tx_intr_done: 5476 mutex_exit(&txring->txr_mutex); 5477 5478 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_tx_irq[ringidx])); 5479 return n; 5480 } 5481 5482 static int 5483 aq_rx_intr(void *arg) 5484 { 5485 struct aq_rxring * const rxring = arg; 5486 struct aq_softc * const sc = rxring->rxr_sc; 5487 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 5488 const int ringidx = rxring->rxr_index; 5489 aq_rx_desc_t *rxd; 5490 struct mbuf *m, *m0, *mprev, *new_m; 5491 uint32_t rxd_type, rxd_hash __unused; 5492 uint16_t rxd_status, rxd_pktlen; 5493 uint16_t rxd_nextdescptr __unused, rxd_vlan __unused; 5494 unsigned int idx, n = 0; 5495 bool discarding; 5496 5497 mutex_enter(&rxring->rxr_mutex); 5498 5499 if (!rxring->rxr_active) 5500 goto rx_intr_done; 5501 5502 if (rxring->rxr_readidx == AQ_READ_REG_BIT(sc, 5503 RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR)) { 5504 goto rx_intr_done; 5505 } 5506 5507 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 5508 5509 /* restore ring context */ 5510 discarding = rxring->rxr_discarding; 5511 m0 = rxring->rxr_receiving_m; 5512 mprev = rxring->rxr_receiving_m_last; 5513 5514 for (idx = rxring->rxr_readidx; 5515 idx != AQ_READ_REG_BIT(sc, RX_DMA_DESC_HEAD_PTR_REG(ringidx), 5516 RX_DMA_DESC_HEAD_PTR); idx = RXRING_NEXTIDX(idx), n++) { 5517 5518 bus_dmamap_sync(sc->sc_dmat, rxring->rxr_rxdesc_dmamap, 5519 sizeof(aq_rx_desc_t) * idx, sizeof(aq_rx_desc_t), 5520 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 5521 5522 rxd = &rxring->rxr_rxdesc[idx]; 5523 rxd_status = le16toh(rxd->wb.status); 5524 5525 if ((rxd_status & RXDESC_STATUS_DD) == 0) 5526 break; /* not yet done */ 5527 5528 rxd_type = le32toh(rxd->wb.type); 5529 rxd_pktlen = le16toh(rxd->wb.pkt_len); 5530 rxd_nextdescptr = le16toh(rxd->wb.next_desc_ptr); 5531 rxd_hash = le32toh(rxd->wb.rss_hash); 5532 rxd_vlan = le16toh(rxd->wb.vlan); 5533 5534 /* 5535 * Some segments are being dropped while receiving jumboframe. 5536 * Discard until EOP. 5537 */ 5538 if (discarding) 5539 goto rx_next; 5540 5541 if ((rxd_status & RXDESC_STATUS_MACERR) || 5542 (rxd_type & RXDESC_TYPE_MAC_DMA_ERR)) { 5543 if_statinc_ref(nsr, if_ierrors); 5544 if (m0 != NULL) { 5545 m_freem(m0); 5546 m0 = mprev = NULL; 5547 } 5548 discarding = true; 5549 goto rx_next; 5550 } 5551 5552 bus_dmamap_sync(sc->sc_dmat, rxring->rxr_mbufs[idx].dmamap, 0, 5553 rxring->rxr_mbufs[idx].dmamap->dm_mapsize, 5554 BUS_DMASYNC_POSTREAD); 5555 m = rxring->rxr_mbufs[idx].m; 5556 5557 new_m = aq_alloc_mbuf(); 5558 if (new_m == NULL) { 5559 /* 5560 * cannot allocate new mbuf. 5561 * discard this packet, and reuse mbuf for next. 5562 */ 5563 if_statinc_ref(nsr, if_iqdrops); 5564 if (m0 != NULL) { 5565 m_freem(m0); 5566 m0 = mprev = NULL; 5567 } 5568 discarding = true; 5569 goto rx_next; 5570 } 5571 rxring->rxr_mbufs[idx].m = NULL; 5572 aq_rxring_setmbuf(sc, rxring, idx, new_m); 5573 5574 if (m0 == NULL) { 5575 m0 = m; 5576 } else { 5577 if (m->m_flags & M_PKTHDR) 5578 m_remove_pkthdr(m); 5579 mprev->m_next = m; 5580 } 5581 mprev = m; 5582 5583 if ((rxd_status & RXDESC_STATUS_EOP) == 0) { 5584 /* to be continued in the next segment */ 5585 m->m_len = MCLBYTES; 5586 } else { 5587 /* the last segment */ 5588 int mlen = rxd_pktlen % MCLBYTES; 5589 if (mlen == 0) 5590 mlen = MCLBYTES; 5591 m->m_len = mlen; 5592 m0->m_pkthdr.len = rxd_pktlen; 5593 /* VLAN offloading */ 5594 if ((sc->sc_ethercom.ec_capenable & 5595 ETHERCAP_VLAN_HWTAGGING) && 5596 (__SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_VLAN) || 5597 __SHIFTOUT(rxd_type, 5598 RXDESC_TYPE_PKTTYPE_VLAN_DOUBLE))) { 5599 vlan_set_tag(m0, rxd_vlan); 5600 } 5601 5602 /* Checksum offloading */ 5603 unsigned int pkttype_eth = 5604 __SHIFTOUT(rxd_type, RXDESC_TYPE_PKTTYPE_ETHER); 5605 if ((ifp->if_capabilities & IFCAP_CSUM_IPv4_Rx) && 5606 (pkttype_eth == RXDESC_TYPE_PKTTYPE_ETHER_IPV4) && 5607 __SHIFTOUT(rxd_type, 5608 RXDESC_TYPE_IPV4_CSUM_CHECKED)) { 5609 m0->m_pkthdr.csum_flags |= M_CSUM_IPv4; 5610 if (__SHIFTOUT(rxd_status, 5611 RXDESC_STATUS_IPV4_CSUM_NG)) 5612 m0->m_pkthdr.csum_flags |= 5613 M_CSUM_IPv4_BAD; 5614 } 5615 5616 /* 5617 * aq will always mark BAD for fragment packets, 5618 * but this is not a problem because the IP stack 5619 * ignores the CSUM flag in fragment packets. 5620 */ 5621 if (__SHIFTOUT(rxd_type, 5622 RXDESC_TYPE_TCPUDP_CSUM_CHECKED)) { 5623 bool checked = false; 5624 unsigned int pkttype_proto = 5625 __SHIFTOUT(rxd_type, 5626 RXDESC_TYPE_PKTTYPE_PROTO); 5627 5628 if (pkttype_proto == 5629 RXDESC_TYPE_PKTTYPE_PROTO_TCP) { 5630 if ((pkttype_eth == 5631 RXDESC_TYPE_PKTTYPE_ETHER_IPV4) && 5632 (ifp->if_capabilities & 5633 IFCAP_CSUM_TCPv4_Rx)) { 5634 m0->m_pkthdr.csum_flags |= 5635 M_CSUM_TCPv4; 5636 checked = true; 5637 } else if ((pkttype_eth == 5638 RXDESC_TYPE_PKTTYPE_ETHER_IPV6) && 5639 (ifp->if_capabilities & 5640 IFCAP_CSUM_TCPv6_Rx)) { 5641 m0->m_pkthdr.csum_flags |= 5642 M_CSUM_TCPv6; 5643 checked = true; 5644 } 5645 } else if (pkttype_proto == 5646 RXDESC_TYPE_PKTTYPE_PROTO_UDP) { 5647 if ((pkttype_eth == 5648 RXDESC_TYPE_PKTTYPE_ETHER_IPV4) && 5649 (ifp->if_capabilities & 5650 IFCAP_CSUM_UDPv4_Rx)) { 5651 m0->m_pkthdr.csum_flags |= 5652 M_CSUM_UDPv4; 5653 checked = true; 5654 } else if ((pkttype_eth == 5655 RXDESC_TYPE_PKTTYPE_ETHER_IPV6) && 5656 (ifp->if_capabilities & 5657 IFCAP_CSUM_UDPv6_Rx)) { 5658 m0->m_pkthdr.csum_flags |= 5659 M_CSUM_UDPv6; 5660 checked = true; 5661 } 5662 } 5663 if (checked && 5664 (__SHIFTOUT(rxd_status, 5665 RXDESC_STATUS_TCPUDP_CSUM_ERROR) || 5666 !__SHIFTOUT(rxd_status, 5667 RXDESC_STATUS_TCPUDP_CSUM_OK))) { 5668 m0->m_pkthdr.csum_flags |= 5669 M_CSUM_TCP_UDP_BAD; 5670 } 5671 } 5672 5673 m_set_rcvif(m0, ifp); 5674 if_statinc_ref(nsr, if_ipackets); 5675 if_statadd_ref(nsr, if_ibytes, m0->m_pkthdr.len); 5676 if_percpuq_enqueue(ifp->if_percpuq, m0); 5677 m0 = mprev = NULL; 5678 } 5679 5680 rx_next: 5681 if (discarding && (rxd_status & RXDESC_STATUS_EOP) != 0) 5682 discarding = false; 5683 5684 aq_rxring_reset_desc(sc, rxring, idx); 5685 AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx), idx); 5686 } 5687 /* save ring context */ 5688 rxring->rxr_readidx = idx; 5689 rxring->rxr_discarding = discarding; 5690 rxring->rxr_receiving_m = m0; 5691 rxring->rxr_receiving_m_last = mprev; 5692 5693 IF_STAT_PUTREF(ifp); 5694 5695 rx_intr_done: 5696 mutex_exit(&rxring->rxr_mutex); 5697 5698 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_rx_irq[ringidx])); 5699 return n; 5700 } 5701 5702 static int 5703 aq_vlan_cb(struct ethercom *ec, uint16_t vid, bool set) 5704 { 5705 struct ifnet * const ifp = &ec->ec_if; 5706 struct aq_softc * const sc = ifp->if_softc; 5707 5708 aq_set_vlan_filters(sc); 5709 return 0; 5710 } 5711 5712 static int 5713 aq_ifflags_cb(struct ethercom *ec) 5714 { 5715 struct ifnet * const ifp = &ec->ec_if; 5716 struct aq_softc * const sc = ifp->if_softc; 5717 int i, ecchange, error = 0; 5718 unsigned short iffchange; 5719 5720 AQ_LOCK(sc); 5721 5722 iffchange = ifp->if_flags ^ sc->sc_if_flags; 5723 if ((iffchange & IFF_PROMISC) != 0) 5724 error = aq_set_filter(sc); 5725 5726 ecchange = ec->ec_capenable ^ sc->sc_ec_capenable; 5727 if (ecchange & ETHERCAP_VLAN_HWTAGGING) { 5728 for (i = 0; i < AQ_RINGS_NUM; i++) { 5729 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(i), 5730 RX_DMA_DESC_VLAN_STRIP, 5731 (ec->ec_capenable & ETHERCAP_VLAN_HWTAGGING) ? 5732 1 : 0); 5733 } 5734 } 5735 5736 /* vlan configuration depends on also interface promiscuous mode */ 5737 if ((ecchange & ETHERCAP_VLAN_HWFILTER) || (iffchange & IFF_PROMISC)) 5738 aq_set_vlan_filters(sc); 5739 5740 sc->sc_ec_capenable = ec->ec_capenable; 5741 sc->sc_if_flags = ifp->if_flags; 5742 5743 AQ_UNLOCK(sc); 5744 5745 return error; 5746 } 5747 5748 5749 static int 5750 aq_init(struct ifnet *ifp) 5751 { 5752 struct aq_softc * const sc = ifp->if_softc; 5753 5754 AQ_LOCK(sc); 5755 5756 int ret = aq_init_locked(ifp); 5757 5758 AQ_UNLOCK(sc); 5759 5760 return ret; 5761 } 5762 5763 static int 5764 aq_init_locked(struct ifnet *ifp) 5765 { 5766 struct aq_softc * const sc = ifp->if_softc; 5767 int i, error = 0; 5768 5769 KASSERT(IFNET_LOCKED(ifp)); 5770 AQ_LOCKED(sc); 5771 5772 aq_stop_locked(ifp, false); 5773 5774 aq_set_vlan_filters(sc); 5775 aq_set_capability(sc); 5776 5777 for (i = 0; i < sc->sc_nqueues; i++) { 5778 aq_txring_reset(sc, &sc->sc_queue[i].txring, true); 5779 } 5780 5781 /* invalidate RX descriptor cache */ 5782 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT, 5783 AQ_READ_REG_BIT(sc, 5784 RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT) ^ 1); 5785 5786 /* start RX */ 5787 for (i = 0; i < sc->sc_nqueues; i++) { 5788 error = aq_rxring_reset(sc, &sc->sc_queue[i].rxring, true); 5789 if (error != 0) { 5790 device_printf(sc->sc_dev, "%s: cannot allocate rxbuf\n", 5791 __func__); 5792 goto aq_init_failure; 5793 } 5794 } 5795 aq_init_rss(sc); 5796 if (HWTYPE_AQ1_P(sc)) 5797 aq1_hw_l3_filter_set(sc); 5798 5799 /* ring reset? */ 5800 aq_unset_stopping_flags(sc); 5801 5802 callout_schedule(&sc->sc_tick_ch, hz); 5803 5804 /* ready */ 5805 ifp->if_flags |= IFF_RUNNING; 5806 5807 /* start TX and RX */ 5808 aq_enable_intr(sc, /*link*/true, /*txrx*/true); 5809 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 1); 5810 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 1); 5811 5812 aq_init_failure: 5813 sc->sc_if_flags = ifp->if_flags; 5814 5815 return error; 5816 } 5817 5818 static void 5819 aq_send_common_locked(struct ifnet *ifp, struct aq_softc *sc, 5820 struct aq_txring *txring, bool is_transmit) 5821 { 5822 struct mbuf *m, *n; 5823 int npkt, error; 5824 5825 if (txring->txr_nfree < AQ_TXD_MIN) 5826 return; 5827 5828 for (npkt = 0; ; npkt++) { 5829 if (is_transmit) 5830 m = pcq_peek(txring->txr_pcq); 5831 else 5832 IFQ_POLL(&ifp->if_snd, m); 5833 if (m == NULL) 5834 break; 5835 5836 error = aq_encap_txring(sc, txring, m); 5837 if (error == EAGAIN) { 5838 /* Not enough descriptors available. try again later */ 5839 break; 5840 } 5841 5842 if (is_transmit) 5843 pcq_get(txring->txr_pcq); 5844 else 5845 IFQ_DEQUEUE(&ifp->if_snd, n); 5846 5847 if (error != 0) { 5848 /* too many mbuf chains? or other errors. */ 5849 m_freem(m); 5850 if_statinc(ifp, if_oerrors); 5851 break; 5852 } 5853 5854 /* update tail ptr */ 5855 AQ_WRITE_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(txring->txr_index), 5856 txring->txr_prodidx); 5857 5858 /* Pass the packet to any BPF listeners */ 5859 bpf_mtap(ifp, m, BPF_D_OUT); 5860 } 5861 5862 if (npkt) { 5863 /* Set a watchdog timer in case the chip flakes out. */ 5864 txring->txr_lastsent = time_uptime; 5865 txring->txr_sending = true; 5866 } 5867 } 5868 5869 static void 5870 aq_start(struct ifnet *ifp) 5871 { 5872 struct aq_softc * const sc = ifp->if_softc; 5873 /* aq_start() always use TX ring[0] */ 5874 struct aq_txring * const txring = &sc->sc_queue[0].txring; 5875 5876 mutex_enter(&txring->txr_mutex); 5877 if (txring->txr_active && !txring->txr_stopping) 5878 aq_send_common_locked(ifp, sc, txring, false); 5879 mutex_exit(&txring->txr_mutex); 5880 } 5881 5882 static inline unsigned int 5883 aq_select_txqueue(struct aq_softc *sc, struct mbuf *m) 5884 { 5885 return (cpu_index(curcpu()) % sc->sc_nqueues); 5886 } 5887 5888 static int 5889 aq_transmit(struct ifnet *ifp, struct mbuf *m) 5890 { 5891 struct aq_softc * const sc = ifp->if_softc; 5892 const int ringidx = aq_select_txqueue(sc, m); 5893 struct aq_txring * const txring = &sc->sc_queue[ringidx].txring; 5894 5895 if (__predict_false(!pcq_put(txring->txr_pcq, m))) { 5896 m_freem(m); 5897 return ENOBUFS; 5898 } 5899 5900 if (mutex_tryenter(&txring->txr_mutex)) { 5901 aq_send_common_locked(ifp, sc, txring, true); 5902 mutex_exit(&txring->txr_mutex); 5903 } else { 5904 kpreempt_disable(); 5905 softint_schedule(txring->txr_softint); 5906 kpreempt_enable(); 5907 } 5908 return 0; 5909 } 5910 5911 static void 5912 aq_deferred_transmit(void *arg) 5913 { 5914 struct aq_txring * const txring = arg; 5915 struct aq_softc * const sc = txring->txr_sc; 5916 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 5917 5918 mutex_enter(&txring->txr_mutex); 5919 if (pcq_peek(txring->txr_pcq) != NULL) 5920 aq_send_common_locked(ifp, sc, txring, true); 5921 mutex_exit(&txring->txr_mutex); 5922 } 5923 5924 5925 static void 5926 aq_unset_stopping_flags(struct aq_softc *sc) 5927 { 5928 5929 AQ_LOCKED(sc); 5930 5931 /* Must unset stopping flags in ascending order. */ 5932 for (int i = 0; i < sc->sc_nqueues; i++) { 5933 struct aq_txring *txr = &sc->sc_queue[i].txring; 5934 struct aq_rxring *rxr = &sc->sc_queue[i].rxring; 5935 5936 mutex_enter(&txr->txr_mutex); 5937 txr->txr_stopping = false; 5938 mutex_exit(&txr->txr_mutex); 5939 5940 mutex_enter(&rxr->rxr_mutex); 5941 rxr->rxr_stopping = false; 5942 mutex_exit(&rxr->rxr_mutex); 5943 } 5944 5945 sc->sc_stopping = false; 5946 } 5947 5948 static void 5949 aq_set_stopping_flags(struct aq_softc *sc) 5950 { 5951 5952 AQ_LOCKED(sc); 5953 5954 /* Must unset stopping flags in ascending order. */ 5955 for (int i = 0; i < sc->sc_nqueues; i++) { 5956 struct aq_txring *txr = &sc->sc_queue[i].txring; 5957 struct aq_rxring *rxr = &sc->sc_queue[i].rxring; 5958 5959 mutex_enter(&txr->txr_mutex); 5960 txr->txr_stopping = true; 5961 mutex_exit(&txr->txr_mutex); 5962 5963 mutex_enter(&rxr->rxr_mutex); 5964 rxr->rxr_stopping = true; 5965 mutex_exit(&rxr->rxr_mutex); 5966 } 5967 5968 sc->sc_stopping = true; 5969 } 5970 5971 5972 static void 5973 aq_stop(struct ifnet *ifp, int disable) 5974 { 5975 struct aq_softc * const sc = ifp->if_softc; 5976 5977 ASSERT_SLEEPABLE(); 5978 KASSERT(IFNET_LOCKED(ifp)); 5979 5980 AQ_LOCK(sc); 5981 aq_stop_locked(ifp, disable ? true : false); 5982 AQ_UNLOCK(sc); 5983 } 5984 5985 5986 5987 static void 5988 aq_stop_locked(struct ifnet *ifp, bool disable) 5989 { 5990 struct aq_softc * const sc = ifp->if_softc; 5991 int i; 5992 5993 KASSERT(IFNET_LOCKED(ifp)); 5994 AQ_LOCKED(sc); 5995 5996 aq_set_stopping_flags(sc); 5997 5998 if ((ifp->if_flags & IFF_RUNNING) == 0) 5999 goto already_stopped; 6000 6001 /* disable tx/rx interrupts */ 6002 aq_enable_intr(sc, /*link*/true, /*txrx*/false); 6003 6004 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 0); 6005 for (i = 0; i < sc->sc_nqueues; i++) { 6006 aq_txring_reset(sc, &sc->sc_queue[i].txring, false); 6007 } 6008 6009 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 0); 6010 for (i = 0; i < sc->sc_nqueues; i++) { 6011 aq_rxring_reset(sc, &sc->sc_queue[i].rxring, false); 6012 } 6013 6014 /* invalidate RX descriptor cache */ 6015 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT, 6016 AQ_READ_REG_BIT(sc, 6017 RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT) ^ 1); 6018 6019 already_stopped: 6020 aq_enable_intr(sc, /*link*/false, /*txrx*/false); 6021 callout_halt(&sc->sc_tick_ch, &sc->sc_mutex); 6022 6023 ifp->if_flags &= ~IFF_RUNNING; 6024 sc->sc_if_flags = ifp->if_flags; 6025 } 6026 6027 6028 static void 6029 aq_handle_reset_work(struct work *work, void *arg) 6030 { 6031 struct aq_softc * const sc = arg; 6032 struct ifnet * const ifp = &sc->sc_ethercom.ec_if; 6033 6034 printf("%s: watchdog timeout -- resetting\n", ifp->if_xname); 6035 6036 AQ_LOCK(sc); 6037 6038 device_printf(sc->sc_dev, "%s: INTR_MASK/STATUS = %08x/%08x\n", 6039 __func__, AQ_READ_REG(sc, AQ_INTR_MASK_REG), 6040 AQ_READ_REG(sc, AQ_INTR_STATUS_REG)); 6041 6042 for (int n = 0; n < sc->sc_nqueues; n++) { 6043 struct aq_txring *txring = &sc->sc_queue[n].txring; 6044 u_int head = AQ_READ_REG_BIT(sc, 6045 TX_DMA_DESC_HEAD_PTR_REG(txring->txr_index), 6046 TX_DMA_DESC_HEAD_PTR); 6047 u_int tail = AQ_READ_REG(sc, 6048 TX_DMA_DESC_TAIL_PTR_REG(txring->txr_index)); 6049 6050 device_printf(sc->sc_dev, "%s: TXring[%u] HEAD/TAIL=%u/%u\n", 6051 __func__, txring->txr_index, head, tail); 6052 6053 aq_tx_intr(txring); 6054 } 6055 6056 AQ_UNLOCK(sc); 6057 6058 /* Don't want ioctl operations to happen */ 6059 IFNET_LOCK(ifp); 6060 6061 /* reset the interface. */ 6062 aq_init(ifp); 6063 6064 IFNET_UNLOCK(ifp); 6065 6066 atomic_store_relaxed(&sc->sc_reset_pending, 0); 6067 } 6068 6069 static int 6070 aq_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 6071 { 6072 struct aq_softc * const sc = ifp->if_softc; 6073 struct ifreq * const ifr = data; 6074 int error = 0; 6075 6076 switch (cmd) { 6077 case SIOCADDMULTI: 6078 case SIOCDELMULTI: 6079 break; 6080 default: 6081 KASSERT(IFNET_LOCKED(ifp)); 6082 } 6083 6084 const int s = splnet(); 6085 switch (cmd) { 6086 case SIOCSIFMTU: 6087 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > sc->sc_max_mtu) { 6088 error = EINVAL; 6089 } else { 6090 ifp->if_mtu = ifr->ifr_mtu; 6091 error = 0; /* no need to reset (no ENETRESET) */ 6092 } 6093 break; 6094 default: 6095 error = ether_ioctl(ifp, cmd, data); 6096 break; 6097 } 6098 splx(s); 6099 6100 if (error != ENETRESET) 6101 return error; 6102 6103 switch (cmd) { 6104 case SIOCSIFCAP: 6105 error = aq_set_capability(sc); 6106 break; 6107 case SIOCADDMULTI: 6108 case SIOCDELMULTI: 6109 AQ_LOCK(sc); 6110 if ((sc->sc_if_flags & IFF_RUNNING) != 0) { 6111 /* 6112 * Multicast list has changed; set the hardware filter 6113 * accordingly. 6114 */ 6115 error = aq_set_filter(sc); 6116 } 6117 AQ_UNLOCK(sc); 6118 break; 6119 } 6120 6121 return error; 6122 } 6123 6124 6125 MODULE(MODULE_CLASS_DRIVER, if_aq, "pci"); 6126 6127 #ifdef _MODULE 6128 #include "ioconf.c" 6129 #endif 6130 6131 static int 6132 if_aq_modcmd(modcmd_t cmd, void *opaque) 6133 { 6134 int error = 0; 6135 6136 switch (cmd) { 6137 case MODULE_CMD_INIT: 6138 #ifdef _MODULE 6139 error = config_init_component(cfdriver_ioconf_if_aq, 6140 cfattach_ioconf_if_aq, cfdata_ioconf_if_aq); 6141 #endif 6142 return error; 6143 case MODULE_CMD_FINI: 6144 #ifdef _MODULE 6145 error = config_fini_component(cfdriver_ioconf_if_aq, 6146 cfattach_ioconf_if_aq, cfdata_ioconf_if_aq); 6147 #endif 6148 return error; 6149 default: 6150 return ENOTTY; 6151 } 6152 } 6153