1 /* $NetBSD: if_ale.c,v 1.3 2009/04/28 11:49:15 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 */ 31 32 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.3 2009/04/28 11:49:15 cegger Exp $"); 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/proc.h> 42 #include <sys/endian.h> 43 #include <sys/systm.h> 44 #include <sys/types.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/queue.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/callout.h> 51 #include <sys/socket.h> 52 53 #include <sys/bus.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_llc.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #ifdef INET 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/in_var.h> 65 #include <netinet/ip.h> 66 #endif 67 68 #include <net/if_types.h> 69 #include <net/if_vlanvar.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <sys/rnd.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcidevs.h> 83 84 #include <dev/pci/if_alereg.h> 85 86 static int ale_match(device_t, cfdata_t, void *); 87 static void ale_attach(device_t, device_t, void *); 88 static int ale_detach(device_t, int); 89 90 static int ale_miibus_readreg(device_t, int, int); 91 static void ale_miibus_writereg(device_t, int, int, int); 92 static void ale_miibus_statchg(device_t); 93 94 static int ale_init(struct ifnet *); 95 static void ale_start(struct ifnet *); 96 static int ale_ioctl(struct ifnet *, u_long, void *); 97 static void ale_watchdog(struct ifnet *); 98 static int ale_mediachange(struct ifnet *); 99 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 100 101 static int ale_intr(void *); 102 static int ale_rxeof(struct ale_softc *sc); 103 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 104 uint32_t, uint32_t *); 105 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 106 static void ale_txeof(struct ale_softc *); 107 108 static int ale_dma_alloc(struct ale_softc *); 109 static void ale_dma_free(struct ale_softc *); 110 static int ale_encap(struct ale_softc *, struct mbuf **); 111 static void ale_init_rx_pages(struct ale_softc *); 112 static void ale_init_tx_ring(struct ale_softc *); 113 114 static void ale_stop(struct ifnet *, int); 115 static void ale_tick(void *); 116 static void ale_get_macaddr(struct ale_softc *); 117 static void ale_mac_config(struct ale_softc *); 118 static void ale_phy_reset(struct ale_softc *); 119 static void ale_reset(struct ale_softc *); 120 static void ale_rxfilter(struct ale_softc *); 121 static void ale_rxvlan(struct ale_softc *); 122 static void ale_stats_clear(struct ale_softc *); 123 static void ale_stats_update(struct ale_softc *); 124 static void ale_stop_mac(struct ale_softc *); 125 126 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 127 ale_match, ale_attach, ale_detach, NULL); 128 129 int aledebug = 0; 130 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 ale_miibus_readreg(device_t dev, int phy, int reg) 137 { 138 struct ale_softc *sc = device_private(dev); 139 uint32_t v; 140 int i; 141 142 if (phy != sc->ale_phyaddr) 143 return 0; 144 145 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 146 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 147 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 148 DELAY(5); 149 v = CSR_READ_4(sc, ALE_MDIO); 150 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 151 break; 152 } 153 154 if (i == 0) { 155 printf("%s: phy read timeout: phy %d, reg %d\n", 156 device_xname(sc->sc_dev), phy, reg); 157 return 0; 158 } 159 160 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 161 } 162 163 static void 164 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 165 { 166 struct ale_softc *sc = device_private(dev); 167 uint32_t v; 168 int i; 169 170 if (phy != sc->ale_phyaddr) 171 return; 172 173 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 174 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 175 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 176 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 177 DELAY(5); 178 v = CSR_READ_4(sc, ALE_MDIO); 179 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 180 break; 181 } 182 183 if (i == 0) 184 printf("%s: phy write timeout: phy %d, reg %d\n", 185 device_xname(sc->sc_dev), phy, reg); 186 } 187 188 static void 189 ale_miibus_statchg(device_t dev) 190 { 191 struct ale_softc *sc = device_private(dev); 192 struct ifnet *ifp = &sc->sc_ec.ec_if; 193 struct mii_data *mii; 194 uint32_t reg; 195 196 if ((ifp->if_flags & IFF_RUNNING) == 0) 197 return; 198 199 mii = &sc->sc_miibus; 200 201 sc->ale_flags &= ~ALE_FLAG_LINK; 202 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 203 (IFM_ACTIVE | IFM_AVALID)) { 204 switch (IFM_SUBTYPE(mii->mii_media_active)) { 205 case IFM_10_T: 206 case IFM_100_TX: 207 sc->ale_flags |= ALE_FLAG_LINK; 208 break; 209 210 case IFM_1000_T: 211 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 212 sc->ale_flags |= ALE_FLAG_LINK; 213 break; 214 215 default: 216 break; 217 } 218 } 219 220 /* Stop Rx/Tx MACs. */ 221 ale_stop_mac(sc); 222 223 /* Program MACs with resolved speed/duplex/flow-control. */ 224 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 225 ale_mac_config(sc); 226 /* Reenable Tx/Rx MACs. */ 227 reg = CSR_READ_4(sc, ALE_MAC_CFG); 228 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 229 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 230 } 231 } 232 233 void 234 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 235 { 236 struct ale_softc *sc = ifp->if_softc; 237 struct mii_data *mii = &sc->sc_miibus; 238 239 mii_pollstat(mii); 240 ifmr->ifm_status = mii->mii_media_status; 241 ifmr->ifm_active = mii->mii_media_active; 242 } 243 244 int 245 ale_mediachange(struct ifnet *ifp) 246 { 247 struct ale_softc *sc = ifp->if_softc; 248 struct mii_data *mii = &sc->sc_miibus; 249 int error; 250 251 if (mii->mii_instance != 0) { 252 struct mii_softc *miisc; 253 254 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 255 mii_phy_reset(miisc); 256 } 257 error = mii_mediachg(mii); 258 259 return error; 260 } 261 262 int 263 ale_match(device_t dev, cfdata_t match, void *aux) 264 { 265 struct pci_attach_args *pa = aux; 266 267 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 268 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 269 } 270 271 void 272 ale_get_macaddr(struct ale_softc *sc) 273 { 274 uint32_t ea[2], reg; 275 int i, vpdc; 276 277 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 278 if ((reg & SPI_VPD_ENB) != 0) { 279 reg &= ~SPI_VPD_ENB; 280 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 281 } 282 283 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 284 &vpdc, NULL)) { 285 /* 286 * PCI VPD capability found, let TWSI reload EEPROM. 287 * This will set ethernet address of controller. 288 */ 289 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 290 TWSI_CTRL_SW_LD_START); 291 for (i = 100; i > 0; i--) { 292 DELAY(1000); 293 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 294 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 295 break; 296 } 297 if (i == 0) 298 printf("%s: reloading EEPROM timeout!\n", 299 device_xname(sc->sc_dev)); 300 } else { 301 if (aledebug) 302 printf("%s: PCI VPD capability not found!\n", 303 device_xname(sc->sc_dev)); 304 } 305 306 ea[0] = CSR_READ_4(sc, ALE_PAR0); 307 ea[1] = CSR_READ_4(sc, ALE_PAR1); 308 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 309 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 310 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 311 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 312 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 313 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 314 } 315 316 void 317 ale_phy_reset(struct ale_softc *sc) 318 { 319 /* Reset magic from Linux. */ 320 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 321 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 322 GPHY_CTRL_PHY_PLL_ON); 323 DELAY(1000); 324 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 325 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 326 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 327 DELAY(1000); 328 329 #define ATPHY_DBG_ADDR 0x1D 330 #define ATPHY_DBG_DATA 0x1E 331 332 /* Enable hibernation mode. */ 333 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 334 ATPHY_DBG_ADDR, 0x0B); 335 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 336 ATPHY_DBG_DATA, 0xBC00); 337 /* Set Class A/B for all modes. */ 338 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 339 ATPHY_DBG_ADDR, 0x00); 340 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 341 ATPHY_DBG_DATA, 0x02EF); 342 /* Enable 10BT power saving. */ 343 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 344 ATPHY_DBG_ADDR, 0x12); 345 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 346 ATPHY_DBG_DATA, 0x4C04); 347 /* Adjust 1000T power. */ 348 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 349 ATPHY_DBG_ADDR, 0x04); 350 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 351 ATPHY_DBG_ADDR, 0x8BBB); 352 /* 10BT center tap voltage. */ 353 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 354 ATPHY_DBG_ADDR, 0x05); 355 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 356 ATPHY_DBG_ADDR, 0x2C46); 357 358 #undef ATPHY_DBG_ADDR 359 #undef ATPHY_DBG_DATA 360 DELAY(1000); 361 } 362 363 void 364 ale_attach(device_t parent, device_t self, void *aux) 365 { 366 struct ale_softc *sc = device_private(self); 367 struct pci_attach_args *pa = aux; 368 pci_chipset_tag_t pc = pa->pa_pc; 369 pci_intr_handle_t ih; 370 const char *intrstr; 371 struct ifnet *ifp; 372 pcireg_t memtype; 373 int error = 0; 374 uint32_t rxf_len, txf_len; 375 376 aprint_naive("\n"); 377 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 378 379 sc->sc_dev = self; 380 sc->sc_dmat = pa->pa_dmat; 381 sc->sc_pct = pa->pa_pc; 382 sc->sc_pcitag = pa->pa_tag; 383 384 /* 385 * Allocate IO memory 386 */ 387 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 388 switch (memtype) { 389 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 390 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 391 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 392 break; 393 default: 394 aprint_error_dev(self, "invalid base address register\n"); 395 break; 396 } 397 398 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 399 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 400 aprint_error_dev(self, "could not map mem space\n"); 401 return; 402 } 403 404 if (pci_intr_map(pa, &ih) != 0) { 405 aprint_error_dev(self, "could not map interrupt\n"); 406 goto fail; 407 } 408 409 /* 410 * Allocate IRQ 411 */ 412 intrstr = pci_intr_string(sc->sc_pct, ih); 413 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc); 414 if (sc->sc_irq_handle == NULL) { 415 aprint_error_dev(self, "could not establish interrupt"); 416 if (intrstr != NULL) 417 aprint_error(" at %s", intrstr); 418 aprint_error("\n"); 419 goto fail; 420 } 421 aprint_normal_dev(self, "%s\n", intrstr); 422 423 /* Set PHY address. */ 424 sc->ale_phyaddr = ALE_PHY_ADDR; 425 426 /* Reset PHY. */ 427 ale_phy_reset(sc); 428 429 /* Reset the ethernet controller. */ 430 ale_reset(sc); 431 432 /* Get PCI and chip id/revision. */ 433 sc->ale_rev = PCI_REVISION(pa->pa_class); 434 if (sc->ale_rev >= 0xF0) { 435 /* L2E Rev. B. AR8114 */ 436 sc->ale_flags |= ALE_FLAG_FASTETHER; 437 } else { 438 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 439 /* L1E AR8121 */ 440 sc->ale_flags |= ALE_FLAG_JUMBO; 441 } else { 442 /* L2E Rev. A. AR8113 */ 443 sc->ale_flags |= ALE_FLAG_FASTETHER; 444 } 445 } 446 447 /* 448 * All known controllers seems to require 4 bytes alignment 449 * of Tx buffers to make Tx checksum offload with custom 450 * checksum generation method work. 451 */ 452 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 453 454 /* 455 * All known controllers seems to have issues on Rx checksum 456 * offload for fragmented IP datagrams. 457 */ 458 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 459 460 /* 461 * Don't use Tx CMB. It is known to cause RRS update failure 462 * under certain circumstances. Typical phenomenon of the 463 * issue would be unexpected sequence number encountered in 464 * Rx handler. 465 */ 466 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 467 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 468 MASTER_CHIP_REV_SHIFT; 469 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 470 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 471 472 /* 473 * Uninitialized hardware returns an invalid chip id/revision 474 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 475 */ 476 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 477 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 478 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 479 rxf_len == 0xFFFFFFF) { 480 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 481 "%u Rx FIFO -- not initialized?\n", 482 sc->ale_chip_rev, txf_len, rxf_len); 483 goto fail; 484 } 485 486 if (aledebug) { 487 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 488 txf_len, rxf_len); 489 } 490 491 /* Set max allowable DMA size. */ 492 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 493 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 494 495 callout_init(&sc->sc_tick_ch, 0); 496 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 497 498 error = ale_dma_alloc(sc); 499 if (error) 500 goto fail; 501 502 /* Load station address. */ 503 ale_get_macaddr(sc); 504 505 aprint_normal_dev(self, "Ethernet address %s\n", 506 ether_sprintf(sc->ale_eaddr)); 507 508 ifp = &sc->sc_ec.ec_if; 509 ifp->if_softc = sc; 510 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 511 ifp->if_init = ale_init; 512 ifp->if_ioctl = ale_ioctl; 513 ifp->if_start = ale_start; 514 ifp->if_stop = ale_stop; 515 ifp->if_watchdog = ale_watchdog; 516 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 517 IFQ_SET_READY(&ifp->if_snd); 518 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 519 520 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 521 522 #ifdef ALE_CHECKSUM 523 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 524 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 525 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 526 #endif 527 528 #if NVLAN > 0 529 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 530 #endif 531 532 /* Set up MII bus. */ 533 sc->sc_miibus.mii_ifp = ifp; 534 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 535 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 536 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 537 538 sc->sc_ec.ec_mii = &sc->sc_miibus; 539 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 540 ale_mediastatus); 541 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 542 MII_OFFSET_ANY, 0); 543 544 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 545 aprint_error_dev(self, "no PHY found!\n"); 546 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 547 0, NULL); 548 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 549 } else 550 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 551 552 if_attach(ifp); 553 ether_ifattach(ifp, sc->ale_eaddr); 554 555 if (!pmf_device_register(self, NULL, NULL)) 556 aprint_error_dev(self, "couldn't establish power handler\n"); 557 else 558 pmf_class_network_register(self, ifp); 559 560 return; 561 fail: 562 ale_dma_free(sc); 563 if (sc->sc_irq_handle != NULL) { 564 pci_intr_disestablish(pc, sc->sc_irq_handle); 565 sc->sc_irq_handle = NULL; 566 } 567 if (sc->sc_mem_size) { 568 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 569 sc->sc_mem_size = 0; 570 } 571 } 572 573 static int 574 ale_detach(device_t self, int flags) 575 { 576 struct ale_softc *sc = device_private(self); 577 struct ifnet *ifp = &sc->sc_ec.ec_if; 578 int s; 579 580 pmf_device_deregister(self); 581 s = splnet(); 582 ale_stop(ifp, 0); 583 splx(s); 584 585 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 586 587 /* Delete all remaining media. */ 588 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 589 590 ether_ifdetach(ifp); 591 if_detach(ifp); 592 ale_dma_free(sc); 593 594 if (sc->sc_irq_handle != NULL) { 595 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 596 sc->sc_irq_handle = NULL; 597 } 598 if (sc->sc_mem_size) { 599 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 600 sc->sc_mem_size = 0; 601 } 602 603 return 0; 604 } 605 606 607 static int 608 ale_dma_alloc(struct ale_softc *sc) 609 { 610 struct ale_txdesc *txd; 611 int nsegs, error, guard_size, i; 612 613 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 614 guard_size = ALE_JUMBO_FRAMELEN; 615 else 616 guard_size = ALE_MAX_FRAMELEN; 617 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 618 ALE_RX_PAGE_ALIGN); 619 620 /* 621 * Create DMA stuffs for TX ring 622 */ 623 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 624 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 625 if (error) { 626 sc->ale_cdata.ale_tx_ring_map = NULL; 627 return ENOBUFS; 628 } 629 630 /* Allocate DMA'able memory for TX ring */ 631 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 632 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 633 &nsegs, BUS_DMA_WAITOK); 634 if (error) { 635 printf("%s: could not allocate DMA'able memory for Tx ring, " 636 "error = %i\n", device_xname(sc->sc_dev), error); 637 return error; 638 } 639 640 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 641 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 642 BUS_DMA_NOWAIT); 643 if (error) 644 return ENOBUFS; 645 646 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 647 648 /* Load the DMA map for Tx ring. */ 649 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 650 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 651 if (error) { 652 printf("%s: could not load DMA'able memory for Tx ring.\n", 653 device_xname(sc->sc_dev)); 654 bus_dmamem_free(sc->sc_dmat, 655 &sc->ale_cdata.ale_tx_ring_seg, 1); 656 return error; 657 } 658 sc->ale_cdata.ale_tx_ring_paddr = 659 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 660 661 for (i = 0; i < ALE_RX_PAGES; i++) { 662 /* 663 * Create DMA stuffs for RX pages 664 */ 665 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 666 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 667 &sc->ale_cdata.ale_rx_page[i].page_map); 668 if (error) { 669 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 670 return ENOBUFS; 671 } 672 673 /* Allocate DMA'able memory for RX pages */ 674 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 675 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 676 1, &nsegs, BUS_DMA_WAITOK); 677 if (error) { 678 printf("%s: could not allocate DMA'able memory for " 679 "Rx ring.\n", device_xname(sc->sc_dev)); 680 return error; 681 } 682 error = bus_dmamem_map(sc->sc_dmat, 683 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 684 sc->ale_pagesize, 685 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 686 BUS_DMA_NOWAIT); 687 if (error) 688 return ENOBUFS; 689 690 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 691 sc->ale_pagesize); 692 693 /* Load the DMA map for Rx pages. */ 694 error = bus_dmamap_load(sc->sc_dmat, 695 sc->ale_cdata.ale_rx_page[i].page_map, 696 sc->ale_cdata.ale_rx_page[i].page_addr, 697 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 698 if (error) { 699 printf("%s: could not load DMA'able memory for " 700 "Rx pages.\n", device_xname(sc->sc_dev)); 701 bus_dmamem_free(sc->sc_dmat, 702 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 703 return error; 704 } 705 sc->ale_cdata.ale_rx_page[i].page_paddr = 706 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 707 } 708 709 /* 710 * Create DMA stuffs for Tx CMB. 711 */ 712 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 713 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 714 if (error) { 715 sc->ale_cdata.ale_tx_cmb_map = NULL; 716 return ENOBUFS; 717 } 718 719 /* Allocate DMA'able memory for Tx CMB. */ 720 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 721 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 722 723 if (error) { 724 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 725 device_xname(sc->sc_dev)); 726 return error; 727 } 728 729 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 730 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 731 BUS_DMA_NOWAIT); 732 if (error) 733 return ENOBUFS; 734 735 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 736 737 /* Load the DMA map for Tx CMB. */ 738 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 739 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 740 if (error) { 741 printf("%s: could not load DMA'able memory for Tx CMB.\n", 742 device_xname(sc->sc_dev)); 743 bus_dmamem_free(sc->sc_dmat, 744 &sc->ale_cdata.ale_tx_cmb_seg, 1); 745 return error; 746 } 747 748 sc->ale_cdata.ale_tx_cmb_paddr = 749 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 750 751 for (i = 0; i < ALE_RX_PAGES; i++) { 752 /* 753 * Create DMA stuffs for Rx CMB. 754 */ 755 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 756 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 757 &sc->ale_cdata.ale_rx_page[i].cmb_map); 758 if (error) { 759 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 760 return ENOBUFS; 761 } 762 763 /* Allocate DMA'able memory for Rx CMB */ 764 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 765 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 766 &nsegs, BUS_DMA_WAITOK); 767 if (error) { 768 printf("%s: could not allocate DMA'able memory for " 769 "Rx CMB\n", device_xname(sc->sc_dev)); 770 return error; 771 } 772 error = bus_dmamem_map(sc->sc_dmat, 773 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 774 ALE_RX_CMB_SZ, 775 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 776 BUS_DMA_NOWAIT); 777 if (error) 778 return ENOBUFS; 779 780 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 781 782 /* Load the DMA map for Rx CMB */ 783 error = bus_dmamap_load(sc->sc_dmat, 784 sc->ale_cdata.ale_rx_page[i].cmb_map, 785 sc->ale_cdata.ale_rx_page[i].cmb_addr, 786 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 787 if (error) { 788 printf("%s: could not load DMA'able memory for Rx CMB" 789 "\n", device_xname(sc->sc_dev)); 790 bus_dmamem_free(sc->sc_dmat, 791 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 792 return error; 793 } 794 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 795 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 796 } 797 798 799 /* Create DMA maps for Tx buffers. */ 800 for (i = 0; i < ALE_TX_RING_CNT; i++) { 801 txd = &sc->ale_cdata.ale_txdesc[i]; 802 txd->tx_m = NULL; 803 txd->tx_dmamap = NULL; 804 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 805 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 806 &txd->tx_dmamap); 807 if (error) { 808 txd->tx_dmamap = NULL; 809 printf("%s: could not create Tx dmamap.\n", 810 device_xname(sc->sc_dev)); 811 return error; 812 } 813 } 814 815 return 0; 816 } 817 818 static void 819 ale_dma_free(struct ale_softc *sc) 820 { 821 struct ale_txdesc *txd; 822 int i; 823 824 /* Tx buffers. */ 825 for (i = 0; i < ALE_TX_RING_CNT; i++) { 826 txd = &sc->ale_cdata.ale_txdesc[i]; 827 if (txd->tx_dmamap != NULL) { 828 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 829 txd->tx_dmamap = NULL; 830 } 831 } 832 833 /* Tx descriptor ring. */ 834 if (sc->ale_cdata.ale_tx_ring_map != NULL) 835 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 836 if (sc->ale_cdata.ale_tx_ring_map != NULL && 837 sc->ale_cdata.ale_tx_ring != NULL) 838 bus_dmamem_free(sc->sc_dmat, 839 &sc->ale_cdata.ale_tx_ring_seg, 1); 840 sc->ale_cdata.ale_tx_ring = NULL; 841 sc->ale_cdata.ale_tx_ring_map = NULL; 842 843 /* Rx page block. */ 844 for (i = 0; i < ALE_RX_PAGES; i++) { 845 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 846 bus_dmamap_unload(sc->sc_dmat, 847 sc->ale_cdata.ale_rx_page[i].page_map); 848 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 849 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 850 bus_dmamem_free(sc->sc_dmat, 851 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 852 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 853 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 854 } 855 856 /* Rx CMB. */ 857 for (i = 0; i < ALE_RX_PAGES; i++) { 858 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 859 bus_dmamap_unload(sc->sc_dmat, 860 sc->ale_cdata.ale_rx_page[i].cmb_map); 861 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 862 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 863 bus_dmamem_free(sc->sc_dmat, 864 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 865 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 866 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 867 } 868 869 /* Tx CMB. */ 870 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 871 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 872 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 873 sc->ale_cdata.ale_tx_cmb != NULL) 874 bus_dmamem_free(sc->sc_dmat, 875 &sc->ale_cdata.ale_tx_cmb_seg, 1); 876 sc->ale_cdata.ale_tx_cmb = NULL; 877 sc->ale_cdata.ale_tx_cmb_map = NULL; 878 879 } 880 881 static int 882 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 883 { 884 struct ale_txdesc *txd, *txd_last; 885 struct tx_desc *desc; 886 struct mbuf *m; 887 bus_dmamap_t map; 888 uint32_t cflags, poff, vtag; 889 int error, i, nsegs, prod; 890 #if NVLAN > 0 891 struct m_tag *mtag; 892 #endif 893 894 m = *m_head; 895 cflags = vtag = 0; 896 poff = 0; 897 898 prod = sc->ale_cdata.ale_tx_prod; 899 txd = &sc->ale_cdata.ale_txdesc[prod]; 900 txd_last = txd; 901 map = txd->tx_dmamap; 902 903 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 904 if (error == EFBIG) { 905 error = 0; 906 907 MGETHDR(m, M_DONTWAIT, MT_DATA); 908 if (m == NULL) { 909 printf("%s: can't defrag TX mbuf\n", 910 device_xname(sc->sc_dev)); 911 m_freem(*m_head); 912 *m_head = NULL; 913 return ENOBUFS; 914 } 915 916 M_COPY_PKTHDR(m, *m_head); 917 if ((*m_head)->m_pkthdr.len > MHLEN) { 918 MCLGET(m, M_DONTWAIT); 919 if (!(m->m_flags & M_EXT)) { 920 m_freem(*m_head); 921 m_freem(m); 922 *m_head = NULL; 923 return ENOBUFS; 924 } 925 } 926 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 927 mtod(m, void *)); 928 m_freem(*m_head); 929 m->m_len = m->m_pkthdr.len; 930 *m_head = m; 931 932 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 933 BUS_DMA_NOWAIT); 934 935 if (error != 0) { 936 printf("%s: could not load defragged TX mbuf\n", 937 device_xname(sc->sc_dev)); 938 if (!error) { 939 bus_dmamap_unload(sc->sc_dmat, map); 940 error = EFBIG; 941 } 942 m_freem(*m_head); 943 *m_head = NULL; 944 return error; 945 } 946 } else if (error) { 947 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 948 return error; 949 } 950 951 nsegs = map->dm_nsegs; 952 953 if (nsegs == 0) { 954 m_freem(*m_head); 955 *m_head = NULL; 956 return EIO; 957 } 958 959 /* Check descriptor overrun. */ 960 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 961 bus_dmamap_unload(sc->sc_dmat, map); 962 return ENOBUFS; 963 } 964 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 965 BUS_DMASYNC_PREWRITE); 966 967 m = *m_head; 968 /* Configure Tx checksum offload. */ 969 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 970 /* 971 * AR81xx supports Tx custom checksum offload feature 972 * that offloads single 16bit checksum computation. 973 * So you can choose one among IP, TCP and UDP. 974 * Normally driver sets checksum start/insertion 975 * position from the information of TCP/UDP frame as 976 * TCP/UDP checksum takes more time than that of IP. 977 * However it seems that custom checksum offload 978 * requires 4 bytes aligned Tx buffers due to hardware 979 * bug. 980 * AR81xx also supports explicit Tx checksum computation 981 * if it is told that the size of IP header and TCP 982 * header(for UDP, the header size does not matter 983 * because it's fixed length). However with this scheme 984 * TSO does not work so you have to choose one either 985 * TSO or explicit Tx checksum offload. I chosen TSO 986 * plus custom checksum offload with work-around which 987 * will cover most common usage for this consumer 988 * ethernet controller. The work-around takes a lot of 989 * CPU cycles if Tx buffer is not aligned on 4 bytes 990 * boundary, though. 991 */ 992 cflags |= ALE_TD_CXSUM; 993 /* Set checksum start offset. */ 994 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 995 } 996 997 #if NVLAN > 0 998 /* Configure VLAN hardware tag insertion. */ 999 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1000 vtag = ALE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1001 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1002 cflags |= ALE_TD_INSERT_VLAN_TAG; 1003 } 1004 #endif 1005 1006 desc = NULL; 1007 for (i = 0; i < nsegs; i++) { 1008 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1009 desc->addr = htole64(map->dm_segs[i].ds_addr); 1010 desc->len = 1011 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1012 desc->flags = htole32(cflags); 1013 sc->ale_cdata.ale_tx_cnt++; 1014 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1015 } 1016 /* Update producer index. */ 1017 sc->ale_cdata.ale_tx_prod = prod; 1018 1019 /* Finally set EOP on the last descriptor. */ 1020 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1021 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1022 desc->flags |= htole32(ALE_TD_EOP); 1023 1024 /* Swap dmamap of the first and the last. */ 1025 txd = &sc->ale_cdata.ale_txdesc[prod]; 1026 map = txd_last->tx_dmamap; 1027 txd_last->tx_dmamap = txd->tx_dmamap; 1028 txd->tx_dmamap = map; 1029 txd->tx_m = m; 1030 1031 /* Sync descriptors. */ 1032 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1033 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1034 1035 return 0; 1036 } 1037 1038 static void 1039 ale_start(struct ifnet *ifp) 1040 { 1041 struct ale_softc *sc = ifp->if_softc; 1042 struct mbuf *m_head; 1043 int enq; 1044 1045 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1046 return; 1047 1048 /* Reclaim transmitted frames. */ 1049 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1050 ale_txeof(sc); 1051 1052 enq = 0; 1053 for (;;) { 1054 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1055 if (m_head == NULL) 1056 break; 1057 1058 /* 1059 * Pack the data into the transmit ring. If we 1060 * don't have room, set the OACTIVE flag and wait 1061 * for the NIC to drain the ring. 1062 */ 1063 if (ale_encap(sc, &m_head)) { 1064 if (m_head == NULL) 1065 break; 1066 ifp->if_flags |= IFF_OACTIVE; 1067 break; 1068 } 1069 enq = 1; 1070 1071 #if NBPFILTER > 0 1072 /* 1073 * If there's a BPF listener, bounce a copy of this frame 1074 * to him. 1075 */ 1076 if (ifp->if_bpf != NULL) 1077 bpf_mtap(ifp->if_bpf, m_head); 1078 #endif 1079 } 1080 1081 if (enq) { 1082 /* Kick. */ 1083 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1084 sc->ale_cdata.ale_tx_prod); 1085 1086 /* Set a timeout in case the chip goes out to lunch. */ 1087 ifp->if_timer = ALE_TX_TIMEOUT; 1088 } 1089 } 1090 1091 static void 1092 ale_watchdog(struct ifnet *ifp) 1093 { 1094 struct ale_softc *sc = ifp->if_softc; 1095 1096 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1097 printf("%s: watchdog timeout (missed link)\n", 1098 device_xname(sc->sc_dev)); 1099 ifp->if_oerrors++; 1100 ale_init(ifp); 1101 return; 1102 } 1103 1104 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1105 ifp->if_oerrors++; 1106 ale_init(ifp); 1107 1108 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1109 ale_start(ifp); 1110 } 1111 1112 static int 1113 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1114 { 1115 struct ale_softc *sc = ifp->if_softc; 1116 int s, error; 1117 1118 s = splnet(); 1119 1120 error = ether_ioctl(ifp, cmd, data); 1121 if (error == ENETRESET) { 1122 if (ifp->if_flags & IFF_RUNNING) 1123 ale_rxfilter(sc); 1124 error = 0; 1125 } 1126 1127 splx(s); 1128 return error; 1129 } 1130 1131 static void 1132 ale_mac_config(struct ale_softc *sc) 1133 { 1134 struct mii_data *mii; 1135 uint32_t reg; 1136 1137 mii = &sc->sc_miibus; 1138 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1139 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1140 MAC_CFG_SPEED_MASK); 1141 1142 /* Reprogram MAC with resolved speed/duplex. */ 1143 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1144 case IFM_10_T: 1145 case IFM_100_TX: 1146 reg |= MAC_CFG_SPEED_10_100; 1147 break; 1148 case IFM_1000_T: 1149 reg |= MAC_CFG_SPEED_1000; 1150 break; 1151 } 1152 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1153 reg |= MAC_CFG_FULL_DUPLEX; 1154 #ifdef notyet 1155 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1156 reg |= MAC_CFG_TX_FC; 1157 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1158 reg |= MAC_CFG_RX_FC; 1159 #endif 1160 } 1161 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1162 } 1163 1164 static void 1165 ale_stats_clear(struct ale_softc *sc) 1166 { 1167 struct smb sb; 1168 uint32_t *reg; 1169 int i; 1170 1171 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1172 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1173 i += sizeof(uint32_t); 1174 } 1175 /* Read Tx statistics. */ 1176 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1177 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1178 i += sizeof(uint32_t); 1179 } 1180 } 1181 1182 static void 1183 ale_stats_update(struct ale_softc *sc) 1184 { 1185 struct ifnet *ifp = &sc->sc_ec.ec_if; 1186 struct ale_hw_stats *stat; 1187 struct smb sb, *smb; 1188 uint32_t *reg; 1189 int i; 1190 1191 stat = &sc->ale_stats; 1192 smb = &sb; 1193 1194 /* Read Rx statistics. */ 1195 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1196 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1197 i += sizeof(uint32_t); 1198 } 1199 /* Read Tx statistics. */ 1200 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1201 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1202 i += sizeof(uint32_t); 1203 } 1204 1205 /* Rx stats. */ 1206 stat->rx_frames += smb->rx_frames; 1207 stat->rx_bcast_frames += smb->rx_bcast_frames; 1208 stat->rx_mcast_frames += smb->rx_mcast_frames; 1209 stat->rx_pause_frames += smb->rx_pause_frames; 1210 stat->rx_control_frames += smb->rx_control_frames; 1211 stat->rx_crcerrs += smb->rx_crcerrs; 1212 stat->rx_lenerrs += smb->rx_lenerrs; 1213 stat->rx_bytes += smb->rx_bytes; 1214 stat->rx_runts += smb->rx_runts; 1215 stat->rx_fragments += smb->rx_fragments; 1216 stat->rx_pkts_64 += smb->rx_pkts_64; 1217 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1218 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1219 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1220 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1221 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1222 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1223 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1224 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1225 stat->rx_rrs_errs += smb->rx_rrs_errs; 1226 stat->rx_alignerrs += smb->rx_alignerrs; 1227 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1228 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1229 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1230 1231 /* Tx stats. */ 1232 stat->tx_frames += smb->tx_frames; 1233 stat->tx_bcast_frames += smb->tx_bcast_frames; 1234 stat->tx_mcast_frames += smb->tx_mcast_frames; 1235 stat->tx_pause_frames += smb->tx_pause_frames; 1236 stat->tx_excess_defer += smb->tx_excess_defer; 1237 stat->tx_control_frames += smb->tx_control_frames; 1238 stat->tx_deferred += smb->tx_deferred; 1239 stat->tx_bytes += smb->tx_bytes; 1240 stat->tx_pkts_64 += smb->tx_pkts_64; 1241 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1242 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1243 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1244 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1245 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1246 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1247 stat->tx_single_colls += smb->tx_single_colls; 1248 stat->tx_multi_colls += smb->tx_multi_colls; 1249 stat->tx_late_colls += smb->tx_late_colls; 1250 stat->tx_excess_colls += smb->tx_excess_colls; 1251 stat->tx_abort += smb->tx_abort; 1252 stat->tx_underrun += smb->tx_underrun; 1253 stat->tx_desc_underrun += smb->tx_desc_underrun; 1254 stat->tx_lenerrs += smb->tx_lenerrs; 1255 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1256 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1257 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1258 1259 /* Update counters in ifnet. */ 1260 ifp->if_opackets += smb->tx_frames; 1261 1262 ifp->if_collisions += smb->tx_single_colls + 1263 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1264 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1265 1266 /* 1267 * XXX 1268 * tx_pkts_truncated counter looks suspicious. It constantly 1269 * increments with no sign of Tx errors. This may indicate 1270 * the counter name is not correct one so I've removed the 1271 * counter in output errors. 1272 */ 1273 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1274 smb->tx_underrun; 1275 1276 ifp->if_ipackets += smb->rx_frames; 1277 1278 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1279 smb->rx_runts + smb->rx_pkts_truncated + 1280 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1281 smb->rx_alignerrs; 1282 } 1283 1284 static int 1285 ale_intr(void *xsc) 1286 { 1287 struct ale_softc *sc = xsc; 1288 struct ifnet *ifp = &sc->sc_ec.ec_if; 1289 uint32_t status; 1290 1291 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1292 if ((status & ALE_INTRS) == 0) 1293 return 0; 1294 1295 /* Acknowledge and disable interrupts. */ 1296 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1297 1298 if (ifp->if_flags & IFF_RUNNING) { 1299 int error; 1300 1301 error = ale_rxeof(sc); 1302 if (error) { 1303 sc->ale_stats.reset_brk_seq++; 1304 ale_init(ifp); 1305 return 0; 1306 } 1307 1308 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1309 if (status & INTR_DMA_RD_TO_RST) 1310 printf("%s: DMA read error! -- resetting\n", 1311 device_xname(sc->sc_dev)); 1312 if (status & INTR_DMA_WR_TO_RST) 1313 printf("%s: DMA write error! -- resetting\n", 1314 device_xname(sc->sc_dev)); 1315 ale_init(ifp); 1316 return 0; 1317 } 1318 1319 ale_txeof(sc); 1320 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1321 ale_start(ifp); 1322 } 1323 1324 /* Re-enable interrupts. */ 1325 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1326 return 1; 1327 } 1328 1329 static void 1330 ale_txeof(struct ale_softc *sc) 1331 { 1332 struct ifnet *ifp = &sc->sc_ec.ec_if; 1333 struct ale_txdesc *txd; 1334 uint32_t cons, prod; 1335 int prog; 1336 1337 if (sc->ale_cdata.ale_tx_cnt == 0) 1338 return; 1339 1340 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1341 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1342 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1343 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1344 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1345 BUS_DMASYNC_POSTREAD); 1346 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1347 } else 1348 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1349 cons = sc->ale_cdata.ale_tx_cons; 1350 /* 1351 * Go through our Tx list and free mbufs for those 1352 * frames which have been transmitted. 1353 */ 1354 for (prog = 0; cons != prod; prog++, 1355 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1356 if (sc->ale_cdata.ale_tx_cnt <= 0) 1357 break; 1358 prog++; 1359 ifp->if_flags &= ~IFF_OACTIVE; 1360 sc->ale_cdata.ale_tx_cnt--; 1361 txd = &sc->ale_cdata.ale_txdesc[cons]; 1362 if (txd->tx_m != NULL) { 1363 /* Reclaim transmitted mbufs. */ 1364 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1365 m_freem(txd->tx_m); 1366 txd->tx_m = NULL; 1367 } 1368 } 1369 1370 if (prog > 0) { 1371 sc->ale_cdata.ale_tx_cons = cons; 1372 /* 1373 * Unarm watchdog timer only when there is no pending 1374 * Tx descriptors in queue. 1375 */ 1376 if (sc->ale_cdata.ale_tx_cnt == 0) 1377 ifp->if_timer = 0; 1378 } 1379 } 1380 1381 static void 1382 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1383 uint32_t length, uint32_t *prod) 1384 { 1385 struct ale_rx_page *rx_page; 1386 1387 rx_page = *page; 1388 /* Update consumer position. */ 1389 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1390 ALE_RX_PAGE_ALIGN); 1391 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1392 /* 1393 * End of Rx page reached, let hardware reuse 1394 * this page. 1395 */ 1396 rx_page->cons = 0; 1397 *rx_page->cmb_addr = 0; 1398 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1399 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1400 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1401 RXF_VALID); 1402 /* Switch to alternate Rx page. */ 1403 sc->ale_cdata.ale_rx_curp ^= 1; 1404 rx_page = *page = 1405 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1406 /* Page flipped, sync CMB and Rx page. */ 1407 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1408 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1409 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1410 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1411 /* Sync completed, cache updated producer index. */ 1412 *prod = *rx_page->cmb_addr; 1413 } 1414 } 1415 1416 1417 /* 1418 * It seems that AR81xx controller can compute partial checksum. 1419 * The partial checksum value can be used to accelerate checksum 1420 * computation for fragmented TCP/UDP packets. Upper network stack 1421 * already takes advantage of the partial checksum value in IP 1422 * reassembly stage. But I'm not sure the correctness of the 1423 * partial hardware checksum assistance due to lack of data sheet. 1424 * In addition, the Rx feature of controller that requires copying 1425 * for every frames effectively nullifies one of most nice offload 1426 * capability of controller. 1427 */ 1428 static void 1429 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1430 { 1431 if (status & ALE_RD_IPCSUM_NOK) 1432 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1433 1434 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1435 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1436 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1437 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1438 { 1439 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1440 } 1441 } else { 1442 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1443 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1444 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1445 } 1446 } 1447 } 1448 /* 1449 * Don't mark bad checksum for TCP/UDP frames 1450 * as fragmented frames may always have set 1451 * bad checksummed bit of frame status. 1452 */ 1453 } 1454 1455 /* Process received frames. */ 1456 static int 1457 ale_rxeof(struct ale_softc *sc) 1458 { 1459 struct ifnet *ifp = &sc->sc_ec.ec_if; 1460 struct ale_rx_page *rx_page; 1461 struct rx_rs *rs; 1462 struct mbuf *m; 1463 uint32_t length, prod, seqno, status; 1464 int prog; 1465 1466 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1467 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1468 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1469 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1470 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1471 /* 1472 * Don't directly access producer index as hardware may 1473 * update it while Rx handler is in progress. It would 1474 * be even better if there is a way to let hardware 1475 * know how far driver processed its received frames. 1476 * Alternatively, hardware could provide a way to disable 1477 * CMB updates until driver acknowledges the end of CMB 1478 * access. 1479 */ 1480 prod = *rx_page->cmb_addr; 1481 for (prog = 0; ; prog++) { 1482 if (rx_page->cons >= prod) 1483 break; 1484 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1485 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1486 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1487 /* 1488 * Normally I believe this should not happen unless 1489 * severe driver bug or corrupted memory. However 1490 * it seems to happen under certain conditions which 1491 * is triggered by abrupt Rx events such as initiation 1492 * of bulk transfer of remote host. It's not easy to 1493 * reproduce this and I doubt it could be related 1494 * with FIFO overflow of hardware or activity of Tx 1495 * CMB updates. I also remember similar behaviour 1496 * seen on RealTek 8139 which uses resembling Rx 1497 * scheme. 1498 */ 1499 if (aledebug) 1500 printf("%s: garbled seq: %u, expected: %u -- " 1501 "resetting!\n", device_xname(sc->sc_dev), 1502 seqno, sc->ale_cdata.ale_rx_seqno); 1503 return EIO; 1504 } 1505 /* Frame received. */ 1506 sc->ale_cdata.ale_rx_seqno++; 1507 length = ALE_RX_BYTES(le32toh(rs->length)); 1508 status = le32toh(rs->flags); 1509 if (status & ALE_RD_ERROR) { 1510 /* 1511 * We want to pass the following frames to upper 1512 * layer regardless of error status of Rx return 1513 * status. 1514 * 1515 * o IP/TCP/UDP checksum is bad. 1516 * o frame length and protocol specific length 1517 * does not match. 1518 */ 1519 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1520 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1521 ALE_RD_TRUNC)) { 1522 ale_rx_update_page(sc, &rx_page, length, &prod); 1523 continue; 1524 } 1525 } 1526 /* 1527 * m_devget(9) is major bottle-neck of ale(4)(It comes 1528 * from hardware limitation). For jumbo frames we could 1529 * get a slightly better performance if driver use 1530 * m_getjcl(9) with proper buffer size argument. However 1531 * that would make code more complicated and I don't 1532 * think users would expect good Rx performance numbers 1533 * on these low-end consumer ethernet controller. 1534 */ 1535 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1536 0, ifp, NULL); 1537 if (m == NULL) { 1538 ifp->if_iqdrops++; 1539 ale_rx_update_page(sc, &rx_page, length, &prod); 1540 continue; 1541 } 1542 if (status & ALE_RD_IPV4) 1543 ale_rxcsum(sc, m, status); 1544 #if NVLAN > 0 1545 if (status & ALE_RD_VLAN) { 1546 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1547 VLAN_INPUT_TAG(ifp, m, ALE_RX_VLAN_TAG(vtags), ); 1548 } 1549 #endif 1550 1551 1552 #if NBPFILTER > 0 1553 if (ifp->if_bpf) 1554 bpf_mtap(ifp->if_bpf, m); 1555 #endif 1556 1557 /* Pass it to upper layer. */ 1558 ether_input(ifp, m); 1559 1560 ale_rx_update_page(sc, &rx_page, length, &prod); 1561 } 1562 1563 return 0; 1564 } 1565 1566 static void 1567 ale_tick(void *xsc) 1568 { 1569 struct ale_softc *sc = xsc; 1570 struct mii_data *mii = &sc->sc_miibus; 1571 int s; 1572 1573 s = splnet(); 1574 mii_tick(mii); 1575 ale_stats_update(sc); 1576 splx(s); 1577 1578 callout_schedule(&sc->sc_tick_ch, hz); 1579 } 1580 1581 static void 1582 ale_reset(struct ale_softc *sc) 1583 { 1584 uint32_t reg; 1585 int i; 1586 1587 /* Initialize PCIe module. From Linux. */ 1588 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1589 1590 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1591 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1592 DELAY(10); 1593 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1594 break; 1595 } 1596 if (i == 0) 1597 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1598 1599 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1600 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1601 break; 1602 DELAY(10); 1603 } 1604 1605 if (i == 0) 1606 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1607 reg); 1608 } 1609 1610 static int 1611 ale_init(struct ifnet *ifp) 1612 { 1613 struct ale_softc *sc = ifp->if_softc; 1614 struct mii_data *mii; 1615 uint8_t eaddr[ETHER_ADDR_LEN]; 1616 bus_addr_t paddr; 1617 uint32_t reg, rxf_hi, rxf_lo; 1618 1619 /* 1620 * Cancel any pending I/O. 1621 */ 1622 ale_stop(ifp, 0); 1623 1624 /* 1625 * Reset the chip to a known state. 1626 */ 1627 ale_reset(sc); 1628 1629 /* Initialize Tx descriptors, DMA memory blocks. */ 1630 ale_init_rx_pages(sc); 1631 ale_init_tx_ring(sc); 1632 1633 /* Reprogram the station address. */ 1634 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1635 CSR_WRITE_4(sc, ALE_PAR0, 1636 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1637 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1638 1639 /* 1640 * Clear WOL status and disable all WOL feature as WOL 1641 * would interfere Rx operation under normal environments. 1642 */ 1643 CSR_READ_4(sc, ALE_WOL_CFG); 1644 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1645 1646 /* 1647 * Set Tx descriptor/RXF0/CMB base addresses. They share 1648 * the same high address part of DMAable region. 1649 */ 1650 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1651 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1652 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1653 CSR_WRITE_4(sc, ALE_TPD_CNT, 1654 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1655 1656 /* Set Rx page base address, note we use single queue. */ 1657 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1658 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1659 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1660 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1661 1662 /* Set Tx/Rx CMB addresses. */ 1663 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1664 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1665 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1666 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1667 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1668 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1669 1670 /* Mark RXF0 is valid. */ 1671 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1672 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1673 /* 1674 * No need to initialize RFX1/RXF2/RXF3. We don't use 1675 * multi-queue yet. 1676 */ 1677 1678 /* Set Rx page size, excluding guard frame size. */ 1679 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1680 1681 /* Tell hardware that we're ready to load DMA blocks. */ 1682 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1683 1684 /* Set Rx/Tx interrupt trigger threshold. */ 1685 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1686 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1687 /* 1688 * XXX 1689 * Set interrupt trigger timer, its purpose and relation 1690 * with interrupt moderation mechanism is not clear yet. 1691 */ 1692 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1693 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1694 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1695 1696 /* Configure interrupt moderation timer. */ 1697 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1698 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1699 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1700 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1701 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1702 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1703 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1704 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1705 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1706 reg |= MASTER_IM_RX_TIMER_ENB; 1707 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1708 reg |= MASTER_IM_TX_TIMER_ENB; 1709 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1710 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1711 1712 /* Set Maximum frame size of controller. */ 1713 if (ifp->if_mtu < ETHERMTU) 1714 sc->ale_max_frame_size = ETHERMTU; 1715 else 1716 sc->ale_max_frame_size = ifp->if_mtu; 1717 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1718 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1719 1720 /* Configure IPG/IFG parameters. */ 1721 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1722 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1723 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1724 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1725 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1726 1727 /* Set parameters for half-duplex media. */ 1728 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1729 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1730 HDPX_CFG_LCOL_MASK) | 1731 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1732 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1733 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1734 HDPX_CFG_ABEBT_MASK) | 1735 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1736 HDPX_CFG_JAMIPG_MASK)); 1737 1738 /* Configure Tx jumbo frame parameters. */ 1739 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1740 if (ifp->if_mtu < ETHERMTU) 1741 reg = sc->ale_max_frame_size; 1742 else if (ifp->if_mtu < 6 * 1024) 1743 reg = (sc->ale_max_frame_size * 2) / 3; 1744 else 1745 reg = sc->ale_max_frame_size / 2; 1746 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1747 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1748 TX_JUMBO_THRESH_UNIT_SHIFT); 1749 } 1750 1751 /* Configure TxQ. */ 1752 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1753 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1754 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1755 TXQ_CFG_TPD_BURST_MASK; 1756 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1757 1758 /* Configure Rx jumbo frame & flow control parameters. */ 1759 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1760 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1761 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1762 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1763 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1764 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1765 RX_JUMBO_LKAH_MASK)); 1766 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1767 rxf_hi = (reg * 7) / 10; 1768 rxf_lo = (reg * 3)/ 10; 1769 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1770 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1771 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1772 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1773 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1774 } 1775 1776 /* Disable RSS. */ 1777 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1778 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1779 1780 /* Configure RxQ. */ 1781 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1782 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1783 1784 /* Configure DMA parameters. */ 1785 reg = 0; 1786 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1787 reg |= DMA_CFG_TXCMB_ENB; 1788 CSR_WRITE_4(sc, ALE_DMA_CFG, 1789 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1790 sc->ale_dma_rd_burst | reg | 1791 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1792 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1793 DMA_CFG_RD_DELAY_CNT_MASK) | 1794 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1795 DMA_CFG_WR_DELAY_CNT_MASK)); 1796 1797 /* 1798 * Hardware can be configured to issue SMB interrupt based 1799 * on programmed interval. Since there is a callout that is 1800 * invoked for every hz in driver we use that instead of 1801 * relying on periodic SMB interrupt. 1802 */ 1803 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1804 1805 /* Clear MAC statistics. */ 1806 ale_stats_clear(sc); 1807 1808 /* 1809 * Configure Tx/Rx MACs. 1810 * - Auto-padding for short frames. 1811 * - Enable CRC generation. 1812 * Actual reconfiguration of MAC for resolved speed/duplex 1813 * is followed after detection of link establishment. 1814 * AR81xx always does checksum computation regardless of 1815 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1816 * cause Rx handling issue for fragmented IP datagrams due 1817 * to silicon bug. 1818 */ 1819 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1820 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1821 MAC_CFG_PREAMBLE_MASK); 1822 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1823 reg |= MAC_CFG_SPEED_10_100; 1824 else 1825 reg |= MAC_CFG_SPEED_1000; 1826 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1827 1828 /* Set up the receive filter. */ 1829 ale_rxfilter(sc); 1830 ale_rxvlan(sc); 1831 1832 /* Acknowledge all pending interrupts and clear it. */ 1833 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1834 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1835 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1836 1837 sc->ale_flags &= ~ALE_FLAG_LINK; 1838 1839 /* Switch to the current media. */ 1840 mii = &sc->sc_miibus; 1841 mii_mediachg(mii); 1842 1843 callout_schedule(&sc->sc_tick_ch, hz); 1844 1845 ifp->if_flags |= IFF_RUNNING; 1846 ifp->if_flags &= ~IFF_OACTIVE; 1847 1848 return 0; 1849 } 1850 1851 static void 1852 ale_stop(struct ifnet *ifp, int disable) 1853 { 1854 struct ale_softc *sc = ifp->if_softc; 1855 struct ale_txdesc *txd; 1856 uint32_t reg; 1857 int i; 1858 1859 callout_stop(&sc->sc_tick_ch); 1860 1861 /* 1862 * Mark the interface down and cancel the watchdog timer. 1863 */ 1864 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1865 ifp->if_timer = 0; 1866 1867 sc->ale_flags &= ~ALE_FLAG_LINK; 1868 1869 ale_stats_update(sc); 1870 1871 mii_down(&sc->sc_miibus); 1872 1873 /* Disable interrupts. */ 1874 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1875 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1876 1877 /* Disable queue processing and DMA. */ 1878 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1879 reg &= ~TXQ_CFG_ENB; 1880 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1881 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1882 reg &= ~RXQ_CFG_ENB; 1883 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1884 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1885 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1886 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1887 DELAY(1000); 1888 1889 /* Stop Rx/Tx MACs. */ 1890 ale_stop_mac(sc); 1891 1892 /* Disable interrupts again? XXX */ 1893 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1894 1895 /* 1896 * Free TX mbufs still in the queues. 1897 */ 1898 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1899 txd = &sc->ale_cdata.ale_txdesc[i]; 1900 if (txd->tx_m != NULL) { 1901 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1902 m_freem(txd->tx_m); 1903 txd->tx_m = NULL; 1904 } 1905 } 1906 } 1907 1908 static void 1909 ale_stop_mac(struct ale_softc *sc) 1910 { 1911 uint32_t reg; 1912 int i; 1913 1914 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1915 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1916 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1917 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1918 } 1919 1920 for (i = ALE_TIMEOUT; i > 0; i--) { 1921 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1922 if (reg == 0) 1923 break; 1924 DELAY(10); 1925 } 1926 if (i == 0) 1927 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1928 device_xname(sc->sc_dev), reg); 1929 } 1930 1931 static void 1932 ale_init_tx_ring(struct ale_softc *sc) 1933 { 1934 struct ale_txdesc *txd; 1935 int i; 1936 1937 sc->ale_cdata.ale_tx_prod = 0; 1938 sc->ale_cdata.ale_tx_cons = 0; 1939 sc->ale_cdata.ale_tx_cnt = 0; 1940 1941 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1942 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1943 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1944 txd = &sc->ale_cdata.ale_txdesc[i]; 1945 txd->tx_m = NULL; 1946 } 1947 *sc->ale_cdata.ale_tx_cmb = 0; 1948 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1949 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1950 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1951 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1952 } 1953 1954 static void 1955 ale_init_rx_pages(struct ale_softc *sc) 1956 { 1957 struct ale_rx_page *rx_page; 1958 int i; 1959 1960 sc->ale_cdata.ale_rx_seqno = 0; 1961 sc->ale_cdata.ale_rx_curp = 0; 1962 1963 for (i = 0; i < ALE_RX_PAGES; i++) { 1964 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1965 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1966 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1967 rx_page->cons = 0; 1968 *rx_page->cmb_addr = 0; 1969 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1970 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1971 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1972 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1973 } 1974 } 1975 1976 static void 1977 ale_rxvlan(struct ale_softc *sc) 1978 { 1979 struct ifnet *ifp = &sc->sc_ec.ec_if; 1980 uint32_t reg; 1981 1982 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1983 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1984 if (ifp->if_capabilities & ETHERCAP_VLAN_HWTAGGING) 1985 reg |= MAC_CFG_VLAN_TAG_STRIP; 1986 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1987 } 1988 1989 static void 1990 ale_rxfilter(struct ale_softc *sc) 1991 { 1992 struct ethercom *ec = &sc->sc_ec; 1993 struct ifnet *ifp = &ec->ec_if; 1994 struct ether_multi *enm; 1995 struct ether_multistep step; 1996 uint32_t crc; 1997 uint32_t mchash[2]; 1998 uint32_t rxcfg; 1999 2000 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2001 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2002 2003 /* 2004 * Always accept broadcast frames. 2005 */ 2006 rxcfg |= MAC_CFG_BCAST; 2007 2008 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC || 2009 ec->ec_multicnt > 0) { 2010 allmulti: 2011 if (ifp->if_flags & IFF_PROMISC) 2012 rxcfg |= MAC_CFG_PROMISC; 2013 else 2014 rxcfg |= MAC_CFG_ALLMULTI; 2015 mchash[0] = mchash[1] = 0xFFFFFFFF; 2016 } else { 2017 /* Program new filter. */ 2018 memset(mchash, 0, sizeof(mchash)); 2019 2020 ETHER_FIRST_MULTI(step, ec, enm); 2021 while (enm != NULL) { 2022 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2023 ETHER_ADDR_LEN)) { 2024 ifp->if_flags |= IFF_ALLMULTI; 2025 goto allmulti; 2026 } 2027 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2028 2029 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2030 ETHER_NEXT_MULTI(step, enm); 2031 } 2032 } 2033 2034 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2035 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2036 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2037 } 2038