1 /* $NetBSD: if_ale.c,v 1.24 2018/06/26 06:48:01 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 */ 31 32 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.24 2018/06/26 06:48:01 msaitoh Exp $"); 36 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <sys/bus.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net/if_types.h> 68 #include <net/if_vlanvar.h> 69 70 #include <net/bpf.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_alereg.h> 80 81 static int ale_match(device_t, cfdata_t, void *); 82 static void ale_attach(device_t, device_t, void *); 83 static int ale_detach(device_t, int); 84 85 static int ale_miibus_readreg(device_t, int, int); 86 static void ale_miibus_writereg(device_t, int, int, int); 87 static void ale_miibus_statchg(struct ifnet *); 88 89 static int ale_init(struct ifnet *); 90 static void ale_start(struct ifnet *); 91 static int ale_ioctl(struct ifnet *, u_long, void *); 92 static void ale_watchdog(struct ifnet *); 93 static int ale_mediachange(struct ifnet *); 94 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 95 96 static int ale_intr(void *); 97 static int ale_rxeof(struct ale_softc *sc); 98 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 99 uint32_t, uint32_t *); 100 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 101 static void ale_txeof(struct ale_softc *); 102 103 static int ale_dma_alloc(struct ale_softc *); 104 static void ale_dma_free(struct ale_softc *); 105 static int ale_encap(struct ale_softc *, struct mbuf **); 106 static void ale_init_rx_pages(struct ale_softc *); 107 static void ale_init_tx_ring(struct ale_softc *); 108 109 static void ale_stop(struct ifnet *, int); 110 static void ale_tick(void *); 111 static void ale_get_macaddr(struct ale_softc *); 112 static void ale_mac_config(struct ale_softc *); 113 static void ale_phy_reset(struct ale_softc *); 114 static void ale_reset(struct ale_softc *); 115 static void ale_rxfilter(struct ale_softc *); 116 static void ale_rxvlan(struct ale_softc *); 117 static void ale_stats_clear(struct ale_softc *); 118 static void ale_stats_update(struct ale_softc *); 119 static void ale_stop_mac(struct ale_softc *); 120 121 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 122 ale_match, ale_attach, ale_detach, NULL); 123 124 int aledebug = 0; 125 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 126 127 #define ETHER_ALIGN 2 128 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 129 130 static int 131 ale_miibus_readreg(device_t dev, int phy, int reg) 132 { 133 struct ale_softc *sc = device_private(dev); 134 uint32_t v; 135 int i; 136 137 if (phy != sc->ale_phyaddr) 138 return 0; 139 140 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 141 switch (reg) { 142 case MII_100T2CR: 143 case MII_100T2SR: 144 case MII_EXTSR: 145 return 0; 146 default: 147 break; 148 } 149 } 150 151 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 152 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 153 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 154 DELAY(5); 155 v = CSR_READ_4(sc, ALE_MDIO); 156 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 157 break; 158 } 159 160 if (i == 0) { 161 printf("%s: phy read timeout: phy %d, reg %d\n", 162 device_xname(sc->sc_dev), phy, reg); 163 return 0; 164 } 165 166 return (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 167 } 168 169 static void 170 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 171 { 172 struct ale_softc *sc = device_private(dev); 173 uint32_t v; 174 int i; 175 176 if (phy != sc->ale_phyaddr) 177 return; 178 179 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 180 switch (reg) { 181 case MII_100T2CR: 182 case MII_100T2SR: 183 case MII_EXTSR: 184 return; 185 default: 186 break; 187 } 188 } 189 190 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 191 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 192 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 193 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 194 DELAY(5); 195 v = CSR_READ_4(sc, ALE_MDIO); 196 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 197 break; 198 } 199 200 if (i == 0) 201 printf("%s: phy write timeout: phy %d, reg %d\n", 202 device_xname(sc->sc_dev), phy, reg); 203 } 204 205 static void 206 ale_miibus_statchg(struct ifnet *ifp) 207 { 208 struct ale_softc *sc = ifp->if_softc; 209 struct mii_data *mii = &sc->sc_miibus; 210 uint32_t reg; 211 212 if ((ifp->if_flags & IFF_RUNNING) == 0) 213 return; 214 215 sc->ale_flags &= ~ALE_FLAG_LINK; 216 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 217 (IFM_ACTIVE | IFM_AVALID)) { 218 switch (IFM_SUBTYPE(mii->mii_media_active)) { 219 case IFM_10_T: 220 case IFM_100_TX: 221 sc->ale_flags |= ALE_FLAG_LINK; 222 break; 223 224 case IFM_1000_T: 225 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 226 sc->ale_flags |= ALE_FLAG_LINK; 227 break; 228 229 default: 230 break; 231 } 232 } 233 234 /* Stop Rx/Tx MACs. */ 235 ale_stop_mac(sc); 236 237 /* Program MACs with resolved speed/duplex/flow-control. */ 238 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 239 ale_mac_config(sc); 240 /* Reenable Tx/Rx MACs. */ 241 reg = CSR_READ_4(sc, ALE_MAC_CFG); 242 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 243 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 244 } 245 } 246 247 void 248 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 249 { 250 struct ale_softc *sc = ifp->if_softc; 251 struct mii_data *mii = &sc->sc_miibus; 252 253 mii_pollstat(mii); 254 ifmr->ifm_status = mii->mii_media_status; 255 ifmr->ifm_active = mii->mii_media_active; 256 } 257 258 int 259 ale_mediachange(struct ifnet *ifp) 260 { 261 struct ale_softc *sc = ifp->if_softc; 262 struct mii_data *mii = &sc->sc_miibus; 263 int error; 264 265 if (mii->mii_instance != 0) { 266 struct mii_softc *miisc; 267 268 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 269 mii_phy_reset(miisc); 270 } 271 error = mii_mediachg(mii); 272 273 return error; 274 } 275 276 int 277 ale_match(device_t dev, cfdata_t match, void *aux) 278 { 279 struct pci_attach_args *pa = aux; 280 281 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 282 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 283 } 284 285 void 286 ale_get_macaddr(struct ale_softc *sc) 287 { 288 uint32_t ea[2], reg; 289 int i, vpdc; 290 291 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 292 if ((reg & SPI_VPD_ENB) != 0) { 293 reg &= ~SPI_VPD_ENB; 294 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 295 } 296 297 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 298 &vpdc, NULL)) { 299 /* 300 * PCI VPD capability found, let TWSI reload EEPROM. 301 * This will set ethernet address of controller. 302 */ 303 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 304 TWSI_CTRL_SW_LD_START); 305 for (i = 100; i > 0; i--) { 306 DELAY(1000); 307 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 308 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 309 break; 310 } 311 if (i == 0) 312 printf("%s: reloading EEPROM timeout!\n", 313 device_xname(sc->sc_dev)); 314 } else { 315 if (aledebug) 316 printf("%s: PCI VPD capability not found!\n", 317 device_xname(sc->sc_dev)); 318 } 319 320 ea[0] = CSR_READ_4(sc, ALE_PAR0); 321 ea[1] = CSR_READ_4(sc, ALE_PAR1); 322 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 323 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 324 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 325 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 326 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 327 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 328 } 329 330 void 331 ale_phy_reset(struct ale_softc *sc) 332 { 333 /* Reset magic from Linux. */ 334 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 335 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 336 GPHY_CTRL_PHY_PLL_ON); 337 DELAY(1000); 338 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 339 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 340 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 341 DELAY(1000); 342 343 #define ATPHY_DBG_ADDR 0x1D 344 #define ATPHY_DBG_DATA 0x1E 345 346 /* Enable hibernation mode. */ 347 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 348 ATPHY_DBG_ADDR, 0x0B); 349 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 350 ATPHY_DBG_DATA, 0xBC00); 351 /* Set Class A/B for all modes. */ 352 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 353 ATPHY_DBG_ADDR, 0x00); 354 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 355 ATPHY_DBG_DATA, 0x02EF); 356 /* Enable 10BT power saving. */ 357 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 358 ATPHY_DBG_ADDR, 0x12); 359 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 360 ATPHY_DBG_DATA, 0x4C04); 361 /* Adjust 1000T power. */ 362 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 363 ATPHY_DBG_ADDR, 0x04); 364 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 365 ATPHY_DBG_DATA, 0x8BBB); 366 /* 10BT center tap voltage. */ 367 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 368 ATPHY_DBG_ADDR, 0x05); 369 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 370 ATPHY_DBG_DATA, 0x2C46); 371 372 #undef ATPHY_DBG_ADDR 373 #undef ATPHY_DBG_DATA 374 DELAY(1000); 375 } 376 377 void 378 ale_attach(device_t parent, device_t self, void *aux) 379 { 380 struct ale_softc *sc = device_private(self); 381 struct pci_attach_args *pa = aux; 382 pci_chipset_tag_t pc = pa->pa_pc; 383 pci_intr_handle_t ih; 384 const char *intrstr; 385 struct ifnet *ifp; 386 pcireg_t memtype; 387 int mii_flags, error = 0; 388 uint32_t rxf_len, txf_len; 389 const char *chipname; 390 char intrbuf[PCI_INTRSTR_LEN]; 391 392 aprint_naive("\n"); 393 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 394 395 sc->sc_dev = self; 396 sc->sc_dmat = pa->pa_dmat; 397 sc->sc_pct = pa->pa_pc; 398 sc->sc_pcitag = pa->pa_tag; 399 400 /* 401 * Allocate IO memory 402 */ 403 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 404 switch (memtype) { 405 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 406 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 407 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 408 break; 409 default: 410 aprint_error_dev(self, "invalid base address register\n"); 411 break; 412 } 413 414 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 415 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 416 aprint_error_dev(self, "could not map mem space\n"); 417 return; 418 } 419 420 if (pci_intr_map(pa, &ih) != 0) { 421 aprint_error_dev(self, "could not map interrupt\n"); 422 goto fail; 423 } 424 425 /* 426 * Allocate IRQ 427 */ 428 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 429 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc); 430 if (sc->sc_irq_handle == NULL) { 431 aprint_error_dev(self, "could not establish interrupt"); 432 if (intrstr != NULL) 433 aprint_error(" at %s", intrstr); 434 aprint_error("\n"); 435 goto fail; 436 } 437 438 /* Set PHY address. */ 439 sc->ale_phyaddr = ALE_PHY_ADDR; 440 441 /* Reset PHY. */ 442 ale_phy_reset(sc); 443 444 /* Reset the ethernet controller. */ 445 ale_reset(sc); 446 447 /* Get PCI and chip id/revision. */ 448 sc->ale_rev = PCI_REVISION(pa->pa_class); 449 if (sc->ale_rev >= 0xF0) { 450 /* L2E Rev. B. AR8114 */ 451 sc->ale_flags |= ALE_FLAG_FASTETHER; 452 chipname = "AR8114 (L2E RevB)"; 453 } else { 454 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 455 /* L1E AR8121 */ 456 sc->ale_flags |= ALE_FLAG_JUMBO; 457 chipname = "AR8121 (L1E)"; 458 } else { 459 /* L2E Rev. A. AR8113 */ 460 sc->ale_flags |= ALE_FLAG_FASTETHER; 461 chipname = "AR8113 (L2E RevA)"; 462 } 463 } 464 aprint_normal_dev(self, "%s, %s\n", chipname, intrstr); 465 466 /* 467 * All known controllers seems to require 4 bytes alignment 468 * of Tx buffers to make Tx checksum offload with custom 469 * checksum generation method work. 470 */ 471 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 472 473 /* 474 * All known controllers seems to have issues on Rx checksum 475 * offload for fragmented IP datagrams. 476 */ 477 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 478 479 /* 480 * Don't use Tx CMB. It is known to cause RRS update failure 481 * under certain circumstances. Typical phenomenon of the 482 * issue would be unexpected sequence number encountered in 483 * Rx handler. 484 */ 485 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 486 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 487 MASTER_CHIP_REV_SHIFT; 488 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 489 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 490 491 /* 492 * Uninitialized hardware returns an invalid chip id/revision 493 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 494 */ 495 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 496 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 497 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 498 rxf_len == 0xFFFFFFF) { 499 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 500 "%u Rx FIFO -- not initialized?\n", 501 sc->ale_chip_rev, txf_len, rxf_len); 502 goto fail; 503 } 504 505 if (aledebug) { 506 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 507 txf_len, rxf_len); 508 } 509 510 /* Set max allowable DMA size. */ 511 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 512 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 513 514 callout_init(&sc->sc_tick_ch, 0); 515 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 516 517 error = ale_dma_alloc(sc); 518 if (error) 519 goto fail; 520 521 /* Load station address. */ 522 ale_get_macaddr(sc); 523 524 aprint_normal_dev(self, "Ethernet address %s\n", 525 ether_sprintf(sc->ale_eaddr)); 526 527 ifp = &sc->sc_ec.ec_if; 528 ifp->if_softc = sc; 529 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 530 ifp->if_init = ale_init; 531 ifp->if_ioctl = ale_ioctl; 532 ifp->if_start = ale_start; 533 ifp->if_stop = ale_stop; 534 ifp->if_watchdog = ale_watchdog; 535 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 536 IFQ_SET_READY(&ifp->if_snd); 537 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 538 539 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 540 541 #ifdef ALE_CHECKSUM 542 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 543 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 544 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 545 #endif 546 547 #if NVLAN > 0 548 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 549 #endif 550 551 /* Set up MII bus. */ 552 sc->sc_miibus.mii_ifp = ifp; 553 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 554 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 555 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 556 557 sc->sc_ec.ec_mii = &sc->sc_miibus; 558 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 559 ale_mediastatus); 560 mii_flags = 0; 561 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 562 mii_flags |= MIIF_DOPAUSE; 563 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 564 MII_OFFSET_ANY, mii_flags); 565 566 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 567 aprint_error_dev(self, "no PHY found!\n"); 568 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 569 0, NULL); 570 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 571 } else 572 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 573 574 if_attach(ifp); 575 if_deferred_start_init(ifp, NULL); 576 ether_ifattach(ifp, sc->ale_eaddr); 577 578 if (pmf_device_register(self, NULL, NULL)) 579 pmf_class_network_register(self, ifp); 580 else 581 aprint_error_dev(self, "couldn't establish power handler\n"); 582 583 return; 584 fail: 585 ale_dma_free(sc); 586 if (sc->sc_irq_handle != NULL) { 587 pci_intr_disestablish(pc, sc->sc_irq_handle); 588 sc->sc_irq_handle = NULL; 589 } 590 if (sc->sc_mem_size) { 591 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 592 sc->sc_mem_size = 0; 593 } 594 } 595 596 static int 597 ale_detach(device_t self, int flags) 598 { 599 struct ale_softc *sc = device_private(self); 600 struct ifnet *ifp = &sc->sc_ec.ec_if; 601 int s; 602 603 pmf_device_deregister(self); 604 s = splnet(); 605 ale_stop(ifp, 0); 606 splx(s); 607 608 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 609 610 /* Delete all remaining media. */ 611 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 612 613 ether_ifdetach(ifp); 614 if_detach(ifp); 615 ale_dma_free(sc); 616 617 if (sc->sc_irq_handle != NULL) { 618 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 619 sc->sc_irq_handle = NULL; 620 } 621 if (sc->sc_mem_size) { 622 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 623 sc->sc_mem_size = 0; 624 } 625 626 return 0; 627 } 628 629 630 static int 631 ale_dma_alloc(struct ale_softc *sc) 632 { 633 struct ale_txdesc *txd; 634 int nsegs, error, guard_size, i; 635 636 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 637 guard_size = ALE_JUMBO_FRAMELEN; 638 else 639 guard_size = ALE_MAX_FRAMELEN; 640 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 641 ALE_RX_PAGE_ALIGN); 642 643 /* 644 * Create DMA stuffs for TX ring 645 */ 646 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 647 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 648 if (error) { 649 sc->ale_cdata.ale_tx_ring_map = NULL; 650 return ENOBUFS; 651 } 652 653 /* Allocate DMA'able memory for TX ring */ 654 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 655 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 656 &nsegs, BUS_DMA_WAITOK); 657 if (error) { 658 printf("%s: could not allocate DMA'able memory for Tx ring, " 659 "error = %i\n", device_xname(sc->sc_dev), error); 660 return error; 661 } 662 663 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 664 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 665 BUS_DMA_NOWAIT); 666 if (error) 667 return ENOBUFS; 668 669 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 670 671 /* Load the DMA map for Tx ring. */ 672 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 673 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 674 if (error) { 675 printf("%s: could not load DMA'able memory for Tx ring.\n", 676 device_xname(sc->sc_dev)); 677 bus_dmamem_free(sc->sc_dmat, 678 &sc->ale_cdata.ale_tx_ring_seg, 1); 679 return error; 680 } 681 sc->ale_cdata.ale_tx_ring_paddr = 682 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 683 684 for (i = 0; i < ALE_RX_PAGES; i++) { 685 /* 686 * Create DMA stuffs for RX pages 687 */ 688 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 689 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 690 &sc->ale_cdata.ale_rx_page[i].page_map); 691 if (error) { 692 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 693 return ENOBUFS; 694 } 695 696 /* Allocate DMA'able memory for RX pages */ 697 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 698 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 699 1, &nsegs, BUS_DMA_WAITOK); 700 if (error) { 701 printf("%s: could not allocate DMA'able memory for " 702 "Rx ring.\n", device_xname(sc->sc_dev)); 703 return error; 704 } 705 error = bus_dmamem_map(sc->sc_dmat, 706 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 707 sc->ale_pagesize, 708 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 709 BUS_DMA_NOWAIT); 710 if (error) 711 return ENOBUFS; 712 713 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 714 sc->ale_pagesize); 715 716 /* Load the DMA map for Rx pages. */ 717 error = bus_dmamap_load(sc->sc_dmat, 718 sc->ale_cdata.ale_rx_page[i].page_map, 719 sc->ale_cdata.ale_rx_page[i].page_addr, 720 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 721 if (error) { 722 printf("%s: could not load DMA'able memory for " 723 "Rx pages.\n", device_xname(sc->sc_dev)); 724 bus_dmamem_free(sc->sc_dmat, 725 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 726 return error; 727 } 728 sc->ale_cdata.ale_rx_page[i].page_paddr = 729 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 730 } 731 732 /* 733 * Create DMA stuffs for Tx CMB. 734 */ 735 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 736 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 737 if (error) { 738 sc->ale_cdata.ale_tx_cmb_map = NULL; 739 return ENOBUFS; 740 } 741 742 /* Allocate DMA'able memory for Tx CMB. */ 743 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 744 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 745 746 if (error) { 747 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 748 device_xname(sc->sc_dev)); 749 return error; 750 } 751 752 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 753 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 754 BUS_DMA_NOWAIT); 755 if (error) 756 return ENOBUFS; 757 758 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 759 760 /* Load the DMA map for Tx CMB. */ 761 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 762 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 763 if (error) { 764 printf("%s: could not load DMA'able memory for Tx CMB.\n", 765 device_xname(sc->sc_dev)); 766 bus_dmamem_free(sc->sc_dmat, 767 &sc->ale_cdata.ale_tx_cmb_seg, 1); 768 return error; 769 } 770 771 sc->ale_cdata.ale_tx_cmb_paddr = 772 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 773 774 for (i = 0; i < ALE_RX_PAGES; i++) { 775 /* 776 * Create DMA stuffs for Rx CMB. 777 */ 778 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 779 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 780 &sc->ale_cdata.ale_rx_page[i].cmb_map); 781 if (error) { 782 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 783 return ENOBUFS; 784 } 785 786 /* Allocate DMA'able memory for Rx CMB */ 787 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 788 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 789 &nsegs, BUS_DMA_WAITOK); 790 if (error) { 791 printf("%s: could not allocate DMA'able memory for " 792 "Rx CMB\n", device_xname(sc->sc_dev)); 793 return error; 794 } 795 error = bus_dmamem_map(sc->sc_dmat, 796 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 797 ALE_RX_CMB_SZ, 798 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 799 BUS_DMA_NOWAIT); 800 if (error) 801 return ENOBUFS; 802 803 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 804 805 /* Load the DMA map for Rx CMB */ 806 error = bus_dmamap_load(sc->sc_dmat, 807 sc->ale_cdata.ale_rx_page[i].cmb_map, 808 sc->ale_cdata.ale_rx_page[i].cmb_addr, 809 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 810 if (error) { 811 printf("%s: could not load DMA'able memory for Rx CMB" 812 "\n", device_xname(sc->sc_dev)); 813 bus_dmamem_free(sc->sc_dmat, 814 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 815 return error; 816 } 817 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 818 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 819 } 820 821 822 /* Create DMA maps for Tx buffers. */ 823 for (i = 0; i < ALE_TX_RING_CNT; i++) { 824 txd = &sc->ale_cdata.ale_txdesc[i]; 825 txd->tx_m = NULL; 826 txd->tx_dmamap = NULL; 827 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 828 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 829 &txd->tx_dmamap); 830 if (error) { 831 txd->tx_dmamap = NULL; 832 printf("%s: could not create Tx dmamap.\n", 833 device_xname(sc->sc_dev)); 834 return error; 835 } 836 } 837 838 return 0; 839 } 840 841 static void 842 ale_dma_free(struct ale_softc *sc) 843 { 844 struct ale_txdesc *txd; 845 int i; 846 847 /* Tx buffers. */ 848 for (i = 0; i < ALE_TX_RING_CNT; i++) { 849 txd = &sc->ale_cdata.ale_txdesc[i]; 850 if (txd->tx_dmamap != NULL) { 851 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 852 txd->tx_dmamap = NULL; 853 } 854 } 855 856 /* Tx descriptor ring. */ 857 if (sc->ale_cdata.ale_tx_ring_map != NULL) 858 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 859 if (sc->ale_cdata.ale_tx_ring_map != NULL && 860 sc->ale_cdata.ale_tx_ring != NULL) 861 bus_dmamem_free(sc->sc_dmat, 862 &sc->ale_cdata.ale_tx_ring_seg, 1); 863 sc->ale_cdata.ale_tx_ring = NULL; 864 sc->ale_cdata.ale_tx_ring_map = NULL; 865 866 /* Rx page block. */ 867 for (i = 0; i < ALE_RX_PAGES; i++) { 868 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 869 bus_dmamap_unload(sc->sc_dmat, 870 sc->ale_cdata.ale_rx_page[i].page_map); 871 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 872 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 873 bus_dmamem_free(sc->sc_dmat, 874 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 875 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 876 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 877 } 878 879 /* Rx CMB. */ 880 for (i = 0; i < ALE_RX_PAGES; i++) { 881 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 882 bus_dmamap_unload(sc->sc_dmat, 883 sc->ale_cdata.ale_rx_page[i].cmb_map); 884 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 885 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 886 bus_dmamem_free(sc->sc_dmat, 887 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 888 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 889 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 890 } 891 892 /* Tx CMB. */ 893 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 894 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 895 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 896 sc->ale_cdata.ale_tx_cmb != NULL) 897 bus_dmamem_free(sc->sc_dmat, 898 &sc->ale_cdata.ale_tx_cmb_seg, 1); 899 sc->ale_cdata.ale_tx_cmb = NULL; 900 sc->ale_cdata.ale_tx_cmb_map = NULL; 901 902 } 903 904 static int 905 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 906 { 907 struct ale_txdesc *txd, *txd_last; 908 struct tx_desc *desc; 909 struct mbuf *m; 910 bus_dmamap_t map; 911 uint32_t cflags, poff, vtag; 912 int error, i, nsegs, prod; 913 914 m = *m_head; 915 cflags = vtag = 0; 916 poff = 0; 917 918 prod = sc->ale_cdata.ale_tx_prod; 919 txd = &sc->ale_cdata.ale_txdesc[prod]; 920 txd_last = txd; 921 map = txd->tx_dmamap; 922 923 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 924 if (error == EFBIG) { 925 error = 0; 926 927 *m_head = m_pullup(*m_head, MHLEN); 928 if (*m_head == NULL) { 929 printf("%s: can't defrag TX mbuf\n", 930 device_xname(sc->sc_dev)); 931 return ENOBUFS; 932 } 933 934 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 935 BUS_DMA_NOWAIT); 936 937 if (error != 0) { 938 printf("%s: could not load defragged TX mbuf\n", 939 device_xname(sc->sc_dev)); 940 m_freem(*m_head); 941 *m_head = NULL; 942 return error; 943 } 944 } else if (error) { 945 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 946 return error; 947 } 948 949 nsegs = map->dm_nsegs; 950 951 if (nsegs == 0) { 952 m_freem(*m_head); 953 *m_head = NULL; 954 return EIO; 955 } 956 957 /* Check descriptor overrun. */ 958 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 959 bus_dmamap_unload(sc->sc_dmat, map); 960 return ENOBUFS; 961 } 962 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 963 BUS_DMASYNC_PREWRITE); 964 965 m = *m_head; 966 /* Configure Tx checksum offload. */ 967 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 968 /* 969 * AR81xx supports Tx custom checksum offload feature 970 * that offloads single 16bit checksum computation. 971 * So you can choose one among IP, TCP and UDP. 972 * Normally driver sets checksum start/insertion 973 * position from the information of TCP/UDP frame as 974 * TCP/UDP checksum takes more time than that of IP. 975 * However it seems that custom checksum offload 976 * requires 4 bytes aligned Tx buffers due to hardware 977 * bug. 978 * AR81xx also supports explicit Tx checksum computation 979 * if it is told that the size of IP header and TCP 980 * header(for UDP, the header size does not matter 981 * because it's fixed length). However with this scheme 982 * TSO does not work so you have to choose one either 983 * TSO or explicit Tx checksum offload. I chosen TSO 984 * plus custom checksum offload with work-around which 985 * will cover most common usage for this consumer 986 * ethernet controller. The work-around takes a lot of 987 * CPU cycles if Tx buffer is not aligned on 4 bytes 988 * boundary, though. 989 */ 990 cflags |= ALE_TD_CXSUM; 991 /* Set checksum start offset. */ 992 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 993 } 994 995 #if NVLAN > 0 996 /* Configure VLAN hardware tag insertion. */ 997 if (vlan_has_tag(m)) { 998 vtag = ALE_TX_VLAN_TAG(htons(vlan_get_tag(m))); 999 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1000 cflags |= ALE_TD_INSERT_VLAN_TAG; 1001 } 1002 #endif 1003 1004 desc = NULL; 1005 for (i = 0; i < nsegs; i++) { 1006 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1007 desc->addr = htole64(map->dm_segs[i].ds_addr); 1008 desc->len = 1009 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1010 desc->flags = htole32(cflags); 1011 sc->ale_cdata.ale_tx_cnt++; 1012 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1013 } 1014 /* Update producer index. */ 1015 sc->ale_cdata.ale_tx_prod = prod; 1016 1017 /* Finally set EOP on the last descriptor. */ 1018 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1019 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1020 desc->flags |= htole32(ALE_TD_EOP); 1021 1022 /* Swap dmamap of the first and the last. */ 1023 txd = &sc->ale_cdata.ale_txdesc[prod]; 1024 map = txd_last->tx_dmamap; 1025 txd_last->tx_dmamap = txd->tx_dmamap; 1026 txd->tx_dmamap = map; 1027 txd->tx_m = m; 1028 1029 /* Sync descriptors. */ 1030 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1031 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1032 1033 return 0; 1034 } 1035 1036 static void 1037 ale_start(struct ifnet *ifp) 1038 { 1039 struct ale_softc *sc = ifp->if_softc; 1040 struct mbuf *m_head; 1041 int enq; 1042 1043 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1044 return; 1045 1046 /* Reclaim transmitted frames. */ 1047 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1048 ale_txeof(sc); 1049 1050 enq = 0; 1051 for (;;) { 1052 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1053 if (m_head == NULL) 1054 break; 1055 1056 /* 1057 * Pack the data into the transmit ring. If we 1058 * don't have room, set the OACTIVE flag and wait 1059 * for the NIC to drain the ring. 1060 */ 1061 if (ale_encap(sc, &m_head)) { 1062 if (m_head == NULL) 1063 break; 1064 IF_PREPEND(&ifp->if_snd, m_head); 1065 ifp->if_flags |= IFF_OACTIVE; 1066 break; 1067 } 1068 enq = 1; 1069 1070 /* 1071 * If there's a BPF listener, bounce a copy of this frame 1072 * to him. 1073 */ 1074 bpf_mtap(ifp, m_head, BPF_D_OUT); 1075 } 1076 1077 if (enq) { 1078 /* Kick. */ 1079 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1080 sc->ale_cdata.ale_tx_prod); 1081 1082 /* Set a timeout in case the chip goes out to lunch. */ 1083 ifp->if_timer = ALE_TX_TIMEOUT; 1084 } 1085 } 1086 1087 static void 1088 ale_watchdog(struct ifnet *ifp) 1089 { 1090 struct ale_softc *sc = ifp->if_softc; 1091 1092 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1093 printf("%s: watchdog timeout (missed link)\n", 1094 device_xname(sc->sc_dev)); 1095 ifp->if_oerrors++; 1096 ale_init(ifp); 1097 return; 1098 } 1099 1100 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1101 ifp->if_oerrors++; 1102 ale_init(ifp); 1103 1104 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1105 ale_start(ifp); 1106 } 1107 1108 static int 1109 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1110 { 1111 struct ale_softc *sc = ifp->if_softc; 1112 int s, error; 1113 1114 s = splnet(); 1115 1116 error = ether_ioctl(ifp, cmd, data); 1117 if (error == ENETRESET) { 1118 if (ifp->if_flags & IFF_RUNNING) 1119 ale_rxfilter(sc); 1120 error = 0; 1121 } 1122 1123 splx(s); 1124 return error; 1125 } 1126 1127 static void 1128 ale_mac_config(struct ale_softc *sc) 1129 { 1130 struct mii_data *mii; 1131 uint32_t reg; 1132 1133 mii = &sc->sc_miibus; 1134 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1135 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1136 MAC_CFG_SPEED_MASK); 1137 1138 /* Reprogram MAC with resolved speed/duplex. */ 1139 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1140 case IFM_10_T: 1141 case IFM_100_TX: 1142 reg |= MAC_CFG_SPEED_10_100; 1143 break; 1144 case IFM_1000_T: 1145 reg |= MAC_CFG_SPEED_1000; 1146 break; 1147 } 1148 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1149 reg |= MAC_CFG_FULL_DUPLEX; 1150 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1151 reg |= MAC_CFG_TX_FC; 1152 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1153 reg |= MAC_CFG_RX_FC; 1154 } 1155 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1156 } 1157 1158 static void 1159 ale_stats_clear(struct ale_softc *sc) 1160 { 1161 struct smb sb; 1162 uint32_t *reg; 1163 int i; 1164 1165 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1166 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1167 i += sizeof(uint32_t); 1168 } 1169 /* Read Tx statistics. */ 1170 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1171 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1172 i += sizeof(uint32_t); 1173 } 1174 } 1175 1176 static void 1177 ale_stats_update(struct ale_softc *sc) 1178 { 1179 struct ifnet *ifp = &sc->sc_ec.ec_if; 1180 struct ale_hw_stats *stat; 1181 struct smb sb, *smb; 1182 uint32_t *reg; 1183 int i; 1184 1185 stat = &sc->ale_stats; 1186 smb = &sb; 1187 1188 /* Read Rx statistics. */ 1189 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1190 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1191 i += sizeof(uint32_t); 1192 } 1193 /* Read Tx statistics. */ 1194 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1195 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1196 i += sizeof(uint32_t); 1197 } 1198 1199 /* Rx stats. */ 1200 stat->rx_frames += smb->rx_frames; 1201 stat->rx_bcast_frames += smb->rx_bcast_frames; 1202 stat->rx_mcast_frames += smb->rx_mcast_frames; 1203 stat->rx_pause_frames += smb->rx_pause_frames; 1204 stat->rx_control_frames += smb->rx_control_frames; 1205 stat->rx_crcerrs += smb->rx_crcerrs; 1206 stat->rx_lenerrs += smb->rx_lenerrs; 1207 stat->rx_bytes += smb->rx_bytes; 1208 stat->rx_runts += smb->rx_runts; 1209 stat->rx_fragments += smb->rx_fragments; 1210 stat->rx_pkts_64 += smb->rx_pkts_64; 1211 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1212 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1213 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1214 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1215 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1216 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1217 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1218 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1219 stat->rx_rrs_errs += smb->rx_rrs_errs; 1220 stat->rx_alignerrs += smb->rx_alignerrs; 1221 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1222 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1223 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1224 1225 /* Tx stats. */ 1226 stat->tx_frames += smb->tx_frames; 1227 stat->tx_bcast_frames += smb->tx_bcast_frames; 1228 stat->tx_mcast_frames += smb->tx_mcast_frames; 1229 stat->tx_pause_frames += smb->tx_pause_frames; 1230 stat->tx_excess_defer += smb->tx_excess_defer; 1231 stat->tx_control_frames += smb->tx_control_frames; 1232 stat->tx_deferred += smb->tx_deferred; 1233 stat->tx_bytes += smb->tx_bytes; 1234 stat->tx_pkts_64 += smb->tx_pkts_64; 1235 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1236 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1237 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1238 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1239 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1240 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1241 stat->tx_single_colls += smb->tx_single_colls; 1242 stat->tx_multi_colls += smb->tx_multi_colls; 1243 stat->tx_late_colls += smb->tx_late_colls; 1244 stat->tx_excess_colls += smb->tx_excess_colls; 1245 stat->tx_abort += smb->tx_abort; 1246 stat->tx_underrun += smb->tx_underrun; 1247 stat->tx_desc_underrun += smb->tx_desc_underrun; 1248 stat->tx_lenerrs += smb->tx_lenerrs; 1249 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1250 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1251 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1252 1253 /* Update counters in ifnet. */ 1254 ifp->if_opackets += smb->tx_frames; 1255 1256 ifp->if_collisions += smb->tx_single_colls + 1257 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1258 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1259 1260 /* 1261 * XXX 1262 * tx_pkts_truncated counter looks suspicious. It constantly 1263 * increments with no sign of Tx errors. This may indicate 1264 * the counter name is not correct one so I've removed the 1265 * counter in output errors. 1266 */ 1267 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1268 smb->tx_underrun; 1269 1270 ifp->if_ipackets += smb->rx_frames; 1271 1272 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1273 smb->rx_runts + smb->rx_pkts_truncated + 1274 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1275 smb->rx_alignerrs; 1276 } 1277 1278 static int 1279 ale_intr(void *xsc) 1280 { 1281 struct ale_softc *sc = xsc; 1282 struct ifnet *ifp = &sc->sc_ec.ec_if; 1283 uint32_t status; 1284 1285 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1286 if ((status & ALE_INTRS) == 0) 1287 return 0; 1288 1289 /* Acknowledge and disable interrupts. */ 1290 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1291 1292 if (ifp->if_flags & IFF_RUNNING) { 1293 int error; 1294 1295 error = ale_rxeof(sc); 1296 if (error) { 1297 sc->ale_stats.reset_brk_seq++; 1298 ale_init(ifp); 1299 return 0; 1300 } 1301 1302 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1303 if (status & INTR_DMA_RD_TO_RST) 1304 printf("%s: DMA read error! -- resetting\n", 1305 device_xname(sc->sc_dev)); 1306 if (status & INTR_DMA_WR_TO_RST) 1307 printf("%s: DMA write error! -- resetting\n", 1308 device_xname(sc->sc_dev)); 1309 ale_init(ifp); 1310 return 0; 1311 } 1312 1313 ale_txeof(sc); 1314 if_schedule_deferred_start(ifp); 1315 } 1316 1317 /* Re-enable interrupts. */ 1318 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1319 return 1; 1320 } 1321 1322 static void 1323 ale_txeof(struct ale_softc *sc) 1324 { 1325 struct ifnet *ifp = &sc->sc_ec.ec_if; 1326 struct ale_txdesc *txd; 1327 uint32_t cons, prod; 1328 int prog; 1329 1330 if (sc->ale_cdata.ale_tx_cnt == 0) 1331 return; 1332 1333 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1334 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1335 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1336 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1337 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1338 BUS_DMASYNC_POSTREAD); 1339 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1340 } else 1341 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1342 cons = sc->ale_cdata.ale_tx_cons; 1343 /* 1344 * Go through our Tx list and free mbufs for those 1345 * frames which have been transmitted. 1346 */ 1347 for (prog = 0; cons != prod; prog++, 1348 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1349 if (sc->ale_cdata.ale_tx_cnt <= 0) 1350 break; 1351 prog++; 1352 ifp->if_flags &= ~IFF_OACTIVE; 1353 sc->ale_cdata.ale_tx_cnt--; 1354 txd = &sc->ale_cdata.ale_txdesc[cons]; 1355 if (txd->tx_m != NULL) { 1356 /* Reclaim transmitted mbufs. */ 1357 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1358 m_freem(txd->tx_m); 1359 txd->tx_m = NULL; 1360 } 1361 } 1362 1363 if (prog > 0) { 1364 sc->ale_cdata.ale_tx_cons = cons; 1365 /* 1366 * Unarm watchdog timer only when there is no pending 1367 * Tx descriptors in queue. 1368 */ 1369 if (sc->ale_cdata.ale_tx_cnt == 0) 1370 ifp->if_timer = 0; 1371 } 1372 } 1373 1374 static void 1375 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1376 uint32_t length, uint32_t *prod) 1377 { 1378 struct ale_rx_page *rx_page; 1379 1380 rx_page = *page; 1381 /* Update consumer position. */ 1382 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1383 ALE_RX_PAGE_ALIGN); 1384 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1385 /* 1386 * End of Rx page reached, let hardware reuse 1387 * this page. 1388 */ 1389 rx_page->cons = 0; 1390 *rx_page->cmb_addr = 0; 1391 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1392 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1393 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1394 RXF_VALID); 1395 /* Switch to alternate Rx page. */ 1396 sc->ale_cdata.ale_rx_curp ^= 1; 1397 rx_page = *page = 1398 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1399 /* Page flipped, sync CMB and Rx page. */ 1400 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1401 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1402 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1403 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1404 /* Sync completed, cache updated producer index. */ 1405 *prod = *rx_page->cmb_addr; 1406 } 1407 } 1408 1409 1410 /* 1411 * It seems that AR81xx controller can compute partial checksum. 1412 * The partial checksum value can be used to accelerate checksum 1413 * computation for fragmented TCP/UDP packets. Upper network stack 1414 * already takes advantage of the partial checksum value in IP 1415 * reassembly stage. But I'm not sure the correctness of the 1416 * partial hardware checksum assistance due to lack of data sheet. 1417 * In addition, the Rx feature of controller that requires copying 1418 * for every frames effectively nullifies one of most nice offload 1419 * capability of controller. 1420 */ 1421 static void 1422 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1423 { 1424 if (status & ALE_RD_IPCSUM_NOK) 1425 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1426 1427 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1428 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1429 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1430 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1431 { 1432 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1433 } 1434 } else { 1435 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1436 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1437 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1438 } 1439 } 1440 } 1441 /* 1442 * Don't mark bad checksum for TCP/UDP frames 1443 * as fragmented frames may always have set 1444 * bad checksummed bit of frame status. 1445 */ 1446 } 1447 1448 /* Process received frames. */ 1449 static int 1450 ale_rxeof(struct ale_softc *sc) 1451 { 1452 struct ifnet *ifp = &sc->sc_ec.ec_if; 1453 struct ale_rx_page *rx_page; 1454 struct rx_rs *rs; 1455 struct mbuf *m; 1456 uint32_t length, prod, seqno, status; 1457 int prog; 1458 1459 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1460 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1461 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1462 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1463 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1464 /* 1465 * Don't directly access producer index as hardware may 1466 * update it while Rx handler is in progress. It would 1467 * be even better if there is a way to let hardware 1468 * know how far driver processed its received frames. 1469 * Alternatively, hardware could provide a way to disable 1470 * CMB updates until driver acknowledges the end of CMB 1471 * access. 1472 */ 1473 prod = *rx_page->cmb_addr; 1474 for (prog = 0; ; prog++) { 1475 if (rx_page->cons >= prod) 1476 break; 1477 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1478 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1479 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1480 /* 1481 * Normally I believe this should not happen unless 1482 * severe driver bug or corrupted memory. However 1483 * it seems to happen under certain conditions which 1484 * is triggered by abrupt Rx events such as initiation 1485 * of bulk transfer of remote host. It's not easy to 1486 * reproduce this and I doubt it could be related 1487 * with FIFO overflow of hardware or activity of Tx 1488 * CMB updates. I also remember similar behaviour 1489 * seen on RealTek 8139 which uses resembling Rx 1490 * scheme. 1491 */ 1492 if (aledebug) 1493 printf("%s: garbled seq: %u, expected: %u -- " 1494 "resetting!\n", device_xname(sc->sc_dev), 1495 seqno, sc->ale_cdata.ale_rx_seqno); 1496 return EIO; 1497 } 1498 /* Frame received. */ 1499 sc->ale_cdata.ale_rx_seqno++; 1500 length = ALE_RX_BYTES(le32toh(rs->length)); 1501 status = le32toh(rs->flags); 1502 if (status & ALE_RD_ERROR) { 1503 /* 1504 * We want to pass the following frames to upper 1505 * layer regardless of error status of Rx return 1506 * status. 1507 * 1508 * o IP/TCP/UDP checksum is bad. 1509 * o frame length and protocol specific length 1510 * does not match. 1511 */ 1512 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1513 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1514 ALE_RD_TRUNC)) { 1515 ale_rx_update_page(sc, &rx_page, length, &prod); 1516 continue; 1517 } 1518 } 1519 /* 1520 * m_devget(9) is major bottle-neck of ale(4)(It comes 1521 * from hardware limitation). For jumbo frames we could 1522 * get a slightly better performance if driver use 1523 * m_getjcl(9) with proper buffer size argument. However 1524 * that would make code more complicated and I don't 1525 * think users would expect good Rx performance numbers 1526 * on these low-end consumer ethernet controller. 1527 */ 1528 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1529 0, ifp, NULL); 1530 if (m == NULL) { 1531 ifp->if_iqdrops++; 1532 ale_rx_update_page(sc, &rx_page, length, &prod); 1533 continue; 1534 } 1535 if (status & ALE_RD_IPV4) 1536 ale_rxcsum(sc, m, status); 1537 #if NVLAN > 0 1538 if (status & ALE_RD_VLAN) { 1539 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1540 vlan_set_tag(m, ALE_RX_VLAN_TAG(vtags)); 1541 } 1542 #endif 1543 1544 /* Pass it to upper layer. */ 1545 if_percpuq_enqueue(ifp->if_percpuq, m); 1546 1547 ale_rx_update_page(sc, &rx_page, length, &prod); 1548 } 1549 1550 return 0; 1551 } 1552 1553 static void 1554 ale_tick(void *xsc) 1555 { 1556 struct ale_softc *sc = xsc; 1557 struct mii_data *mii = &sc->sc_miibus; 1558 int s; 1559 1560 s = splnet(); 1561 mii_tick(mii); 1562 ale_stats_update(sc); 1563 splx(s); 1564 1565 callout_schedule(&sc->sc_tick_ch, hz); 1566 } 1567 1568 static void 1569 ale_reset(struct ale_softc *sc) 1570 { 1571 uint32_t reg; 1572 int i; 1573 1574 /* Initialize PCIe module. From Linux. */ 1575 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1576 1577 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1578 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1579 DELAY(10); 1580 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1581 break; 1582 } 1583 if (i == 0) 1584 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1585 1586 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1587 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1588 break; 1589 DELAY(10); 1590 } 1591 1592 if (i == 0) 1593 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1594 reg); 1595 } 1596 1597 static int 1598 ale_init(struct ifnet *ifp) 1599 { 1600 struct ale_softc *sc = ifp->if_softc; 1601 struct mii_data *mii; 1602 uint8_t eaddr[ETHER_ADDR_LEN]; 1603 bus_addr_t paddr; 1604 uint32_t reg, rxf_hi, rxf_lo; 1605 1606 /* 1607 * Cancel any pending I/O. 1608 */ 1609 ale_stop(ifp, 0); 1610 1611 /* 1612 * Reset the chip to a known state. 1613 */ 1614 ale_reset(sc); 1615 1616 /* Initialize Tx descriptors, DMA memory blocks. */ 1617 ale_init_rx_pages(sc); 1618 ale_init_tx_ring(sc); 1619 1620 /* Reprogram the station address. */ 1621 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1622 CSR_WRITE_4(sc, ALE_PAR0, 1623 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1624 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1625 1626 /* 1627 * Clear WOL status and disable all WOL feature as WOL 1628 * would interfere Rx operation under normal environments. 1629 */ 1630 CSR_READ_4(sc, ALE_WOL_CFG); 1631 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1632 1633 /* 1634 * Set Tx descriptor/RXF0/CMB base addresses. They share 1635 * the same high address part of DMAable region. 1636 */ 1637 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1638 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1639 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1640 CSR_WRITE_4(sc, ALE_TPD_CNT, 1641 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1642 1643 /* Set Rx page base address, note we use single queue. */ 1644 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1645 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1646 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1647 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1648 1649 /* Set Tx/Rx CMB addresses. */ 1650 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1651 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1652 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1653 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1654 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1655 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1656 1657 /* Mark RXF0 is valid. */ 1658 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1659 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1660 /* 1661 * No need to initialize RFX1/RXF2/RXF3. We don't use 1662 * multi-queue yet. 1663 */ 1664 1665 /* Set Rx page size, excluding guard frame size. */ 1666 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1667 1668 /* Tell hardware that we're ready to load DMA blocks. */ 1669 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1670 1671 /* Set Rx/Tx interrupt trigger threshold. */ 1672 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1673 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1674 /* 1675 * XXX 1676 * Set interrupt trigger timer, its purpose and relation 1677 * with interrupt moderation mechanism is not clear yet. 1678 */ 1679 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1680 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1681 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1682 1683 /* Configure interrupt moderation timer. */ 1684 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1685 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1686 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1687 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1688 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1689 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1690 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1691 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1692 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1693 reg |= MASTER_IM_RX_TIMER_ENB; 1694 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1695 reg |= MASTER_IM_TX_TIMER_ENB; 1696 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1697 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1698 1699 /* Set Maximum frame size of controller. */ 1700 if (ifp->if_mtu < ETHERMTU) 1701 sc->ale_max_frame_size = ETHERMTU; 1702 else 1703 sc->ale_max_frame_size = ifp->if_mtu; 1704 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1705 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1706 1707 /* Configure IPG/IFG parameters. */ 1708 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1709 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1710 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1711 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1712 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1713 1714 /* Set parameters for half-duplex media. */ 1715 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1716 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1717 HDPX_CFG_LCOL_MASK) | 1718 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1719 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1720 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1721 HDPX_CFG_ABEBT_MASK) | 1722 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1723 HDPX_CFG_JAMIPG_MASK)); 1724 1725 /* Configure Tx jumbo frame parameters. */ 1726 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1727 if (ifp->if_mtu < ETHERMTU) 1728 reg = sc->ale_max_frame_size; 1729 else if (ifp->if_mtu < 6 * 1024) 1730 reg = (sc->ale_max_frame_size * 2) / 3; 1731 else 1732 reg = sc->ale_max_frame_size / 2; 1733 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1734 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1735 TX_JUMBO_THRESH_UNIT_SHIFT); 1736 } 1737 1738 /* Configure TxQ. */ 1739 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1740 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1741 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1742 TXQ_CFG_TPD_BURST_MASK; 1743 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1744 1745 /* Configure Rx jumbo frame & flow control parameters. */ 1746 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1747 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1748 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1749 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1750 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1751 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1752 RX_JUMBO_LKAH_MASK)); 1753 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1754 rxf_hi = (reg * 7) / 10; 1755 rxf_lo = (reg * 3)/ 10; 1756 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1757 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1758 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1759 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1760 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1761 } 1762 1763 /* Disable RSS. */ 1764 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1765 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1766 1767 /* Configure RxQ. */ 1768 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1769 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1770 1771 /* Configure DMA parameters. */ 1772 reg = 0; 1773 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1774 reg |= DMA_CFG_TXCMB_ENB; 1775 CSR_WRITE_4(sc, ALE_DMA_CFG, 1776 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1777 sc->ale_dma_rd_burst | reg | 1778 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1779 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1780 DMA_CFG_RD_DELAY_CNT_MASK) | 1781 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1782 DMA_CFG_WR_DELAY_CNT_MASK)); 1783 1784 /* 1785 * Hardware can be configured to issue SMB interrupt based 1786 * on programmed interval. Since there is a callout that is 1787 * invoked for every hz in driver we use that instead of 1788 * relying on periodic SMB interrupt. 1789 */ 1790 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1791 1792 /* Clear MAC statistics. */ 1793 ale_stats_clear(sc); 1794 1795 /* 1796 * Configure Tx/Rx MACs. 1797 * - Auto-padding for short frames. 1798 * - Enable CRC generation. 1799 * Actual reconfiguration of MAC for resolved speed/duplex 1800 * is followed after detection of link establishment. 1801 * AR81xx always does checksum computation regardless of 1802 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1803 * cause Rx handling issue for fragmented IP datagrams due 1804 * to silicon bug. 1805 */ 1806 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1807 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1808 MAC_CFG_PREAMBLE_MASK); 1809 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1810 reg |= MAC_CFG_SPEED_10_100; 1811 else 1812 reg |= MAC_CFG_SPEED_1000; 1813 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1814 1815 /* Set up the receive filter. */ 1816 ale_rxfilter(sc); 1817 ale_rxvlan(sc); 1818 1819 /* Acknowledge all pending interrupts and clear it. */ 1820 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1821 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1822 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1823 1824 sc->ale_flags &= ~ALE_FLAG_LINK; 1825 1826 /* Switch to the current media. */ 1827 mii = &sc->sc_miibus; 1828 mii_mediachg(mii); 1829 1830 callout_schedule(&sc->sc_tick_ch, hz); 1831 1832 ifp->if_flags |= IFF_RUNNING; 1833 ifp->if_flags &= ~IFF_OACTIVE; 1834 1835 return 0; 1836 } 1837 1838 static void 1839 ale_stop(struct ifnet *ifp, int disable) 1840 { 1841 struct ale_softc *sc = ifp->if_softc; 1842 struct ale_txdesc *txd; 1843 uint32_t reg; 1844 int i; 1845 1846 callout_stop(&sc->sc_tick_ch); 1847 1848 /* 1849 * Mark the interface down and cancel the watchdog timer. 1850 */ 1851 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1852 ifp->if_timer = 0; 1853 1854 sc->ale_flags &= ~ALE_FLAG_LINK; 1855 1856 ale_stats_update(sc); 1857 1858 mii_down(&sc->sc_miibus); 1859 1860 /* Disable interrupts. */ 1861 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1862 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1863 1864 /* Disable queue processing and DMA. */ 1865 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1866 reg &= ~TXQ_CFG_ENB; 1867 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1868 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1869 reg &= ~RXQ_CFG_ENB; 1870 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1871 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1872 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1873 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1874 DELAY(1000); 1875 1876 /* Stop Rx/Tx MACs. */ 1877 ale_stop_mac(sc); 1878 1879 /* Disable interrupts again? XXX */ 1880 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1881 1882 /* 1883 * Free TX mbufs still in the queues. 1884 */ 1885 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1886 txd = &sc->ale_cdata.ale_txdesc[i]; 1887 if (txd->tx_m != NULL) { 1888 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1889 m_freem(txd->tx_m); 1890 txd->tx_m = NULL; 1891 } 1892 } 1893 } 1894 1895 static void 1896 ale_stop_mac(struct ale_softc *sc) 1897 { 1898 uint32_t reg; 1899 int i; 1900 1901 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1902 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1903 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1904 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1905 } 1906 1907 for (i = ALE_TIMEOUT; i > 0; i--) { 1908 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1909 if (reg == 0) 1910 break; 1911 DELAY(10); 1912 } 1913 if (i == 0) 1914 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1915 device_xname(sc->sc_dev), reg); 1916 } 1917 1918 static void 1919 ale_init_tx_ring(struct ale_softc *sc) 1920 { 1921 struct ale_txdesc *txd; 1922 int i; 1923 1924 sc->ale_cdata.ale_tx_prod = 0; 1925 sc->ale_cdata.ale_tx_cons = 0; 1926 sc->ale_cdata.ale_tx_cnt = 0; 1927 1928 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1929 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1930 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1931 txd = &sc->ale_cdata.ale_txdesc[i]; 1932 txd->tx_m = NULL; 1933 } 1934 *sc->ale_cdata.ale_tx_cmb = 0; 1935 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1936 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1937 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1938 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1939 } 1940 1941 static void 1942 ale_init_rx_pages(struct ale_softc *sc) 1943 { 1944 struct ale_rx_page *rx_page; 1945 int i; 1946 1947 sc->ale_cdata.ale_rx_seqno = 0; 1948 sc->ale_cdata.ale_rx_curp = 0; 1949 1950 for (i = 0; i < ALE_RX_PAGES; i++) { 1951 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1952 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1953 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1954 rx_page->cons = 0; 1955 *rx_page->cmb_addr = 0; 1956 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1957 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1958 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1959 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1960 } 1961 } 1962 1963 static void 1964 ale_rxvlan(struct ale_softc *sc) 1965 { 1966 uint32_t reg; 1967 1968 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1969 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1970 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 1971 reg |= MAC_CFG_VLAN_TAG_STRIP; 1972 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1973 } 1974 1975 static void 1976 ale_rxfilter(struct ale_softc *sc) 1977 { 1978 struct ethercom *ec = &sc->sc_ec; 1979 struct ifnet *ifp = &ec->ec_if; 1980 struct ether_multi *enm; 1981 struct ether_multistep step; 1982 uint32_t crc; 1983 uint32_t mchash[2]; 1984 uint32_t rxcfg; 1985 1986 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 1987 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 1988 ifp->if_flags &= ~IFF_ALLMULTI; 1989 1990 /* 1991 * Always accept broadcast frames. 1992 */ 1993 rxcfg |= MAC_CFG_BCAST; 1994 1995 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 1996 ifp->if_flags |= IFF_ALLMULTI; 1997 if (ifp->if_flags & IFF_PROMISC) 1998 rxcfg |= MAC_CFG_PROMISC; 1999 else 2000 rxcfg |= MAC_CFG_ALLMULTI; 2001 mchash[0] = mchash[1] = 0xFFFFFFFF; 2002 } else { 2003 /* Program new filter. */ 2004 memset(mchash, 0, sizeof(mchash)); 2005 2006 ETHER_FIRST_MULTI(step, ec, enm); 2007 while (enm != NULL) { 2008 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2009 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2010 ETHER_NEXT_MULTI(step, enm); 2011 } 2012 } 2013 2014 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2015 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2016 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2017 } 2018