1 /* $NetBSD: if_ale.c,v 1.17 2014/03/29 19:28:24 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 */ 31 32 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.17 2014/03/29 19:28:24 christos Exp $"); 36 37 #include "vlan.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/types.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/queue.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 #include <sys/socket.h> 51 52 #include <sys/bus.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #ifdef INET 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net/if_types.h> 68 #include <net/if_vlanvar.h> 69 70 #include <net/bpf.h> 71 72 #include <sys/rnd.h> 73 74 #include <dev/mii/mii.h> 75 #include <dev/mii/miivar.h> 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/pci/if_alereg.h> 82 83 static int ale_match(device_t, cfdata_t, void *); 84 static void ale_attach(device_t, device_t, void *); 85 static int ale_detach(device_t, int); 86 87 static int ale_miibus_readreg(device_t, int, int); 88 static void ale_miibus_writereg(device_t, int, int, int); 89 static void ale_miibus_statchg(struct ifnet *); 90 91 static int ale_init(struct ifnet *); 92 static void ale_start(struct ifnet *); 93 static int ale_ioctl(struct ifnet *, u_long, void *); 94 static void ale_watchdog(struct ifnet *); 95 static int ale_mediachange(struct ifnet *); 96 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 97 98 static int ale_intr(void *); 99 static int ale_rxeof(struct ale_softc *sc); 100 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 101 uint32_t, uint32_t *); 102 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 103 static void ale_txeof(struct ale_softc *); 104 105 static int ale_dma_alloc(struct ale_softc *); 106 static void ale_dma_free(struct ale_softc *); 107 static int ale_encap(struct ale_softc *, struct mbuf **); 108 static void ale_init_rx_pages(struct ale_softc *); 109 static void ale_init_tx_ring(struct ale_softc *); 110 111 static void ale_stop(struct ifnet *, int); 112 static void ale_tick(void *); 113 static void ale_get_macaddr(struct ale_softc *); 114 static void ale_mac_config(struct ale_softc *); 115 static void ale_phy_reset(struct ale_softc *); 116 static void ale_reset(struct ale_softc *); 117 static void ale_rxfilter(struct ale_softc *); 118 static void ale_rxvlan(struct ale_softc *); 119 static void ale_stats_clear(struct ale_softc *); 120 static void ale_stats_update(struct ale_softc *); 121 static void ale_stop_mac(struct ale_softc *); 122 123 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 124 ale_match, ale_attach, ale_detach, NULL); 125 126 int aledebug = 0; 127 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 128 129 #define ETHER_ALIGN 2 130 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 131 132 static int 133 ale_miibus_readreg(device_t dev, int phy, int reg) 134 { 135 struct ale_softc *sc = device_private(dev); 136 uint32_t v; 137 int i; 138 139 if (phy != sc->ale_phyaddr) 140 return 0; 141 142 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 143 switch (reg) { 144 case MII_100T2CR: 145 case MII_100T2SR: 146 case MII_EXTSR: 147 return 0; 148 default: 149 break; 150 } 151 } 152 153 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 154 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 155 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 156 DELAY(5); 157 v = CSR_READ_4(sc, ALE_MDIO); 158 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 159 break; 160 } 161 162 if (i == 0) { 163 printf("%s: phy read timeout: phy %d, reg %d\n", 164 device_xname(sc->sc_dev), phy, reg); 165 return 0; 166 } 167 168 return (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 169 } 170 171 static void 172 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 173 { 174 struct ale_softc *sc = device_private(dev); 175 uint32_t v; 176 int i; 177 178 if (phy != sc->ale_phyaddr) 179 return; 180 181 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 182 switch (reg) { 183 case MII_100T2CR: 184 case MII_100T2SR: 185 case MII_EXTSR: 186 return; 187 default: 188 break; 189 } 190 } 191 192 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 193 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 194 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 195 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 196 DELAY(5); 197 v = CSR_READ_4(sc, ALE_MDIO); 198 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 199 break; 200 } 201 202 if (i == 0) 203 printf("%s: phy write timeout: phy %d, reg %d\n", 204 device_xname(sc->sc_dev), phy, reg); 205 } 206 207 static void 208 ale_miibus_statchg(struct ifnet *ifp) 209 { 210 struct ale_softc *sc = ifp->if_softc; 211 struct mii_data *mii = &sc->sc_miibus; 212 uint32_t reg; 213 214 if ((ifp->if_flags & IFF_RUNNING) == 0) 215 return; 216 217 sc->ale_flags &= ~ALE_FLAG_LINK; 218 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 219 (IFM_ACTIVE | IFM_AVALID)) { 220 switch (IFM_SUBTYPE(mii->mii_media_active)) { 221 case IFM_10_T: 222 case IFM_100_TX: 223 sc->ale_flags |= ALE_FLAG_LINK; 224 break; 225 226 case IFM_1000_T: 227 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 228 sc->ale_flags |= ALE_FLAG_LINK; 229 break; 230 231 default: 232 break; 233 } 234 } 235 236 /* Stop Rx/Tx MACs. */ 237 ale_stop_mac(sc); 238 239 /* Program MACs with resolved speed/duplex/flow-control. */ 240 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 241 ale_mac_config(sc); 242 /* Reenable Tx/Rx MACs. */ 243 reg = CSR_READ_4(sc, ALE_MAC_CFG); 244 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 245 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 246 } 247 } 248 249 void 250 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 251 { 252 struct ale_softc *sc = ifp->if_softc; 253 struct mii_data *mii = &sc->sc_miibus; 254 255 mii_pollstat(mii); 256 ifmr->ifm_status = mii->mii_media_status; 257 ifmr->ifm_active = mii->mii_media_active; 258 } 259 260 int 261 ale_mediachange(struct ifnet *ifp) 262 { 263 struct ale_softc *sc = ifp->if_softc; 264 struct mii_data *mii = &sc->sc_miibus; 265 int error; 266 267 if (mii->mii_instance != 0) { 268 struct mii_softc *miisc; 269 270 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 271 mii_phy_reset(miisc); 272 } 273 error = mii_mediachg(mii); 274 275 return error; 276 } 277 278 int 279 ale_match(device_t dev, cfdata_t match, void *aux) 280 { 281 struct pci_attach_args *pa = aux; 282 283 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 284 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 285 } 286 287 void 288 ale_get_macaddr(struct ale_softc *sc) 289 { 290 uint32_t ea[2], reg; 291 int i, vpdc; 292 293 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 294 if ((reg & SPI_VPD_ENB) != 0) { 295 reg &= ~SPI_VPD_ENB; 296 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 297 } 298 299 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 300 &vpdc, NULL)) { 301 /* 302 * PCI VPD capability found, let TWSI reload EEPROM. 303 * This will set ethernet address of controller. 304 */ 305 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 306 TWSI_CTRL_SW_LD_START); 307 for (i = 100; i > 0; i--) { 308 DELAY(1000); 309 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 310 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 311 break; 312 } 313 if (i == 0) 314 printf("%s: reloading EEPROM timeout!\n", 315 device_xname(sc->sc_dev)); 316 } else { 317 if (aledebug) 318 printf("%s: PCI VPD capability not found!\n", 319 device_xname(sc->sc_dev)); 320 } 321 322 ea[0] = CSR_READ_4(sc, ALE_PAR0); 323 ea[1] = CSR_READ_4(sc, ALE_PAR1); 324 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 325 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 326 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 327 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 328 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 329 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 330 } 331 332 void 333 ale_phy_reset(struct ale_softc *sc) 334 { 335 /* Reset magic from Linux. */ 336 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 337 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 338 GPHY_CTRL_PHY_PLL_ON); 339 DELAY(1000); 340 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 341 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 342 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 343 DELAY(1000); 344 345 #define ATPHY_DBG_ADDR 0x1D 346 #define ATPHY_DBG_DATA 0x1E 347 348 /* Enable hibernation mode. */ 349 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 350 ATPHY_DBG_ADDR, 0x0B); 351 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 352 ATPHY_DBG_DATA, 0xBC00); 353 /* Set Class A/B for all modes. */ 354 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 355 ATPHY_DBG_ADDR, 0x00); 356 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 357 ATPHY_DBG_DATA, 0x02EF); 358 /* Enable 10BT power saving. */ 359 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 360 ATPHY_DBG_ADDR, 0x12); 361 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 362 ATPHY_DBG_DATA, 0x4C04); 363 /* Adjust 1000T power. */ 364 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 365 ATPHY_DBG_ADDR, 0x04); 366 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 367 ATPHY_DBG_DATA, 0x8BBB); 368 /* 10BT center tap voltage. */ 369 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 370 ATPHY_DBG_ADDR, 0x05); 371 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 372 ATPHY_DBG_DATA, 0x2C46); 373 374 #undef ATPHY_DBG_ADDR 375 #undef ATPHY_DBG_DATA 376 DELAY(1000); 377 } 378 379 void 380 ale_attach(device_t parent, device_t self, void *aux) 381 { 382 struct ale_softc *sc = device_private(self); 383 struct pci_attach_args *pa = aux; 384 pci_chipset_tag_t pc = pa->pa_pc; 385 pci_intr_handle_t ih; 386 const char *intrstr; 387 struct ifnet *ifp; 388 pcireg_t memtype; 389 int mii_flags, error = 0; 390 uint32_t rxf_len, txf_len; 391 const char *chipname; 392 char intrbuf[PCI_INTRSTR_LEN]; 393 394 aprint_naive("\n"); 395 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 396 397 sc->sc_dev = self; 398 sc->sc_dmat = pa->pa_dmat; 399 sc->sc_pct = pa->pa_pc; 400 sc->sc_pcitag = pa->pa_tag; 401 402 /* 403 * Allocate IO memory 404 */ 405 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 406 switch (memtype) { 407 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 408 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 409 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 410 break; 411 default: 412 aprint_error_dev(self, "invalid base address register\n"); 413 break; 414 } 415 416 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 417 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 418 aprint_error_dev(self, "could not map mem space\n"); 419 return; 420 } 421 422 if (pci_intr_map(pa, &ih) != 0) { 423 aprint_error_dev(self, "could not map interrupt\n"); 424 goto fail; 425 } 426 427 /* 428 * Allocate IRQ 429 */ 430 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 431 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc); 432 if (sc->sc_irq_handle == NULL) { 433 aprint_error_dev(self, "could not establish interrupt"); 434 if (intrstr != NULL) 435 aprint_error(" at %s", intrstr); 436 aprint_error("\n"); 437 goto fail; 438 } 439 440 /* Set PHY address. */ 441 sc->ale_phyaddr = ALE_PHY_ADDR; 442 443 /* Reset PHY. */ 444 ale_phy_reset(sc); 445 446 /* Reset the ethernet controller. */ 447 ale_reset(sc); 448 449 /* Get PCI and chip id/revision. */ 450 sc->ale_rev = PCI_REVISION(pa->pa_class); 451 if (sc->ale_rev >= 0xF0) { 452 /* L2E Rev. B. AR8114 */ 453 sc->ale_flags |= ALE_FLAG_FASTETHER; 454 chipname = "AR8114 (L2E RevB)"; 455 } else { 456 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 457 /* L1E AR8121 */ 458 sc->ale_flags |= ALE_FLAG_JUMBO; 459 chipname = "AR8121 (L1E)"; 460 } else { 461 /* L2E Rev. A. AR8113 */ 462 sc->ale_flags |= ALE_FLAG_FASTETHER; 463 chipname = "AR8113 (L2E RevA)"; 464 } 465 } 466 aprint_normal_dev(self, "%s, %s\n", chipname, intrstr); 467 468 /* 469 * All known controllers seems to require 4 bytes alignment 470 * of Tx buffers to make Tx checksum offload with custom 471 * checksum generation method work. 472 */ 473 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 474 475 /* 476 * All known controllers seems to have issues on Rx checksum 477 * offload for fragmented IP datagrams. 478 */ 479 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 480 481 /* 482 * Don't use Tx CMB. It is known to cause RRS update failure 483 * under certain circumstances. Typical phenomenon of the 484 * issue would be unexpected sequence number encountered in 485 * Rx handler. 486 */ 487 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 488 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 489 MASTER_CHIP_REV_SHIFT; 490 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 491 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 492 493 /* 494 * Uninitialized hardware returns an invalid chip id/revision 495 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 496 */ 497 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 498 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 499 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 500 rxf_len == 0xFFFFFFF) { 501 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 502 "%u Rx FIFO -- not initialized?\n", 503 sc->ale_chip_rev, txf_len, rxf_len); 504 goto fail; 505 } 506 507 if (aledebug) { 508 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 509 txf_len, rxf_len); 510 } 511 512 /* Set max allowable DMA size. */ 513 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 514 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 515 516 callout_init(&sc->sc_tick_ch, 0); 517 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 518 519 error = ale_dma_alloc(sc); 520 if (error) 521 goto fail; 522 523 /* Load station address. */ 524 ale_get_macaddr(sc); 525 526 aprint_normal_dev(self, "Ethernet address %s\n", 527 ether_sprintf(sc->ale_eaddr)); 528 529 ifp = &sc->sc_ec.ec_if; 530 ifp->if_softc = sc; 531 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 532 ifp->if_init = ale_init; 533 ifp->if_ioctl = ale_ioctl; 534 ifp->if_start = ale_start; 535 ifp->if_stop = ale_stop; 536 ifp->if_watchdog = ale_watchdog; 537 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 538 IFQ_SET_READY(&ifp->if_snd); 539 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 540 541 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 542 543 #ifdef ALE_CHECKSUM 544 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 545 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 546 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 547 #endif 548 549 #if NVLAN > 0 550 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 551 #endif 552 553 /* Set up MII bus. */ 554 sc->sc_miibus.mii_ifp = ifp; 555 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 556 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 557 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 558 559 sc->sc_ec.ec_mii = &sc->sc_miibus; 560 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 561 ale_mediastatus); 562 mii_flags = 0; 563 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 564 mii_flags |= MIIF_DOPAUSE; 565 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 566 MII_OFFSET_ANY, mii_flags); 567 568 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 569 aprint_error_dev(self, "no PHY found!\n"); 570 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 571 0, NULL); 572 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 573 } else 574 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 575 576 if_attach(ifp); 577 ether_ifattach(ifp, sc->ale_eaddr); 578 579 if (pmf_device_register(self, NULL, NULL)) 580 pmf_class_network_register(self, ifp); 581 else 582 aprint_error_dev(self, "couldn't establish power handler\n"); 583 584 return; 585 fail: 586 ale_dma_free(sc); 587 if (sc->sc_irq_handle != NULL) { 588 pci_intr_disestablish(pc, sc->sc_irq_handle); 589 sc->sc_irq_handle = NULL; 590 } 591 if (sc->sc_mem_size) { 592 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 593 sc->sc_mem_size = 0; 594 } 595 } 596 597 static int 598 ale_detach(device_t self, int flags) 599 { 600 struct ale_softc *sc = device_private(self); 601 struct ifnet *ifp = &sc->sc_ec.ec_if; 602 int s; 603 604 pmf_device_deregister(self); 605 s = splnet(); 606 ale_stop(ifp, 0); 607 splx(s); 608 609 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 610 611 /* Delete all remaining media. */ 612 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 613 614 ether_ifdetach(ifp); 615 if_detach(ifp); 616 ale_dma_free(sc); 617 618 if (sc->sc_irq_handle != NULL) { 619 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 620 sc->sc_irq_handle = NULL; 621 } 622 if (sc->sc_mem_size) { 623 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 624 sc->sc_mem_size = 0; 625 } 626 627 return 0; 628 } 629 630 631 static int 632 ale_dma_alloc(struct ale_softc *sc) 633 { 634 struct ale_txdesc *txd; 635 int nsegs, error, guard_size, i; 636 637 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 638 guard_size = ALE_JUMBO_FRAMELEN; 639 else 640 guard_size = ALE_MAX_FRAMELEN; 641 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 642 ALE_RX_PAGE_ALIGN); 643 644 /* 645 * Create DMA stuffs for TX ring 646 */ 647 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 648 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 649 if (error) { 650 sc->ale_cdata.ale_tx_ring_map = NULL; 651 return ENOBUFS; 652 } 653 654 /* Allocate DMA'able memory for TX ring */ 655 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 656 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 657 &nsegs, BUS_DMA_WAITOK); 658 if (error) { 659 printf("%s: could not allocate DMA'able memory for Tx ring, " 660 "error = %i\n", device_xname(sc->sc_dev), error); 661 return error; 662 } 663 664 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 665 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 666 BUS_DMA_NOWAIT); 667 if (error) 668 return ENOBUFS; 669 670 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 671 672 /* Load the DMA map for Tx ring. */ 673 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 674 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 675 if (error) { 676 printf("%s: could not load DMA'able memory for Tx ring.\n", 677 device_xname(sc->sc_dev)); 678 bus_dmamem_free(sc->sc_dmat, 679 &sc->ale_cdata.ale_tx_ring_seg, 1); 680 return error; 681 } 682 sc->ale_cdata.ale_tx_ring_paddr = 683 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 684 685 for (i = 0; i < ALE_RX_PAGES; i++) { 686 /* 687 * Create DMA stuffs for RX pages 688 */ 689 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 690 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 691 &sc->ale_cdata.ale_rx_page[i].page_map); 692 if (error) { 693 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 694 return ENOBUFS; 695 } 696 697 /* Allocate DMA'able memory for RX pages */ 698 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 699 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 700 1, &nsegs, BUS_DMA_WAITOK); 701 if (error) { 702 printf("%s: could not allocate DMA'able memory for " 703 "Rx ring.\n", device_xname(sc->sc_dev)); 704 return error; 705 } 706 error = bus_dmamem_map(sc->sc_dmat, 707 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 708 sc->ale_pagesize, 709 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 710 BUS_DMA_NOWAIT); 711 if (error) 712 return ENOBUFS; 713 714 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 715 sc->ale_pagesize); 716 717 /* Load the DMA map for Rx pages. */ 718 error = bus_dmamap_load(sc->sc_dmat, 719 sc->ale_cdata.ale_rx_page[i].page_map, 720 sc->ale_cdata.ale_rx_page[i].page_addr, 721 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 722 if (error) { 723 printf("%s: could not load DMA'able memory for " 724 "Rx pages.\n", device_xname(sc->sc_dev)); 725 bus_dmamem_free(sc->sc_dmat, 726 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 727 return error; 728 } 729 sc->ale_cdata.ale_rx_page[i].page_paddr = 730 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 731 } 732 733 /* 734 * Create DMA stuffs for Tx CMB. 735 */ 736 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 737 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 738 if (error) { 739 sc->ale_cdata.ale_tx_cmb_map = NULL; 740 return ENOBUFS; 741 } 742 743 /* Allocate DMA'able memory for Tx CMB. */ 744 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 745 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 746 747 if (error) { 748 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 749 device_xname(sc->sc_dev)); 750 return error; 751 } 752 753 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 754 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 755 BUS_DMA_NOWAIT); 756 if (error) 757 return ENOBUFS; 758 759 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 760 761 /* Load the DMA map for Tx CMB. */ 762 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 763 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 764 if (error) { 765 printf("%s: could not load DMA'able memory for Tx CMB.\n", 766 device_xname(sc->sc_dev)); 767 bus_dmamem_free(sc->sc_dmat, 768 &sc->ale_cdata.ale_tx_cmb_seg, 1); 769 return error; 770 } 771 772 sc->ale_cdata.ale_tx_cmb_paddr = 773 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 774 775 for (i = 0; i < ALE_RX_PAGES; i++) { 776 /* 777 * Create DMA stuffs for Rx CMB. 778 */ 779 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 780 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 781 &sc->ale_cdata.ale_rx_page[i].cmb_map); 782 if (error) { 783 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 784 return ENOBUFS; 785 } 786 787 /* Allocate DMA'able memory for Rx CMB */ 788 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 789 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 790 &nsegs, BUS_DMA_WAITOK); 791 if (error) { 792 printf("%s: could not allocate DMA'able memory for " 793 "Rx CMB\n", device_xname(sc->sc_dev)); 794 return error; 795 } 796 error = bus_dmamem_map(sc->sc_dmat, 797 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 798 ALE_RX_CMB_SZ, 799 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 800 BUS_DMA_NOWAIT); 801 if (error) 802 return ENOBUFS; 803 804 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 805 806 /* Load the DMA map for Rx CMB */ 807 error = bus_dmamap_load(sc->sc_dmat, 808 sc->ale_cdata.ale_rx_page[i].cmb_map, 809 sc->ale_cdata.ale_rx_page[i].cmb_addr, 810 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 811 if (error) { 812 printf("%s: could not load DMA'able memory for Rx CMB" 813 "\n", device_xname(sc->sc_dev)); 814 bus_dmamem_free(sc->sc_dmat, 815 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 816 return error; 817 } 818 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 819 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 820 } 821 822 823 /* Create DMA maps for Tx buffers. */ 824 for (i = 0; i < ALE_TX_RING_CNT; i++) { 825 txd = &sc->ale_cdata.ale_txdesc[i]; 826 txd->tx_m = NULL; 827 txd->tx_dmamap = NULL; 828 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 829 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 830 &txd->tx_dmamap); 831 if (error) { 832 txd->tx_dmamap = NULL; 833 printf("%s: could not create Tx dmamap.\n", 834 device_xname(sc->sc_dev)); 835 return error; 836 } 837 } 838 839 return 0; 840 } 841 842 static void 843 ale_dma_free(struct ale_softc *sc) 844 { 845 struct ale_txdesc *txd; 846 int i; 847 848 /* Tx buffers. */ 849 for (i = 0; i < ALE_TX_RING_CNT; i++) { 850 txd = &sc->ale_cdata.ale_txdesc[i]; 851 if (txd->tx_dmamap != NULL) { 852 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 853 txd->tx_dmamap = NULL; 854 } 855 } 856 857 /* Tx descriptor ring. */ 858 if (sc->ale_cdata.ale_tx_ring_map != NULL) 859 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 860 if (sc->ale_cdata.ale_tx_ring_map != NULL && 861 sc->ale_cdata.ale_tx_ring != NULL) 862 bus_dmamem_free(sc->sc_dmat, 863 &sc->ale_cdata.ale_tx_ring_seg, 1); 864 sc->ale_cdata.ale_tx_ring = NULL; 865 sc->ale_cdata.ale_tx_ring_map = NULL; 866 867 /* Rx page block. */ 868 for (i = 0; i < ALE_RX_PAGES; i++) { 869 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 870 bus_dmamap_unload(sc->sc_dmat, 871 sc->ale_cdata.ale_rx_page[i].page_map); 872 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 873 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 874 bus_dmamem_free(sc->sc_dmat, 875 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 876 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 877 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 878 } 879 880 /* Rx CMB. */ 881 for (i = 0; i < ALE_RX_PAGES; i++) { 882 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 883 bus_dmamap_unload(sc->sc_dmat, 884 sc->ale_cdata.ale_rx_page[i].cmb_map); 885 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 886 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 887 bus_dmamem_free(sc->sc_dmat, 888 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 889 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 890 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 891 } 892 893 /* Tx CMB. */ 894 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 895 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 896 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 897 sc->ale_cdata.ale_tx_cmb != NULL) 898 bus_dmamem_free(sc->sc_dmat, 899 &sc->ale_cdata.ale_tx_cmb_seg, 1); 900 sc->ale_cdata.ale_tx_cmb = NULL; 901 sc->ale_cdata.ale_tx_cmb_map = NULL; 902 903 } 904 905 static int 906 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 907 { 908 struct ale_txdesc *txd, *txd_last; 909 struct tx_desc *desc; 910 struct mbuf *m; 911 bus_dmamap_t map; 912 uint32_t cflags, poff, vtag; 913 int error, i, nsegs, prod; 914 #if NVLAN > 0 915 struct m_tag *mtag; 916 #endif 917 918 m = *m_head; 919 cflags = vtag = 0; 920 poff = 0; 921 922 prod = sc->ale_cdata.ale_tx_prod; 923 txd = &sc->ale_cdata.ale_txdesc[prod]; 924 txd_last = txd; 925 map = txd->tx_dmamap; 926 927 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 928 if (error == EFBIG) { 929 error = 0; 930 931 *m_head = m_pullup(*m_head, MHLEN); 932 if (*m_head == NULL) { 933 printf("%s: can't defrag TX mbuf\n", 934 device_xname(sc->sc_dev)); 935 return ENOBUFS; 936 } 937 938 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 939 BUS_DMA_NOWAIT); 940 941 if (error != 0) { 942 printf("%s: could not load defragged TX mbuf\n", 943 device_xname(sc->sc_dev)); 944 m_freem(*m_head); 945 *m_head = NULL; 946 return error; 947 } 948 } else if (error) { 949 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 950 return error; 951 } 952 953 nsegs = map->dm_nsegs; 954 955 if (nsegs == 0) { 956 m_freem(*m_head); 957 *m_head = NULL; 958 return EIO; 959 } 960 961 /* Check descriptor overrun. */ 962 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 963 bus_dmamap_unload(sc->sc_dmat, map); 964 return ENOBUFS; 965 } 966 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 967 BUS_DMASYNC_PREWRITE); 968 969 m = *m_head; 970 /* Configure Tx checksum offload. */ 971 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 972 /* 973 * AR81xx supports Tx custom checksum offload feature 974 * that offloads single 16bit checksum computation. 975 * So you can choose one among IP, TCP and UDP. 976 * Normally driver sets checksum start/insertion 977 * position from the information of TCP/UDP frame as 978 * TCP/UDP checksum takes more time than that of IP. 979 * However it seems that custom checksum offload 980 * requires 4 bytes aligned Tx buffers due to hardware 981 * bug. 982 * AR81xx also supports explicit Tx checksum computation 983 * if it is told that the size of IP header and TCP 984 * header(for UDP, the header size does not matter 985 * because it's fixed length). However with this scheme 986 * TSO does not work so you have to choose one either 987 * TSO or explicit Tx checksum offload. I chosen TSO 988 * plus custom checksum offload with work-around which 989 * will cover most common usage for this consumer 990 * ethernet controller. The work-around takes a lot of 991 * CPU cycles if Tx buffer is not aligned on 4 bytes 992 * boundary, though. 993 */ 994 cflags |= ALE_TD_CXSUM; 995 /* Set checksum start offset. */ 996 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 997 } 998 999 #if NVLAN > 0 1000 /* Configure VLAN hardware tag insertion. */ 1001 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1002 vtag = ALE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1003 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1004 cflags |= ALE_TD_INSERT_VLAN_TAG; 1005 } 1006 #endif 1007 1008 desc = NULL; 1009 for (i = 0; i < nsegs; i++) { 1010 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1011 desc->addr = htole64(map->dm_segs[i].ds_addr); 1012 desc->len = 1013 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1014 desc->flags = htole32(cflags); 1015 sc->ale_cdata.ale_tx_cnt++; 1016 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1017 } 1018 /* Update producer index. */ 1019 sc->ale_cdata.ale_tx_prod = prod; 1020 1021 /* Finally set EOP on the last descriptor. */ 1022 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1023 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1024 desc->flags |= htole32(ALE_TD_EOP); 1025 1026 /* Swap dmamap of the first and the last. */ 1027 txd = &sc->ale_cdata.ale_txdesc[prod]; 1028 map = txd_last->tx_dmamap; 1029 txd_last->tx_dmamap = txd->tx_dmamap; 1030 txd->tx_dmamap = map; 1031 txd->tx_m = m; 1032 1033 /* Sync descriptors. */ 1034 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1035 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1036 1037 return 0; 1038 } 1039 1040 static void 1041 ale_start(struct ifnet *ifp) 1042 { 1043 struct ale_softc *sc = ifp->if_softc; 1044 struct mbuf *m_head; 1045 int enq; 1046 1047 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1048 return; 1049 1050 /* Reclaim transmitted frames. */ 1051 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1052 ale_txeof(sc); 1053 1054 enq = 0; 1055 for (;;) { 1056 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1057 if (m_head == NULL) 1058 break; 1059 1060 /* 1061 * Pack the data into the transmit ring. If we 1062 * don't have room, set the OACTIVE flag and wait 1063 * for the NIC to drain the ring. 1064 */ 1065 if (ale_encap(sc, &m_head)) { 1066 if (m_head == NULL) 1067 break; 1068 IF_PREPEND(&ifp->if_snd, m_head); 1069 ifp->if_flags |= IFF_OACTIVE; 1070 break; 1071 } 1072 enq = 1; 1073 1074 /* 1075 * If there's a BPF listener, bounce a copy of this frame 1076 * to him. 1077 */ 1078 bpf_mtap(ifp, m_head); 1079 } 1080 1081 if (enq) { 1082 /* Kick. */ 1083 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1084 sc->ale_cdata.ale_tx_prod); 1085 1086 /* Set a timeout in case the chip goes out to lunch. */ 1087 ifp->if_timer = ALE_TX_TIMEOUT; 1088 } 1089 } 1090 1091 static void 1092 ale_watchdog(struct ifnet *ifp) 1093 { 1094 struct ale_softc *sc = ifp->if_softc; 1095 1096 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1097 printf("%s: watchdog timeout (missed link)\n", 1098 device_xname(sc->sc_dev)); 1099 ifp->if_oerrors++; 1100 ale_init(ifp); 1101 return; 1102 } 1103 1104 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1105 ifp->if_oerrors++; 1106 ale_init(ifp); 1107 1108 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1109 ale_start(ifp); 1110 } 1111 1112 static int 1113 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1114 { 1115 struct ale_softc *sc = ifp->if_softc; 1116 int s, error; 1117 1118 s = splnet(); 1119 1120 error = ether_ioctl(ifp, cmd, data); 1121 if (error == ENETRESET) { 1122 if (ifp->if_flags & IFF_RUNNING) 1123 ale_rxfilter(sc); 1124 error = 0; 1125 } 1126 1127 splx(s); 1128 return error; 1129 } 1130 1131 static void 1132 ale_mac_config(struct ale_softc *sc) 1133 { 1134 struct mii_data *mii; 1135 uint32_t reg; 1136 1137 mii = &sc->sc_miibus; 1138 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1139 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1140 MAC_CFG_SPEED_MASK); 1141 1142 /* Reprogram MAC with resolved speed/duplex. */ 1143 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1144 case IFM_10_T: 1145 case IFM_100_TX: 1146 reg |= MAC_CFG_SPEED_10_100; 1147 break; 1148 case IFM_1000_T: 1149 reg |= MAC_CFG_SPEED_1000; 1150 break; 1151 } 1152 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1153 reg |= MAC_CFG_FULL_DUPLEX; 1154 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1155 reg |= MAC_CFG_TX_FC; 1156 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1157 reg |= MAC_CFG_RX_FC; 1158 } 1159 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1160 } 1161 1162 static void 1163 ale_stats_clear(struct ale_softc *sc) 1164 { 1165 struct smb sb; 1166 uint32_t *reg; 1167 int i; 1168 1169 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1170 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1171 i += sizeof(uint32_t); 1172 } 1173 /* Read Tx statistics. */ 1174 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1175 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1176 i += sizeof(uint32_t); 1177 } 1178 } 1179 1180 static void 1181 ale_stats_update(struct ale_softc *sc) 1182 { 1183 struct ifnet *ifp = &sc->sc_ec.ec_if; 1184 struct ale_hw_stats *stat; 1185 struct smb sb, *smb; 1186 uint32_t *reg; 1187 int i; 1188 1189 stat = &sc->ale_stats; 1190 smb = &sb; 1191 1192 /* Read Rx statistics. */ 1193 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1194 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1195 i += sizeof(uint32_t); 1196 } 1197 /* Read Tx statistics. */ 1198 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1199 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1200 i += sizeof(uint32_t); 1201 } 1202 1203 /* Rx stats. */ 1204 stat->rx_frames += smb->rx_frames; 1205 stat->rx_bcast_frames += smb->rx_bcast_frames; 1206 stat->rx_mcast_frames += smb->rx_mcast_frames; 1207 stat->rx_pause_frames += smb->rx_pause_frames; 1208 stat->rx_control_frames += smb->rx_control_frames; 1209 stat->rx_crcerrs += smb->rx_crcerrs; 1210 stat->rx_lenerrs += smb->rx_lenerrs; 1211 stat->rx_bytes += smb->rx_bytes; 1212 stat->rx_runts += smb->rx_runts; 1213 stat->rx_fragments += smb->rx_fragments; 1214 stat->rx_pkts_64 += smb->rx_pkts_64; 1215 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1216 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1217 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1218 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1219 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1220 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1221 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1222 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1223 stat->rx_rrs_errs += smb->rx_rrs_errs; 1224 stat->rx_alignerrs += smb->rx_alignerrs; 1225 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1226 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1227 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1228 1229 /* Tx stats. */ 1230 stat->tx_frames += smb->tx_frames; 1231 stat->tx_bcast_frames += smb->tx_bcast_frames; 1232 stat->tx_mcast_frames += smb->tx_mcast_frames; 1233 stat->tx_pause_frames += smb->tx_pause_frames; 1234 stat->tx_excess_defer += smb->tx_excess_defer; 1235 stat->tx_control_frames += smb->tx_control_frames; 1236 stat->tx_deferred += smb->tx_deferred; 1237 stat->tx_bytes += smb->tx_bytes; 1238 stat->tx_pkts_64 += smb->tx_pkts_64; 1239 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1240 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1241 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1242 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1243 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1244 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1245 stat->tx_single_colls += smb->tx_single_colls; 1246 stat->tx_multi_colls += smb->tx_multi_colls; 1247 stat->tx_late_colls += smb->tx_late_colls; 1248 stat->tx_excess_colls += smb->tx_excess_colls; 1249 stat->tx_abort += smb->tx_abort; 1250 stat->tx_underrun += smb->tx_underrun; 1251 stat->tx_desc_underrun += smb->tx_desc_underrun; 1252 stat->tx_lenerrs += smb->tx_lenerrs; 1253 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1254 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1255 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1256 1257 /* Update counters in ifnet. */ 1258 ifp->if_opackets += smb->tx_frames; 1259 1260 ifp->if_collisions += smb->tx_single_colls + 1261 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1262 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1263 1264 /* 1265 * XXX 1266 * tx_pkts_truncated counter looks suspicious. It constantly 1267 * increments with no sign of Tx errors. This may indicate 1268 * the counter name is not correct one so I've removed the 1269 * counter in output errors. 1270 */ 1271 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1272 smb->tx_underrun; 1273 1274 ifp->if_ipackets += smb->rx_frames; 1275 1276 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1277 smb->rx_runts + smb->rx_pkts_truncated + 1278 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1279 smb->rx_alignerrs; 1280 } 1281 1282 static int 1283 ale_intr(void *xsc) 1284 { 1285 struct ale_softc *sc = xsc; 1286 struct ifnet *ifp = &sc->sc_ec.ec_if; 1287 uint32_t status; 1288 1289 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1290 if ((status & ALE_INTRS) == 0) 1291 return 0; 1292 1293 /* Acknowledge and disable interrupts. */ 1294 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1295 1296 if (ifp->if_flags & IFF_RUNNING) { 1297 int error; 1298 1299 error = ale_rxeof(sc); 1300 if (error) { 1301 sc->ale_stats.reset_brk_seq++; 1302 ale_init(ifp); 1303 return 0; 1304 } 1305 1306 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1307 if (status & INTR_DMA_RD_TO_RST) 1308 printf("%s: DMA read error! -- resetting\n", 1309 device_xname(sc->sc_dev)); 1310 if (status & INTR_DMA_WR_TO_RST) 1311 printf("%s: DMA write error! -- resetting\n", 1312 device_xname(sc->sc_dev)); 1313 ale_init(ifp); 1314 return 0; 1315 } 1316 1317 ale_txeof(sc); 1318 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1319 ale_start(ifp); 1320 } 1321 1322 /* Re-enable interrupts. */ 1323 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1324 return 1; 1325 } 1326 1327 static void 1328 ale_txeof(struct ale_softc *sc) 1329 { 1330 struct ifnet *ifp = &sc->sc_ec.ec_if; 1331 struct ale_txdesc *txd; 1332 uint32_t cons, prod; 1333 int prog; 1334 1335 if (sc->ale_cdata.ale_tx_cnt == 0) 1336 return; 1337 1338 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1339 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1340 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1341 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1342 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1343 BUS_DMASYNC_POSTREAD); 1344 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1345 } else 1346 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1347 cons = sc->ale_cdata.ale_tx_cons; 1348 /* 1349 * Go through our Tx list and free mbufs for those 1350 * frames which have been transmitted. 1351 */ 1352 for (prog = 0; cons != prod; prog++, 1353 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1354 if (sc->ale_cdata.ale_tx_cnt <= 0) 1355 break; 1356 prog++; 1357 ifp->if_flags &= ~IFF_OACTIVE; 1358 sc->ale_cdata.ale_tx_cnt--; 1359 txd = &sc->ale_cdata.ale_txdesc[cons]; 1360 if (txd->tx_m != NULL) { 1361 /* Reclaim transmitted mbufs. */ 1362 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1363 m_freem(txd->tx_m); 1364 txd->tx_m = NULL; 1365 } 1366 } 1367 1368 if (prog > 0) { 1369 sc->ale_cdata.ale_tx_cons = cons; 1370 /* 1371 * Unarm watchdog timer only when there is no pending 1372 * Tx descriptors in queue. 1373 */ 1374 if (sc->ale_cdata.ale_tx_cnt == 0) 1375 ifp->if_timer = 0; 1376 } 1377 } 1378 1379 static void 1380 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1381 uint32_t length, uint32_t *prod) 1382 { 1383 struct ale_rx_page *rx_page; 1384 1385 rx_page = *page; 1386 /* Update consumer position. */ 1387 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1388 ALE_RX_PAGE_ALIGN); 1389 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1390 /* 1391 * End of Rx page reached, let hardware reuse 1392 * this page. 1393 */ 1394 rx_page->cons = 0; 1395 *rx_page->cmb_addr = 0; 1396 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1397 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1398 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1399 RXF_VALID); 1400 /* Switch to alternate Rx page. */ 1401 sc->ale_cdata.ale_rx_curp ^= 1; 1402 rx_page = *page = 1403 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1404 /* Page flipped, sync CMB and Rx page. */ 1405 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1406 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1407 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1408 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1409 /* Sync completed, cache updated producer index. */ 1410 *prod = *rx_page->cmb_addr; 1411 } 1412 } 1413 1414 1415 /* 1416 * It seems that AR81xx controller can compute partial checksum. 1417 * The partial checksum value can be used to accelerate checksum 1418 * computation for fragmented TCP/UDP packets. Upper network stack 1419 * already takes advantage of the partial checksum value in IP 1420 * reassembly stage. But I'm not sure the correctness of the 1421 * partial hardware checksum assistance due to lack of data sheet. 1422 * In addition, the Rx feature of controller that requires copying 1423 * for every frames effectively nullifies one of most nice offload 1424 * capability of controller. 1425 */ 1426 static void 1427 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1428 { 1429 if (status & ALE_RD_IPCSUM_NOK) 1430 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1431 1432 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1433 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1434 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1435 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1436 { 1437 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1438 } 1439 } else { 1440 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1441 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1442 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1443 } 1444 } 1445 } 1446 /* 1447 * Don't mark bad checksum for TCP/UDP frames 1448 * as fragmented frames may always have set 1449 * bad checksummed bit of frame status. 1450 */ 1451 } 1452 1453 /* Process received frames. */ 1454 static int 1455 ale_rxeof(struct ale_softc *sc) 1456 { 1457 struct ifnet *ifp = &sc->sc_ec.ec_if; 1458 struct ale_rx_page *rx_page; 1459 struct rx_rs *rs; 1460 struct mbuf *m; 1461 uint32_t length, prod, seqno, status; 1462 int prog; 1463 1464 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1465 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1466 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1467 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1468 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1469 /* 1470 * Don't directly access producer index as hardware may 1471 * update it while Rx handler is in progress. It would 1472 * be even better if there is a way to let hardware 1473 * know how far driver processed its received frames. 1474 * Alternatively, hardware could provide a way to disable 1475 * CMB updates until driver acknowledges the end of CMB 1476 * access. 1477 */ 1478 prod = *rx_page->cmb_addr; 1479 for (prog = 0; ; prog++) { 1480 if (rx_page->cons >= prod) 1481 break; 1482 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1483 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1484 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1485 /* 1486 * Normally I believe this should not happen unless 1487 * severe driver bug or corrupted memory. However 1488 * it seems to happen under certain conditions which 1489 * is triggered by abrupt Rx events such as initiation 1490 * of bulk transfer of remote host. It's not easy to 1491 * reproduce this and I doubt it could be related 1492 * with FIFO overflow of hardware or activity of Tx 1493 * CMB updates. I also remember similar behaviour 1494 * seen on RealTek 8139 which uses resembling Rx 1495 * scheme. 1496 */ 1497 if (aledebug) 1498 printf("%s: garbled seq: %u, expected: %u -- " 1499 "resetting!\n", device_xname(sc->sc_dev), 1500 seqno, sc->ale_cdata.ale_rx_seqno); 1501 return EIO; 1502 } 1503 /* Frame received. */ 1504 sc->ale_cdata.ale_rx_seqno++; 1505 length = ALE_RX_BYTES(le32toh(rs->length)); 1506 status = le32toh(rs->flags); 1507 if (status & ALE_RD_ERROR) { 1508 /* 1509 * We want to pass the following frames to upper 1510 * layer regardless of error status of Rx return 1511 * status. 1512 * 1513 * o IP/TCP/UDP checksum is bad. 1514 * o frame length and protocol specific length 1515 * does not match. 1516 */ 1517 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1518 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1519 ALE_RD_TRUNC)) { 1520 ale_rx_update_page(sc, &rx_page, length, &prod); 1521 continue; 1522 } 1523 } 1524 /* 1525 * m_devget(9) is major bottle-neck of ale(4)(It comes 1526 * from hardware limitation). For jumbo frames we could 1527 * get a slightly better performance if driver use 1528 * m_getjcl(9) with proper buffer size argument. However 1529 * that would make code more complicated and I don't 1530 * think users would expect good Rx performance numbers 1531 * on these low-end consumer ethernet controller. 1532 */ 1533 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1534 0, ifp, NULL); 1535 if (m == NULL) { 1536 ifp->if_iqdrops++; 1537 ale_rx_update_page(sc, &rx_page, length, &prod); 1538 continue; 1539 } 1540 if (status & ALE_RD_IPV4) 1541 ale_rxcsum(sc, m, status); 1542 #if NVLAN > 0 1543 if (status & ALE_RD_VLAN) { 1544 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1545 VLAN_INPUT_TAG(ifp, m, ALE_RX_VLAN_TAG(vtags), ); 1546 } 1547 #endif 1548 1549 1550 bpf_mtap(ifp, m); 1551 1552 /* Pass it to upper layer. */ 1553 (*ifp->if_input)(ifp, m); 1554 1555 ale_rx_update_page(sc, &rx_page, length, &prod); 1556 } 1557 1558 return 0; 1559 } 1560 1561 static void 1562 ale_tick(void *xsc) 1563 { 1564 struct ale_softc *sc = xsc; 1565 struct mii_data *mii = &sc->sc_miibus; 1566 int s; 1567 1568 s = splnet(); 1569 mii_tick(mii); 1570 ale_stats_update(sc); 1571 splx(s); 1572 1573 callout_schedule(&sc->sc_tick_ch, hz); 1574 } 1575 1576 static void 1577 ale_reset(struct ale_softc *sc) 1578 { 1579 uint32_t reg; 1580 int i; 1581 1582 /* Initialize PCIe module. From Linux. */ 1583 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1584 1585 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1586 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1587 DELAY(10); 1588 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1589 break; 1590 } 1591 if (i == 0) 1592 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1593 1594 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1595 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1596 break; 1597 DELAY(10); 1598 } 1599 1600 if (i == 0) 1601 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1602 reg); 1603 } 1604 1605 static int 1606 ale_init(struct ifnet *ifp) 1607 { 1608 struct ale_softc *sc = ifp->if_softc; 1609 struct mii_data *mii; 1610 uint8_t eaddr[ETHER_ADDR_LEN]; 1611 bus_addr_t paddr; 1612 uint32_t reg, rxf_hi, rxf_lo; 1613 1614 /* 1615 * Cancel any pending I/O. 1616 */ 1617 ale_stop(ifp, 0); 1618 1619 /* 1620 * Reset the chip to a known state. 1621 */ 1622 ale_reset(sc); 1623 1624 /* Initialize Tx descriptors, DMA memory blocks. */ 1625 ale_init_rx_pages(sc); 1626 ale_init_tx_ring(sc); 1627 1628 /* Reprogram the station address. */ 1629 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1630 CSR_WRITE_4(sc, ALE_PAR0, 1631 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1632 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1633 1634 /* 1635 * Clear WOL status and disable all WOL feature as WOL 1636 * would interfere Rx operation under normal environments. 1637 */ 1638 CSR_READ_4(sc, ALE_WOL_CFG); 1639 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1640 1641 /* 1642 * Set Tx descriptor/RXF0/CMB base addresses. They share 1643 * the same high address part of DMAable region. 1644 */ 1645 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1646 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1647 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1648 CSR_WRITE_4(sc, ALE_TPD_CNT, 1649 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1650 1651 /* Set Rx page base address, note we use single queue. */ 1652 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1653 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1654 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1655 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1656 1657 /* Set Tx/Rx CMB addresses. */ 1658 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1659 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1660 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1661 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1662 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1663 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1664 1665 /* Mark RXF0 is valid. */ 1666 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1667 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1668 /* 1669 * No need to initialize RFX1/RXF2/RXF3. We don't use 1670 * multi-queue yet. 1671 */ 1672 1673 /* Set Rx page size, excluding guard frame size. */ 1674 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1675 1676 /* Tell hardware that we're ready to load DMA blocks. */ 1677 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1678 1679 /* Set Rx/Tx interrupt trigger threshold. */ 1680 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1681 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1682 /* 1683 * XXX 1684 * Set interrupt trigger timer, its purpose and relation 1685 * with interrupt moderation mechanism is not clear yet. 1686 */ 1687 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1688 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1689 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1690 1691 /* Configure interrupt moderation timer. */ 1692 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1693 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1694 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1695 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1696 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1697 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1698 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1699 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1700 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1701 reg |= MASTER_IM_RX_TIMER_ENB; 1702 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1703 reg |= MASTER_IM_TX_TIMER_ENB; 1704 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1705 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1706 1707 /* Set Maximum frame size of controller. */ 1708 if (ifp->if_mtu < ETHERMTU) 1709 sc->ale_max_frame_size = ETHERMTU; 1710 else 1711 sc->ale_max_frame_size = ifp->if_mtu; 1712 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1713 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1714 1715 /* Configure IPG/IFG parameters. */ 1716 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1717 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1718 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1719 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1720 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1721 1722 /* Set parameters for half-duplex media. */ 1723 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1724 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1725 HDPX_CFG_LCOL_MASK) | 1726 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1727 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1728 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1729 HDPX_CFG_ABEBT_MASK) | 1730 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1731 HDPX_CFG_JAMIPG_MASK)); 1732 1733 /* Configure Tx jumbo frame parameters. */ 1734 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1735 if (ifp->if_mtu < ETHERMTU) 1736 reg = sc->ale_max_frame_size; 1737 else if (ifp->if_mtu < 6 * 1024) 1738 reg = (sc->ale_max_frame_size * 2) / 3; 1739 else 1740 reg = sc->ale_max_frame_size / 2; 1741 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1742 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1743 TX_JUMBO_THRESH_UNIT_SHIFT); 1744 } 1745 1746 /* Configure TxQ. */ 1747 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1748 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1749 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1750 TXQ_CFG_TPD_BURST_MASK; 1751 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1752 1753 /* Configure Rx jumbo frame & flow control parameters. */ 1754 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1755 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1756 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1757 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1758 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1759 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1760 RX_JUMBO_LKAH_MASK)); 1761 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1762 rxf_hi = (reg * 7) / 10; 1763 rxf_lo = (reg * 3)/ 10; 1764 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1765 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1766 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1767 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1768 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1769 } 1770 1771 /* Disable RSS. */ 1772 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1773 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1774 1775 /* Configure RxQ. */ 1776 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1777 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1778 1779 /* Configure DMA parameters. */ 1780 reg = 0; 1781 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1782 reg |= DMA_CFG_TXCMB_ENB; 1783 CSR_WRITE_4(sc, ALE_DMA_CFG, 1784 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1785 sc->ale_dma_rd_burst | reg | 1786 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1787 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1788 DMA_CFG_RD_DELAY_CNT_MASK) | 1789 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1790 DMA_CFG_WR_DELAY_CNT_MASK)); 1791 1792 /* 1793 * Hardware can be configured to issue SMB interrupt based 1794 * on programmed interval. Since there is a callout that is 1795 * invoked for every hz in driver we use that instead of 1796 * relying on periodic SMB interrupt. 1797 */ 1798 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1799 1800 /* Clear MAC statistics. */ 1801 ale_stats_clear(sc); 1802 1803 /* 1804 * Configure Tx/Rx MACs. 1805 * - Auto-padding for short frames. 1806 * - Enable CRC generation. 1807 * Actual reconfiguration of MAC for resolved speed/duplex 1808 * is followed after detection of link establishment. 1809 * AR81xx always does checksum computation regardless of 1810 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1811 * cause Rx handling issue for fragmented IP datagrams due 1812 * to silicon bug. 1813 */ 1814 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1815 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1816 MAC_CFG_PREAMBLE_MASK); 1817 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1818 reg |= MAC_CFG_SPEED_10_100; 1819 else 1820 reg |= MAC_CFG_SPEED_1000; 1821 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1822 1823 /* Set up the receive filter. */ 1824 ale_rxfilter(sc); 1825 ale_rxvlan(sc); 1826 1827 /* Acknowledge all pending interrupts and clear it. */ 1828 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1829 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1830 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1831 1832 sc->ale_flags &= ~ALE_FLAG_LINK; 1833 1834 /* Switch to the current media. */ 1835 mii = &sc->sc_miibus; 1836 mii_mediachg(mii); 1837 1838 callout_schedule(&sc->sc_tick_ch, hz); 1839 1840 ifp->if_flags |= IFF_RUNNING; 1841 ifp->if_flags &= ~IFF_OACTIVE; 1842 1843 return 0; 1844 } 1845 1846 static void 1847 ale_stop(struct ifnet *ifp, int disable) 1848 { 1849 struct ale_softc *sc = ifp->if_softc; 1850 struct ale_txdesc *txd; 1851 uint32_t reg; 1852 int i; 1853 1854 callout_stop(&sc->sc_tick_ch); 1855 1856 /* 1857 * Mark the interface down and cancel the watchdog timer. 1858 */ 1859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1860 ifp->if_timer = 0; 1861 1862 sc->ale_flags &= ~ALE_FLAG_LINK; 1863 1864 ale_stats_update(sc); 1865 1866 mii_down(&sc->sc_miibus); 1867 1868 /* Disable interrupts. */ 1869 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1870 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1871 1872 /* Disable queue processing and DMA. */ 1873 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1874 reg &= ~TXQ_CFG_ENB; 1875 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1876 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1877 reg &= ~RXQ_CFG_ENB; 1878 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1879 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1880 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1881 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1882 DELAY(1000); 1883 1884 /* Stop Rx/Tx MACs. */ 1885 ale_stop_mac(sc); 1886 1887 /* Disable interrupts again? XXX */ 1888 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1889 1890 /* 1891 * Free TX mbufs still in the queues. 1892 */ 1893 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1894 txd = &sc->ale_cdata.ale_txdesc[i]; 1895 if (txd->tx_m != NULL) { 1896 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1897 m_freem(txd->tx_m); 1898 txd->tx_m = NULL; 1899 } 1900 } 1901 } 1902 1903 static void 1904 ale_stop_mac(struct ale_softc *sc) 1905 { 1906 uint32_t reg; 1907 int i; 1908 1909 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1910 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1911 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 1912 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1913 } 1914 1915 for (i = ALE_TIMEOUT; i > 0; i--) { 1916 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1917 if (reg == 0) 1918 break; 1919 DELAY(10); 1920 } 1921 if (i == 0) 1922 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1923 device_xname(sc->sc_dev), reg); 1924 } 1925 1926 static void 1927 ale_init_tx_ring(struct ale_softc *sc) 1928 { 1929 struct ale_txdesc *txd; 1930 int i; 1931 1932 sc->ale_cdata.ale_tx_prod = 0; 1933 sc->ale_cdata.ale_tx_cons = 0; 1934 sc->ale_cdata.ale_tx_cnt = 0; 1935 1936 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1937 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1938 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1939 txd = &sc->ale_cdata.ale_txdesc[i]; 1940 txd->tx_m = NULL; 1941 } 1942 *sc->ale_cdata.ale_tx_cmb = 0; 1943 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1944 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1945 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1946 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1947 } 1948 1949 static void 1950 ale_init_rx_pages(struct ale_softc *sc) 1951 { 1952 struct ale_rx_page *rx_page; 1953 int i; 1954 1955 sc->ale_cdata.ale_rx_seqno = 0; 1956 sc->ale_cdata.ale_rx_curp = 0; 1957 1958 for (i = 0; i < ALE_RX_PAGES; i++) { 1959 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1960 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1961 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1962 rx_page->cons = 0; 1963 *rx_page->cmb_addr = 0; 1964 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1965 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1966 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1967 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1968 } 1969 } 1970 1971 static void 1972 ale_rxvlan(struct ale_softc *sc) 1973 { 1974 uint32_t reg; 1975 1976 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1977 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1978 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 1979 reg |= MAC_CFG_VLAN_TAG_STRIP; 1980 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1981 } 1982 1983 static void 1984 ale_rxfilter(struct ale_softc *sc) 1985 { 1986 struct ethercom *ec = &sc->sc_ec; 1987 struct ifnet *ifp = &ec->ec_if; 1988 struct ether_multi *enm; 1989 struct ether_multistep step; 1990 uint32_t crc; 1991 uint32_t mchash[2]; 1992 uint32_t rxcfg; 1993 1994 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 1995 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 1996 ifp->if_flags &= ~IFF_ALLMULTI; 1997 1998 /* 1999 * Always accept broadcast frames. 2000 */ 2001 rxcfg |= MAC_CFG_BCAST; 2002 2003 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2004 ifp->if_flags |= IFF_ALLMULTI; 2005 if (ifp->if_flags & IFF_PROMISC) 2006 rxcfg |= MAC_CFG_PROMISC; 2007 else 2008 rxcfg |= MAC_CFG_ALLMULTI; 2009 mchash[0] = mchash[1] = 0xFFFFFFFF; 2010 } else { 2011 /* Program new filter. */ 2012 memset(mchash, 0, sizeof(mchash)); 2013 2014 ETHER_FIRST_MULTI(step, ec, enm); 2015 while (enm != NULL) { 2016 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2017 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2018 ETHER_NEXT_MULTI(step, enm); 2019 } 2020 } 2021 2022 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2023 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2024 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2025 } 2026