1 /* $NetBSD: if_ale.c,v 1.9 2009/10/08 08:57:19 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 */ 31 32 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.9 2009/10/08 08:57:19 cegger Exp $"); 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/proc.h> 42 #include <sys/endian.h> 43 #include <sys/systm.h> 44 #include <sys/types.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/queue.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/callout.h> 51 #include <sys/socket.h> 52 53 #include <sys/bus.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_llc.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #ifdef INET 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/in_var.h> 65 #include <netinet/ip.h> 66 #endif 67 68 #include <net/if_types.h> 69 #include <net/if_vlanvar.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <sys/rnd.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcidevs.h> 83 84 #include <dev/pci/if_alereg.h> 85 86 static int ale_match(device_t, cfdata_t, void *); 87 static void ale_attach(device_t, device_t, void *); 88 static int ale_detach(device_t, int); 89 90 static int ale_miibus_readreg(device_t, int, int); 91 static void ale_miibus_writereg(device_t, int, int, int); 92 static void ale_miibus_statchg(device_t); 93 94 static int ale_init(struct ifnet *); 95 static void ale_start(struct ifnet *); 96 static int ale_ioctl(struct ifnet *, u_long, void *); 97 static void ale_watchdog(struct ifnet *); 98 static int ale_mediachange(struct ifnet *); 99 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 100 101 static int ale_intr(void *); 102 static int ale_rxeof(struct ale_softc *sc); 103 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 104 uint32_t, uint32_t *); 105 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 106 static void ale_txeof(struct ale_softc *); 107 108 static int ale_dma_alloc(struct ale_softc *); 109 static void ale_dma_free(struct ale_softc *); 110 static int ale_encap(struct ale_softc *, struct mbuf **); 111 static void ale_init_rx_pages(struct ale_softc *); 112 static void ale_init_tx_ring(struct ale_softc *); 113 114 static void ale_stop(struct ifnet *, int); 115 static void ale_tick(void *); 116 static void ale_get_macaddr(struct ale_softc *); 117 static void ale_mac_config(struct ale_softc *); 118 static void ale_phy_reset(struct ale_softc *); 119 static void ale_reset(struct ale_softc *); 120 static void ale_rxfilter(struct ale_softc *); 121 static void ale_rxvlan(struct ale_softc *); 122 static void ale_stats_clear(struct ale_softc *); 123 static void ale_stats_update(struct ale_softc *); 124 static void ale_stop_mac(struct ale_softc *); 125 126 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 127 ale_match, ale_attach, ale_detach, NULL); 128 129 int aledebug = 0; 130 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 ale_miibus_readreg(device_t dev, int phy, int reg) 137 { 138 struct ale_softc *sc = device_private(dev); 139 uint32_t v; 140 int i; 141 142 if (phy != sc->ale_phyaddr) 143 return 0; 144 145 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 146 switch (reg) { 147 case MII_100T2CR: 148 case MII_100T2SR: 149 case MII_EXTSR: 150 return 0; 151 default: 152 break; 153 } 154 } 155 156 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 157 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 158 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 159 DELAY(5); 160 v = CSR_READ_4(sc, ALE_MDIO); 161 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 162 break; 163 } 164 165 if (i == 0) { 166 printf("%s: phy read timeout: phy %d, reg %d\n", 167 device_xname(sc->sc_dev), phy, reg); 168 return 0; 169 } 170 171 return (v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT; 172 } 173 174 static void 175 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 176 { 177 struct ale_softc *sc = device_private(dev); 178 uint32_t v; 179 int i; 180 181 if (phy != sc->ale_phyaddr) 182 return; 183 184 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 185 switch (reg) { 186 case MII_100T2CR: 187 case MII_100T2SR: 188 case MII_EXTSR: 189 return; 190 default: 191 break; 192 } 193 } 194 195 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 196 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 197 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 198 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 199 DELAY(5); 200 v = CSR_READ_4(sc, ALE_MDIO); 201 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 202 break; 203 } 204 205 if (i == 0) 206 printf("%s: phy write timeout: phy %d, reg %d\n", 207 device_xname(sc->sc_dev), phy, reg); 208 } 209 210 static void 211 ale_miibus_statchg(device_t dev) 212 { 213 struct ale_softc *sc = device_private(dev); 214 struct ifnet *ifp = &sc->sc_ec.ec_if; 215 struct mii_data *mii; 216 uint32_t reg; 217 218 if ((ifp->if_flags & IFF_RUNNING) == 0) 219 return; 220 221 mii = &sc->sc_miibus; 222 223 sc->ale_flags &= ~ALE_FLAG_LINK; 224 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 225 (IFM_ACTIVE | IFM_AVALID)) { 226 switch (IFM_SUBTYPE(mii->mii_media_active)) { 227 case IFM_10_T: 228 case IFM_100_TX: 229 sc->ale_flags |= ALE_FLAG_LINK; 230 break; 231 232 case IFM_1000_T: 233 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 234 sc->ale_flags |= ALE_FLAG_LINK; 235 break; 236 237 default: 238 break; 239 } 240 } 241 242 /* Stop Rx/Tx MACs. */ 243 ale_stop_mac(sc); 244 245 /* Program MACs with resolved speed/duplex/flow-control. */ 246 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 247 ale_mac_config(sc); 248 /* Reenable Tx/Rx MACs. */ 249 reg = CSR_READ_4(sc, ALE_MAC_CFG); 250 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 251 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 252 } 253 } 254 255 void 256 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 257 { 258 struct ale_softc *sc = ifp->if_softc; 259 struct mii_data *mii = &sc->sc_miibus; 260 261 mii_pollstat(mii); 262 ifmr->ifm_status = mii->mii_media_status; 263 ifmr->ifm_active = mii->mii_media_active; 264 } 265 266 int 267 ale_mediachange(struct ifnet *ifp) 268 { 269 struct ale_softc *sc = ifp->if_softc; 270 struct mii_data *mii = &sc->sc_miibus; 271 int error; 272 273 if (mii->mii_instance != 0) { 274 struct mii_softc *miisc; 275 276 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 277 mii_phy_reset(miisc); 278 } 279 error = mii_mediachg(mii); 280 281 return error; 282 } 283 284 int 285 ale_match(device_t dev, cfdata_t match, void *aux) 286 { 287 struct pci_attach_args *pa = aux; 288 289 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 290 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 291 } 292 293 void 294 ale_get_macaddr(struct ale_softc *sc) 295 { 296 uint32_t ea[2], reg; 297 int i, vpdc; 298 299 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 300 if ((reg & SPI_VPD_ENB) != 0) { 301 reg &= ~SPI_VPD_ENB; 302 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 303 } 304 305 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 306 &vpdc, NULL)) { 307 /* 308 * PCI VPD capability found, let TWSI reload EEPROM. 309 * This will set ethernet address of controller. 310 */ 311 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 312 TWSI_CTRL_SW_LD_START); 313 for (i = 100; i > 0; i--) { 314 DELAY(1000); 315 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 316 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 317 break; 318 } 319 if (i == 0) 320 printf("%s: reloading EEPROM timeout!\n", 321 device_xname(sc->sc_dev)); 322 } else { 323 if (aledebug) 324 printf("%s: PCI VPD capability not found!\n", 325 device_xname(sc->sc_dev)); 326 } 327 328 ea[0] = CSR_READ_4(sc, ALE_PAR0); 329 ea[1] = CSR_READ_4(sc, ALE_PAR1); 330 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 331 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 332 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 333 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 334 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 335 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 336 } 337 338 void 339 ale_phy_reset(struct ale_softc *sc) 340 { 341 /* Reset magic from Linux. */ 342 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 343 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 344 GPHY_CTRL_PHY_PLL_ON); 345 DELAY(1000); 346 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 347 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 348 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 349 DELAY(1000); 350 351 #define ATPHY_DBG_ADDR 0x1D 352 #define ATPHY_DBG_DATA 0x1E 353 354 /* Enable hibernation mode. */ 355 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 356 ATPHY_DBG_ADDR, 0x0B); 357 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 358 ATPHY_DBG_DATA, 0xBC00); 359 /* Set Class A/B for all modes. */ 360 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 361 ATPHY_DBG_ADDR, 0x00); 362 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 363 ATPHY_DBG_DATA, 0x02EF); 364 /* Enable 10BT power saving. */ 365 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 366 ATPHY_DBG_ADDR, 0x12); 367 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 368 ATPHY_DBG_DATA, 0x4C04); 369 /* Adjust 1000T power. */ 370 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 371 ATPHY_DBG_ADDR, 0x04); 372 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 373 ATPHY_DBG_ADDR, 0x8BBB); 374 /* 10BT center tap voltage. */ 375 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 376 ATPHY_DBG_ADDR, 0x05); 377 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 378 ATPHY_DBG_ADDR, 0x2C46); 379 380 #undef ATPHY_DBG_ADDR 381 #undef ATPHY_DBG_DATA 382 DELAY(1000); 383 } 384 385 void 386 ale_attach(device_t parent, device_t self, void *aux) 387 { 388 struct ale_softc *sc = device_private(self); 389 struct pci_attach_args *pa = aux; 390 pci_chipset_tag_t pc = pa->pa_pc; 391 pci_intr_handle_t ih; 392 const char *intrstr; 393 struct ifnet *ifp; 394 pcireg_t memtype; 395 int mii_flags, error = 0; 396 uint32_t rxf_len, txf_len; 397 const char *chipname; 398 399 aprint_naive("\n"); 400 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 401 402 sc->sc_dev = self; 403 sc->sc_dmat = pa->pa_dmat; 404 sc->sc_pct = pa->pa_pc; 405 sc->sc_pcitag = pa->pa_tag; 406 407 /* 408 * Allocate IO memory 409 */ 410 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 411 switch (memtype) { 412 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 413 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 414 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 415 break; 416 default: 417 aprint_error_dev(self, "invalid base address register\n"); 418 break; 419 } 420 421 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 422 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 423 aprint_error_dev(self, "could not map mem space\n"); 424 return; 425 } 426 427 if (pci_intr_map(pa, &ih) != 0) { 428 aprint_error_dev(self, "could not map interrupt\n"); 429 goto fail; 430 } 431 432 /* 433 * Allocate IRQ 434 */ 435 intrstr = pci_intr_string(sc->sc_pct, ih); 436 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc); 437 if (sc->sc_irq_handle == NULL) { 438 aprint_error_dev(self, "could not establish interrupt"); 439 if (intrstr != NULL) 440 aprint_error(" at %s", intrstr); 441 aprint_error("\n"); 442 goto fail; 443 } 444 445 /* Set PHY address. */ 446 sc->ale_phyaddr = ALE_PHY_ADDR; 447 448 /* Reset PHY. */ 449 ale_phy_reset(sc); 450 451 /* Reset the ethernet controller. */ 452 ale_reset(sc); 453 454 /* Get PCI and chip id/revision. */ 455 sc->ale_rev = PCI_REVISION(pa->pa_class); 456 if (sc->ale_rev >= 0xF0) { 457 /* L2E Rev. B. AR8114 */ 458 sc->ale_flags |= ALE_FLAG_FASTETHER; 459 chipname = "AR8114 (L2E RevB)"; 460 } else { 461 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 462 /* L1E AR8121 */ 463 sc->ale_flags |= ALE_FLAG_JUMBO; 464 chipname = "AR8121 (L1E)"; 465 } else { 466 /* L2E Rev. A. AR8113 */ 467 sc->ale_flags |= ALE_FLAG_FASTETHER; 468 chipname = "AR8113 (L2E RevA)"; 469 } 470 } 471 aprint_normal_dev(self, "%s, %s\n", chipname, intrstr); 472 473 /* 474 * All known controllers seems to require 4 bytes alignment 475 * of Tx buffers to make Tx checksum offload with custom 476 * checksum generation method work. 477 */ 478 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 479 480 /* 481 * All known controllers seems to have issues on Rx checksum 482 * offload for fragmented IP datagrams. 483 */ 484 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 485 486 /* 487 * Don't use Tx CMB. It is known to cause RRS update failure 488 * under certain circumstances. Typical phenomenon of the 489 * issue would be unexpected sequence number encountered in 490 * Rx handler. 491 */ 492 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 493 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 494 MASTER_CHIP_REV_SHIFT; 495 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 496 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 497 498 /* 499 * Uninitialized hardware returns an invalid chip id/revision 500 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 501 */ 502 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 503 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 504 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 505 rxf_len == 0xFFFFFFF) { 506 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 507 "%u Rx FIFO -- not initialized?\n", 508 sc->ale_chip_rev, txf_len, rxf_len); 509 goto fail; 510 } 511 512 if (aledebug) { 513 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 514 txf_len, rxf_len); 515 } 516 517 /* Set max allowable DMA size. */ 518 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 519 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 520 521 callout_init(&sc->sc_tick_ch, 0); 522 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 523 524 error = ale_dma_alloc(sc); 525 if (error) 526 goto fail; 527 528 /* Load station address. */ 529 ale_get_macaddr(sc); 530 531 aprint_normal_dev(self, "Ethernet address %s\n", 532 ether_sprintf(sc->ale_eaddr)); 533 534 ifp = &sc->sc_ec.ec_if; 535 ifp->if_softc = sc; 536 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 537 ifp->if_init = ale_init; 538 ifp->if_ioctl = ale_ioctl; 539 ifp->if_start = ale_start; 540 ifp->if_stop = ale_stop; 541 ifp->if_watchdog = ale_watchdog; 542 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 543 IFQ_SET_READY(&ifp->if_snd); 544 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 545 546 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 547 548 #ifdef ALE_CHECKSUM 549 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 550 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 551 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 552 #endif 553 554 #if NVLAN > 0 555 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 556 #endif 557 558 /* Set up MII bus. */ 559 sc->sc_miibus.mii_ifp = ifp; 560 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 561 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 562 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 563 564 sc->sc_ec.ec_mii = &sc->sc_miibus; 565 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 566 ale_mediastatus); 567 mii_flags = 0; 568 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 569 mii_flags |= MIIF_DOPAUSE; 570 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 571 MII_OFFSET_ANY, mii_flags); 572 573 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 574 aprint_error_dev(self, "no PHY found!\n"); 575 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 576 0, NULL); 577 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 578 } else 579 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 580 581 if_attach(ifp); 582 ether_ifattach(ifp, sc->ale_eaddr); 583 584 if (pmf_device_register(self, NULL, NULL)) 585 pmf_class_network_register(self, ifp); 586 else 587 aprint_error_dev(self, "couldn't establish power handler\n"); 588 589 return; 590 fail: 591 ale_dma_free(sc); 592 if (sc->sc_irq_handle != NULL) { 593 pci_intr_disestablish(pc, sc->sc_irq_handle); 594 sc->sc_irq_handle = NULL; 595 } 596 if (sc->sc_mem_size) { 597 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 598 sc->sc_mem_size = 0; 599 } 600 } 601 602 static int 603 ale_detach(device_t self, int flags) 604 { 605 struct ale_softc *sc = device_private(self); 606 struct ifnet *ifp = &sc->sc_ec.ec_if; 607 int s; 608 609 pmf_device_deregister(self); 610 s = splnet(); 611 ale_stop(ifp, 0); 612 splx(s); 613 614 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 615 616 /* Delete all remaining media. */ 617 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 618 619 ether_ifdetach(ifp); 620 if_detach(ifp); 621 ale_dma_free(sc); 622 623 if (sc->sc_irq_handle != NULL) { 624 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 625 sc->sc_irq_handle = NULL; 626 } 627 if (sc->sc_mem_size) { 628 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 629 sc->sc_mem_size = 0; 630 } 631 632 return 0; 633 } 634 635 636 static int 637 ale_dma_alloc(struct ale_softc *sc) 638 { 639 struct ale_txdesc *txd; 640 int nsegs, error, guard_size, i; 641 642 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 643 guard_size = ALE_JUMBO_FRAMELEN; 644 else 645 guard_size = ALE_MAX_FRAMELEN; 646 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 647 ALE_RX_PAGE_ALIGN); 648 649 /* 650 * Create DMA stuffs for TX ring 651 */ 652 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 653 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 654 if (error) { 655 sc->ale_cdata.ale_tx_ring_map = NULL; 656 return ENOBUFS; 657 } 658 659 /* Allocate DMA'able memory for TX ring */ 660 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 661 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 662 &nsegs, BUS_DMA_WAITOK); 663 if (error) { 664 printf("%s: could not allocate DMA'able memory for Tx ring, " 665 "error = %i\n", device_xname(sc->sc_dev), error); 666 return error; 667 } 668 669 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 670 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 671 BUS_DMA_NOWAIT); 672 if (error) 673 return ENOBUFS; 674 675 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 676 677 /* Load the DMA map for Tx ring. */ 678 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 679 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 680 if (error) { 681 printf("%s: could not load DMA'able memory for Tx ring.\n", 682 device_xname(sc->sc_dev)); 683 bus_dmamem_free(sc->sc_dmat, 684 &sc->ale_cdata.ale_tx_ring_seg, 1); 685 return error; 686 } 687 sc->ale_cdata.ale_tx_ring_paddr = 688 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 689 690 for (i = 0; i < ALE_RX_PAGES; i++) { 691 /* 692 * Create DMA stuffs for RX pages 693 */ 694 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 695 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 696 &sc->ale_cdata.ale_rx_page[i].page_map); 697 if (error) { 698 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 699 return ENOBUFS; 700 } 701 702 /* Allocate DMA'able memory for RX pages */ 703 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 704 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 705 1, &nsegs, BUS_DMA_WAITOK); 706 if (error) { 707 printf("%s: could not allocate DMA'able memory for " 708 "Rx ring.\n", device_xname(sc->sc_dev)); 709 return error; 710 } 711 error = bus_dmamem_map(sc->sc_dmat, 712 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 713 sc->ale_pagesize, 714 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 715 BUS_DMA_NOWAIT); 716 if (error) 717 return ENOBUFS; 718 719 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 720 sc->ale_pagesize); 721 722 /* Load the DMA map for Rx pages. */ 723 error = bus_dmamap_load(sc->sc_dmat, 724 sc->ale_cdata.ale_rx_page[i].page_map, 725 sc->ale_cdata.ale_rx_page[i].page_addr, 726 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 727 if (error) { 728 printf("%s: could not load DMA'able memory for " 729 "Rx pages.\n", device_xname(sc->sc_dev)); 730 bus_dmamem_free(sc->sc_dmat, 731 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 732 return error; 733 } 734 sc->ale_cdata.ale_rx_page[i].page_paddr = 735 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 736 } 737 738 /* 739 * Create DMA stuffs for Tx CMB. 740 */ 741 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 742 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 743 if (error) { 744 sc->ale_cdata.ale_tx_cmb_map = NULL; 745 return ENOBUFS; 746 } 747 748 /* Allocate DMA'able memory for Tx CMB. */ 749 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 750 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 751 752 if (error) { 753 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 754 device_xname(sc->sc_dev)); 755 return error; 756 } 757 758 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 759 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 760 BUS_DMA_NOWAIT); 761 if (error) 762 return ENOBUFS; 763 764 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 765 766 /* Load the DMA map for Tx CMB. */ 767 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 768 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 769 if (error) { 770 printf("%s: could not load DMA'able memory for Tx CMB.\n", 771 device_xname(sc->sc_dev)); 772 bus_dmamem_free(sc->sc_dmat, 773 &sc->ale_cdata.ale_tx_cmb_seg, 1); 774 return error; 775 } 776 777 sc->ale_cdata.ale_tx_cmb_paddr = 778 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 779 780 for (i = 0; i < ALE_RX_PAGES; i++) { 781 /* 782 * Create DMA stuffs for Rx CMB. 783 */ 784 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 785 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 786 &sc->ale_cdata.ale_rx_page[i].cmb_map); 787 if (error) { 788 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 789 return ENOBUFS; 790 } 791 792 /* Allocate DMA'able memory for Rx CMB */ 793 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 794 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 795 &nsegs, BUS_DMA_WAITOK); 796 if (error) { 797 printf("%s: could not allocate DMA'able memory for " 798 "Rx CMB\n", device_xname(sc->sc_dev)); 799 return error; 800 } 801 error = bus_dmamem_map(sc->sc_dmat, 802 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 803 ALE_RX_CMB_SZ, 804 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 805 BUS_DMA_NOWAIT); 806 if (error) 807 return ENOBUFS; 808 809 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 810 811 /* Load the DMA map for Rx CMB */ 812 error = bus_dmamap_load(sc->sc_dmat, 813 sc->ale_cdata.ale_rx_page[i].cmb_map, 814 sc->ale_cdata.ale_rx_page[i].cmb_addr, 815 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 816 if (error) { 817 printf("%s: could not load DMA'able memory for Rx CMB" 818 "\n", device_xname(sc->sc_dev)); 819 bus_dmamem_free(sc->sc_dmat, 820 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 821 return error; 822 } 823 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 824 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 825 } 826 827 828 /* Create DMA maps for Tx buffers. */ 829 for (i = 0; i < ALE_TX_RING_CNT; i++) { 830 txd = &sc->ale_cdata.ale_txdesc[i]; 831 txd->tx_m = NULL; 832 txd->tx_dmamap = NULL; 833 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 834 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 835 &txd->tx_dmamap); 836 if (error) { 837 txd->tx_dmamap = NULL; 838 printf("%s: could not create Tx dmamap.\n", 839 device_xname(sc->sc_dev)); 840 return error; 841 } 842 } 843 844 return 0; 845 } 846 847 static void 848 ale_dma_free(struct ale_softc *sc) 849 { 850 struct ale_txdesc *txd; 851 int i; 852 853 /* Tx buffers. */ 854 for (i = 0; i < ALE_TX_RING_CNT; i++) { 855 txd = &sc->ale_cdata.ale_txdesc[i]; 856 if (txd->tx_dmamap != NULL) { 857 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 858 txd->tx_dmamap = NULL; 859 } 860 } 861 862 /* Tx descriptor ring. */ 863 if (sc->ale_cdata.ale_tx_ring_map != NULL) 864 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 865 if (sc->ale_cdata.ale_tx_ring_map != NULL && 866 sc->ale_cdata.ale_tx_ring != NULL) 867 bus_dmamem_free(sc->sc_dmat, 868 &sc->ale_cdata.ale_tx_ring_seg, 1); 869 sc->ale_cdata.ale_tx_ring = NULL; 870 sc->ale_cdata.ale_tx_ring_map = NULL; 871 872 /* Rx page block. */ 873 for (i = 0; i < ALE_RX_PAGES; i++) { 874 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 875 bus_dmamap_unload(sc->sc_dmat, 876 sc->ale_cdata.ale_rx_page[i].page_map); 877 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 878 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 879 bus_dmamem_free(sc->sc_dmat, 880 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 881 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 882 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 883 } 884 885 /* Rx CMB. */ 886 for (i = 0; i < ALE_RX_PAGES; i++) { 887 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 888 bus_dmamap_unload(sc->sc_dmat, 889 sc->ale_cdata.ale_rx_page[i].cmb_map); 890 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 891 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 892 bus_dmamem_free(sc->sc_dmat, 893 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 894 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 895 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 896 } 897 898 /* Tx CMB. */ 899 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 900 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 901 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 902 sc->ale_cdata.ale_tx_cmb != NULL) 903 bus_dmamem_free(sc->sc_dmat, 904 &sc->ale_cdata.ale_tx_cmb_seg, 1); 905 sc->ale_cdata.ale_tx_cmb = NULL; 906 sc->ale_cdata.ale_tx_cmb_map = NULL; 907 908 } 909 910 static int 911 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 912 { 913 struct ale_txdesc *txd, *txd_last; 914 struct tx_desc *desc; 915 struct mbuf *m; 916 bus_dmamap_t map; 917 uint32_t cflags, poff, vtag; 918 int error, i, nsegs, prod; 919 #if NVLAN > 0 920 struct m_tag *mtag; 921 #endif 922 923 m = *m_head; 924 cflags = vtag = 0; 925 poff = 0; 926 927 prod = sc->ale_cdata.ale_tx_prod; 928 txd = &sc->ale_cdata.ale_txdesc[prod]; 929 txd_last = txd; 930 map = txd->tx_dmamap; 931 932 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 933 if (error == EFBIG) { 934 error = 0; 935 936 *m_head = m_pullup(*m_head, MHLEN); 937 if (*m_head == NULL) { 938 printf("%s: can't defrag TX mbuf\n", 939 device_xname(sc->sc_dev)); 940 return ENOBUFS; 941 } 942 943 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 944 BUS_DMA_NOWAIT); 945 946 if (error != 0) { 947 printf("%s: could not load defragged TX mbuf\n", 948 device_xname(sc->sc_dev)); 949 m_freem(*m_head); 950 *m_head = NULL; 951 return error; 952 } 953 } else if (error) { 954 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 955 return error; 956 } 957 958 nsegs = map->dm_nsegs; 959 960 if (nsegs == 0) { 961 m_freem(*m_head); 962 *m_head = NULL; 963 return EIO; 964 } 965 966 /* Check descriptor overrun. */ 967 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 968 bus_dmamap_unload(sc->sc_dmat, map); 969 return ENOBUFS; 970 } 971 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 972 BUS_DMASYNC_PREWRITE); 973 974 m = *m_head; 975 /* Configure Tx checksum offload. */ 976 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 977 /* 978 * AR81xx supports Tx custom checksum offload feature 979 * that offloads single 16bit checksum computation. 980 * So you can choose one among IP, TCP and UDP. 981 * Normally driver sets checksum start/insertion 982 * position from the information of TCP/UDP frame as 983 * TCP/UDP checksum takes more time than that of IP. 984 * However it seems that custom checksum offload 985 * requires 4 bytes aligned Tx buffers due to hardware 986 * bug. 987 * AR81xx also supports explicit Tx checksum computation 988 * if it is told that the size of IP header and TCP 989 * header(for UDP, the header size does not matter 990 * because it's fixed length). However with this scheme 991 * TSO does not work so you have to choose one either 992 * TSO or explicit Tx checksum offload. I chosen TSO 993 * plus custom checksum offload with work-around which 994 * will cover most common usage for this consumer 995 * ethernet controller. The work-around takes a lot of 996 * CPU cycles if Tx buffer is not aligned on 4 bytes 997 * boundary, though. 998 */ 999 cflags |= ALE_TD_CXSUM; 1000 /* Set checksum start offset. */ 1001 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1002 } 1003 1004 #if NVLAN > 0 1005 /* Configure VLAN hardware tag insertion. */ 1006 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1007 vtag = ALE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1008 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1009 cflags |= ALE_TD_INSERT_VLAN_TAG; 1010 } 1011 #endif 1012 1013 desc = NULL; 1014 for (i = 0; i < nsegs; i++) { 1015 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1016 desc->addr = htole64(map->dm_segs[i].ds_addr); 1017 desc->len = 1018 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1019 desc->flags = htole32(cflags); 1020 sc->ale_cdata.ale_tx_cnt++; 1021 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1022 } 1023 /* Update producer index. */ 1024 sc->ale_cdata.ale_tx_prod = prod; 1025 1026 /* Finally set EOP on the last descriptor. */ 1027 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1028 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1029 desc->flags |= htole32(ALE_TD_EOP); 1030 1031 /* Swap dmamap of the first and the last. */ 1032 txd = &sc->ale_cdata.ale_txdesc[prod]; 1033 map = txd_last->tx_dmamap; 1034 txd_last->tx_dmamap = txd->tx_dmamap; 1035 txd->tx_dmamap = map; 1036 txd->tx_m = m; 1037 1038 /* Sync descriptors. */ 1039 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1040 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1041 1042 return 0; 1043 } 1044 1045 static void 1046 ale_start(struct ifnet *ifp) 1047 { 1048 struct ale_softc *sc = ifp->if_softc; 1049 struct mbuf *m_head; 1050 int enq; 1051 1052 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1053 return; 1054 1055 /* Reclaim transmitted frames. */ 1056 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1057 ale_txeof(sc); 1058 1059 enq = 0; 1060 for (;;) { 1061 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1062 if (m_head == NULL) 1063 break; 1064 1065 /* 1066 * Pack the data into the transmit ring. If we 1067 * don't have room, set the OACTIVE flag and wait 1068 * for the NIC to drain the ring. 1069 */ 1070 if (ale_encap(sc, &m_head)) { 1071 if (m_head == NULL) 1072 break; 1073 IF_PREPEND(&ifp->if_snd, m_head); 1074 ifp->if_flags |= IFF_OACTIVE; 1075 break; 1076 } 1077 enq = 1; 1078 1079 #if NBPFILTER > 0 1080 /* 1081 * If there's a BPF listener, bounce a copy of this frame 1082 * to him. 1083 */ 1084 if (ifp->if_bpf != NULL) 1085 bpf_mtap(ifp->if_bpf, m_head); 1086 #endif 1087 } 1088 1089 if (enq) { 1090 /* Kick. */ 1091 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1092 sc->ale_cdata.ale_tx_prod); 1093 1094 /* Set a timeout in case the chip goes out to lunch. */ 1095 ifp->if_timer = ALE_TX_TIMEOUT; 1096 } 1097 } 1098 1099 static void 1100 ale_watchdog(struct ifnet *ifp) 1101 { 1102 struct ale_softc *sc = ifp->if_softc; 1103 1104 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1105 printf("%s: watchdog timeout (missed link)\n", 1106 device_xname(sc->sc_dev)); 1107 ifp->if_oerrors++; 1108 ale_init(ifp); 1109 return; 1110 } 1111 1112 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1113 ifp->if_oerrors++; 1114 ale_init(ifp); 1115 1116 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1117 ale_start(ifp); 1118 } 1119 1120 static int 1121 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1122 { 1123 struct ale_softc *sc = ifp->if_softc; 1124 int s, error; 1125 1126 s = splnet(); 1127 1128 error = ether_ioctl(ifp, cmd, data); 1129 if (error == ENETRESET) { 1130 if (ifp->if_flags & IFF_RUNNING) 1131 ale_rxfilter(sc); 1132 error = 0; 1133 } 1134 1135 splx(s); 1136 return error; 1137 } 1138 1139 static void 1140 ale_mac_config(struct ale_softc *sc) 1141 { 1142 struct mii_data *mii; 1143 uint32_t reg; 1144 1145 mii = &sc->sc_miibus; 1146 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1147 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1148 MAC_CFG_SPEED_MASK); 1149 1150 /* Reprogram MAC with resolved speed/duplex. */ 1151 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1152 case IFM_10_T: 1153 case IFM_100_TX: 1154 reg |= MAC_CFG_SPEED_10_100; 1155 break; 1156 case IFM_1000_T: 1157 reg |= MAC_CFG_SPEED_1000; 1158 break; 1159 } 1160 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1161 reg |= MAC_CFG_FULL_DUPLEX; 1162 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1163 reg |= MAC_CFG_TX_FC; 1164 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1165 reg |= MAC_CFG_RX_FC; 1166 } 1167 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1168 } 1169 1170 static void 1171 ale_stats_clear(struct ale_softc *sc) 1172 { 1173 struct smb sb; 1174 uint32_t *reg; 1175 int i; 1176 1177 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1178 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1179 i += sizeof(uint32_t); 1180 } 1181 /* Read Tx statistics. */ 1182 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1183 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1184 i += sizeof(uint32_t); 1185 } 1186 } 1187 1188 static void 1189 ale_stats_update(struct ale_softc *sc) 1190 { 1191 struct ifnet *ifp = &sc->sc_ec.ec_if; 1192 struct ale_hw_stats *stat; 1193 struct smb sb, *smb; 1194 uint32_t *reg; 1195 int i; 1196 1197 stat = &sc->ale_stats; 1198 smb = &sb; 1199 1200 /* Read Rx statistics. */ 1201 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1202 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1203 i += sizeof(uint32_t); 1204 } 1205 /* Read Tx statistics. */ 1206 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1207 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1208 i += sizeof(uint32_t); 1209 } 1210 1211 /* Rx stats. */ 1212 stat->rx_frames += smb->rx_frames; 1213 stat->rx_bcast_frames += smb->rx_bcast_frames; 1214 stat->rx_mcast_frames += smb->rx_mcast_frames; 1215 stat->rx_pause_frames += smb->rx_pause_frames; 1216 stat->rx_control_frames += smb->rx_control_frames; 1217 stat->rx_crcerrs += smb->rx_crcerrs; 1218 stat->rx_lenerrs += smb->rx_lenerrs; 1219 stat->rx_bytes += smb->rx_bytes; 1220 stat->rx_runts += smb->rx_runts; 1221 stat->rx_fragments += smb->rx_fragments; 1222 stat->rx_pkts_64 += smb->rx_pkts_64; 1223 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1224 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1225 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1226 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1227 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1228 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1229 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1230 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1231 stat->rx_rrs_errs += smb->rx_rrs_errs; 1232 stat->rx_alignerrs += smb->rx_alignerrs; 1233 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1234 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1235 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1236 1237 /* Tx stats. */ 1238 stat->tx_frames += smb->tx_frames; 1239 stat->tx_bcast_frames += smb->tx_bcast_frames; 1240 stat->tx_mcast_frames += smb->tx_mcast_frames; 1241 stat->tx_pause_frames += smb->tx_pause_frames; 1242 stat->tx_excess_defer += smb->tx_excess_defer; 1243 stat->tx_control_frames += smb->tx_control_frames; 1244 stat->tx_deferred += smb->tx_deferred; 1245 stat->tx_bytes += smb->tx_bytes; 1246 stat->tx_pkts_64 += smb->tx_pkts_64; 1247 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1248 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1249 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1250 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1251 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1252 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1253 stat->tx_single_colls += smb->tx_single_colls; 1254 stat->tx_multi_colls += smb->tx_multi_colls; 1255 stat->tx_late_colls += smb->tx_late_colls; 1256 stat->tx_excess_colls += smb->tx_excess_colls; 1257 stat->tx_abort += smb->tx_abort; 1258 stat->tx_underrun += smb->tx_underrun; 1259 stat->tx_desc_underrun += smb->tx_desc_underrun; 1260 stat->tx_lenerrs += smb->tx_lenerrs; 1261 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1262 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1263 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1264 1265 /* Update counters in ifnet. */ 1266 ifp->if_opackets += smb->tx_frames; 1267 1268 ifp->if_collisions += smb->tx_single_colls + 1269 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1270 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1271 1272 /* 1273 * XXX 1274 * tx_pkts_truncated counter looks suspicious. It constantly 1275 * increments with no sign of Tx errors. This may indicate 1276 * the counter name is not correct one so I've removed the 1277 * counter in output errors. 1278 */ 1279 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1280 smb->tx_underrun; 1281 1282 ifp->if_ipackets += smb->rx_frames; 1283 1284 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1285 smb->rx_runts + smb->rx_pkts_truncated + 1286 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1287 smb->rx_alignerrs; 1288 } 1289 1290 static int 1291 ale_intr(void *xsc) 1292 { 1293 struct ale_softc *sc = xsc; 1294 struct ifnet *ifp = &sc->sc_ec.ec_if; 1295 uint32_t status; 1296 1297 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1298 if ((status & ALE_INTRS) == 0) 1299 return 0; 1300 1301 /* Acknowledge and disable interrupts. */ 1302 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1303 1304 if (ifp->if_flags & IFF_RUNNING) { 1305 int error; 1306 1307 error = ale_rxeof(sc); 1308 if (error) { 1309 sc->ale_stats.reset_brk_seq++; 1310 ale_init(ifp); 1311 return 0; 1312 } 1313 1314 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1315 if (status & INTR_DMA_RD_TO_RST) 1316 printf("%s: DMA read error! -- resetting\n", 1317 device_xname(sc->sc_dev)); 1318 if (status & INTR_DMA_WR_TO_RST) 1319 printf("%s: DMA write error! -- resetting\n", 1320 device_xname(sc->sc_dev)); 1321 ale_init(ifp); 1322 return 0; 1323 } 1324 1325 ale_txeof(sc); 1326 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1327 ale_start(ifp); 1328 } 1329 1330 /* Re-enable interrupts. */ 1331 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1332 return 1; 1333 } 1334 1335 static void 1336 ale_txeof(struct ale_softc *sc) 1337 { 1338 struct ifnet *ifp = &sc->sc_ec.ec_if; 1339 struct ale_txdesc *txd; 1340 uint32_t cons, prod; 1341 int prog; 1342 1343 if (sc->ale_cdata.ale_tx_cnt == 0) 1344 return; 1345 1346 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1347 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1348 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1349 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1350 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1351 BUS_DMASYNC_POSTREAD); 1352 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1353 } else 1354 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1355 cons = sc->ale_cdata.ale_tx_cons; 1356 /* 1357 * Go through our Tx list and free mbufs for those 1358 * frames which have been transmitted. 1359 */ 1360 for (prog = 0; cons != prod; prog++, 1361 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1362 if (sc->ale_cdata.ale_tx_cnt <= 0) 1363 break; 1364 prog++; 1365 ifp->if_flags &= ~IFF_OACTIVE; 1366 sc->ale_cdata.ale_tx_cnt--; 1367 txd = &sc->ale_cdata.ale_txdesc[cons]; 1368 if (txd->tx_m != NULL) { 1369 /* Reclaim transmitted mbufs. */ 1370 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1371 m_freem(txd->tx_m); 1372 txd->tx_m = NULL; 1373 } 1374 } 1375 1376 if (prog > 0) { 1377 sc->ale_cdata.ale_tx_cons = cons; 1378 /* 1379 * Unarm watchdog timer only when there is no pending 1380 * Tx descriptors in queue. 1381 */ 1382 if (sc->ale_cdata.ale_tx_cnt == 0) 1383 ifp->if_timer = 0; 1384 } 1385 } 1386 1387 static void 1388 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1389 uint32_t length, uint32_t *prod) 1390 { 1391 struct ale_rx_page *rx_page; 1392 1393 rx_page = *page; 1394 /* Update consumer position. */ 1395 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1396 ALE_RX_PAGE_ALIGN); 1397 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1398 /* 1399 * End of Rx page reached, let hardware reuse 1400 * this page. 1401 */ 1402 rx_page->cons = 0; 1403 *rx_page->cmb_addr = 0; 1404 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1405 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1406 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1407 RXF_VALID); 1408 /* Switch to alternate Rx page. */ 1409 sc->ale_cdata.ale_rx_curp ^= 1; 1410 rx_page = *page = 1411 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1412 /* Page flipped, sync CMB and Rx page. */ 1413 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1414 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1415 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1416 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1417 /* Sync completed, cache updated producer index. */ 1418 *prod = *rx_page->cmb_addr; 1419 } 1420 } 1421 1422 1423 /* 1424 * It seems that AR81xx controller can compute partial checksum. 1425 * The partial checksum value can be used to accelerate checksum 1426 * computation for fragmented TCP/UDP packets. Upper network stack 1427 * already takes advantage of the partial checksum value in IP 1428 * reassembly stage. But I'm not sure the correctness of the 1429 * partial hardware checksum assistance due to lack of data sheet. 1430 * In addition, the Rx feature of controller that requires copying 1431 * for every frames effectively nullifies one of most nice offload 1432 * capability of controller. 1433 */ 1434 static void 1435 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1436 { 1437 if (status & ALE_RD_IPCSUM_NOK) 1438 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1439 1440 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1441 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1442 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1443 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1444 { 1445 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1446 } 1447 } else { 1448 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1449 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1450 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1451 } 1452 } 1453 } 1454 /* 1455 * Don't mark bad checksum for TCP/UDP frames 1456 * as fragmented frames may always have set 1457 * bad checksummed bit of frame status. 1458 */ 1459 } 1460 1461 /* Process received frames. */ 1462 static int 1463 ale_rxeof(struct ale_softc *sc) 1464 { 1465 struct ifnet *ifp = &sc->sc_ec.ec_if; 1466 struct ale_rx_page *rx_page; 1467 struct rx_rs *rs; 1468 struct mbuf *m; 1469 uint32_t length, prod, seqno, status; 1470 int prog; 1471 1472 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1473 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1474 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1475 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1476 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1477 /* 1478 * Don't directly access producer index as hardware may 1479 * update it while Rx handler is in progress. It would 1480 * be even better if there is a way to let hardware 1481 * know how far driver processed its received frames. 1482 * Alternatively, hardware could provide a way to disable 1483 * CMB updates until driver acknowledges the end of CMB 1484 * access. 1485 */ 1486 prod = *rx_page->cmb_addr; 1487 for (prog = 0; ; prog++) { 1488 if (rx_page->cons >= prod) 1489 break; 1490 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1491 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1492 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1493 /* 1494 * Normally I believe this should not happen unless 1495 * severe driver bug or corrupted memory. However 1496 * it seems to happen under certain conditions which 1497 * is triggered by abrupt Rx events such as initiation 1498 * of bulk transfer of remote host. It's not easy to 1499 * reproduce this and I doubt it could be related 1500 * with FIFO overflow of hardware or activity of Tx 1501 * CMB updates. I also remember similar behaviour 1502 * seen on RealTek 8139 which uses resembling Rx 1503 * scheme. 1504 */ 1505 if (aledebug) 1506 printf("%s: garbled seq: %u, expected: %u -- " 1507 "resetting!\n", device_xname(sc->sc_dev), 1508 seqno, sc->ale_cdata.ale_rx_seqno); 1509 return EIO; 1510 } 1511 /* Frame received. */ 1512 sc->ale_cdata.ale_rx_seqno++; 1513 length = ALE_RX_BYTES(le32toh(rs->length)); 1514 status = le32toh(rs->flags); 1515 if (status & ALE_RD_ERROR) { 1516 /* 1517 * We want to pass the following frames to upper 1518 * layer regardless of error status of Rx return 1519 * status. 1520 * 1521 * o IP/TCP/UDP checksum is bad. 1522 * o frame length and protocol specific length 1523 * does not match. 1524 */ 1525 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1526 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1527 ALE_RD_TRUNC)) { 1528 ale_rx_update_page(sc, &rx_page, length, &prod); 1529 continue; 1530 } 1531 } 1532 /* 1533 * m_devget(9) is major bottle-neck of ale(4)(It comes 1534 * from hardware limitation). For jumbo frames we could 1535 * get a slightly better performance if driver use 1536 * m_getjcl(9) with proper buffer size argument. However 1537 * that would make code more complicated and I don't 1538 * think users would expect good Rx performance numbers 1539 * on these low-end consumer ethernet controller. 1540 */ 1541 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1542 0, ifp, NULL); 1543 if (m == NULL) { 1544 ifp->if_iqdrops++; 1545 ale_rx_update_page(sc, &rx_page, length, &prod); 1546 continue; 1547 } 1548 if (status & ALE_RD_IPV4) 1549 ale_rxcsum(sc, m, status); 1550 #if NVLAN > 0 1551 if (status & ALE_RD_VLAN) { 1552 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1553 VLAN_INPUT_TAG(ifp, m, ALE_RX_VLAN_TAG(vtags), ); 1554 } 1555 #endif 1556 1557 1558 #if NBPFILTER > 0 1559 if (ifp->if_bpf) 1560 bpf_mtap(ifp->if_bpf, m); 1561 #endif 1562 1563 /* Pass it to upper layer. */ 1564 ether_input(ifp, m); 1565 1566 ale_rx_update_page(sc, &rx_page, length, &prod); 1567 } 1568 1569 return 0; 1570 } 1571 1572 static void 1573 ale_tick(void *xsc) 1574 { 1575 struct ale_softc *sc = xsc; 1576 struct mii_data *mii = &sc->sc_miibus; 1577 int s; 1578 1579 s = splnet(); 1580 mii_tick(mii); 1581 ale_stats_update(sc); 1582 splx(s); 1583 1584 callout_schedule(&sc->sc_tick_ch, hz); 1585 } 1586 1587 static void 1588 ale_reset(struct ale_softc *sc) 1589 { 1590 uint32_t reg; 1591 int i; 1592 1593 /* Initialize PCIe module. From Linux. */ 1594 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1595 1596 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1597 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1598 DELAY(10); 1599 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1600 break; 1601 } 1602 if (i == 0) 1603 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1604 1605 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1606 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1607 break; 1608 DELAY(10); 1609 } 1610 1611 if (i == 0) 1612 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1613 reg); 1614 } 1615 1616 static int 1617 ale_init(struct ifnet *ifp) 1618 { 1619 struct ale_softc *sc = ifp->if_softc; 1620 struct mii_data *mii; 1621 uint8_t eaddr[ETHER_ADDR_LEN]; 1622 bus_addr_t paddr; 1623 uint32_t reg, rxf_hi, rxf_lo; 1624 1625 /* 1626 * Cancel any pending I/O. 1627 */ 1628 ale_stop(ifp, 0); 1629 1630 /* 1631 * Reset the chip to a known state. 1632 */ 1633 ale_reset(sc); 1634 1635 /* Initialize Tx descriptors, DMA memory blocks. */ 1636 ale_init_rx_pages(sc); 1637 ale_init_tx_ring(sc); 1638 1639 /* Reprogram the station address. */ 1640 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1641 CSR_WRITE_4(sc, ALE_PAR0, 1642 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1643 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1644 1645 /* 1646 * Clear WOL status and disable all WOL feature as WOL 1647 * would interfere Rx operation under normal environments. 1648 */ 1649 CSR_READ_4(sc, ALE_WOL_CFG); 1650 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1651 1652 /* 1653 * Set Tx descriptor/RXF0/CMB base addresses. They share 1654 * the same high address part of DMAable region. 1655 */ 1656 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1657 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1658 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1659 CSR_WRITE_4(sc, ALE_TPD_CNT, 1660 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1661 1662 /* Set Rx page base address, note we use single queue. */ 1663 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1664 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1665 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1666 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1667 1668 /* Set Tx/Rx CMB addresses. */ 1669 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1670 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1671 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1672 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1673 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1674 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1675 1676 /* Mark RXF0 is valid. */ 1677 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1678 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1679 /* 1680 * No need to initialize RFX1/RXF2/RXF3. We don't use 1681 * multi-queue yet. 1682 */ 1683 1684 /* Set Rx page size, excluding guard frame size. */ 1685 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1686 1687 /* Tell hardware that we're ready to load DMA blocks. */ 1688 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1689 1690 /* Set Rx/Tx interrupt trigger threshold. */ 1691 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1692 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1693 /* 1694 * XXX 1695 * Set interrupt trigger timer, its purpose and relation 1696 * with interrupt moderation mechanism is not clear yet. 1697 */ 1698 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1699 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1700 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1701 1702 /* Configure interrupt moderation timer. */ 1703 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1704 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1705 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1706 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1707 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1708 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1709 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1710 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1711 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1712 reg |= MASTER_IM_RX_TIMER_ENB; 1713 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1714 reg |= MASTER_IM_TX_TIMER_ENB; 1715 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1716 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1717 1718 /* Set Maximum frame size of controller. */ 1719 if (ifp->if_mtu < ETHERMTU) 1720 sc->ale_max_frame_size = ETHERMTU; 1721 else 1722 sc->ale_max_frame_size = ifp->if_mtu; 1723 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1724 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1725 1726 /* Configure IPG/IFG parameters. */ 1727 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1728 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1729 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1730 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1731 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1732 1733 /* Set parameters for half-duplex media. */ 1734 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1735 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1736 HDPX_CFG_LCOL_MASK) | 1737 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1738 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1739 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1740 HDPX_CFG_ABEBT_MASK) | 1741 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1742 HDPX_CFG_JAMIPG_MASK)); 1743 1744 /* Configure Tx jumbo frame parameters. */ 1745 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1746 if (ifp->if_mtu < ETHERMTU) 1747 reg = sc->ale_max_frame_size; 1748 else if (ifp->if_mtu < 6 * 1024) 1749 reg = (sc->ale_max_frame_size * 2) / 3; 1750 else 1751 reg = sc->ale_max_frame_size / 2; 1752 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1753 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1754 TX_JUMBO_THRESH_UNIT_SHIFT); 1755 } 1756 1757 /* Configure TxQ. */ 1758 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1759 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1760 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1761 TXQ_CFG_TPD_BURST_MASK; 1762 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1763 1764 /* Configure Rx jumbo frame & flow control parameters. */ 1765 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1766 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1767 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1768 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1769 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1770 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1771 RX_JUMBO_LKAH_MASK)); 1772 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1773 rxf_hi = (reg * 7) / 10; 1774 rxf_lo = (reg * 3)/ 10; 1775 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1776 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1777 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1778 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1779 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1780 } 1781 1782 /* Disable RSS. */ 1783 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1784 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1785 1786 /* Configure RxQ. */ 1787 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1788 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1789 1790 /* Configure DMA parameters. */ 1791 reg = 0; 1792 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1793 reg |= DMA_CFG_TXCMB_ENB; 1794 CSR_WRITE_4(sc, ALE_DMA_CFG, 1795 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1796 sc->ale_dma_rd_burst | reg | 1797 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1798 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1799 DMA_CFG_RD_DELAY_CNT_MASK) | 1800 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1801 DMA_CFG_WR_DELAY_CNT_MASK)); 1802 1803 /* 1804 * Hardware can be configured to issue SMB interrupt based 1805 * on programmed interval. Since there is a callout that is 1806 * invoked for every hz in driver we use that instead of 1807 * relying on periodic SMB interrupt. 1808 */ 1809 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1810 1811 /* Clear MAC statistics. */ 1812 ale_stats_clear(sc); 1813 1814 /* 1815 * Configure Tx/Rx MACs. 1816 * - Auto-padding for short frames. 1817 * - Enable CRC generation. 1818 * Actual reconfiguration of MAC for resolved speed/duplex 1819 * is followed after detection of link establishment. 1820 * AR81xx always does checksum computation regardless of 1821 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1822 * cause Rx handling issue for fragmented IP datagrams due 1823 * to silicon bug. 1824 */ 1825 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1826 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1827 MAC_CFG_PREAMBLE_MASK); 1828 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1829 reg |= MAC_CFG_SPEED_10_100; 1830 else 1831 reg |= MAC_CFG_SPEED_1000; 1832 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1833 1834 /* Set up the receive filter. */ 1835 ale_rxfilter(sc); 1836 ale_rxvlan(sc); 1837 1838 /* Acknowledge all pending interrupts and clear it. */ 1839 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1840 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1841 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1842 1843 sc->ale_flags &= ~ALE_FLAG_LINK; 1844 1845 /* Switch to the current media. */ 1846 mii = &sc->sc_miibus; 1847 mii_mediachg(mii); 1848 1849 callout_schedule(&sc->sc_tick_ch, hz); 1850 1851 ifp->if_flags |= IFF_RUNNING; 1852 ifp->if_flags &= ~IFF_OACTIVE; 1853 1854 return 0; 1855 } 1856 1857 static void 1858 ale_stop(struct ifnet *ifp, int disable) 1859 { 1860 struct ale_softc *sc = ifp->if_softc; 1861 struct ale_txdesc *txd; 1862 uint32_t reg; 1863 int i; 1864 1865 callout_stop(&sc->sc_tick_ch); 1866 1867 /* 1868 * Mark the interface down and cancel the watchdog timer. 1869 */ 1870 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1871 ifp->if_timer = 0; 1872 1873 sc->ale_flags &= ~ALE_FLAG_LINK; 1874 1875 ale_stats_update(sc); 1876 1877 mii_down(&sc->sc_miibus); 1878 1879 /* Disable interrupts. */ 1880 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1881 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1882 1883 /* Disable queue processing and DMA. */ 1884 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1885 reg &= ~TXQ_CFG_ENB; 1886 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1887 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1888 reg &= ~RXQ_CFG_ENB; 1889 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1890 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1891 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1892 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1893 DELAY(1000); 1894 1895 /* Stop Rx/Tx MACs. */ 1896 ale_stop_mac(sc); 1897 1898 /* Disable interrupts again? XXX */ 1899 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1900 1901 /* 1902 * Free TX mbufs still in the queues. 1903 */ 1904 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1905 txd = &sc->ale_cdata.ale_txdesc[i]; 1906 if (txd->tx_m != NULL) { 1907 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1908 m_freem(txd->tx_m); 1909 txd->tx_m = NULL; 1910 } 1911 } 1912 } 1913 1914 static void 1915 ale_stop_mac(struct ale_softc *sc) 1916 { 1917 uint32_t reg; 1918 int i; 1919 1920 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1921 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1922 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1923 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1924 } 1925 1926 for (i = ALE_TIMEOUT; i > 0; i--) { 1927 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1928 if (reg == 0) 1929 break; 1930 DELAY(10); 1931 } 1932 if (i == 0) 1933 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1934 device_xname(sc->sc_dev), reg); 1935 } 1936 1937 static void 1938 ale_init_tx_ring(struct ale_softc *sc) 1939 { 1940 struct ale_txdesc *txd; 1941 int i; 1942 1943 sc->ale_cdata.ale_tx_prod = 0; 1944 sc->ale_cdata.ale_tx_cons = 0; 1945 sc->ale_cdata.ale_tx_cnt = 0; 1946 1947 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1948 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1949 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1950 txd = &sc->ale_cdata.ale_txdesc[i]; 1951 txd->tx_m = NULL; 1952 } 1953 *sc->ale_cdata.ale_tx_cmb = 0; 1954 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1955 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1956 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1957 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1958 } 1959 1960 static void 1961 ale_init_rx_pages(struct ale_softc *sc) 1962 { 1963 struct ale_rx_page *rx_page; 1964 int i; 1965 1966 sc->ale_cdata.ale_rx_seqno = 0; 1967 sc->ale_cdata.ale_rx_curp = 0; 1968 1969 for (i = 0; i < ALE_RX_PAGES; i++) { 1970 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1971 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1972 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1973 rx_page->cons = 0; 1974 *rx_page->cmb_addr = 0; 1975 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1976 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1977 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1978 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1979 } 1980 } 1981 1982 static void 1983 ale_rxvlan(struct ale_softc *sc) 1984 { 1985 struct ifnet *ifp = &sc->sc_ec.ec_if; 1986 uint32_t reg; 1987 1988 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1989 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1990 if (ifp->if_capabilities & ETHERCAP_VLAN_HWTAGGING) 1991 reg |= MAC_CFG_VLAN_TAG_STRIP; 1992 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1993 } 1994 1995 static void 1996 ale_rxfilter(struct ale_softc *sc) 1997 { 1998 struct ethercom *ec = &sc->sc_ec; 1999 struct ifnet *ifp = &ec->ec_if; 2000 struct ether_multi *enm; 2001 struct ether_multistep step; 2002 uint32_t crc; 2003 uint32_t mchash[2]; 2004 uint32_t rxcfg; 2005 2006 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2007 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2008 ifp->if_flags &= ~IFF_ALLMULTI; 2009 2010 /* 2011 * Always accept broadcast frames. 2012 */ 2013 rxcfg |= MAC_CFG_BCAST; 2014 2015 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2016 ifp->if_flags |= IFF_ALLMULTI; 2017 if (ifp->if_flags & IFF_PROMISC) 2018 rxcfg |= MAC_CFG_PROMISC; 2019 else 2020 rxcfg |= MAC_CFG_ALLMULTI; 2021 mchash[0] = mchash[1] = 0xFFFFFFFF; 2022 } else { 2023 /* Program new filter. */ 2024 memset(mchash, 0, sizeof(mchash)); 2025 2026 ETHER_FIRST_MULTI(step, ec, enm); 2027 while (enm != NULL) { 2028 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2029 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2030 ETHER_NEXT_MULTI(step, enm); 2031 } 2032 } 2033 2034 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2035 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2036 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2037 } 2038