1 /* $NetBSD: if_ale.c,v 1.4 2009/07/28 06:02:34 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 30 */ 31 32 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.4 2009/07/28 06:02:34 cegger Exp $"); 36 37 #include "bpfilter.h" 38 #include "vlan.h" 39 40 #include <sys/param.h> 41 #include <sys/proc.h> 42 #include <sys/endian.h> 43 #include <sys/systm.h> 44 #include <sys/types.h> 45 #include <sys/sockio.h> 46 #include <sys/mbuf.h> 47 #include <sys/queue.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/callout.h> 51 #include <sys/socket.h> 52 53 #include <sys/bus.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_llc.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #ifdef INET 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/in_var.h> 65 #include <netinet/ip.h> 66 #endif 67 68 #include <net/if_types.h> 69 #include <net/if_vlanvar.h> 70 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #endif 74 75 #include <sys/rnd.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcidevs.h> 83 84 #include <dev/pci/if_alereg.h> 85 86 static int ale_match(device_t, cfdata_t, void *); 87 static void ale_attach(device_t, device_t, void *); 88 static int ale_detach(device_t, int); 89 90 static int ale_miibus_readreg(device_t, int, int); 91 static void ale_miibus_writereg(device_t, int, int, int); 92 static void ale_miibus_statchg(device_t); 93 94 static int ale_init(struct ifnet *); 95 static void ale_start(struct ifnet *); 96 static int ale_ioctl(struct ifnet *, u_long, void *); 97 static void ale_watchdog(struct ifnet *); 98 static int ale_mediachange(struct ifnet *); 99 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 100 101 static int ale_intr(void *); 102 static int ale_rxeof(struct ale_softc *sc); 103 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 104 uint32_t, uint32_t *); 105 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 106 static void ale_txeof(struct ale_softc *); 107 108 static int ale_dma_alloc(struct ale_softc *); 109 static void ale_dma_free(struct ale_softc *); 110 static int ale_encap(struct ale_softc *, struct mbuf **); 111 static void ale_init_rx_pages(struct ale_softc *); 112 static void ale_init_tx_ring(struct ale_softc *); 113 114 static void ale_stop(struct ifnet *, int); 115 static void ale_tick(void *); 116 static void ale_get_macaddr(struct ale_softc *); 117 static void ale_mac_config(struct ale_softc *); 118 static void ale_phy_reset(struct ale_softc *); 119 static void ale_reset(struct ale_softc *); 120 static void ale_rxfilter(struct ale_softc *); 121 static void ale_rxvlan(struct ale_softc *); 122 static void ale_stats_clear(struct ale_softc *); 123 static void ale_stats_update(struct ale_softc *); 124 static void ale_stop_mac(struct ale_softc *); 125 126 CFATTACH_DECL_NEW(ale, sizeof(struct ale_softc), 127 ale_match, ale_attach, ale_detach, NULL); 128 129 int aledebug = 0; 130 #define DPRINTF(x) do { if (aledebug) printf x; } while (0) 131 132 #define ETHER_ALIGN 2 133 #define ALE_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 134 135 static int 136 ale_miibus_readreg(device_t dev, int phy, int reg) 137 { 138 struct ale_softc *sc = device_private(dev); 139 uint32_t v; 140 int i; 141 142 if (phy != sc->ale_phyaddr) 143 return 0; 144 145 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 146 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 147 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 148 DELAY(5); 149 v = CSR_READ_4(sc, ALE_MDIO); 150 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 151 break; 152 } 153 154 if (i == 0) { 155 printf("%s: phy read timeout: phy %d, reg %d\n", 156 device_xname(sc->sc_dev), phy, reg); 157 return 0; 158 } 159 160 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 161 } 162 163 static void 164 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 165 { 166 struct ale_softc *sc = device_private(dev); 167 uint32_t v; 168 int i; 169 170 if (phy != sc->ale_phyaddr) 171 return; 172 173 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 174 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 175 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 176 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 177 DELAY(5); 178 v = CSR_READ_4(sc, ALE_MDIO); 179 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 180 break; 181 } 182 183 if (i == 0) 184 printf("%s: phy write timeout: phy %d, reg %d\n", 185 device_xname(sc->sc_dev), phy, reg); 186 } 187 188 static void 189 ale_miibus_statchg(device_t dev) 190 { 191 struct ale_softc *sc = device_private(dev); 192 struct ifnet *ifp = &sc->sc_ec.ec_if; 193 struct mii_data *mii; 194 uint32_t reg; 195 196 if ((ifp->if_flags & IFF_RUNNING) == 0) 197 return; 198 199 mii = &sc->sc_miibus; 200 201 sc->ale_flags &= ~ALE_FLAG_LINK; 202 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 203 (IFM_ACTIVE | IFM_AVALID)) { 204 switch (IFM_SUBTYPE(mii->mii_media_active)) { 205 case IFM_10_T: 206 case IFM_100_TX: 207 sc->ale_flags |= ALE_FLAG_LINK; 208 break; 209 210 case IFM_1000_T: 211 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 212 sc->ale_flags |= ALE_FLAG_LINK; 213 break; 214 215 default: 216 break; 217 } 218 } 219 220 /* Stop Rx/Tx MACs. */ 221 ale_stop_mac(sc); 222 223 /* Program MACs with resolved speed/duplex/flow-control. */ 224 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 225 ale_mac_config(sc); 226 /* Reenable Tx/Rx MACs. */ 227 reg = CSR_READ_4(sc, ALE_MAC_CFG); 228 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 229 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 230 } 231 } 232 233 void 234 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 235 { 236 struct ale_softc *sc = ifp->if_softc; 237 struct mii_data *mii = &sc->sc_miibus; 238 239 mii_pollstat(mii); 240 ifmr->ifm_status = mii->mii_media_status; 241 ifmr->ifm_active = mii->mii_media_active; 242 } 243 244 int 245 ale_mediachange(struct ifnet *ifp) 246 { 247 struct ale_softc *sc = ifp->if_softc; 248 struct mii_data *mii = &sc->sc_miibus; 249 int error; 250 251 if (mii->mii_instance != 0) { 252 struct mii_softc *miisc; 253 254 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 255 mii_phy_reset(miisc); 256 } 257 error = mii_mediachg(mii); 258 259 return error; 260 } 261 262 int 263 ale_match(device_t dev, cfdata_t match, void *aux) 264 { 265 struct pci_attach_args *pa = aux; 266 267 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC && 268 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_L1E); 269 } 270 271 void 272 ale_get_macaddr(struct ale_softc *sc) 273 { 274 uint32_t ea[2], reg; 275 int i, vpdc; 276 277 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 278 if ((reg & SPI_VPD_ENB) != 0) { 279 reg &= ~SPI_VPD_ENB; 280 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 281 } 282 283 if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, 284 &vpdc, NULL)) { 285 /* 286 * PCI VPD capability found, let TWSI reload EEPROM. 287 * This will set ethernet address of controller. 288 */ 289 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 290 TWSI_CTRL_SW_LD_START); 291 for (i = 100; i > 0; i--) { 292 DELAY(1000); 293 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 294 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 295 break; 296 } 297 if (i == 0) 298 printf("%s: reloading EEPROM timeout!\n", 299 device_xname(sc->sc_dev)); 300 } else { 301 if (aledebug) 302 printf("%s: PCI VPD capability not found!\n", 303 device_xname(sc->sc_dev)); 304 } 305 306 ea[0] = CSR_READ_4(sc, ALE_PAR0); 307 ea[1] = CSR_READ_4(sc, ALE_PAR1); 308 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 309 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 310 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 311 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 312 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 313 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 314 } 315 316 void 317 ale_phy_reset(struct ale_softc *sc) 318 { 319 /* Reset magic from Linux. */ 320 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 321 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 322 GPHY_CTRL_PHY_PLL_ON); 323 DELAY(1000); 324 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 325 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 326 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 327 DELAY(1000); 328 329 #define ATPHY_DBG_ADDR 0x1D 330 #define ATPHY_DBG_DATA 0x1E 331 332 /* Enable hibernation mode. */ 333 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 334 ATPHY_DBG_ADDR, 0x0B); 335 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 336 ATPHY_DBG_DATA, 0xBC00); 337 /* Set Class A/B for all modes. */ 338 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 339 ATPHY_DBG_ADDR, 0x00); 340 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 341 ATPHY_DBG_DATA, 0x02EF); 342 /* Enable 10BT power saving. */ 343 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 344 ATPHY_DBG_ADDR, 0x12); 345 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 346 ATPHY_DBG_DATA, 0x4C04); 347 /* Adjust 1000T power. */ 348 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 349 ATPHY_DBG_ADDR, 0x04); 350 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 351 ATPHY_DBG_ADDR, 0x8BBB); 352 /* 10BT center tap voltage. */ 353 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 354 ATPHY_DBG_ADDR, 0x05); 355 ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr, 356 ATPHY_DBG_ADDR, 0x2C46); 357 358 #undef ATPHY_DBG_ADDR 359 #undef ATPHY_DBG_DATA 360 DELAY(1000); 361 } 362 363 void 364 ale_attach(device_t parent, device_t self, void *aux) 365 { 366 struct ale_softc *sc = device_private(self); 367 struct pci_attach_args *pa = aux; 368 pci_chipset_tag_t pc = pa->pa_pc; 369 pci_intr_handle_t ih; 370 const char *intrstr; 371 struct ifnet *ifp; 372 pcireg_t memtype; 373 int error = 0; 374 uint32_t rxf_len, txf_len; 375 const char *chipname; 376 377 aprint_naive("\n"); 378 aprint_normal(": Attansic/Atheros L1E Ethernet\n"); 379 380 sc->sc_dev = self; 381 sc->sc_dmat = pa->pa_dmat; 382 sc->sc_pct = pa->pa_pc; 383 sc->sc_pcitag = pa->pa_tag; 384 385 /* 386 * Allocate IO memory 387 */ 388 memtype = pci_mapreg_type(sc->sc_pct, sc->sc_pcitag, ALE_PCIR_BAR); 389 switch (memtype) { 390 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 391 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 392 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 393 break; 394 default: 395 aprint_error_dev(self, "invalid base address register\n"); 396 break; 397 } 398 399 if (pci_mapreg_map(pa, ALE_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 400 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 401 aprint_error_dev(self, "could not map mem space\n"); 402 return; 403 } 404 405 if (pci_intr_map(pa, &ih) != 0) { 406 aprint_error_dev(self, "could not map interrupt\n"); 407 goto fail; 408 } 409 410 /* 411 * Allocate IRQ 412 */ 413 intrstr = pci_intr_string(sc->sc_pct, ih); 414 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, ale_intr, sc); 415 if (sc->sc_irq_handle == NULL) { 416 aprint_error_dev(self, "could not establish interrupt"); 417 if (intrstr != NULL) 418 aprint_error(" at %s", intrstr); 419 aprint_error("\n"); 420 goto fail; 421 } 422 423 /* Set PHY address. */ 424 sc->ale_phyaddr = ALE_PHY_ADDR; 425 426 /* Reset PHY. */ 427 ale_phy_reset(sc); 428 429 /* Reset the ethernet controller. */ 430 ale_reset(sc); 431 432 /* Get PCI and chip id/revision. */ 433 sc->ale_rev = PCI_REVISION(pa->pa_class); 434 if (sc->ale_rev >= 0xF0) { 435 /* L2E Rev. B. AR8114 */ 436 sc->ale_flags |= ALE_FLAG_FASTETHER; 437 chipname = "AR8114 (L2E RevB)"; 438 } else { 439 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 440 /* L1E AR8121 */ 441 sc->ale_flags |= ALE_FLAG_JUMBO; 442 chipname = "AR8121 (L1E)"; 443 } else { 444 /* L2E Rev. A. AR8113 */ 445 sc->ale_flags |= ALE_FLAG_FASTETHER; 446 chipname = "AR8113 (L2E RevA)"; 447 } 448 } 449 aprint_normal_dev(self, "%s, %s\n", chipname, intrstr); 450 451 /* 452 * All known controllers seems to require 4 bytes alignment 453 * of Tx buffers to make Tx checksum offload with custom 454 * checksum generation method work. 455 */ 456 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 457 458 /* 459 * All known controllers seems to have issues on Rx checksum 460 * offload for fragmented IP datagrams. 461 */ 462 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 463 464 /* 465 * Don't use Tx CMB. It is known to cause RRS update failure 466 * under certain circumstances. Typical phenomenon of the 467 * issue would be unexpected sequence number encountered in 468 * Rx handler. 469 */ 470 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 471 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 472 MASTER_CHIP_REV_SHIFT; 473 aprint_debug_dev(self, "PCI device revision : 0x%04x\n", sc->ale_rev); 474 aprint_debug_dev(self, "Chip id/revision : 0x%04x\n", sc->ale_chip_rev); 475 476 /* 477 * Uninitialized hardware returns an invalid chip id/revision 478 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 479 */ 480 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 481 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 482 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 483 rxf_len == 0xFFFFFFF) { 484 aprint_error_dev(self, "chip revision : 0x%04x, %u Tx FIFO " 485 "%u Rx FIFO -- not initialized?\n", 486 sc->ale_chip_rev, txf_len, rxf_len); 487 goto fail; 488 } 489 490 if (aledebug) { 491 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 492 txf_len, rxf_len); 493 } 494 495 /* Set max allowable DMA size. */ 496 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 497 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 498 499 callout_init(&sc->sc_tick_ch, 0); 500 callout_setfunc(&sc->sc_tick_ch, ale_tick, sc); 501 502 error = ale_dma_alloc(sc); 503 if (error) 504 goto fail; 505 506 /* Load station address. */ 507 ale_get_macaddr(sc); 508 509 aprint_normal_dev(self, "Ethernet address %s\n", 510 ether_sprintf(sc->ale_eaddr)); 511 512 ifp = &sc->sc_ec.ec_if; 513 ifp->if_softc = sc; 514 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 515 ifp->if_init = ale_init; 516 ifp->if_ioctl = ale_ioctl; 517 ifp->if_start = ale_start; 518 ifp->if_stop = ale_stop; 519 ifp->if_watchdog = ale_watchdog; 520 IFQ_SET_MAXLEN(&ifp->if_snd, ALE_TX_RING_CNT - 1); 521 IFQ_SET_READY(&ifp->if_snd); 522 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 523 524 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 525 526 #ifdef ALE_CHECKSUM 527 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 528 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 529 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 530 #endif 531 532 #if NVLAN > 0 533 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 534 #endif 535 536 /* Set up MII bus. */ 537 sc->sc_miibus.mii_ifp = ifp; 538 sc->sc_miibus.mii_readreg = ale_miibus_readreg; 539 sc->sc_miibus.mii_writereg = ale_miibus_writereg; 540 sc->sc_miibus.mii_statchg = ale_miibus_statchg; 541 542 sc->sc_ec.ec_mii = &sc->sc_miibus; 543 ifmedia_init(&sc->sc_miibus.mii_media, 0, ale_mediachange, 544 ale_mediastatus); 545 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 546 MII_OFFSET_ANY, 0); 547 548 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 549 aprint_error_dev(self, "no PHY found!\n"); 550 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 551 0, NULL); 552 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 553 } else 554 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 555 556 if_attach(ifp); 557 ether_ifattach(ifp, sc->ale_eaddr); 558 559 if (!pmf_device_register(self, NULL, NULL)) 560 aprint_error_dev(self, "couldn't establish power handler\n"); 561 else 562 pmf_class_network_register(self, ifp); 563 564 return; 565 fail: 566 ale_dma_free(sc); 567 if (sc->sc_irq_handle != NULL) { 568 pci_intr_disestablish(pc, sc->sc_irq_handle); 569 sc->sc_irq_handle = NULL; 570 } 571 if (sc->sc_mem_size) { 572 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 573 sc->sc_mem_size = 0; 574 } 575 } 576 577 static int 578 ale_detach(device_t self, int flags) 579 { 580 struct ale_softc *sc = device_private(self); 581 struct ifnet *ifp = &sc->sc_ec.ec_if; 582 int s; 583 584 pmf_device_deregister(self); 585 s = splnet(); 586 ale_stop(ifp, 0); 587 splx(s); 588 589 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 590 591 /* Delete all remaining media. */ 592 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 593 594 ether_ifdetach(ifp); 595 if_detach(ifp); 596 ale_dma_free(sc); 597 598 if (sc->sc_irq_handle != NULL) { 599 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 600 sc->sc_irq_handle = NULL; 601 } 602 if (sc->sc_mem_size) { 603 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 604 sc->sc_mem_size = 0; 605 } 606 607 return 0; 608 } 609 610 611 static int 612 ale_dma_alloc(struct ale_softc *sc) 613 { 614 struct ale_txdesc *txd; 615 int nsegs, error, guard_size, i; 616 617 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 618 guard_size = ALE_JUMBO_FRAMELEN; 619 else 620 guard_size = ALE_MAX_FRAMELEN; 621 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 622 ALE_RX_PAGE_ALIGN); 623 624 /* 625 * Create DMA stuffs for TX ring 626 */ 627 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_RING_SZ, 1, 628 ALE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_ring_map); 629 if (error) { 630 sc->ale_cdata.ale_tx_ring_map = NULL; 631 return ENOBUFS; 632 } 633 634 /* Allocate DMA'able memory for TX ring */ 635 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, 636 0, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, 637 &nsegs, BUS_DMA_WAITOK); 638 if (error) { 639 printf("%s: could not allocate DMA'able memory for Tx ring, " 640 "error = %i\n", device_xname(sc->sc_dev), error); 641 return error; 642 } 643 644 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_ring_seg, 645 nsegs, ALE_TX_RING_SZ, (void **)&sc->ale_cdata.ale_tx_ring, 646 BUS_DMA_NOWAIT); 647 if (error) 648 return ENOBUFS; 649 650 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 651 652 /* Load the DMA map for Tx ring. */ 653 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 654 sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 655 if (error) { 656 printf("%s: could not load DMA'able memory for Tx ring.\n", 657 device_xname(sc->sc_dev)); 658 bus_dmamem_free(sc->sc_dmat, 659 &sc->ale_cdata.ale_tx_ring_seg, 1); 660 return error; 661 } 662 sc->ale_cdata.ale_tx_ring_paddr = 663 sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; 664 665 for (i = 0; i < ALE_RX_PAGES; i++) { 666 /* 667 * Create DMA stuffs for RX pages 668 */ 669 error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, 670 sc->ale_pagesize, 0, BUS_DMA_NOWAIT, 671 &sc->ale_cdata.ale_rx_page[i].page_map); 672 if (error) { 673 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 674 return ENOBUFS; 675 } 676 677 /* Allocate DMA'able memory for RX pages */ 678 error = bus_dmamem_alloc(sc->sc_dmat, sc->ale_pagesize, 679 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].page_seg, 680 1, &nsegs, BUS_DMA_WAITOK); 681 if (error) { 682 printf("%s: could not allocate DMA'able memory for " 683 "Rx ring.\n", device_xname(sc->sc_dev)); 684 return error; 685 } 686 error = bus_dmamem_map(sc->sc_dmat, 687 &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, 688 sc->ale_pagesize, 689 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 690 BUS_DMA_NOWAIT); 691 if (error) 692 return ENOBUFS; 693 694 memset(sc->ale_cdata.ale_rx_page[i].page_addr, 0, 695 sc->ale_pagesize); 696 697 /* Load the DMA map for Rx pages. */ 698 error = bus_dmamap_load(sc->sc_dmat, 699 sc->ale_cdata.ale_rx_page[i].page_map, 700 sc->ale_cdata.ale_rx_page[i].page_addr, 701 sc->ale_pagesize, NULL, BUS_DMA_WAITOK); 702 if (error) { 703 printf("%s: could not load DMA'able memory for " 704 "Rx pages.\n", device_xname(sc->sc_dev)); 705 bus_dmamem_free(sc->sc_dmat, 706 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 707 return error; 708 } 709 sc->ale_cdata.ale_rx_page[i].page_paddr = 710 sc->ale_cdata.ale_rx_page[i].page_map->dm_segs[0].ds_addr; 711 } 712 713 /* 714 * Create DMA stuffs for Tx CMB. 715 */ 716 error = bus_dmamap_create(sc->sc_dmat, ALE_TX_CMB_SZ, 1, 717 ALE_TX_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_tx_cmb_map); 718 if (error) { 719 sc->ale_cdata.ale_tx_cmb_map = NULL; 720 return ENOBUFS; 721 } 722 723 /* Allocate DMA'able memory for Tx CMB. */ 724 error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_CMB_SZ, ETHER_ALIGN, 0, 725 &sc->ale_cdata.ale_tx_cmb_seg, 1, &nsegs, BUS_DMA_WAITOK); 726 727 if (error) { 728 printf("%s: could not allocate DMA'able memory for Tx CMB.\n", 729 device_xname(sc->sc_dev)); 730 return error; 731 } 732 733 error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, 734 nsegs, ALE_TX_CMB_SZ, (void **)&sc->ale_cdata.ale_tx_cmb, 735 BUS_DMA_NOWAIT); 736 if (error) 737 return ENOBUFS; 738 739 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 740 741 /* Load the DMA map for Tx CMB. */ 742 error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 743 sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); 744 if (error) { 745 printf("%s: could not load DMA'able memory for Tx CMB.\n", 746 device_xname(sc->sc_dev)); 747 bus_dmamem_free(sc->sc_dmat, 748 &sc->ale_cdata.ale_tx_cmb_seg, 1); 749 return error; 750 } 751 752 sc->ale_cdata.ale_tx_cmb_paddr = 753 sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; 754 755 for (i = 0; i < ALE_RX_PAGES; i++) { 756 /* 757 * Create DMA stuffs for Rx CMB. 758 */ 759 error = bus_dmamap_create(sc->sc_dmat, ALE_RX_CMB_SZ, 1, 760 ALE_RX_CMB_SZ, 0, BUS_DMA_NOWAIT, 761 &sc->ale_cdata.ale_rx_page[i].cmb_map); 762 if (error) { 763 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 764 return ENOBUFS; 765 } 766 767 /* Allocate DMA'able memory for Rx CMB */ 768 error = bus_dmamem_alloc(sc->sc_dmat, ALE_RX_CMB_SZ, 769 ETHER_ALIGN, 0, &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1, 770 &nsegs, BUS_DMA_WAITOK); 771 if (error) { 772 printf("%s: could not allocate DMA'able memory for " 773 "Rx CMB\n", device_xname(sc->sc_dev)); 774 return error; 775 } 776 error = bus_dmamem_map(sc->sc_dmat, 777 &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, 778 ALE_RX_CMB_SZ, 779 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 780 BUS_DMA_NOWAIT); 781 if (error) 782 return ENOBUFS; 783 784 memset(sc->ale_cdata.ale_rx_page[i].cmb_addr, 0, ALE_RX_CMB_SZ); 785 786 /* Load the DMA map for Rx CMB */ 787 error = bus_dmamap_load(sc->sc_dmat, 788 sc->ale_cdata.ale_rx_page[i].cmb_map, 789 sc->ale_cdata.ale_rx_page[i].cmb_addr, 790 ALE_RX_CMB_SZ, NULL, BUS_DMA_WAITOK); 791 if (error) { 792 printf("%s: could not load DMA'able memory for Rx CMB" 793 "\n", device_xname(sc->sc_dev)); 794 bus_dmamem_free(sc->sc_dmat, 795 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 796 return error; 797 } 798 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 799 sc->ale_cdata.ale_rx_page[i].cmb_map->dm_segs[0].ds_addr; 800 } 801 802 803 /* Create DMA maps for Tx buffers. */ 804 for (i = 0; i < ALE_TX_RING_CNT; i++) { 805 txd = &sc->ale_cdata.ale_txdesc[i]; 806 txd->tx_m = NULL; 807 txd->tx_dmamap = NULL; 808 error = bus_dmamap_create(sc->sc_dmat, ALE_TSO_MAXSIZE, 809 ALE_MAXTXSEGS, ALE_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 810 &txd->tx_dmamap); 811 if (error) { 812 txd->tx_dmamap = NULL; 813 printf("%s: could not create Tx dmamap.\n", 814 device_xname(sc->sc_dev)); 815 return error; 816 } 817 } 818 819 return 0; 820 } 821 822 static void 823 ale_dma_free(struct ale_softc *sc) 824 { 825 struct ale_txdesc *txd; 826 int i; 827 828 /* Tx buffers. */ 829 for (i = 0; i < ALE_TX_RING_CNT; i++) { 830 txd = &sc->ale_cdata.ale_txdesc[i]; 831 if (txd->tx_dmamap != NULL) { 832 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 833 txd->tx_dmamap = NULL; 834 } 835 } 836 837 /* Tx descriptor ring. */ 838 if (sc->ale_cdata.ale_tx_ring_map != NULL) 839 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map); 840 if (sc->ale_cdata.ale_tx_ring_map != NULL && 841 sc->ale_cdata.ale_tx_ring != NULL) 842 bus_dmamem_free(sc->sc_dmat, 843 &sc->ale_cdata.ale_tx_ring_seg, 1); 844 sc->ale_cdata.ale_tx_ring = NULL; 845 sc->ale_cdata.ale_tx_ring_map = NULL; 846 847 /* Rx page block. */ 848 for (i = 0; i < ALE_RX_PAGES; i++) { 849 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 850 bus_dmamap_unload(sc->sc_dmat, 851 sc->ale_cdata.ale_rx_page[i].page_map); 852 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 853 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 854 bus_dmamem_free(sc->sc_dmat, 855 &sc->ale_cdata.ale_rx_page[i].page_seg, 1); 856 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 857 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 858 } 859 860 /* Rx CMB. */ 861 for (i = 0; i < ALE_RX_PAGES; i++) { 862 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 863 bus_dmamap_unload(sc->sc_dmat, 864 sc->ale_cdata.ale_rx_page[i].cmb_map); 865 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 866 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 867 bus_dmamem_free(sc->sc_dmat, 868 &sc->ale_cdata.ale_rx_page[i].cmb_seg, 1); 869 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 870 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 871 } 872 873 /* Tx CMB. */ 874 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 875 bus_dmamap_unload(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map); 876 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 877 sc->ale_cdata.ale_tx_cmb != NULL) 878 bus_dmamem_free(sc->sc_dmat, 879 &sc->ale_cdata.ale_tx_cmb_seg, 1); 880 sc->ale_cdata.ale_tx_cmb = NULL; 881 sc->ale_cdata.ale_tx_cmb_map = NULL; 882 883 } 884 885 static int 886 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 887 { 888 struct ale_txdesc *txd, *txd_last; 889 struct tx_desc *desc; 890 struct mbuf *m; 891 bus_dmamap_t map; 892 uint32_t cflags, poff, vtag; 893 int error, i, nsegs, prod; 894 #if NVLAN > 0 895 struct m_tag *mtag; 896 #endif 897 898 m = *m_head; 899 cflags = vtag = 0; 900 poff = 0; 901 902 prod = sc->ale_cdata.ale_tx_prod; 903 txd = &sc->ale_cdata.ale_txdesc[prod]; 904 txd_last = txd; 905 map = txd->tx_dmamap; 906 907 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 908 if (error == EFBIG) { 909 error = 0; 910 911 MGETHDR(m, M_DONTWAIT, MT_DATA); 912 if (m == NULL) { 913 printf("%s: can't defrag TX mbuf\n", 914 device_xname(sc->sc_dev)); 915 m_freem(*m_head); 916 *m_head = NULL; 917 return ENOBUFS; 918 } 919 920 M_COPY_PKTHDR(m, *m_head); 921 if ((*m_head)->m_pkthdr.len > MHLEN) { 922 MCLGET(m, M_DONTWAIT); 923 if (!(m->m_flags & M_EXT)) { 924 m_freem(*m_head); 925 m_freem(m); 926 *m_head = NULL; 927 return ENOBUFS; 928 } 929 } 930 m_copydata(*m_head, 0, (*m_head)->m_pkthdr.len, 931 mtod(m, void *)); 932 m_freem(*m_head); 933 m->m_len = m->m_pkthdr.len; 934 *m_head = m; 935 936 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 937 BUS_DMA_NOWAIT); 938 939 if (error != 0) { 940 printf("%s: could not load defragged TX mbuf\n", 941 device_xname(sc->sc_dev)); 942 if (!error) { 943 bus_dmamap_unload(sc->sc_dmat, map); 944 error = EFBIG; 945 } 946 m_freem(*m_head); 947 *m_head = NULL; 948 return error; 949 } 950 } else if (error) { 951 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 952 return error; 953 } 954 955 nsegs = map->dm_nsegs; 956 957 if (nsegs == 0) { 958 m_freem(*m_head); 959 *m_head = NULL; 960 return EIO; 961 } 962 963 /* Check descriptor overrun. */ 964 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 965 bus_dmamap_unload(sc->sc_dmat, map); 966 return ENOBUFS; 967 } 968 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 969 BUS_DMASYNC_PREWRITE); 970 971 m = *m_head; 972 /* Configure Tx checksum offload. */ 973 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 974 /* 975 * AR81xx supports Tx custom checksum offload feature 976 * that offloads single 16bit checksum computation. 977 * So you can choose one among IP, TCP and UDP. 978 * Normally driver sets checksum start/insertion 979 * position from the information of TCP/UDP frame as 980 * TCP/UDP checksum takes more time than that of IP. 981 * However it seems that custom checksum offload 982 * requires 4 bytes aligned Tx buffers due to hardware 983 * bug. 984 * AR81xx also supports explicit Tx checksum computation 985 * if it is told that the size of IP header and TCP 986 * header(for UDP, the header size does not matter 987 * because it's fixed length). However with this scheme 988 * TSO does not work so you have to choose one either 989 * TSO or explicit Tx checksum offload. I chosen TSO 990 * plus custom checksum offload with work-around which 991 * will cover most common usage for this consumer 992 * ethernet controller. The work-around takes a lot of 993 * CPU cycles if Tx buffer is not aligned on 4 bytes 994 * boundary, though. 995 */ 996 cflags |= ALE_TD_CXSUM; 997 /* Set checksum start offset. */ 998 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 999 } 1000 1001 #if NVLAN > 0 1002 /* Configure VLAN hardware tag insertion. */ 1003 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1004 vtag = ALE_TX_VLAN_TAG(htons(VLAN_TAG_VALUE(mtag))); 1005 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1006 cflags |= ALE_TD_INSERT_VLAN_TAG; 1007 } 1008 #endif 1009 1010 desc = NULL; 1011 for (i = 0; i < nsegs; i++) { 1012 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1013 desc->addr = htole64(map->dm_segs[i].ds_addr); 1014 desc->len = 1015 htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); 1016 desc->flags = htole32(cflags); 1017 sc->ale_cdata.ale_tx_cnt++; 1018 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1019 } 1020 /* Update producer index. */ 1021 sc->ale_cdata.ale_tx_prod = prod; 1022 1023 /* Finally set EOP on the last descriptor. */ 1024 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1025 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1026 desc->flags |= htole32(ALE_TD_EOP); 1027 1028 /* Swap dmamap of the first and the last. */ 1029 txd = &sc->ale_cdata.ale_txdesc[prod]; 1030 map = txd_last->tx_dmamap; 1031 txd_last->tx_dmamap = txd->tx_dmamap; 1032 txd->tx_dmamap = map; 1033 txd->tx_m = m; 1034 1035 /* Sync descriptors. */ 1036 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1037 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1038 1039 return 0; 1040 } 1041 1042 static void 1043 ale_start(struct ifnet *ifp) 1044 { 1045 struct ale_softc *sc = ifp->if_softc; 1046 struct mbuf *m_head; 1047 int enq; 1048 1049 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1050 return; 1051 1052 /* Reclaim transmitted frames. */ 1053 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1054 ale_txeof(sc); 1055 1056 enq = 0; 1057 for (;;) { 1058 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1059 if (m_head == NULL) 1060 break; 1061 1062 /* 1063 * Pack the data into the transmit ring. If we 1064 * don't have room, set the OACTIVE flag and wait 1065 * for the NIC to drain the ring. 1066 */ 1067 if (ale_encap(sc, &m_head)) { 1068 if (m_head == NULL) 1069 break; 1070 ifp->if_flags |= IFF_OACTIVE; 1071 break; 1072 } 1073 enq = 1; 1074 1075 #if NBPFILTER > 0 1076 /* 1077 * If there's a BPF listener, bounce a copy of this frame 1078 * to him. 1079 */ 1080 if (ifp->if_bpf != NULL) 1081 bpf_mtap(ifp->if_bpf, m_head); 1082 #endif 1083 } 1084 1085 if (enq) { 1086 /* Kick. */ 1087 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1088 sc->ale_cdata.ale_tx_prod); 1089 1090 /* Set a timeout in case the chip goes out to lunch. */ 1091 ifp->if_timer = ALE_TX_TIMEOUT; 1092 } 1093 } 1094 1095 static void 1096 ale_watchdog(struct ifnet *ifp) 1097 { 1098 struct ale_softc *sc = ifp->if_softc; 1099 1100 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1101 printf("%s: watchdog timeout (missed link)\n", 1102 device_xname(sc->sc_dev)); 1103 ifp->if_oerrors++; 1104 ale_init(ifp); 1105 return; 1106 } 1107 1108 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1109 ifp->if_oerrors++; 1110 ale_init(ifp); 1111 1112 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1113 ale_start(ifp); 1114 } 1115 1116 static int 1117 ale_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1118 { 1119 struct ale_softc *sc = ifp->if_softc; 1120 int s, error; 1121 1122 s = splnet(); 1123 1124 error = ether_ioctl(ifp, cmd, data); 1125 if (error == ENETRESET) { 1126 if (ifp->if_flags & IFF_RUNNING) 1127 ale_rxfilter(sc); 1128 error = 0; 1129 } 1130 1131 splx(s); 1132 return error; 1133 } 1134 1135 static void 1136 ale_mac_config(struct ale_softc *sc) 1137 { 1138 struct mii_data *mii; 1139 uint32_t reg; 1140 1141 mii = &sc->sc_miibus; 1142 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1143 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1144 MAC_CFG_SPEED_MASK); 1145 1146 /* Reprogram MAC with resolved speed/duplex. */ 1147 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1148 case IFM_10_T: 1149 case IFM_100_TX: 1150 reg |= MAC_CFG_SPEED_10_100; 1151 break; 1152 case IFM_1000_T: 1153 reg |= MAC_CFG_SPEED_1000; 1154 break; 1155 } 1156 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1157 reg |= MAC_CFG_FULL_DUPLEX; 1158 #ifdef notyet 1159 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1160 reg |= MAC_CFG_TX_FC; 1161 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1162 reg |= MAC_CFG_RX_FC; 1163 #endif 1164 } 1165 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1166 } 1167 1168 static void 1169 ale_stats_clear(struct ale_softc *sc) 1170 { 1171 struct smb sb; 1172 uint32_t *reg; 1173 int i; 1174 1175 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1176 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1177 i += sizeof(uint32_t); 1178 } 1179 /* Read Tx statistics. */ 1180 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1181 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1182 i += sizeof(uint32_t); 1183 } 1184 } 1185 1186 static void 1187 ale_stats_update(struct ale_softc *sc) 1188 { 1189 struct ifnet *ifp = &sc->sc_ec.ec_if; 1190 struct ale_hw_stats *stat; 1191 struct smb sb, *smb; 1192 uint32_t *reg; 1193 int i; 1194 1195 stat = &sc->ale_stats; 1196 smb = &sb; 1197 1198 /* Read Rx statistics. */ 1199 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1200 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1201 i += sizeof(uint32_t); 1202 } 1203 /* Read Tx statistics. */ 1204 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1205 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1206 i += sizeof(uint32_t); 1207 } 1208 1209 /* Rx stats. */ 1210 stat->rx_frames += smb->rx_frames; 1211 stat->rx_bcast_frames += smb->rx_bcast_frames; 1212 stat->rx_mcast_frames += smb->rx_mcast_frames; 1213 stat->rx_pause_frames += smb->rx_pause_frames; 1214 stat->rx_control_frames += smb->rx_control_frames; 1215 stat->rx_crcerrs += smb->rx_crcerrs; 1216 stat->rx_lenerrs += smb->rx_lenerrs; 1217 stat->rx_bytes += smb->rx_bytes; 1218 stat->rx_runts += smb->rx_runts; 1219 stat->rx_fragments += smb->rx_fragments; 1220 stat->rx_pkts_64 += smb->rx_pkts_64; 1221 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1222 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1223 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1224 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1225 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1226 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1227 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1228 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1229 stat->rx_rrs_errs += smb->rx_rrs_errs; 1230 stat->rx_alignerrs += smb->rx_alignerrs; 1231 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1232 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1233 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1234 1235 /* Tx stats. */ 1236 stat->tx_frames += smb->tx_frames; 1237 stat->tx_bcast_frames += smb->tx_bcast_frames; 1238 stat->tx_mcast_frames += smb->tx_mcast_frames; 1239 stat->tx_pause_frames += smb->tx_pause_frames; 1240 stat->tx_excess_defer += smb->tx_excess_defer; 1241 stat->tx_control_frames += smb->tx_control_frames; 1242 stat->tx_deferred += smb->tx_deferred; 1243 stat->tx_bytes += smb->tx_bytes; 1244 stat->tx_pkts_64 += smb->tx_pkts_64; 1245 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1246 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1247 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1248 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1249 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1250 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1251 stat->tx_single_colls += smb->tx_single_colls; 1252 stat->tx_multi_colls += smb->tx_multi_colls; 1253 stat->tx_late_colls += smb->tx_late_colls; 1254 stat->tx_excess_colls += smb->tx_excess_colls; 1255 stat->tx_abort += smb->tx_abort; 1256 stat->tx_underrun += smb->tx_underrun; 1257 stat->tx_desc_underrun += smb->tx_desc_underrun; 1258 stat->tx_lenerrs += smb->tx_lenerrs; 1259 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1260 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1261 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1262 1263 /* Update counters in ifnet. */ 1264 ifp->if_opackets += smb->tx_frames; 1265 1266 ifp->if_collisions += smb->tx_single_colls + 1267 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1268 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1269 1270 /* 1271 * XXX 1272 * tx_pkts_truncated counter looks suspicious. It constantly 1273 * increments with no sign of Tx errors. This may indicate 1274 * the counter name is not correct one so I've removed the 1275 * counter in output errors. 1276 */ 1277 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1278 smb->tx_underrun; 1279 1280 ifp->if_ipackets += smb->rx_frames; 1281 1282 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1283 smb->rx_runts + smb->rx_pkts_truncated + 1284 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1285 smb->rx_alignerrs; 1286 } 1287 1288 static int 1289 ale_intr(void *xsc) 1290 { 1291 struct ale_softc *sc = xsc; 1292 struct ifnet *ifp = &sc->sc_ec.ec_if; 1293 uint32_t status; 1294 1295 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1296 if ((status & ALE_INTRS) == 0) 1297 return 0; 1298 1299 /* Acknowledge and disable interrupts. */ 1300 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1301 1302 if (ifp->if_flags & IFF_RUNNING) { 1303 int error; 1304 1305 error = ale_rxeof(sc); 1306 if (error) { 1307 sc->ale_stats.reset_brk_seq++; 1308 ale_init(ifp); 1309 return 0; 1310 } 1311 1312 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) { 1313 if (status & INTR_DMA_RD_TO_RST) 1314 printf("%s: DMA read error! -- resetting\n", 1315 device_xname(sc->sc_dev)); 1316 if (status & INTR_DMA_WR_TO_RST) 1317 printf("%s: DMA write error! -- resetting\n", 1318 device_xname(sc->sc_dev)); 1319 ale_init(ifp); 1320 return 0; 1321 } 1322 1323 ale_txeof(sc); 1324 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1325 ale_start(ifp); 1326 } 1327 1328 /* Re-enable interrupts. */ 1329 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 1330 return 1; 1331 } 1332 1333 static void 1334 ale_txeof(struct ale_softc *sc) 1335 { 1336 struct ifnet *ifp = &sc->sc_ec.ec_if; 1337 struct ale_txdesc *txd; 1338 uint32_t cons, prod; 1339 int prog; 1340 1341 if (sc->ale_cdata.ale_tx_cnt == 0) 1342 return; 1343 1344 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1345 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1346 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 1347 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1348 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, 1349 BUS_DMASYNC_POSTREAD); 1350 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 1351 } else 1352 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 1353 cons = sc->ale_cdata.ale_tx_cons; 1354 /* 1355 * Go through our Tx list and free mbufs for those 1356 * frames which have been transmitted. 1357 */ 1358 for (prog = 0; cons != prod; prog++, 1359 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 1360 if (sc->ale_cdata.ale_tx_cnt <= 0) 1361 break; 1362 prog++; 1363 ifp->if_flags &= ~IFF_OACTIVE; 1364 sc->ale_cdata.ale_tx_cnt--; 1365 txd = &sc->ale_cdata.ale_txdesc[cons]; 1366 if (txd->tx_m != NULL) { 1367 /* Reclaim transmitted mbufs. */ 1368 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1369 m_freem(txd->tx_m); 1370 txd->tx_m = NULL; 1371 } 1372 } 1373 1374 if (prog > 0) { 1375 sc->ale_cdata.ale_tx_cons = cons; 1376 /* 1377 * Unarm watchdog timer only when there is no pending 1378 * Tx descriptors in queue. 1379 */ 1380 if (sc->ale_cdata.ale_tx_cnt == 0) 1381 ifp->if_timer = 0; 1382 } 1383 } 1384 1385 static void 1386 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 1387 uint32_t length, uint32_t *prod) 1388 { 1389 struct ale_rx_page *rx_page; 1390 1391 rx_page = *page; 1392 /* Update consumer position. */ 1393 rx_page->cons += roundup(length + sizeof(struct rx_rs), 1394 ALE_RX_PAGE_ALIGN); 1395 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 1396 /* 1397 * End of Rx page reached, let hardware reuse 1398 * this page. 1399 */ 1400 rx_page->cons = 0; 1401 *rx_page->cmb_addr = 0; 1402 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1403 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1404 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 1405 RXF_VALID); 1406 /* Switch to alternate Rx page. */ 1407 sc->ale_cdata.ale_rx_curp ^= 1; 1408 rx_page = *page = 1409 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1410 /* Page flipped, sync CMB and Rx page. */ 1411 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1412 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1413 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1414 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1415 /* Sync completed, cache updated producer index. */ 1416 *prod = *rx_page->cmb_addr; 1417 } 1418 } 1419 1420 1421 /* 1422 * It seems that AR81xx controller can compute partial checksum. 1423 * The partial checksum value can be used to accelerate checksum 1424 * computation for fragmented TCP/UDP packets. Upper network stack 1425 * already takes advantage of the partial checksum value in IP 1426 * reassembly stage. But I'm not sure the correctness of the 1427 * partial hardware checksum assistance due to lack of data sheet. 1428 * In addition, the Rx feature of controller that requires copying 1429 * for every frames effectively nullifies one of most nice offload 1430 * capability of controller. 1431 */ 1432 static void 1433 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 1434 { 1435 if (status & ALE_RD_IPCSUM_NOK) 1436 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1437 1438 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 1439 if (((status & ALE_RD_IPV4_FRAG) == 0) && 1440 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 1441 (status & ALE_RD_TCP_UDPCSUM_NOK)) 1442 { 1443 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1444 } 1445 } else { 1446 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) { 1447 if (status & ALE_RD_TCP_UDPCSUM_NOK) { 1448 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1449 } 1450 } 1451 } 1452 /* 1453 * Don't mark bad checksum for TCP/UDP frames 1454 * as fragmented frames may always have set 1455 * bad checksummed bit of frame status. 1456 */ 1457 } 1458 1459 /* Process received frames. */ 1460 static int 1461 ale_rxeof(struct ale_softc *sc) 1462 { 1463 struct ifnet *ifp = &sc->sc_ec.ec_if; 1464 struct ale_rx_page *rx_page; 1465 struct rx_rs *rs; 1466 struct mbuf *m; 1467 uint32_t length, prod, seqno, status; 1468 int prog; 1469 1470 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 1471 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1472 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1473 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1474 rx_page->page_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1475 /* 1476 * Don't directly access producer index as hardware may 1477 * update it while Rx handler is in progress. It would 1478 * be even better if there is a way to let hardware 1479 * know how far driver processed its received frames. 1480 * Alternatively, hardware could provide a way to disable 1481 * CMB updates until driver acknowledges the end of CMB 1482 * access. 1483 */ 1484 prod = *rx_page->cmb_addr; 1485 for (prog = 0; ; prog++) { 1486 if (rx_page->cons >= prod) 1487 break; 1488 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 1489 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 1490 if (sc->ale_cdata.ale_rx_seqno != seqno) { 1491 /* 1492 * Normally I believe this should not happen unless 1493 * severe driver bug or corrupted memory. However 1494 * it seems to happen under certain conditions which 1495 * is triggered by abrupt Rx events such as initiation 1496 * of bulk transfer of remote host. It's not easy to 1497 * reproduce this and I doubt it could be related 1498 * with FIFO overflow of hardware or activity of Tx 1499 * CMB updates. I also remember similar behaviour 1500 * seen on RealTek 8139 which uses resembling Rx 1501 * scheme. 1502 */ 1503 if (aledebug) 1504 printf("%s: garbled seq: %u, expected: %u -- " 1505 "resetting!\n", device_xname(sc->sc_dev), 1506 seqno, sc->ale_cdata.ale_rx_seqno); 1507 return EIO; 1508 } 1509 /* Frame received. */ 1510 sc->ale_cdata.ale_rx_seqno++; 1511 length = ALE_RX_BYTES(le32toh(rs->length)); 1512 status = le32toh(rs->flags); 1513 if (status & ALE_RD_ERROR) { 1514 /* 1515 * We want to pass the following frames to upper 1516 * layer regardless of error status of Rx return 1517 * status. 1518 * 1519 * o IP/TCP/UDP checksum is bad. 1520 * o frame length and protocol specific length 1521 * does not match. 1522 */ 1523 if (status & (ALE_RD_CRC | ALE_RD_CODE | 1524 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 1525 ALE_RD_TRUNC)) { 1526 ale_rx_update_page(sc, &rx_page, length, &prod); 1527 continue; 1528 } 1529 } 1530 /* 1531 * m_devget(9) is major bottle-neck of ale(4)(It comes 1532 * from hardware limitation). For jumbo frames we could 1533 * get a slightly better performance if driver use 1534 * m_getjcl(9) with proper buffer size argument. However 1535 * that would make code more complicated and I don't 1536 * think users would expect good Rx performance numbers 1537 * on these low-end consumer ethernet controller. 1538 */ 1539 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 1540 0, ifp, NULL); 1541 if (m == NULL) { 1542 ifp->if_iqdrops++; 1543 ale_rx_update_page(sc, &rx_page, length, &prod); 1544 continue; 1545 } 1546 if (status & ALE_RD_IPV4) 1547 ale_rxcsum(sc, m, status); 1548 #if NVLAN > 0 1549 if (status & ALE_RD_VLAN) { 1550 uint32_t vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 1551 VLAN_INPUT_TAG(ifp, m, ALE_RX_VLAN_TAG(vtags), ); 1552 } 1553 #endif 1554 1555 1556 #if NBPFILTER > 0 1557 if (ifp->if_bpf) 1558 bpf_mtap(ifp->if_bpf, m); 1559 #endif 1560 1561 /* Pass it to upper layer. */ 1562 ether_input(ifp, m); 1563 1564 ale_rx_update_page(sc, &rx_page, length, &prod); 1565 } 1566 1567 return 0; 1568 } 1569 1570 static void 1571 ale_tick(void *xsc) 1572 { 1573 struct ale_softc *sc = xsc; 1574 struct mii_data *mii = &sc->sc_miibus; 1575 int s; 1576 1577 s = splnet(); 1578 mii_tick(mii); 1579 ale_stats_update(sc); 1580 splx(s); 1581 1582 callout_schedule(&sc->sc_tick_ch, hz); 1583 } 1584 1585 static void 1586 ale_reset(struct ale_softc *sc) 1587 { 1588 uint32_t reg; 1589 int i; 1590 1591 /* Initialize PCIe module. From Linux. */ 1592 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 1593 1594 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 1595 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1596 DELAY(10); 1597 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 1598 break; 1599 } 1600 if (i == 0) 1601 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 1602 1603 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 1604 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 1605 break; 1606 DELAY(10); 1607 } 1608 1609 if (i == 0) 1610 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 1611 reg); 1612 } 1613 1614 static int 1615 ale_init(struct ifnet *ifp) 1616 { 1617 struct ale_softc *sc = ifp->if_softc; 1618 struct mii_data *mii; 1619 uint8_t eaddr[ETHER_ADDR_LEN]; 1620 bus_addr_t paddr; 1621 uint32_t reg, rxf_hi, rxf_lo; 1622 1623 /* 1624 * Cancel any pending I/O. 1625 */ 1626 ale_stop(ifp, 0); 1627 1628 /* 1629 * Reset the chip to a known state. 1630 */ 1631 ale_reset(sc); 1632 1633 /* Initialize Tx descriptors, DMA memory blocks. */ 1634 ale_init_rx_pages(sc); 1635 ale_init_tx_ring(sc); 1636 1637 /* Reprogram the station address. */ 1638 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1639 CSR_WRITE_4(sc, ALE_PAR0, 1640 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 1641 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 1642 1643 /* 1644 * Clear WOL status and disable all WOL feature as WOL 1645 * would interfere Rx operation under normal environments. 1646 */ 1647 CSR_READ_4(sc, ALE_WOL_CFG); 1648 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1649 1650 /* 1651 * Set Tx descriptor/RXF0/CMB base addresses. They share 1652 * the same high address part of DMAable region. 1653 */ 1654 paddr = sc->ale_cdata.ale_tx_ring_paddr; 1655 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 1656 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 1657 CSR_WRITE_4(sc, ALE_TPD_CNT, 1658 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 1659 1660 /* Set Rx page base address, note we use single queue. */ 1661 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 1662 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 1663 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 1664 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 1665 1666 /* Set Tx/Rx CMB addresses. */ 1667 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 1668 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 1669 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 1670 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 1671 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 1672 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 1673 1674 /* Mark RXF0 is valid. */ 1675 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 1676 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 1677 /* 1678 * No need to initialize RFX1/RXF2/RXF3. We don't use 1679 * multi-queue yet. 1680 */ 1681 1682 /* Set Rx page size, excluding guard frame size. */ 1683 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 1684 1685 /* Tell hardware that we're ready to load DMA blocks. */ 1686 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 1687 1688 /* Set Rx/Tx interrupt trigger threshold. */ 1689 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 1690 (4 << INT_TRIG_TX_THRESH_SHIFT)); 1691 /* 1692 * XXX 1693 * Set interrupt trigger timer, its purpose and relation 1694 * with interrupt moderation mechanism is not clear yet. 1695 */ 1696 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 1697 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 1698 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 1699 1700 /* Configure interrupt moderation timer. */ 1701 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 1702 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 1703 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 1704 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 1705 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 1706 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 1707 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 1708 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 1709 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 1710 reg |= MASTER_IM_RX_TIMER_ENB; 1711 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 1712 reg |= MASTER_IM_TX_TIMER_ENB; 1713 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 1714 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 1715 1716 /* Set Maximum frame size of controller. */ 1717 if (ifp->if_mtu < ETHERMTU) 1718 sc->ale_max_frame_size = ETHERMTU; 1719 else 1720 sc->ale_max_frame_size = ifp->if_mtu; 1721 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1722 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 1723 1724 /* Configure IPG/IFG parameters. */ 1725 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 1726 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 1727 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 1728 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 1729 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 1730 1731 /* Set parameters for half-duplex media. */ 1732 CSR_WRITE_4(sc, ALE_HDPX_CFG, 1733 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 1734 HDPX_CFG_LCOL_MASK) | 1735 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 1736 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 1737 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 1738 HDPX_CFG_ABEBT_MASK) | 1739 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 1740 HDPX_CFG_JAMIPG_MASK)); 1741 1742 /* Configure Tx jumbo frame parameters. */ 1743 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1744 if (ifp->if_mtu < ETHERMTU) 1745 reg = sc->ale_max_frame_size; 1746 else if (ifp->if_mtu < 6 * 1024) 1747 reg = (sc->ale_max_frame_size * 2) / 3; 1748 else 1749 reg = sc->ale_max_frame_size / 2; 1750 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 1751 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 1752 TX_JUMBO_THRESH_UNIT_SHIFT); 1753 } 1754 1755 /* Configure TxQ. */ 1756 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 1757 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 1758 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 1759 TXQ_CFG_TPD_BURST_MASK; 1760 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 1761 1762 /* Configure Rx jumbo frame & flow control parameters. */ 1763 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 1764 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 1765 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 1766 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 1767 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 1768 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 1769 RX_JUMBO_LKAH_MASK)); 1770 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 1771 rxf_hi = (reg * 7) / 10; 1772 rxf_lo = (reg * 3)/ 10; 1773 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 1774 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 1775 RX_FIFO_PAUSE_THRESH_LO_MASK) | 1776 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 1777 RX_FIFO_PAUSE_THRESH_HI_MASK)); 1778 } 1779 1780 /* Disable RSS. */ 1781 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 1782 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 1783 1784 /* Configure RxQ. */ 1785 CSR_WRITE_4(sc, ALE_RXQ_CFG, 1786 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 1787 1788 /* Configure DMA parameters. */ 1789 reg = 0; 1790 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 1791 reg |= DMA_CFG_TXCMB_ENB; 1792 CSR_WRITE_4(sc, ALE_DMA_CFG, 1793 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 1794 sc->ale_dma_rd_burst | reg | 1795 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 1796 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 1797 DMA_CFG_RD_DELAY_CNT_MASK) | 1798 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 1799 DMA_CFG_WR_DELAY_CNT_MASK)); 1800 1801 /* 1802 * Hardware can be configured to issue SMB interrupt based 1803 * on programmed interval. Since there is a callout that is 1804 * invoked for every hz in driver we use that instead of 1805 * relying on periodic SMB interrupt. 1806 */ 1807 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 1808 1809 /* Clear MAC statistics. */ 1810 ale_stats_clear(sc); 1811 1812 /* 1813 * Configure Tx/Rx MACs. 1814 * - Auto-padding for short frames. 1815 * - Enable CRC generation. 1816 * Actual reconfiguration of MAC for resolved speed/duplex 1817 * is followed after detection of link establishment. 1818 * AR81xx always does checksum computation regardless of 1819 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 1820 * cause Rx handling issue for fragmented IP datagrams due 1821 * to silicon bug. 1822 */ 1823 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 1824 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 1825 MAC_CFG_PREAMBLE_MASK); 1826 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 1827 reg |= MAC_CFG_SPEED_10_100; 1828 else 1829 reg |= MAC_CFG_SPEED_1000; 1830 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1831 1832 /* Set up the receive filter. */ 1833 ale_rxfilter(sc); 1834 ale_rxvlan(sc); 1835 1836 /* Acknowledge all pending interrupts and clear it. */ 1837 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 1838 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1839 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 1840 1841 sc->ale_flags &= ~ALE_FLAG_LINK; 1842 1843 /* Switch to the current media. */ 1844 mii = &sc->sc_miibus; 1845 mii_mediachg(mii); 1846 1847 callout_schedule(&sc->sc_tick_ch, hz); 1848 1849 ifp->if_flags |= IFF_RUNNING; 1850 ifp->if_flags &= ~IFF_OACTIVE; 1851 1852 return 0; 1853 } 1854 1855 static void 1856 ale_stop(struct ifnet *ifp, int disable) 1857 { 1858 struct ale_softc *sc = ifp->if_softc; 1859 struct ale_txdesc *txd; 1860 uint32_t reg; 1861 int i; 1862 1863 callout_stop(&sc->sc_tick_ch); 1864 1865 /* 1866 * Mark the interface down and cancel the watchdog timer. 1867 */ 1868 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1869 ifp->if_timer = 0; 1870 1871 sc->ale_flags &= ~ALE_FLAG_LINK; 1872 1873 ale_stats_update(sc); 1874 1875 mii_down(&sc->sc_miibus); 1876 1877 /* Disable interrupts. */ 1878 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 1879 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1880 1881 /* Disable queue processing and DMA. */ 1882 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 1883 reg &= ~TXQ_CFG_ENB; 1884 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 1885 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 1886 reg &= ~RXQ_CFG_ENB; 1887 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 1888 reg = CSR_READ_4(sc, ALE_DMA_CFG); 1889 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 1890 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 1891 DELAY(1000); 1892 1893 /* Stop Rx/Tx MACs. */ 1894 ale_stop_mac(sc); 1895 1896 /* Disable interrupts again? XXX */ 1897 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 1898 1899 /* 1900 * Free TX mbufs still in the queues. 1901 */ 1902 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1903 txd = &sc->ale_cdata.ale_txdesc[i]; 1904 if (txd->tx_m != NULL) { 1905 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1906 m_freem(txd->tx_m); 1907 txd->tx_m = NULL; 1908 } 1909 } 1910 } 1911 1912 static void 1913 ale_stop_mac(struct ale_softc *sc) 1914 { 1915 uint32_t reg; 1916 int i; 1917 1918 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1919 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 1920 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1921 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1922 } 1923 1924 for (i = ALE_TIMEOUT; i > 0; i--) { 1925 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 1926 if (reg == 0) 1927 break; 1928 DELAY(10); 1929 } 1930 if (i == 0) 1931 printf("%s: could not disable Tx/Rx MAC(0x%08x)!\n", 1932 device_xname(sc->sc_dev), reg); 1933 } 1934 1935 static void 1936 ale_init_tx_ring(struct ale_softc *sc) 1937 { 1938 struct ale_txdesc *txd; 1939 int i; 1940 1941 sc->ale_cdata.ale_tx_prod = 0; 1942 sc->ale_cdata.ale_tx_cons = 0; 1943 sc->ale_cdata.ale_tx_cnt = 0; 1944 1945 memset(sc->ale_cdata.ale_tx_ring, 0, ALE_TX_RING_SZ); 1946 memset(sc->ale_cdata.ale_tx_cmb, 0, ALE_TX_CMB_SZ); 1947 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1948 txd = &sc->ale_cdata.ale_txdesc[i]; 1949 txd->tx_m = NULL; 1950 } 1951 *sc->ale_cdata.ale_tx_cmb = 0; 1952 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, 1953 sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1954 bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, 0, 1955 sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1956 } 1957 1958 static void 1959 ale_init_rx_pages(struct ale_softc *sc) 1960 { 1961 struct ale_rx_page *rx_page; 1962 int i; 1963 1964 sc->ale_cdata.ale_rx_seqno = 0; 1965 sc->ale_cdata.ale_rx_curp = 0; 1966 1967 for (i = 0; i < ALE_RX_PAGES; i++) { 1968 rx_page = &sc->ale_cdata.ale_rx_page[i]; 1969 memset(rx_page->page_addr, 0, sc->ale_pagesize); 1970 memset(rx_page->cmb_addr, 0, ALE_RX_CMB_SZ); 1971 rx_page->cons = 0; 1972 *rx_page->cmb_addr = 0; 1973 bus_dmamap_sync(sc->sc_dmat, rx_page->page_map, 0, 1974 rx_page->page_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1975 bus_dmamap_sync(sc->sc_dmat, rx_page->cmb_map, 0, 1976 rx_page->cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1977 } 1978 } 1979 1980 static void 1981 ale_rxvlan(struct ale_softc *sc) 1982 { 1983 struct ifnet *ifp = &sc->sc_ec.ec_if; 1984 uint32_t reg; 1985 1986 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1987 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 1988 if (ifp->if_capabilities & ETHERCAP_VLAN_HWTAGGING) 1989 reg |= MAC_CFG_VLAN_TAG_STRIP; 1990 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1991 } 1992 1993 static void 1994 ale_rxfilter(struct ale_softc *sc) 1995 { 1996 struct ethercom *ec = &sc->sc_ec; 1997 struct ifnet *ifp = &ec->ec_if; 1998 struct ether_multi *enm; 1999 struct ether_multistep step; 2000 uint32_t crc; 2001 uint32_t mchash[2]; 2002 uint32_t rxcfg; 2003 2004 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2005 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2006 2007 /* 2008 * Always accept broadcast frames. 2009 */ 2010 rxcfg |= MAC_CFG_BCAST; 2011 2012 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC || 2013 ec->ec_multicnt > 0) { 2014 allmulti: 2015 if (ifp->if_flags & IFF_PROMISC) 2016 rxcfg |= MAC_CFG_PROMISC; 2017 else 2018 rxcfg |= MAC_CFG_ALLMULTI; 2019 mchash[0] = mchash[1] = 0xFFFFFFFF; 2020 } else { 2021 /* Program new filter. */ 2022 memset(mchash, 0, sizeof(mchash)); 2023 2024 ETHER_FIRST_MULTI(step, ec, enm); 2025 while (enm != NULL) { 2026 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2027 ETHER_ADDR_LEN)) { 2028 ifp->if_flags |= IFF_ALLMULTI; 2029 goto allmulti; 2030 } 2031 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2032 2033 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2034 ETHER_NEXT_MULTI(step, enm); 2035 } 2036 } 2037 2038 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2039 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2040 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2041 } 2042