1 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 30 31 #ifdef _KERNEL_OPT 32 #include "vlan.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/callout.h> 46 #include <sys/socket.h> 47 #include <sys/module.h> 48 49 #include <sys/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <net/bpf.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcidevs.h> 77 78 #include <dev/pci/if_alcreg.h> 79 80 /* 81 * Devices supported by this driver. 82 */ 83 static struct alc_ident alc_ident_table[] = { 84 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 85 "Atheros AR8131 PCIe Gigabit Ethernet" }, 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 87 "Atheros AR8132 PCIe Fast Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 89 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 91 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 93 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 95 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161, 9 * 1024, 97 "Atheros AR8161 PCIe Gigabit Ethernet" }, 98 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162, 9 * 1024, 99 "Atheros AR8162 PCIe Fast Ethernet" }, 100 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171, 9 * 1024, 101 "Atheros AR8171 PCIe Gigabit Ethernet" }, 102 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172, 9 * 1024, 103 "Atheros AR8172 PCIe Fast Ethernet" }, 104 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_E2200, 9 * 1024, 105 "Killer E2200 Gigabit Ethernet" }, 106 { 0, 0, 0, NULL }, 107 }; 108 109 static int alc_match(device_t, cfdata_t, void *); 110 static void alc_attach(device_t, device_t, void *); 111 static int alc_detach(device_t, int); 112 113 static int alc_init(struct ifnet *); 114 static int alc_init_backend(struct ifnet *, bool); 115 static void alc_start(struct ifnet *); 116 static int alc_ioctl(struct ifnet *, u_long, void *); 117 static void alc_watchdog(struct ifnet *); 118 static int alc_mediachange(struct ifnet *); 119 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 120 121 static void alc_aspm(struct alc_softc *, int, int); 122 static void alc_aspm_813x(struct alc_softc *, int); 123 static void alc_aspm_816x(struct alc_softc *, int); 124 static void alc_disable_l0s_l1(struct alc_softc *); 125 static int alc_dma_alloc(struct alc_softc *); 126 static void alc_dma_free(struct alc_softc *); 127 static void alc_dsp_fixup(struct alc_softc *, int); 128 static int alc_encap(struct alc_softc *, struct mbuf **); 129 static struct alc_ident * 130 alc_find_ident(struct pci_attach_args *); 131 static void alc_get_macaddr(struct alc_softc *); 132 static void alc_get_macaddr_813x(struct alc_softc *); 133 static void alc_get_macaddr_816x(struct alc_softc *); 134 static void alc_get_macaddr_par(struct alc_softc *); 135 static void alc_init_cmb(struct alc_softc *); 136 static void alc_init_rr_ring(struct alc_softc *); 137 static int alc_init_rx_ring(struct alc_softc *, bool); 138 static void alc_init_smb(struct alc_softc *); 139 static void alc_init_tx_ring(struct alc_softc *); 140 static int alc_intr(void *); 141 static void alc_mac_config(struct alc_softc *); 142 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 143 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 144 static void alc_mii_writereg_813x(struct alc_softc *, int, int, int); 145 static void alc_mii_writereg_816x(struct alc_softc *, int, int, int); 146 static int alc_miibus_readreg(device_t, int, int); 147 static void alc_miibus_statchg(struct ifnet *); 148 static void alc_miibus_writereg(device_t, int, int, int); 149 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 150 static void alc_miidbg_writereg(struct alc_softc *, int, int); 151 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 152 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 153 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 154 static void alc_phy_down(struct alc_softc *); 155 static void alc_phy_reset(struct alc_softc *); 156 static void alc_phy_reset_813x(struct alc_softc *); 157 static void alc_phy_reset_816x(struct alc_softc *); 158 static void alc_reset(struct alc_softc *); 159 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 160 static int alc_rxintr(struct alc_softc *); 161 static void alc_iff(struct alc_softc *); 162 static void alc_rxvlan(struct alc_softc *); 163 static void alc_start_queue(struct alc_softc *); 164 static void alc_stats_clear(struct alc_softc *); 165 static void alc_stats_update(struct alc_softc *); 166 static void alc_stop(struct ifnet *, int); 167 static void alc_stop_mac(struct alc_softc *); 168 static void alc_stop_queue(struct alc_softc *); 169 static void alc_tick(void *); 170 static void alc_txeof(struct alc_softc *); 171 172 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 173 174 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 175 alc_match, alc_attach, alc_detach, NULL); 176 177 int alcdebug = 0; 178 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 179 180 #define ETHER_ALIGN 2 181 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 182 183 static int 184 alc_miibus_readreg(device_t dev, int phy, int reg) 185 { 186 struct alc_softc *sc = device_private(dev); 187 int v; 188 189 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 190 v = alc_mii_readreg_816x(sc, phy, reg); 191 else 192 v = alc_mii_readreg_813x(sc, phy, reg); 193 return (v); 194 } 195 196 static uint32_t 197 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 198 { 199 uint32_t v; 200 int i; 201 202 if (phy != sc->alc_phyaddr) 203 return (0); 204 205 /* 206 * For AR8132 fast ethernet controller, do not report 1000baseT 207 * capability to mii(4). Even though AR8132 uses the same 208 * model/revision number of F1 gigabit PHY, the PHY has no 209 * ability to establish 1000baseT link. 210 */ 211 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 212 reg == MII_EXTSR) 213 return 0; 214 215 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 216 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 217 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 218 DELAY(5); 219 v = CSR_READ_4(sc, ALC_MDIO); 220 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 221 break; 222 } 223 224 if (i == 0) { 225 printf("%s: phy read timeout: phy %d, reg %d\n", 226 device_xname(sc->sc_dev), phy, reg); 227 return (0); 228 } 229 230 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 231 } 232 233 static uint32_t 234 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 235 { 236 uint32_t clk, v; 237 int i; 238 239 if (phy != sc->alc_phyaddr) 240 return (0); 241 242 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 243 clk = MDIO_CLK_25_128; 244 else 245 clk = MDIO_CLK_25_4; 246 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 247 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 248 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 249 DELAY(5); 250 v = CSR_READ_4(sc, ALC_MDIO); 251 if ((v & MDIO_OP_BUSY) == 0) 252 break; 253 } 254 255 if (i == 0) { 256 printf("%s: phy read timeout: phy %d, reg %d\n", 257 device_xname(sc->sc_dev), phy, reg); 258 return (0); 259 } 260 261 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 262 } 263 264 static void 265 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 266 { 267 struct alc_softc *sc = device_private(dev); 268 269 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 270 alc_mii_writereg_816x(sc, phy, reg, val); 271 else 272 alc_mii_writereg_813x(sc, phy, reg, val); 273 274 return; 275 } 276 277 static void 278 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 279 { 280 uint32_t v; 281 int i; 282 283 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 284 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 285 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 286 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 287 DELAY(5); 288 v = CSR_READ_4(sc, ALC_MDIO); 289 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 290 break; 291 } 292 293 if (i == 0) 294 printf("%s: phy write timeout: phy %d, reg %d\n", 295 device_xname(sc->sc_dev), phy, reg); 296 297 return; 298 } 299 300 static void 301 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 302 { 303 uint32_t clk, v; 304 int i; 305 306 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 307 clk = MDIO_CLK_25_128; 308 else 309 clk = MDIO_CLK_25_4; 310 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 311 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 312 MDIO_SUP_PREAMBLE | clk); 313 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 314 DELAY(5); 315 v = CSR_READ_4(sc, ALC_MDIO); 316 if ((v & MDIO_OP_BUSY) == 0) 317 break; 318 } 319 320 if (i == 0) 321 printf("%s: phy write timeout: phy %d, reg %d\n", 322 device_xname(sc->sc_dev), phy, reg); 323 324 return; 325 } 326 327 static void 328 alc_miibus_statchg(struct ifnet *ifp) 329 { 330 struct alc_softc *sc = ifp->if_softc; 331 struct mii_data *mii = &sc->sc_miibus; 332 uint32_t reg; 333 334 if ((ifp->if_flags & IFF_RUNNING) == 0) 335 return; 336 337 sc->alc_flags &= ~ALC_FLAG_LINK; 338 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 339 (IFM_ACTIVE | IFM_AVALID)) { 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_10_T: 342 case IFM_100_TX: 343 sc->alc_flags |= ALC_FLAG_LINK; 344 break; 345 case IFM_1000_T: 346 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 347 sc->alc_flags |= ALC_FLAG_LINK; 348 break; 349 default: 350 break; 351 } 352 } 353 /* Stop Rx/Tx MACs. */ 354 alc_stop_mac(sc); 355 356 /* Program MACs with resolved speed/duplex/flow-control. */ 357 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 358 alc_start_queue(sc); 359 alc_mac_config(sc); 360 /* Re-enable Tx/Rx MACs. */ 361 reg = CSR_READ_4(sc, ALC_MAC_CFG); 362 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 363 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 364 } 365 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 366 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 367 } 368 369 static uint32_t 370 alc_miidbg_readreg(struct alc_softc *sc, int reg) 371 { 372 373 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 374 reg); 375 return (alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 376 ALC_MII_DBG_DATA)); 377 } 378 379 static void 380 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 381 { 382 383 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 384 reg); 385 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, val); 386 387 return; 388 } 389 390 static uint32_t 391 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 392 { 393 uint32_t clk, v; 394 int i; 395 396 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 397 EXT_MDIO_DEVADDR(devaddr)); 398 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 399 clk = MDIO_CLK_25_128; 400 else 401 clk = MDIO_CLK_25_4; 402 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 403 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 404 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 405 DELAY(5); 406 v = CSR_READ_4(sc, ALC_MDIO); 407 if ((v & MDIO_OP_BUSY) == 0) 408 break; 409 } 410 411 if (i == 0) { 412 printf("%s: phy ext read timeout: %d\n", 413 device_xname(sc->sc_dev), reg); 414 return (0); 415 } 416 417 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 418 } 419 420 static uint32_t 421 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 422 { 423 uint32_t clk, v; 424 int i; 425 426 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 427 EXT_MDIO_DEVADDR(devaddr)); 428 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 429 clk = MDIO_CLK_25_128; 430 else 431 clk = MDIO_CLK_25_4; 432 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 433 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 434 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 435 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 436 DELAY(5); 437 v = CSR_READ_4(sc, ALC_MDIO); 438 if ((v & MDIO_OP_BUSY) == 0) 439 break; 440 } 441 442 if (i == 0) { 443 printf("%s: phy ext write timeout: reg %d\n", 444 device_xname(sc->sc_dev), reg); 445 return (0); 446 } 447 448 return (0); 449 } 450 451 static void 452 alc_dsp_fixup(struct alc_softc *sc, int media) 453 { 454 uint16_t agc, len, val; 455 456 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 457 return; 458 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 459 return; 460 461 /* 462 * Vendor PHY magic. 463 * 1000BT/AZ, wrong cable length 464 */ 465 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 466 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 467 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 468 EXT_CLDCTL6_CAB_LEN_MASK; 469 /* XXX: used to be (alc >> shift) & mask which is 0 */ 470 agc = alc_miidbg_readreg(sc, MII_DBG_AGC) & DBG_AGC_2_VGA_MASK; 471 agc >>= DBG_AGC_2_VGA_SHIFT; 472 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 473 agc > DBG_AGC_LONG1G_LIMT) || 474 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 475 agc > DBG_AGC_LONG1G_LIMT)) { 476 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 477 DBG_AZ_ANADECT_LONG); 478 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 479 MII_EXT_ANEG_AFE); 480 val |= ANEG_AFEE_10BT_100M_TH; 481 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 482 val); 483 } else { 484 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 485 DBG_AZ_ANADECT_DEFAULT); 486 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 487 MII_EXT_ANEG_AFE); 488 val &= ~ANEG_AFEE_10BT_100M_TH; 489 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 490 val); 491 } 492 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 493 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 494 if (media == IFM_1000_T) { 495 /* 496 * Giga link threshold, raise the tolerance of 497 * noise 50%. 498 */ 499 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 500 val &= ~DBG_MSE20DB_TH_MASK; 501 val |= (DBG_MSE20DB_TH_HI << 502 DBG_MSE20DB_TH_SHIFT); 503 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 504 } else if (media == IFM_100_TX) 505 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 506 DBG_MSE16DB_UP); 507 } 508 } else { 509 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 510 val &= ~ANEG_AFEE_10BT_100M_TH; 511 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 512 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 513 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 514 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 515 DBG_MSE16DB_DOWN); 516 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 517 val &= ~DBG_MSE20DB_TH_MASK; 518 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 519 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 520 } 521 } 522 } 523 524 static void 525 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 526 { 527 struct alc_softc *sc = ifp->if_softc; 528 struct mii_data *mii = &sc->sc_miibus; 529 530 mii_pollstat(mii); 531 ifmr->ifm_status = mii->mii_media_status; 532 ifmr->ifm_active = mii->mii_media_active; 533 } 534 535 static int 536 alc_mediachange(struct ifnet *ifp) 537 { 538 struct alc_softc *sc = ifp->if_softc; 539 struct mii_data *mii = &sc->sc_miibus; 540 int error; 541 542 if (mii->mii_instance != 0) { 543 struct mii_softc *miisc; 544 545 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 546 mii_phy_reset(miisc); 547 } 548 error = mii_mediachg(mii); 549 550 return (error); 551 } 552 553 static struct alc_ident * 554 alc_find_ident(struct pci_attach_args *pa) 555 { 556 struct alc_ident *ident; 557 uint16_t vendor, devid; 558 559 vendor = PCI_VENDOR(pa->pa_id); 560 devid = PCI_PRODUCT(pa->pa_id); 561 for (ident = alc_ident_table; ident->name != NULL; ident++) { 562 if (vendor == ident->vendorid && devid == ident->deviceid) 563 return (ident); 564 } 565 566 return (NULL); 567 } 568 569 static int 570 alc_match(device_t dev, cfdata_t match, void *aux) 571 { 572 struct pci_attach_args *pa = aux; 573 574 return alc_find_ident(pa) != NULL; 575 } 576 577 static void 578 alc_get_macaddr(struct alc_softc *sc) 579 { 580 581 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 582 alc_get_macaddr_816x(sc); 583 else 584 alc_get_macaddr_813x(sc); 585 } 586 587 static void 588 alc_get_macaddr_813x(struct alc_softc *sc) 589 { 590 uint32_t opt; 591 uint16_t val; 592 int eeprom, i; 593 594 eeprom = 0; 595 opt = CSR_READ_4(sc, ALC_OPT_CFG); 596 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 597 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 598 /* 599 * EEPROM found, let TWSI reload EEPROM configuration. 600 * This will set ethernet address of controller. 601 */ 602 eeprom++; 603 switch (sc->alc_ident->deviceid) { 604 case PCI_PRODUCT_ATTANSIC_AR8131: 605 case PCI_PRODUCT_ATTANSIC_AR8132: 606 if ((opt & OPT_CFG_CLK_ENB) == 0) { 607 opt |= OPT_CFG_CLK_ENB; 608 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 609 CSR_READ_4(sc, ALC_OPT_CFG); 610 DELAY(1000); 611 } 612 break; 613 case PCI_PRODUCT_ATTANSIC_AR8151: 614 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 615 case PCI_PRODUCT_ATTANSIC_AR8152_B: 616 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 617 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 618 ALC_MII_DBG_ADDR, 0x00); 619 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 620 ALC_MII_DBG_DATA); 621 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 622 ALC_MII_DBG_DATA, val & 0xFF7F); 623 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 624 ALC_MII_DBG_ADDR, 0x3B); 625 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 626 ALC_MII_DBG_DATA); 627 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 628 ALC_MII_DBG_DATA, val | 0x0008); 629 DELAY(20); 630 break; 631 } 632 633 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 634 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 635 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 636 CSR_READ_4(sc, ALC_WOL_CFG); 637 638 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 639 TWSI_CFG_SW_LD_START); 640 for (i = 100; i > 0; i--) { 641 DELAY(1000); 642 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 643 TWSI_CFG_SW_LD_START) == 0) 644 break; 645 } 646 if (i == 0) 647 printf("%s: reloading EEPROM timeout!\n", 648 device_xname(sc->sc_dev)); 649 } else { 650 if (alcdebug) 651 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 652 } 653 if (eeprom != 0) { 654 switch (sc->alc_ident->deviceid) { 655 case PCI_PRODUCT_ATTANSIC_AR8131: 656 case PCI_PRODUCT_ATTANSIC_AR8132: 657 if ((opt & OPT_CFG_CLK_ENB) != 0) { 658 opt &= ~OPT_CFG_CLK_ENB; 659 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 660 CSR_READ_4(sc, ALC_OPT_CFG); 661 DELAY(1000); 662 } 663 break; 664 case PCI_PRODUCT_ATTANSIC_AR8151: 665 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 666 case PCI_PRODUCT_ATTANSIC_AR8152_B: 667 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 668 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 669 ALC_MII_DBG_ADDR, 0x00); 670 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 671 ALC_MII_DBG_DATA); 672 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 673 ALC_MII_DBG_DATA, val | 0x0080); 674 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 675 ALC_MII_DBG_ADDR, 0x3B); 676 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 677 ALC_MII_DBG_DATA); 678 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 679 ALC_MII_DBG_DATA, val & 0xFFF7); 680 DELAY(20); 681 break; 682 } 683 } 684 685 alc_get_macaddr_par(sc); 686 } 687 688 static void 689 alc_get_macaddr_816x(struct alc_softc *sc) 690 { 691 uint32_t reg; 692 int i, reloaded; 693 694 reloaded = 0; 695 /* Try to reload station address via TWSI. */ 696 for (i = 100; i > 0; i--) { 697 reg = CSR_READ_4(sc, ALC_SLD); 698 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 699 break; 700 DELAY(1000); 701 } 702 if (i != 0) { 703 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 704 for (i = 100; i > 0; i--) { 705 DELAY(1000); 706 reg = CSR_READ_4(sc, ALC_SLD); 707 if ((reg & SLD_START) == 0) 708 break; 709 } 710 if (i != 0) 711 reloaded++; 712 else if (alcdebug) 713 printf("%s: reloading station address via TWSI timed out!\n", 714 device_xname(sc->sc_dev)); 715 } 716 717 /* Try to reload station address from EEPROM or FLASH. */ 718 if (reloaded == 0) { 719 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 720 if ((reg & (EEPROM_LD_EEPROM_EXIST | 721 EEPROM_LD_FLASH_EXIST)) != 0) { 722 for (i = 100; i > 0; i--) { 723 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 724 if ((reg & (EEPROM_LD_PROGRESS | 725 EEPROM_LD_START)) == 0) 726 break; 727 DELAY(1000); 728 } 729 if (i != 0) { 730 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 731 EEPROM_LD_START); 732 for (i = 100; i > 0; i--) { 733 DELAY(1000); 734 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 735 if ((reg & EEPROM_LD_START) == 0) 736 break; 737 } 738 } else if (alcdebug) 739 printf("%s: reloading EEPROM/FLASH timed out!\n", 740 device_xname(sc->sc_dev)); 741 } 742 } 743 744 alc_get_macaddr_par(sc); 745 } 746 747 748 static void 749 alc_get_macaddr_par(struct alc_softc *sc) 750 { 751 uint32_t ea[2]; 752 753 ea[0] = CSR_READ_4(sc, ALC_PAR0); 754 ea[1] = CSR_READ_4(sc, ALC_PAR1); 755 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 756 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 757 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 758 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 759 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 760 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 761 } 762 763 static void 764 alc_disable_l0s_l1(struct alc_softc *sc) 765 { 766 uint32_t pmcfg; 767 768 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 769 /* Another magic from vendor. */ 770 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 771 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 772 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 773 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 774 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 775 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 776 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 777 } 778 } 779 780 static void 781 alc_phy_reset(struct alc_softc *sc) 782 { 783 784 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 785 alc_phy_reset_816x(sc); 786 else 787 alc_phy_reset_813x(sc); 788 } 789 790 static void 791 alc_phy_reset_813x(struct alc_softc *sc) 792 { 793 uint16_t data; 794 795 /* Reset magic from Linux. */ 796 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 797 CSR_READ_2(sc, ALC_GPHY_CFG); 798 DELAY(10 * 1000); 799 800 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 801 GPHY_CFG_SEL_ANA_RESET); 802 CSR_READ_2(sc, ALC_GPHY_CFG); 803 DELAY(10 * 1000); 804 805 /* DSP fixup, Vendor magic. */ 806 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 807 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 808 ALC_MII_DBG_ADDR, 0x000A); 809 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 810 ALC_MII_DBG_DATA); 811 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 812 ALC_MII_DBG_DATA, data & 0xDFFF); 813 } 814 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 815 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 816 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 817 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 818 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 819 ALC_MII_DBG_ADDR, 0x003B); 820 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 821 ALC_MII_DBG_DATA); 822 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 823 ALC_MII_DBG_DATA, data & 0xFFF7); 824 DELAY(20 * 1000); 825 } 826 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 827 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 828 ALC_MII_DBG_ADDR, 0x0029); 829 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 830 ALC_MII_DBG_DATA, 0x929D); 831 } 832 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 833 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 834 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 835 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 836 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 837 ALC_MII_DBG_ADDR, 0x0029); 838 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 839 ALC_MII_DBG_DATA, 0xB6DD); 840 } 841 842 /* Load DSP codes, vendor magic. */ 843 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 844 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 845 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 846 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 847 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 848 ALC_MII_DBG_DATA, data); 849 850 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 851 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 852 ANA_SERDES_EN_LCKDT; 853 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 854 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 855 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 856 ALC_MII_DBG_DATA, data); 857 858 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 859 ANA_LONG_CABLE_TH_100_MASK) | 860 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 861 ANA_SHORT_CABLE_TH_100_SHIFT) | 862 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 863 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 864 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 865 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 866 ALC_MII_DBG_DATA, data); 867 868 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 869 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 870 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 871 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 872 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 873 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 874 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 875 ALC_MII_DBG_DATA, data); 876 877 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 878 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 879 ANA_OEN_125M; 880 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 881 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 882 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 883 ALC_MII_DBG_DATA, data); 884 DELAY(1000); 885 886 /* Disable hibernation. */ 887 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 888 0x0029); 889 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 890 ALC_MII_DBG_DATA); 891 data &= ~0x8000; 892 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 893 data); 894 895 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 896 0x000B); 897 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 898 ALC_MII_DBG_DATA); 899 data &= ~0x8000; 900 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 901 data); 902 } 903 904 static void 905 alc_phy_reset_816x(struct alc_softc *sc) 906 { 907 uint32_t val; 908 909 val = CSR_READ_4(sc, ALC_GPHY_CFG); 910 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 911 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 912 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 913 val |= GPHY_CFG_SEL_ANA_RESET; 914 #ifdef notyet 915 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 916 #else 917 /* Disable PHY hibernation. */ 918 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 919 #endif 920 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 921 DELAY(10); 922 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 923 DELAY(800); 924 925 /* Vendor PHY magic. */ 926 #ifdef notyet 927 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 928 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 929 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 930 EXT_VDRVBIAS_DEFAULT); 931 #else 932 /* Disable PHY hibernation. */ 933 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 934 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 935 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 936 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 937 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 938 #endif 939 940 /* XXX Disable EEE. */ 941 val = CSR_READ_4(sc, ALC_LPI_CTL); 942 val &= ~LPI_CTL_ENB; 943 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 944 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 945 946 /* PHY power saving. */ 947 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 948 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 949 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 950 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 951 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 952 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 953 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 954 955 /* RTL8139C, 120m issue. */ 956 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 957 ANEG_NLP78_120M_DEFAULT); 958 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 959 ANEG_S3DIG10_DEFAULT); 960 961 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 962 /* Turn off half amplitude. */ 963 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 964 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 965 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 966 /* Turn off Green feature. */ 967 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 968 val |= DBG_GREENCFG2_BP_GREEN; 969 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 970 /* Turn off half bias. */ 971 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 972 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 973 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 974 } 975 } 976 977 static void 978 alc_phy_down(struct alc_softc *sc) 979 { 980 uint32_t gphy; 981 982 switch (sc->alc_ident->deviceid) { 983 case PCI_PRODUCT_ATTANSIC_AR8161: 984 case PCI_PRODUCT_ATTANSIC_E2200: 985 case PCI_PRODUCT_ATTANSIC_AR8162: 986 case PCI_PRODUCT_ATTANSIC_AR8171: 987 case PCI_PRODUCT_ATTANSIC_AR8172: 988 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 989 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 990 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 991 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 992 GPHY_CFG_SEL_ANA_RESET; 993 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 994 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 995 break; 996 case PCI_PRODUCT_ATTANSIC_AR8151: 997 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 998 case PCI_PRODUCT_ATTANSIC_AR8152_B: 999 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1000 /* 1001 * GPHY power down caused more problems on AR8151 v2.0. 1002 * When driver is reloaded after GPHY power down, 1003 * accesses to PHY/MAC registers hung the system. Only 1004 * cold boot recovered from it. I'm not sure whether 1005 * AR8151 v1.0 also requires this one though. I don't 1006 * have AR8151 v1.0 controller in hand. 1007 * The only option left is to isolate the PHY and 1008 * initiates power down the PHY which in turn saves 1009 * more power when driver is unloaded. 1010 */ 1011 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 1012 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1013 break; 1014 default: 1015 /* Force PHY down. */ 1016 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1017 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1018 GPHY_CFG_PWDOWN_HW); 1019 DELAY(1000); 1020 break; 1021 } 1022 } 1023 1024 static void 1025 alc_aspm(struct alc_softc *sc, int init, int media) 1026 { 1027 1028 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1029 alc_aspm_816x(sc, init); 1030 else 1031 alc_aspm_813x(sc, media); 1032 } 1033 1034 static void 1035 alc_aspm_813x(struct alc_softc *sc, int media) 1036 { 1037 uint32_t pmcfg; 1038 uint16_t linkcfg; 1039 1040 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1041 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1042 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1043 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1044 PCIE_LCSR); 1045 else 1046 linkcfg = 0; 1047 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1048 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1049 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1050 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1051 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1052 1053 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1054 /* Disable extended sync except AR8152 B v1.0 */ 1055 linkcfg &= ~0x80; 1056 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1057 sc->alc_rev == ATHEROS_AR8152_B_V10) 1058 linkcfg |= 0x80; 1059 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 1060 linkcfg); 1061 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1062 PM_CFG_HOTRST); 1063 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1064 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1065 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1066 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1067 PM_CFG_PM_REQ_TIMER_SHIFT); 1068 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1069 } 1070 1071 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1072 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1073 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1074 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1075 pmcfg |= PM_CFG_ASPM_L1_ENB; 1076 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1077 if (sc->alc_ident->deviceid == 1078 PCI_PRODUCT_ATTANSIC_AR8152_B) 1079 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1080 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1081 PM_CFG_SERDES_PLL_L1_ENB | 1082 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1083 pmcfg |= PM_CFG_CLK_SWH_L1; 1084 if (media == IFM_100_TX || media == IFM_1000_T) { 1085 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1086 switch (sc->alc_ident->deviceid) { 1087 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1088 pmcfg |= (7 << 1089 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1090 break; 1091 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1092 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1093 pmcfg |= (4 << 1094 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1095 break; 1096 default: 1097 pmcfg |= (15 << 1098 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1099 break; 1100 } 1101 } 1102 } else { 1103 pmcfg |= PM_CFG_SERDES_L1_ENB | 1104 PM_CFG_SERDES_PLL_L1_ENB | 1105 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1106 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1107 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1108 } 1109 } else { 1110 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1111 PM_CFG_SERDES_PLL_L1_ENB); 1112 pmcfg |= PM_CFG_CLK_SWH_L1; 1113 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1114 pmcfg |= PM_CFG_ASPM_L1_ENB; 1115 } 1116 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1117 } 1118 1119 static void 1120 alc_aspm_816x(struct alc_softc *sc, int init) 1121 { 1122 uint32_t pmcfg; 1123 1124 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1125 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1126 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1127 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1128 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1129 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1130 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1131 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1132 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1133 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1134 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1135 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1136 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1137 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1138 (sc->alc_rev & 0x01) != 0) 1139 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1140 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1141 /* Link up, enable both L0s, L1s. */ 1142 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1143 PM_CFG_MAC_ASPM_CHK; 1144 } else { 1145 if (init != 0) 1146 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1147 PM_CFG_MAC_ASPM_CHK; 1148 else if ((sc->sc_ec.ec_if.if_flags & IFF_RUNNING) != 0) 1149 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1150 } 1151 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1152 } 1153 1154 static void 1155 alc_attach(device_t parent, device_t self, void *aux) 1156 { 1157 1158 struct alc_softc *sc = device_private(self); 1159 struct pci_attach_args *pa = aux; 1160 pci_chipset_tag_t pc = pa->pa_pc; 1161 pci_intr_handle_t ih; 1162 const char *intrstr; 1163 struct ifnet *ifp; 1164 pcireg_t memtype; 1165 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1166 uint16_t burst; 1167 int base, mii_flags, state, error = 0; 1168 uint32_t cap, ctl, val; 1169 char intrbuf[PCI_INTRSTR_LEN]; 1170 1171 sc->alc_ident = alc_find_ident(pa); 1172 1173 aprint_naive("\n"); 1174 aprint_normal(": %s\n", sc->alc_ident->name); 1175 1176 sc->sc_dev = self; 1177 sc->sc_dmat = pa->pa_dmat; 1178 sc->sc_pct = pa->pa_pc; 1179 sc->sc_pcitag = pa->pa_tag; 1180 1181 /* 1182 * Allocate IO memory 1183 */ 1184 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 1185 switch (memtype) { 1186 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1187 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 1188 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1189 break; 1190 default: 1191 aprint_error_dev(self, "invalid base address register\n"); 1192 break; 1193 } 1194 1195 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 1196 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 1197 aprint_error_dev(self, "could not map mem space\n"); 1198 return; 1199 } 1200 1201 if (pci_intr_map(pa, &ih) != 0) { 1202 printf(": can't map interrupt\n"); 1203 goto fail; 1204 } 1205 1206 /* 1207 * Allocate IRQ 1208 */ 1209 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 1210 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc); 1211 if (sc->sc_irq_handle == NULL) { 1212 printf(": could not establish interrupt"); 1213 if (intrstr != NULL) 1214 printf(" at %s", intrstr); 1215 printf("\n"); 1216 goto fail; 1217 } 1218 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1219 1220 /* Set PHY address. */ 1221 sc->alc_phyaddr = ALC_PHY_ADDR; 1222 1223 /* Initialize DMA parameters. */ 1224 sc->alc_dma_rd_burst = 0; 1225 sc->alc_dma_wr_burst = 0; 1226 sc->alc_rcb = DMA_CFG_RCB_64; 1227 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 1228 &base, NULL)) { 1229 sc->alc_flags |= ALC_FLAG_PCIE; 1230 sc->alc_expcap = base; 1231 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1232 base + PCIE_DCSR) >> 16; 1233 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 1234 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 1235 if (alcdebug) { 1236 printf("%s: Read request size : %u bytes.\n", 1237 device_xname(sc->sc_dev), 1238 alc_dma_burst[sc->alc_dma_rd_burst]); 1239 printf("%s: TLP payload size : %u bytes.\n", 1240 device_xname(sc->sc_dev), 1241 alc_dma_burst[sc->alc_dma_wr_burst]); 1242 } 1243 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1244 sc->alc_dma_rd_burst = 3; 1245 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1246 sc->alc_dma_wr_burst = 3; 1247 1248 /* Clear data link and flow-control protocol error. */ 1249 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1250 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1251 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1252 1253 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1254 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1255 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1256 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1257 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1258 PCIE_PHYMISC_FORCE_RCV_DET); 1259 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 1260 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1261 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1262 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1263 PCIE_PHYMISC2_SERDES_TH_MASK); 1264 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1265 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1266 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1267 } 1268 /* Disable ASPM L0S and L1. */ 1269 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1270 base + PCIE_LCAP) >> 16; 1271 if ((cap & 0x00000c00) != 0) { 1272 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 1273 base + PCIE_LCSR) >> 16; 1274 if ((ctl & 0x08) != 0) 1275 sc->alc_rcb = DMA_CFG_RCB_128; 1276 if (alcdebug) 1277 printf("%s: RCB %u bytes\n", 1278 device_xname(sc->sc_dev), 1279 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1280 state = ctl & 0x03; 1281 if (state & 0x01) 1282 sc->alc_flags |= ALC_FLAG_L0S; 1283 if (state & 0x02) 1284 sc->alc_flags |= ALC_FLAG_L1S; 1285 if (alcdebug) 1286 printf("%s: ASPM %s %s\n", 1287 device_xname(sc->sc_dev), 1288 aspm_state[state], 1289 state == 0 ? "disabled" : "enabled"); 1290 alc_disable_l0s_l1(sc); 1291 } else { 1292 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 1293 } 1294 } else { 1295 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1296 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1297 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1298 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1299 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1300 (sc->alc_rev & 0x01) != 0) { 1301 if ((val & MASTER_WAKEN_25M) == 0 || 1302 (val & MASTER_CLK_SEL_DIS) == 0) { 1303 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1304 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1305 } 1306 } else { 1307 if ((val & MASTER_WAKEN_25M) == 0 || 1308 (val & MASTER_CLK_SEL_DIS) != 0) { 1309 val |= MASTER_WAKEN_25M; 1310 val &= ~MASTER_CLK_SEL_DIS; 1311 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1312 } 1313 } 1314 } 1315 alc_aspm(sc, 1, IFM_UNKNOWN); 1316 } 1317 1318 /* Reset PHY. */ 1319 alc_phy_reset(sc); 1320 1321 /* Reset the ethernet controller. */ 1322 alc_stop_mac(sc); 1323 alc_reset(sc); 1324 1325 /* 1326 * One odd thing is AR8132 uses the same PHY hardware(F1 1327 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1328 * the PHY supports 1000Mbps but that's not true. The PHY 1329 * used in AR8132 can't establish gigabit link even if it 1330 * shows the same PHY model/revision number of AR8131. 1331 */ 1332 switch (sc->alc_ident->deviceid) { 1333 case PCI_PRODUCT_ATTANSIC_AR8161: 1334 if (PCI_SUBSYS_ID(pci_conf_read( 1335 sc->sc_pct, sc->sc_pcitag, PCI_SUBSYS_ID_REG)) == 0x0091 && 1336 sc->alc_rev == 0) 1337 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1338 /* FALLTHROUGH */ 1339 case PCI_PRODUCT_ATTANSIC_E2200: 1340 case PCI_PRODUCT_ATTANSIC_AR8171: 1341 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1342 break; 1343 case PCI_PRODUCT_ATTANSIC_AR8162: 1344 case PCI_PRODUCT_ATTANSIC_AR8172: 1345 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1346 break; 1347 case PCI_PRODUCT_ATTANSIC_AR8152_B: 1348 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 1349 sc->alc_flags |= ALC_FLAG_APS; 1350 /* FALLTHROUGH */ 1351 case PCI_PRODUCT_ATTANSIC_AR8132: 1352 sc->alc_flags |= ALC_FLAG_FASTETHER; 1353 break; 1354 case PCI_PRODUCT_ATTANSIC_AR8151: 1355 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 1356 sc->alc_flags |= ALC_FLAG_APS; 1357 /* FALLTHROUGH */ 1358 default: 1359 break; 1360 } 1361 sc->alc_flags |= ALC_FLAG_JUMBO; 1362 1363 /* 1364 * It seems that AR813x/AR815x has silicon bug for SMB. In 1365 * addition, Atheros said that enabling SMB wouldn't improve 1366 * performance. However I think it's bad to access lots of 1367 * registers to extract MAC statistics. 1368 */ 1369 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1370 /* 1371 * Don't use Tx CMB. It is known to have silicon bug. 1372 */ 1373 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1374 sc->alc_rev = PCI_REVISION(pa->pa_class); 1375 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1376 MASTER_CHIP_REV_SHIFT; 1377 if (alcdebug) { 1378 printf("%s: PCI device revision : 0x%04x\n", 1379 device_xname(sc->sc_dev), sc->alc_rev); 1380 printf("%s: Chip id/revision : 0x%04x\n", 1381 device_xname(sc->sc_dev), sc->alc_chip_rev); 1382 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 1383 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1384 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1385 } 1386 1387 error = alc_dma_alloc(sc); 1388 if (error) 1389 goto fail; 1390 1391 callout_init(&sc->sc_tick_ch, 0); 1392 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 1393 1394 /* Load station address. */ 1395 alc_get_macaddr(sc); 1396 1397 aprint_normal_dev(self, "Ethernet address %s\n", 1398 ether_sprintf(sc->alc_eaddr)); 1399 1400 ifp = &sc->sc_ec.ec_if; 1401 ifp->if_softc = sc; 1402 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1403 ifp->if_init = alc_init; 1404 ifp->if_ioctl = alc_ioctl; 1405 ifp->if_start = alc_start; 1406 ifp->if_stop = alc_stop; 1407 ifp->if_watchdog = alc_watchdog; 1408 ifp->if_baudrate = IF_Gbps(1); 1409 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1410 IFQ_SET_READY(&ifp->if_snd); 1411 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1412 1413 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1414 1415 #ifdef ALC_CHECKSUM 1416 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1417 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1418 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 1419 #endif 1420 1421 #if NVLAN > 0 1422 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 1423 #endif 1424 1425 /* 1426 * XXX 1427 * It seems enabling Tx checksum offloading makes more trouble. 1428 * Sometimes the controller does not receive any frames when 1429 * Tx checksum offloading is enabled. I'm not sure whether this 1430 * is a bug in Tx checksum offloading logic or I got broken 1431 * sample boards. To safety, don't enable Tx checksum offloading 1432 * by default but give chance to users to toggle it if they know 1433 * their controllers work without problems. 1434 * Fortunately, Tx checksum offloading for AR816x family 1435 * seems to work. 1436 */ 1437 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1438 ifp->if_capenable &= ~IFCAP_CSUM_IPv4_Tx; 1439 ifp->if_capabilities &= ~ALC_CSUM_FEATURES; 1440 } 1441 1442 /* Set up MII bus. */ 1443 sc->sc_miibus.mii_ifp = ifp; 1444 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 1445 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 1446 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 1447 1448 sc->sc_ec.ec_mii = &sc->sc_miibus; 1449 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 1450 alc_mediastatus); 1451 mii_flags = 0; 1452 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 1453 mii_flags |= MIIF_DOPAUSE; 1454 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 1455 MII_OFFSET_ANY, mii_flags); 1456 1457 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 1458 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 1459 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 1460 0, NULL); 1461 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 1462 } else 1463 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 1464 1465 if_attach(ifp); 1466 ether_ifattach(ifp, sc->alc_eaddr); 1467 1468 if (!pmf_device_register(self, NULL, NULL)) 1469 aprint_error_dev(self, "couldn't establish power handler\n"); 1470 else 1471 pmf_class_network_register(self, ifp); 1472 1473 return; 1474 fail: 1475 alc_dma_free(sc); 1476 if (sc->sc_irq_handle != NULL) { 1477 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1478 sc->sc_irq_handle = NULL; 1479 } 1480 if (sc->sc_mem_size) { 1481 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1482 sc->sc_mem_size = 0; 1483 } 1484 } 1485 1486 static int 1487 alc_detach(device_t self, int flags) 1488 { 1489 struct alc_softc *sc = device_private(self); 1490 struct ifnet *ifp = &sc->sc_ec.ec_if; 1491 int s; 1492 1493 s = splnet(); 1494 alc_stop(ifp, 0); 1495 splx(s); 1496 1497 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 1498 1499 /* Delete all remaining media. */ 1500 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 1501 1502 ether_ifdetach(ifp); 1503 if_detach(ifp); 1504 alc_dma_free(sc); 1505 1506 alc_phy_down(sc); 1507 if (sc->sc_irq_handle != NULL) { 1508 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 1509 sc->sc_irq_handle = NULL; 1510 } 1511 if (sc->sc_mem_size) { 1512 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 1513 sc->sc_mem_size = 0; 1514 } 1515 1516 return (0); 1517 } 1518 1519 static int 1520 alc_dma_alloc(struct alc_softc *sc) 1521 { 1522 struct alc_txdesc *txd; 1523 struct alc_rxdesc *rxd; 1524 int nsegs, error, i; 1525 1526 /* 1527 * Create DMA stuffs for TX ring 1528 */ 1529 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 1530 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 1531 if (error) { 1532 sc->alc_cdata.alc_tx_ring_map = NULL; 1533 return (ENOBUFS); 1534 } 1535 1536 /* Allocate DMA'able memory for TX ring */ 1537 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 1538 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 1539 &nsegs, BUS_DMA_NOWAIT); 1540 if (error) { 1541 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 1542 device_xname(sc->sc_dev)); 1543 return error; 1544 } 1545 1546 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 1547 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 1548 BUS_DMA_NOWAIT); 1549 if (error) 1550 return (ENOBUFS); 1551 1552 /* Load the DMA map for Tx ring. */ 1553 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 1554 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 1555 if (error) { 1556 printf("%s: could not load DMA'able memory for Tx ring.\n", 1557 device_xname(sc->sc_dev)); 1558 bus_dmamem_free(sc->sc_dmat, 1559 &sc->alc_rdata.alc_tx_ring_seg, 1); 1560 return error; 1561 } 1562 1563 sc->alc_rdata.alc_tx_ring_paddr = 1564 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 1565 1566 /* 1567 * Create DMA stuffs for RX ring 1568 */ 1569 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1570 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1571 if (error) 1572 return (ENOBUFS); 1573 1574 /* Allocate DMA'able memory for RX ring */ 1575 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1576 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1577 &nsegs, BUS_DMA_NOWAIT); 1578 if (error) { 1579 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1580 device_xname(sc->sc_dev)); 1581 return error; 1582 } 1583 1584 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1585 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1586 BUS_DMA_NOWAIT); 1587 if (error) 1588 return (ENOBUFS); 1589 1590 /* Load the DMA map for Rx ring. */ 1591 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1592 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1593 if (error) { 1594 printf("%s: could not load DMA'able memory for Rx ring.\n", 1595 device_xname(sc->sc_dev)); 1596 bus_dmamem_free(sc->sc_dmat, 1597 &sc->alc_rdata.alc_rx_ring_seg, 1); 1598 return error; 1599 } 1600 1601 sc->alc_rdata.alc_rx_ring_paddr = 1602 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1603 1604 /* 1605 * Create DMA stuffs for RX return ring 1606 */ 1607 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1608 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1609 if (error) 1610 return (ENOBUFS); 1611 1612 /* Allocate DMA'able memory for RX return ring */ 1613 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1614 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1615 &nsegs, BUS_DMA_NOWAIT); 1616 if (error) { 1617 printf("%s: could not allocate DMA'able memory for Rx " 1618 "return ring.\n", device_xname(sc->sc_dev)); 1619 return error; 1620 } 1621 1622 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1623 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1624 BUS_DMA_NOWAIT); 1625 if (error) 1626 return (ENOBUFS); 1627 1628 /* Load the DMA map for Rx return ring. */ 1629 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1630 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1631 if (error) { 1632 printf("%s: could not load DMA'able memory for Rx return ring." 1633 "\n", device_xname(sc->sc_dev)); 1634 bus_dmamem_free(sc->sc_dmat, 1635 &sc->alc_rdata.alc_rr_ring_seg, 1); 1636 return error; 1637 } 1638 1639 sc->alc_rdata.alc_rr_ring_paddr = 1640 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1641 1642 /* 1643 * Create DMA stuffs for CMB block 1644 */ 1645 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1646 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1647 &sc->alc_cdata.alc_cmb_map); 1648 if (error) 1649 return (ENOBUFS); 1650 1651 /* Allocate DMA'able memory for CMB block */ 1652 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1653 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1654 &nsegs, BUS_DMA_NOWAIT); 1655 if (error) { 1656 printf("%s: could not allocate DMA'able memory for " 1657 "CMB block\n", device_xname(sc->sc_dev)); 1658 return error; 1659 } 1660 1661 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1662 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1663 BUS_DMA_NOWAIT); 1664 if (error) 1665 return (ENOBUFS); 1666 1667 /* Load the DMA map for CMB block. */ 1668 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1669 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1670 BUS_DMA_WAITOK); 1671 if (error) { 1672 printf("%s: could not load DMA'able memory for CMB block\n", 1673 device_xname(sc->sc_dev)); 1674 bus_dmamem_free(sc->sc_dmat, 1675 &sc->alc_rdata.alc_cmb_seg, 1); 1676 return error; 1677 } 1678 1679 sc->alc_rdata.alc_cmb_paddr = 1680 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1681 1682 /* 1683 * Create DMA stuffs for SMB block 1684 */ 1685 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1686 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1687 &sc->alc_cdata.alc_smb_map); 1688 if (error) 1689 return (ENOBUFS); 1690 1691 /* Allocate DMA'able memory for SMB block */ 1692 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1693 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1694 &nsegs, BUS_DMA_NOWAIT); 1695 if (error) { 1696 printf("%s: could not allocate DMA'able memory for " 1697 "SMB block\n", device_xname(sc->sc_dev)); 1698 return error; 1699 } 1700 1701 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1702 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1703 BUS_DMA_NOWAIT); 1704 if (error) 1705 return (ENOBUFS); 1706 1707 /* Load the DMA map for SMB block */ 1708 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1709 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1710 BUS_DMA_WAITOK); 1711 if (error) { 1712 printf("%s: could not load DMA'able memory for SMB block\n", 1713 device_xname(sc->sc_dev)); 1714 bus_dmamem_free(sc->sc_dmat, 1715 &sc->alc_rdata.alc_smb_seg, 1); 1716 return error; 1717 } 1718 1719 sc->alc_rdata.alc_smb_paddr = 1720 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1721 1722 1723 /* Create DMA maps for Tx buffers. */ 1724 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1725 txd = &sc->alc_cdata.alc_txdesc[i]; 1726 txd->tx_m = NULL; 1727 txd->tx_dmamap = NULL; 1728 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1729 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1730 &txd->tx_dmamap); 1731 if (error) { 1732 printf("%s: could not create Tx dmamap.\n", 1733 device_xname(sc->sc_dev)); 1734 return error; 1735 } 1736 } 1737 1738 /* Create DMA maps for Rx buffers. */ 1739 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1740 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1741 if (error) { 1742 printf("%s: could not create spare Rx dmamap.\n", 1743 device_xname(sc->sc_dev)); 1744 return error; 1745 } 1746 1747 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1748 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1749 rxd->rx_m = NULL; 1750 rxd->rx_dmamap = NULL; 1751 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1752 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1753 if (error) { 1754 printf("%s: could not create Rx dmamap.\n", 1755 device_xname(sc->sc_dev)); 1756 return error; 1757 } 1758 } 1759 1760 return (0); 1761 } 1762 1763 1764 static void 1765 alc_dma_free(struct alc_softc *sc) 1766 { 1767 struct alc_txdesc *txd; 1768 struct alc_rxdesc *rxd; 1769 int i; 1770 1771 /* Tx buffers */ 1772 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1773 txd = &sc->alc_cdata.alc_txdesc[i]; 1774 if (txd->tx_dmamap != NULL) { 1775 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1776 txd->tx_dmamap = NULL; 1777 } 1778 } 1779 /* Rx buffers */ 1780 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1781 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1782 if (rxd->rx_dmamap != NULL) { 1783 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1784 rxd->rx_dmamap = NULL; 1785 } 1786 } 1787 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1788 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1789 sc->alc_cdata.alc_rx_sparemap = NULL; 1790 } 1791 1792 /* Tx ring. */ 1793 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1794 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1795 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1796 sc->alc_rdata.alc_tx_ring != NULL) 1797 bus_dmamem_free(sc->sc_dmat, 1798 &sc->alc_rdata.alc_tx_ring_seg, 1); 1799 sc->alc_rdata.alc_tx_ring = NULL; 1800 sc->alc_cdata.alc_tx_ring_map = NULL; 1801 1802 /* Rx ring. */ 1803 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1804 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1805 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1806 sc->alc_rdata.alc_rx_ring != NULL) 1807 bus_dmamem_free(sc->sc_dmat, 1808 &sc->alc_rdata.alc_rx_ring_seg, 1); 1809 sc->alc_rdata.alc_rx_ring = NULL; 1810 sc->alc_cdata.alc_rx_ring_map = NULL; 1811 1812 /* Rx return ring. */ 1813 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1814 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1815 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1816 sc->alc_rdata.alc_rr_ring != NULL) 1817 bus_dmamem_free(sc->sc_dmat, 1818 &sc->alc_rdata.alc_rr_ring_seg, 1); 1819 sc->alc_rdata.alc_rr_ring = NULL; 1820 sc->alc_cdata.alc_rr_ring_map = NULL; 1821 1822 /* CMB block */ 1823 if (sc->alc_cdata.alc_cmb_map != NULL) 1824 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1825 if (sc->alc_cdata.alc_cmb_map != NULL && 1826 sc->alc_rdata.alc_cmb != NULL) 1827 bus_dmamem_free(sc->sc_dmat, 1828 &sc->alc_rdata.alc_cmb_seg, 1); 1829 sc->alc_rdata.alc_cmb = NULL; 1830 sc->alc_cdata.alc_cmb_map = NULL; 1831 1832 /* SMB block */ 1833 if (sc->alc_cdata.alc_smb_map != NULL) 1834 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1835 if (sc->alc_cdata.alc_smb_map != NULL && 1836 sc->alc_rdata.alc_smb != NULL) 1837 bus_dmamem_free(sc->sc_dmat, 1838 &sc->alc_rdata.alc_smb_seg, 1); 1839 sc->alc_rdata.alc_smb = NULL; 1840 sc->alc_cdata.alc_smb_map = NULL; 1841 } 1842 1843 static int 1844 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1845 { 1846 struct alc_txdesc *txd, *txd_last; 1847 struct tx_desc *desc; 1848 struct mbuf *m; 1849 bus_dmamap_t map; 1850 uint32_t cflags, poff, vtag; 1851 int error, idx, nsegs, prod; 1852 #if NVLAN > 0 1853 struct m_tag *mtag; 1854 #endif 1855 1856 m = *m_head; 1857 cflags = vtag = 0; 1858 poff = 0; 1859 1860 prod = sc->alc_cdata.alc_tx_prod; 1861 txd = &sc->alc_cdata.alc_txdesc[prod]; 1862 txd_last = txd; 1863 map = txd->tx_dmamap; 1864 1865 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1866 1867 if (error == EFBIG) { 1868 error = 0; 1869 1870 *m_head = m_pullup(*m_head, MHLEN); 1871 if (*m_head == NULL) { 1872 printf("%s: can't defrag TX mbuf\n", 1873 device_xname(sc->sc_dev)); 1874 return ENOBUFS; 1875 } 1876 1877 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1878 BUS_DMA_NOWAIT); 1879 1880 if (error != 0) { 1881 printf("%s: could not load defragged TX mbuf\n", 1882 device_xname(sc->sc_dev)); 1883 m_freem(*m_head); 1884 *m_head = NULL; 1885 return error; 1886 } 1887 } else if (error) { 1888 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1889 return (error); 1890 } 1891 1892 nsegs = map->dm_nsegs; 1893 1894 if (nsegs == 0) { 1895 m_freem(*m_head); 1896 *m_head = NULL; 1897 return (EIO); 1898 } 1899 1900 /* Check descriptor overrun. */ 1901 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1902 bus_dmamap_unload(sc->sc_dmat, map); 1903 return (ENOBUFS); 1904 } 1905 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1906 BUS_DMASYNC_PREWRITE); 1907 1908 m = *m_head; 1909 desc = NULL; 1910 idx = 0; 1911 #if NVLAN > 0 1912 /* Configure VLAN hardware tag insertion. */ 1913 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1914 vtag = htons(VLAN_TAG_VALUE(mtag)); 1915 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1916 cflags |= TD_INS_VLAN_TAG; 1917 } 1918 #endif 1919 /* Configure Tx checksum offload. */ 1920 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1921 cflags |= TD_CUSTOM_CSUM; 1922 /* Set checksum start offset. */ 1923 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1924 TD_PLOAD_OFFSET_MASK; 1925 } 1926 for (; idx < nsegs; idx++) { 1927 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1928 desc->len = 1929 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1930 desc->flags = htole32(cflags); 1931 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1932 sc->alc_cdata.alc_tx_cnt++; 1933 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1934 } 1935 /* Update producer index. */ 1936 sc->alc_cdata.alc_tx_prod = prod; 1937 1938 /* Finally set EOP on the last descriptor. */ 1939 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1940 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1941 desc->flags |= htole32(TD_EOP); 1942 1943 /* Swap dmamap of the first and the last. */ 1944 txd = &sc->alc_cdata.alc_txdesc[prod]; 1945 map = txd_last->tx_dmamap; 1946 txd_last->tx_dmamap = txd->tx_dmamap; 1947 txd->tx_dmamap = map; 1948 txd->tx_m = m; 1949 1950 return (0); 1951 } 1952 1953 static void 1954 alc_start(struct ifnet *ifp) 1955 { 1956 struct alc_softc *sc = ifp->if_softc; 1957 struct mbuf *m_head; 1958 int enq; 1959 1960 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1961 return; 1962 1963 /* Reclaim transmitted frames. */ 1964 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1965 alc_txeof(sc); 1966 1967 enq = 0; 1968 for (;;) { 1969 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1970 if (m_head == NULL) 1971 break; 1972 1973 /* 1974 * Pack the data into the transmit ring. If we 1975 * don't have room, set the OACTIVE flag and wait 1976 * for the NIC to drain the ring. 1977 */ 1978 if (alc_encap(sc, &m_head)) { 1979 if (m_head == NULL) 1980 break; 1981 ifp->if_flags |= IFF_OACTIVE; 1982 break; 1983 } 1984 enq = 1; 1985 1986 /* 1987 * If there's a BPF listener, bounce a copy of this frame 1988 * to him. 1989 */ 1990 bpf_mtap(ifp, m_head); 1991 } 1992 1993 if (enq) { 1994 /* Sync descriptors. */ 1995 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1996 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1997 BUS_DMASYNC_PREWRITE); 1998 /* Kick. Assume we're using normal Tx priority queue. */ 1999 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2000 (sc->alc_cdata.alc_tx_prod << 2001 MBOX_TD_PROD_LO_IDX_SHIFT) & 2002 MBOX_TD_PROD_LO_IDX_MASK); 2003 /* Set a timeout in case the chip goes out to lunch. */ 2004 ifp->if_timer = ALC_TX_TIMEOUT; 2005 } 2006 } 2007 2008 static void 2009 alc_watchdog(struct ifnet *ifp) 2010 { 2011 struct alc_softc *sc = ifp->if_softc; 2012 2013 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2014 printf("%s: watchdog timeout (missed link)\n", 2015 device_xname(sc->sc_dev)); 2016 ifp->if_oerrors++; 2017 alc_init_backend(ifp, false); 2018 return; 2019 } 2020 2021 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2022 ifp->if_oerrors++; 2023 alc_init_backend(ifp, false); 2024 2025 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2026 alc_start(ifp); 2027 } 2028 2029 static int 2030 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2031 { 2032 struct alc_softc *sc = ifp->if_softc; 2033 int s, error = 0; 2034 2035 s = splnet(); 2036 2037 error = ether_ioctl(ifp, cmd, data); 2038 if (error == ENETRESET) { 2039 if (ifp->if_flags & IFF_RUNNING) 2040 alc_iff(sc); 2041 error = 0; 2042 } 2043 2044 splx(s); 2045 return (error); 2046 } 2047 2048 static void 2049 alc_mac_config(struct alc_softc *sc) 2050 { 2051 struct mii_data *mii; 2052 uint32_t reg; 2053 2054 mii = &sc->sc_miibus; 2055 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2056 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2057 MAC_CFG_SPEED_MASK); 2058 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2059 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2060 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2061 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2062 /* Reprogram MAC with resolved speed/duplex. */ 2063 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2064 case IFM_10_T: 2065 case IFM_100_TX: 2066 reg |= MAC_CFG_SPEED_10_100; 2067 break; 2068 case IFM_1000_T: 2069 reg |= MAC_CFG_SPEED_1000; 2070 break; 2071 } 2072 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2073 reg |= MAC_CFG_FULL_DUPLEX; 2074 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2075 reg |= MAC_CFG_TX_FC; 2076 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2077 reg |= MAC_CFG_RX_FC; 2078 } 2079 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2080 } 2081 2082 static void 2083 alc_stats_clear(struct alc_softc *sc) 2084 { 2085 struct smb sb, *smb; 2086 uint32_t *reg; 2087 int i; 2088 2089 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2090 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2091 sc->alc_cdata.alc_smb_map->dm_mapsize, 2092 BUS_DMASYNC_POSTREAD); 2093 smb = sc->alc_rdata.alc_smb; 2094 /* Update done, clear. */ 2095 smb->updated = 0; 2096 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2097 sc->alc_cdata.alc_smb_map->dm_mapsize, 2098 BUS_DMASYNC_PREWRITE); 2099 } else { 2100 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2101 reg++) { 2102 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2103 i += sizeof(uint32_t); 2104 } 2105 /* Read Tx statistics. */ 2106 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2107 reg++) { 2108 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2109 i += sizeof(uint32_t); 2110 } 2111 } 2112 } 2113 2114 static void 2115 alc_stats_update(struct alc_softc *sc) 2116 { 2117 struct ifnet *ifp = &sc->sc_ec.ec_if; 2118 struct alc_hw_stats *stat; 2119 struct smb sb, *smb; 2120 uint32_t *reg; 2121 int i; 2122 2123 stat = &sc->alc_stats; 2124 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2125 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2126 sc->alc_cdata.alc_smb_map->dm_mapsize, 2127 BUS_DMASYNC_POSTREAD); 2128 smb = sc->alc_rdata.alc_smb; 2129 if (smb->updated == 0) 2130 return; 2131 } else { 2132 smb = &sb; 2133 /* Read Rx statistics. */ 2134 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2135 reg++) { 2136 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2137 i += sizeof(uint32_t); 2138 } 2139 /* Read Tx statistics. */ 2140 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2141 reg++) { 2142 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2143 i += sizeof(uint32_t); 2144 } 2145 } 2146 2147 /* Rx stats. */ 2148 stat->rx_frames += smb->rx_frames; 2149 stat->rx_bcast_frames += smb->rx_bcast_frames; 2150 stat->rx_mcast_frames += smb->rx_mcast_frames; 2151 stat->rx_pause_frames += smb->rx_pause_frames; 2152 stat->rx_control_frames += smb->rx_control_frames; 2153 stat->rx_crcerrs += smb->rx_crcerrs; 2154 stat->rx_lenerrs += smb->rx_lenerrs; 2155 stat->rx_bytes += smb->rx_bytes; 2156 stat->rx_runts += smb->rx_runts; 2157 stat->rx_fragments += smb->rx_fragments; 2158 stat->rx_pkts_64 += smb->rx_pkts_64; 2159 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2160 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2161 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2162 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2163 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2164 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2165 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2166 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2167 stat->rx_rrs_errs += smb->rx_rrs_errs; 2168 stat->rx_alignerrs += smb->rx_alignerrs; 2169 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2170 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2171 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2172 2173 /* Tx stats. */ 2174 stat->tx_frames += smb->tx_frames; 2175 stat->tx_bcast_frames += smb->tx_bcast_frames; 2176 stat->tx_mcast_frames += smb->tx_mcast_frames; 2177 stat->tx_pause_frames += smb->tx_pause_frames; 2178 stat->tx_excess_defer += smb->tx_excess_defer; 2179 stat->tx_control_frames += smb->tx_control_frames; 2180 stat->tx_deferred += smb->tx_deferred; 2181 stat->tx_bytes += smb->tx_bytes; 2182 stat->tx_pkts_64 += smb->tx_pkts_64; 2183 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2184 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2185 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2186 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2187 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2188 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2189 stat->tx_single_colls += smb->tx_single_colls; 2190 stat->tx_multi_colls += smb->tx_multi_colls; 2191 stat->tx_late_colls += smb->tx_late_colls; 2192 stat->tx_excess_colls += smb->tx_excess_colls; 2193 stat->tx_abort += smb->tx_abort; 2194 stat->tx_underrun += smb->tx_underrun; 2195 stat->tx_desc_underrun += smb->tx_desc_underrun; 2196 stat->tx_lenerrs += smb->tx_lenerrs; 2197 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2198 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2199 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2200 2201 /* Update counters in ifnet. */ 2202 ifp->if_opackets += smb->tx_frames; 2203 2204 ifp->if_collisions += smb->tx_single_colls + 2205 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2206 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2207 2208 /* 2209 * XXX 2210 * tx_pkts_truncated counter looks suspicious. It constantly 2211 * increments with no sign of Tx errors. This may indicate 2212 * the counter name is not correct one so I've removed the 2213 * counter in output errors. 2214 */ 2215 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2216 smb->tx_underrun; 2217 2218 ifp->if_ipackets += smb->rx_frames; 2219 2220 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2221 smb->rx_runts + smb->rx_pkts_truncated + 2222 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2223 smb->rx_alignerrs; 2224 2225 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2226 /* Update done, clear. */ 2227 smb->updated = 0; 2228 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2229 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2230 } 2231 } 2232 2233 static int 2234 alc_intr(void *arg) 2235 { 2236 struct alc_softc *sc = arg; 2237 struct ifnet *ifp = &sc->sc_ec.ec_if; 2238 uint32_t status; 2239 2240 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2241 if ((status & ALC_INTRS) == 0) 2242 return (0); 2243 2244 /* Acknowledge and disable interrupts. */ 2245 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2246 2247 if (ifp->if_flags & IFF_RUNNING) { 2248 if (status & INTR_RX_PKT) { 2249 int error; 2250 2251 error = alc_rxintr(sc); 2252 if (error) { 2253 alc_init_backend(ifp, false); 2254 return (0); 2255 } 2256 } 2257 2258 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2259 INTR_TXQ_TO_RST)) { 2260 if (status & INTR_DMA_RD_TO_RST) 2261 printf("%s: DMA read error! -- resetting\n", 2262 device_xname(sc->sc_dev)); 2263 if (status & INTR_DMA_WR_TO_RST) 2264 printf("%s: DMA write error! -- resetting\n", 2265 device_xname(sc->sc_dev)); 2266 if (status & INTR_TXQ_TO_RST) 2267 printf("%s: TxQ reset! -- resetting\n", 2268 device_xname(sc->sc_dev)); 2269 alc_init_backend(ifp, false); 2270 return (0); 2271 } 2272 2273 alc_txeof(sc); 2274 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2275 alc_start(ifp); 2276 } 2277 2278 /* Re-enable interrupts. */ 2279 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2280 return (1); 2281 } 2282 2283 static void 2284 alc_txeof(struct alc_softc *sc) 2285 { 2286 struct ifnet *ifp = &sc->sc_ec.ec_if; 2287 struct alc_txdesc *txd; 2288 uint32_t cons, prod; 2289 int prog; 2290 2291 if (sc->alc_cdata.alc_tx_cnt == 0) 2292 return; 2293 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2294 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 2295 BUS_DMASYNC_POSTREAD); 2296 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2297 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2298 sc->alc_cdata.alc_cmb_map->dm_mapsize, 2299 BUS_DMASYNC_POSTREAD); 2300 prod = sc->alc_rdata.alc_cmb->cons; 2301 } else 2302 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2303 /* Assume we're using normal Tx priority queue. */ 2304 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2305 MBOX_TD_CONS_LO_IDX_SHIFT; 2306 cons = sc->alc_cdata.alc_tx_cons; 2307 /* 2308 * Go through our Tx list and free mbufs for those 2309 * frames which have been transmitted. 2310 */ 2311 for (prog = 0; cons != prod; prog++, 2312 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2313 if (sc->alc_cdata.alc_tx_cnt <= 0) 2314 break; 2315 prog++; 2316 ifp->if_flags &= ~IFF_OACTIVE; 2317 sc->alc_cdata.alc_tx_cnt--; 2318 txd = &sc->alc_cdata.alc_txdesc[cons]; 2319 if (txd->tx_m != NULL) { 2320 /* Reclaim transmitted mbufs. */ 2321 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2322 m_freem(txd->tx_m); 2323 txd->tx_m = NULL; 2324 } 2325 } 2326 2327 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2328 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2329 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2330 sc->alc_cdata.alc_tx_cons = cons; 2331 /* 2332 * Unarm watchdog timer only when there is no pending 2333 * frames in Tx queue. 2334 */ 2335 if (sc->alc_cdata.alc_tx_cnt == 0) 2336 ifp->if_timer = 0; 2337 } 2338 2339 static int 2340 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 2341 { 2342 struct mbuf *m; 2343 bus_dmamap_t map; 2344 int error; 2345 2346 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 2347 if (m == NULL) 2348 return (ENOBUFS); 2349 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 2350 if (!(m->m_flags & M_EXT)) { 2351 m_freem(m); 2352 return (ENOBUFS); 2353 } 2354 2355 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2356 2357 error = bus_dmamap_load_mbuf(sc->sc_dmat, 2358 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 2359 2360 if (error != 0) { 2361 if (!error) { 2362 bus_dmamap_unload(sc->sc_dmat, 2363 sc->alc_cdata.alc_rx_sparemap); 2364 error = EFBIG; 2365 printf("%s: too many segments?!\n", 2366 device_xname(sc->sc_dev)); 2367 } 2368 m_freem(m); 2369 2370 if (init) 2371 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 2372 2373 return (error); 2374 } 2375 2376 if (rxd->rx_m != NULL) { 2377 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 2378 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2379 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2380 } 2381 map = rxd->rx_dmamap; 2382 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2383 sc->alc_cdata.alc_rx_sparemap = map; 2384 rxd->rx_m = m; 2385 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 2386 return (0); 2387 } 2388 2389 static int 2390 alc_rxintr(struct alc_softc *sc) 2391 { 2392 struct ifnet *ifp = &sc->sc_ec.ec_if; 2393 struct rx_rdesc *rrd; 2394 uint32_t nsegs, status; 2395 int rr_cons, prog; 2396 2397 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2398 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2399 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2400 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 2401 rr_cons = sc->alc_cdata.alc_rr_cons; 2402 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2403 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2404 status = le32toh(rrd->status); 2405 if ((status & RRD_VALID) == 0) 2406 break; 2407 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2408 if (nsegs == 0) { 2409 /* This should not happen! */ 2410 if (alcdebug) 2411 printf("%s: unexpected segment count -- " 2412 "resetting\n", device_xname(sc->sc_dev)); 2413 return (EIO); 2414 } 2415 alc_rxeof(sc, rrd); 2416 /* Clear Rx return status. */ 2417 rrd->status = 0; 2418 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2419 sc->alc_cdata.alc_rx_cons += nsegs; 2420 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2421 prog += nsegs; 2422 } 2423 2424 if (prog > 0) { 2425 /* Update the consumer index. */ 2426 sc->alc_cdata.alc_rr_cons = rr_cons; 2427 /* Sync Rx return descriptors. */ 2428 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2429 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 2430 BUS_DMASYNC_PREWRITE); 2431 /* 2432 * Sync updated Rx descriptors such that controller see 2433 * modified buffer addresses. 2434 */ 2435 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2436 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 2437 BUS_DMASYNC_PREWRITE); 2438 /* 2439 * Let controller know availability of new Rx buffers. 2440 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2441 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2442 * only when Rx buffer pre-fetching is required. In 2443 * addition we already set ALC_RX_RD_FREE_THRESH to 2444 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2445 * it still seems that pre-fetching needs more 2446 * experimentation. 2447 */ 2448 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2449 sc->alc_cdata.alc_rx_cons); 2450 } 2451 2452 return (0); 2453 } 2454 2455 /* Receive a frame. */ 2456 static void 2457 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2458 { 2459 struct ifnet *ifp = &sc->sc_ec.ec_if; 2460 struct alc_rxdesc *rxd; 2461 struct mbuf *mp, *m; 2462 uint32_t rdinfo, status; 2463 int count, nsegs, rx_cons; 2464 2465 status = le32toh(rrd->status); 2466 rdinfo = le32toh(rrd->rdinfo); 2467 rx_cons = RRD_RD_IDX(rdinfo); 2468 nsegs = RRD_RD_CNT(rdinfo); 2469 2470 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2471 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 2472 /* 2473 * We want to pass the following frames to upper 2474 * layer regardless of error status of Rx return 2475 * ring. 2476 * 2477 * o IP/TCP/UDP checksum is bad. 2478 * o frame length and protocol specific length 2479 * does not match. 2480 * 2481 * Force network stack compute checksum for 2482 * errored frames. 2483 */ 2484 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2485 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2486 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2487 return; 2488 } 2489 2490 for (count = 0; count < nsegs; count++, 2491 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2492 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2493 mp = rxd->rx_m; 2494 /* Add a new receive buffer to the ring. */ 2495 if (alc_newbuf(sc, rxd, false) != 0) { 2496 ifp->if_iqdrops++; 2497 /* Reuse Rx buffers. */ 2498 if (sc->alc_cdata.alc_rxhead != NULL) 2499 m_freem(sc->alc_cdata.alc_rxhead); 2500 break; 2501 } 2502 2503 /* 2504 * Assume we've received a full sized frame. 2505 * Actual size is fixed when we encounter the end of 2506 * multi-segmented frame. 2507 */ 2508 mp->m_len = sc->alc_buf_size; 2509 2510 /* Chain received mbufs. */ 2511 if (sc->alc_cdata.alc_rxhead == NULL) { 2512 sc->alc_cdata.alc_rxhead = mp; 2513 sc->alc_cdata.alc_rxtail = mp; 2514 } else { 2515 mp->m_flags &= ~M_PKTHDR; 2516 sc->alc_cdata.alc_rxprev_tail = 2517 sc->alc_cdata.alc_rxtail; 2518 sc->alc_cdata.alc_rxtail->m_next = mp; 2519 sc->alc_cdata.alc_rxtail = mp; 2520 } 2521 2522 if (count == nsegs - 1) { 2523 /* Last desc. for this frame. */ 2524 m = sc->alc_cdata.alc_rxhead; 2525 m->m_flags |= M_PKTHDR; 2526 /* 2527 * It seems that L1C/L2C controller has no way 2528 * to tell hardware to strip CRC bytes. 2529 */ 2530 m->m_pkthdr.len = 2531 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2532 if (nsegs > 1) { 2533 /* Set last mbuf size. */ 2534 mp->m_len = sc->alc_cdata.alc_rxlen - 2535 (nsegs - 1) * sc->alc_buf_size; 2536 /* Remove the CRC bytes in chained mbufs. */ 2537 if (mp->m_len <= ETHER_CRC_LEN) { 2538 sc->alc_cdata.alc_rxtail = 2539 sc->alc_cdata.alc_rxprev_tail; 2540 sc->alc_cdata.alc_rxtail->m_len -= 2541 (ETHER_CRC_LEN - mp->m_len); 2542 sc->alc_cdata.alc_rxtail->m_next = NULL; 2543 m_freem(mp); 2544 } else { 2545 mp->m_len -= ETHER_CRC_LEN; 2546 } 2547 } else 2548 m->m_len = m->m_pkthdr.len; 2549 m->m_pkthdr.rcvif = ifp; 2550 #if NVLAN > 0 2551 /* 2552 * Due to hardware bugs, Rx checksum offloading 2553 * was intentionally disabled. 2554 */ 2555 if (status & RRD_VLAN_TAG) { 2556 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 2557 VLAN_INPUT_TAG(ifp, m, ntohs(vtag), ); 2558 } 2559 #endif 2560 2561 bpf_mtap(ifp, m); 2562 2563 /* Pass it on. */ 2564 (*ifp->if_input)(ifp, m); 2565 } 2566 } 2567 /* Reset mbuf chains. */ 2568 ALC_RXCHAIN_RESET(sc); 2569 } 2570 2571 static void 2572 alc_tick(void *xsc) 2573 { 2574 struct alc_softc *sc = xsc; 2575 struct mii_data *mii = &sc->sc_miibus; 2576 int s; 2577 2578 s = splnet(); 2579 mii_tick(mii); 2580 alc_stats_update(sc); 2581 splx(s); 2582 2583 callout_schedule(&sc->sc_tick_ch, hz); 2584 } 2585 2586 static void 2587 alc_osc_reset(struct alc_softc *sc) 2588 { 2589 uint32_t reg; 2590 2591 reg = CSR_READ_4(sc, ALC_MISC3); 2592 reg &= ~MISC3_25M_BY_SW; 2593 reg |= MISC3_25M_NOTO_INTNL; 2594 CSR_WRITE_4(sc, ALC_MISC3, reg); 2595 2596 reg = CSR_READ_4(sc, ALC_MISC); 2597 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 2598 /* 2599 * Restore over-current protection default value. 2600 * This value could be reset by MAC reset. 2601 */ 2602 reg &= ~MISC_PSW_OCP_MASK; 2603 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 2604 reg &= ~MISC_INTNLOSC_OPEN; 2605 CSR_WRITE_4(sc, ALC_MISC, reg); 2606 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2607 reg = CSR_READ_4(sc, ALC_MISC2); 2608 reg &= ~MISC2_CALB_START; 2609 CSR_WRITE_4(sc, ALC_MISC2, reg); 2610 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 2611 2612 } else { 2613 reg &= ~MISC_INTNLOSC_OPEN; 2614 /* Disable isolate for revision A devices. */ 2615 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2616 reg &= ~MISC_ISO_ENB; 2617 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 2618 CSR_WRITE_4(sc, ALC_MISC, reg); 2619 } 2620 2621 DELAY(20); 2622 } 2623 2624 static void 2625 alc_reset(struct alc_softc *sc) 2626 { 2627 uint32_t pmcfg, reg; 2628 int i; 2629 2630 pmcfg = 0; 2631 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2632 /* Reset workaround. */ 2633 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 2634 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2635 (sc->alc_rev & 0x01) != 0) { 2636 /* Disable L0s/L1s before reset. */ 2637 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 2638 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2639 != 0) { 2640 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 2641 PM_CFG_ASPM_L1_ENB); 2642 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2643 } 2644 } 2645 } 2646 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2647 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2648 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2649 2650 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2651 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2652 DELAY(10); 2653 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 2654 break; 2655 } 2656 if (i == 0) 2657 printf("%s: MAC reset timeout!\n", device_xname(sc->sc_dev)); 2658 } 2659 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2660 DELAY(10); 2661 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2662 break; 2663 } 2664 if (i == 0) 2665 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2666 2667 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2668 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2669 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 2670 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2671 break; 2672 DELAY(10); 2673 } 2674 if (i == 0) 2675 printf("%s: reset timeout(0x%08x)!\n", 2676 device_xname(sc->sc_dev), reg); 2677 2678 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2679 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 2680 (sc->alc_rev & 0x01) != 0) { 2681 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2682 reg |= MASTER_CLK_SEL_DIS; 2683 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2684 /* Restore L0s/L1s config. */ 2685 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 2686 != 0) 2687 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 2688 } 2689 2690 alc_osc_reset(sc); 2691 reg = CSR_READ_4(sc, ALC_MISC3); 2692 reg &= ~MISC3_25M_BY_SW; 2693 reg |= MISC3_25M_NOTO_INTNL; 2694 CSR_WRITE_4(sc, ALC_MISC3, reg); 2695 reg = CSR_READ_4(sc, ALC_MISC); 2696 reg &= ~MISC_INTNLOSC_OPEN; 2697 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 2698 reg &= ~MISC_ISO_ENB; 2699 CSR_WRITE_4(sc, ALC_MISC, reg); 2700 DELAY(20); 2701 } 2702 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 2703 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2704 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2705 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2706 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2707 SERDES_PHY_CLK_SLOWDOWN); 2708 } 2709 2710 static int 2711 alc_init(struct ifnet *ifp) 2712 { 2713 2714 return alc_init_backend(ifp, true); 2715 } 2716 2717 static int 2718 alc_init_backend(struct ifnet *ifp, bool init) 2719 { 2720 struct alc_softc *sc = ifp->if_softc; 2721 struct mii_data *mii; 2722 uint8_t eaddr[ETHER_ADDR_LEN]; 2723 bus_addr_t paddr; 2724 uint32_t reg, rxf_hi, rxf_lo; 2725 int error; 2726 2727 /* 2728 * Cancel any pending I/O. 2729 */ 2730 alc_stop(ifp, 0); 2731 /* 2732 * Reset the chip to a known state. 2733 */ 2734 alc_reset(sc); 2735 2736 /* Initialize Rx descriptors. */ 2737 error = alc_init_rx_ring(sc, init); 2738 if (error != 0) { 2739 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2740 alc_stop(ifp, 0); 2741 return (error); 2742 } 2743 alc_init_rr_ring(sc); 2744 alc_init_tx_ring(sc); 2745 alc_init_cmb(sc); 2746 alc_init_smb(sc); 2747 2748 /* Enable all clocks. */ 2749 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2750 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 2751 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 2752 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 2753 CLK_GATING_RXMAC_ENB); 2754 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 2755 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 2756 IDLE_DECISN_TIMER_DEFAULT_1MS); 2757 } else 2758 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2759 2760 2761 /* Reprogram the station address. */ 2762 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2763 CSR_WRITE_4(sc, ALC_PAR0, 2764 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2765 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2766 /* 2767 * Clear WOL status and disable all WOL feature as WOL 2768 * would interfere Rx operation under normal environments. 2769 */ 2770 CSR_READ_4(sc, ALC_WOL_CFG); 2771 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2772 /* Set Tx descriptor base addresses. */ 2773 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2774 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2775 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2776 /* We don't use high priority ring. */ 2777 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2778 /* Set Tx descriptor counter. */ 2779 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2780 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2781 /* Set Rx descriptor base addresses. */ 2782 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2783 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2784 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2785 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2786 /* We use one Rx ring. */ 2787 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2788 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2789 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2790 } 2791 /* Set Rx descriptor counter. */ 2792 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2793 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2794 2795 /* 2796 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2797 * if it do not fit the buffer size. Rx return descriptor holds 2798 * a counter that indicates how many fragments were made by the 2799 * hardware. The buffer size should be multiple of 8 bytes. 2800 * Since hardware has limit on the size of buffer size, always 2801 * use the maximum value. 2802 * For strict-alignment architectures make sure to reduce buffer 2803 * size by 8 bytes to make room for alignment fixup. 2804 */ 2805 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2806 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2807 2808 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2809 /* Set Rx return descriptor base addresses. */ 2810 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2811 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2812 /* We use one Rx return ring. */ 2813 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2814 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2815 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2816 }\ 2817 /* Set Rx return descriptor counter. */ 2818 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2819 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2820 paddr = sc->alc_rdata.alc_cmb_paddr; 2821 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2822 paddr = sc->alc_rdata.alc_smb_paddr; 2823 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2824 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2825 2826 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2827 /* Reconfigure SRAM - Vendor magic. */ 2828 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2829 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2830 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2831 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2832 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2833 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2834 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2835 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2836 } 2837 2838 /* Tell hardware that we're ready to load DMA blocks. */ 2839 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2840 2841 /* Configure interrupt moderation timer. */ 2842 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2843 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2844 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2845 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 2846 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2847 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2848 /* 2849 * We don't want to automatic interrupt clear as task queue 2850 * for the interrupt should know interrupt status. 2851 */ 2852 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2853 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2854 reg |= MASTER_SA_TIMER_ENB; 2855 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2856 reg |= MASTER_IM_RX_TIMER_ENB; 2857 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 2858 ALC_USECS(sc->alc_int_tx_mod) != 0) 2859 reg |= MASTER_IM_TX_TIMER_ENB; 2860 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2861 /* 2862 * Disable interrupt re-trigger timer. We don't want automatic 2863 * re-triggering of un-ACKed interrupts. 2864 */ 2865 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2866 /* Configure CMB. */ 2867 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2868 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 2869 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 2870 ALC_USECS(sc->alc_int_tx_mod)); 2871 } else { 2872 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2873 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2874 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2875 } else 2876 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2877 } 2878 /* 2879 * Hardware can be configured to issue SMB interrupt based 2880 * on programmed interval. Since there is a callout that is 2881 * invoked for every hz in driver we use that instead of 2882 * relying on periodic SMB interrupt. 2883 */ 2884 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2885 /* Clear MAC statistics. */ 2886 alc_stats_clear(sc); 2887 2888 /* 2889 * Always use maximum frame size that controller can support. 2890 * Otherwise received frames that has larger frame length 2891 * than alc(4) MTU would be silently dropped in hardware. This 2892 * would make path-MTU discovery hard as sender wouldn't get 2893 * any responses from receiver. alc(4) supports 2894 * multi-fragmented frames on Rx path so it has no issue on 2895 * assembling fragmented frames. Using maximum frame size also 2896 * removes the need to reinitialize hardware when interface 2897 * MTU configuration was changed. 2898 * 2899 * Be conservative in what you do, be liberal in what you 2900 * accept from others - RFC 793. 2901 */ 2902 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2903 2904 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 2905 /* Disable header split(?) */ 2906 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2907 2908 /* Configure IPG/IFG parameters. */ 2909 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2910 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 2911 IPG_IFG_IPGT_MASK) | 2912 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 2913 IPG_IFG_MIFG_MASK) | 2914 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 2915 IPG_IFG_IPG1_MASK) | 2916 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 2917 IPG_IFG_IPG2_MASK)); 2918 /* Set parameters for half-duplex media. */ 2919 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2920 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2921 HDPX_CFG_LCOL_MASK) | 2922 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2923 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2924 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2925 HDPX_CFG_ABEBT_MASK) | 2926 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2927 HDPX_CFG_JAMIPG_MASK)); 2928 } 2929 2930 /* 2931 * Set TSO/checksum offload threshold. For frames that is 2932 * larger than this threshold, hardware wouldn't do 2933 * TSO/checksum offloading. 2934 */ 2935 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2936 TSO_OFFLOAD_THRESH_MASK; 2937 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2938 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 2939 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 2940 /* Configure TxQ. */ 2941 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2942 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2943 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2944 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2945 reg >>= 1; 2946 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2947 TXQ_CFG_TD_BURST_MASK; 2948 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 2949 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2950 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2951 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 2952 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 2953 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 2954 HQTD_CFG_BURST_ENB); 2955 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 2956 reg = WRR_PRI_RESTRICT_NONE; 2957 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 2958 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 2959 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 2960 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 2961 CSR_WRITE_4(sc, ALC_WRR, reg); 2962 } else { 2963 /* Configure Rx free descriptor pre-fetching. */ 2964 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2965 ((RX_RD_FREE_THRESH_HI_DEFAULT << 2966 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 2967 ((RX_RD_FREE_THRESH_LO_DEFAULT << 2968 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 2969 } 2970 2971 /* 2972 * Configure flow control parameters. 2973 * XON : 80% of Rx FIFO 2974 * XOFF : 30% of Rx FIFO 2975 */ 2976 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 2977 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2978 reg &= SRAM_RX_FIFO_LEN_MASK; 2979 reg *= 8; 2980 if (reg > 8 * 1024) 2981 reg -= RX_FIFO_PAUSE_816X_RSVD; 2982 else 2983 reg -= RX_BUF_SIZE_MAX; 2984 reg /= 8; 2985 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2986 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2987 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2988 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 2989 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2990 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2991 } else if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 2992 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 2993 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2994 rxf_hi = (reg * 8) / 10; 2995 rxf_lo = (reg * 3) / 10; 2996 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2997 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2998 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2999 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3000 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3001 } 3002 3003 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3004 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3005 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3006 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3007 } 3008 3009 /* Configure RxQ. */ 3010 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3011 RXQ_CFG_RD_BURST_MASK; 3012 reg |= RXQ_CFG_RSS_MODE_DIS; 3013 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3014 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3015 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3016 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 3017 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 3018 sc->alc_ident->deviceid != PCI_PRODUCT_ATTANSIC_AR8151_V2) 3019 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3020 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3021 3022 /* Configure DMA parameters. */ 3023 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3024 reg |= sc->alc_rcb; 3025 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3026 reg |= DMA_CFG_CMB_ENB; 3027 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3028 reg |= DMA_CFG_SMB_ENB; 3029 else 3030 reg |= DMA_CFG_SMB_DIS; 3031 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3032 DMA_CFG_RD_BURST_SHIFT; 3033 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3034 DMA_CFG_WR_BURST_SHIFT; 3035 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3036 DMA_CFG_RD_DELAY_CNT_MASK; 3037 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3038 DMA_CFG_WR_DELAY_CNT_MASK; 3039 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3040 switch (AR816X_REV(sc->alc_rev)) { 3041 case AR816X_REV_A0: 3042 case AR816X_REV_A1: 3043 reg |= DMA_CFG_RD_CHNL_SEL_1; 3044 break; 3045 case AR816X_REV_B0: 3046 /* FALLTHROUGH */ 3047 default: 3048 reg |= DMA_CFG_RD_CHNL_SEL_3; 3049 break; 3050 } 3051 } 3052 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3053 3054 /* 3055 * Configure Tx/Rx MACs. 3056 * - Auto-padding for short frames. 3057 * - Enable CRC generation. 3058 * Actual reconfiguration of MAC for resolved speed/duplex 3059 * is followed after detection of link establishment. 3060 * AR813x/AR815x always does checksum computation regardless 3061 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3062 * have bug in protocol field in Rx return structure so 3063 * these controllers can't handle fragmented frames. Disable 3064 * Rx checksum offloading until there is a newer controller 3065 * that has sane implementation. 3066 */ 3067 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3068 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3069 MAC_CFG_PREAMBLE_MASK); 3070 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3071 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 3072 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 3073 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 3074 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3075 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3076 reg |= MAC_CFG_SPEED_10_100; 3077 else 3078 reg |= MAC_CFG_SPEED_1000; 3079 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3080 3081 /* Set up the receive filter. */ 3082 alc_iff(sc); 3083 alc_rxvlan(sc); 3084 3085 /* Acknowledge all pending interrupts and clear it. */ 3086 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3087 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3088 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3089 3090 sc->alc_flags &= ~ALC_FLAG_LINK; 3091 /* Switch to the current media. */ 3092 mii = &sc->sc_miibus; 3093 mii_mediachg(mii); 3094 3095 callout_schedule(&sc->sc_tick_ch, hz); 3096 3097 ifp->if_flags |= IFF_RUNNING; 3098 ifp->if_flags &= ~IFF_OACTIVE; 3099 3100 return (0); 3101 } 3102 3103 static void 3104 alc_stop(struct ifnet *ifp, int disable) 3105 { 3106 struct alc_softc *sc = ifp->if_softc; 3107 struct alc_txdesc *txd; 3108 struct alc_rxdesc *rxd; 3109 uint32_t reg; 3110 int i; 3111 3112 callout_stop(&sc->sc_tick_ch); 3113 3114 /* 3115 * Mark the interface down and cancel the watchdog timer. 3116 */ 3117 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3118 ifp->if_timer = 0; 3119 3120 sc->alc_flags &= ~ALC_FLAG_LINK; 3121 3122 alc_stats_update(sc); 3123 3124 mii_down(&sc->sc_miibus); 3125 3126 /* Disable interrupts. */ 3127 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3128 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3129 3130 /* Disable DMA. */ 3131 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3132 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3133 reg |= DMA_CFG_SMB_DIS; 3134 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3135 DELAY(1000); 3136 3137 /* Stop Rx/Tx MACs. */ 3138 alc_stop_mac(sc); 3139 3140 /* Disable interrupts which might be touched in taskq handler. */ 3141 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3142 3143 /* Disable L0s/L1s */ 3144 alc_aspm(sc, 0, IFM_UNKNOWN); 3145 3146 /* Reclaim Rx buffers that have been processed. */ 3147 if (sc->alc_cdata.alc_rxhead != NULL) 3148 m_freem(sc->alc_cdata.alc_rxhead); 3149 ALC_RXCHAIN_RESET(sc); 3150 /* 3151 * Free Tx/Rx mbufs still in the queues. 3152 */ 3153 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3154 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3155 if (rxd->rx_m != NULL) { 3156 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 3157 m_freem(rxd->rx_m); 3158 rxd->rx_m = NULL; 3159 } 3160 } 3161 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3162 txd = &sc->alc_cdata.alc_txdesc[i]; 3163 if (txd->tx_m != NULL) { 3164 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 3165 m_freem(txd->tx_m); 3166 txd->tx_m = NULL; 3167 } 3168 } 3169 } 3170 3171 static void 3172 alc_stop_mac(struct alc_softc *sc) 3173 { 3174 uint32_t reg; 3175 int i; 3176 3177 alc_stop_queue(sc); 3178 /* Disable Rx/Tx MAC. */ 3179 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3180 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3181 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3182 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3183 } 3184 for (i = ALC_TIMEOUT; i > 0; i--) { 3185 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3186 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 3187 break; 3188 DELAY(10); 3189 } 3190 if (i == 0) 3191 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 3192 device_xname(sc->sc_dev), reg); 3193 } 3194 3195 static void 3196 alc_start_queue(struct alc_softc *sc) 3197 { 3198 uint32_t qcfg[] = { 3199 0, 3200 RXQ_CFG_QUEUE0_ENB, 3201 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3202 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3203 RXQ_CFG_ENB 3204 }; 3205 uint32_t cfg; 3206 3207 /* Enable RxQ. */ 3208 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3209 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3210 cfg &= ~RXQ_CFG_ENB; 3211 cfg |= qcfg[1]; 3212 } else 3213 cfg |= RXQ_CFG_QUEUE0_ENB; 3214 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3215 /* Enable TxQ. */ 3216 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3217 cfg |= TXQ_CFG_ENB; 3218 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3219 } 3220 3221 static void 3222 alc_stop_queue(struct alc_softc *sc) 3223 { 3224 uint32_t reg; 3225 int i; 3226 3227 /* Disable RxQ. */ 3228 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3229 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3230 if ((reg & RXQ_CFG_ENB) != 0) { 3231 reg &= ~RXQ_CFG_ENB; 3232 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3233 } 3234 } else { 3235 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 3236 reg &= ~RXQ_CFG_QUEUE0_ENB; 3237 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3238 } 3239 } 3240 /* Disable TxQ. */ 3241 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3242 if ((reg & TXQ_CFG_ENB) != 0) { 3243 reg &= ~TXQ_CFG_ENB; 3244 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3245 } 3246 DELAY(40); 3247 for (i = ALC_TIMEOUT; i > 0; i--) { 3248 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3249 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3250 break; 3251 DELAY(10); 3252 } 3253 if (i == 0) 3254 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 3255 device_xname(sc->sc_dev), reg); 3256 } 3257 3258 static void 3259 alc_init_tx_ring(struct alc_softc *sc) 3260 { 3261 struct alc_ring_data *rd; 3262 struct alc_txdesc *txd; 3263 int i; 3264 3265 sc->alc_cdata.alc_tx_prod = 0; 3266 sc->alc_cdata.alc_tx_cons = 0; 3267 sc->alc_cdata.alc_tx_cnt = 0; 3268 3269 rd = &sc->alc_rdata; 3270 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 3271 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3272 txd = &sc->alc_cdata.alc_txdesc[i]; 3273 txd->tx_m = NULL; 3274 } 3275 3276 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 3277 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3278 } 3279 3280 static int 3281 alc_init_rx_ring(struct alc_softc *sc, bool init) 3282 { 3283 struct alc_ring_data *rd; 3284 struct alc_rxdesc *rxd; 3285 int i; 3286 3287 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3288 rd = &sc->alc_rdata; 3289 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 3290 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3291 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3292 rxd->rx_m = NULL; 3293 rxd->rx_desc = &rd->alc_rx_ring[i]; 3294 if (alc_newbuf(sc, rxd, init) != 0) 3295 return (ENOBUFS); 3296 } 3297 3298 /* 3299 * Since controller does not update Rx descriptors, driver 3300 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3301 * is enough to ensure coherence. 3302 */ 3303 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 3304 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3305 /* Let controller know availability of new Rx buffers. */ 3306 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3307 3308 return (0); 3309 } 3310 3311 static void 3312 alc_init_rr_ring(struct alc_softc *sc) 3313 { 3314 struct alc_ring_data *rd; 3315 3316 sc->alc_cdata.alc_rr_cons = 0; 3317 ALC_RXCHAIN_RESET(sc); 3318 3319 rd = &sc->alc_rdata; 3320 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 3321 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 3322 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3323 } 3324 3325 static void 3326 alc_init_cmb(struct alc_softc *sc) 3327 { 3328 struct alc_ring_data *rd; 3329 3330 rd = &sc->alc_rdata; 3331 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 3332 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 3333 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3334 } 3335 3336 static void 3337 alc_init_smb(struct alc_softc *sc) 3338 { 3339 struct alc_ring_data *rd; 3340 3341 rd = &sc->alc_rdata; 3342 memset(rd->alc_smb, 0, ALC_SMB_SZ); 3343 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 3344 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 3345 } 3346 3347 static void 3348 alc_rxvlan(struct alc_softc *sc) 3349 { 3350 uint32_t reg; 3351 3352 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3353 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 3354 reg |= MAC_CFG_VLAN_TAG_STRIP; 3355 else 3356 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3357 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3358 } 3359 3360 static void 3361 alc_iff(struct alc_softc *sc) 3362 { 3363 struct ethercom *ec = &sc->sc_ec; 3364 struct ifnet *ifp = &ec->ec_if; 3365 struct ether_multi *enm; 3366 struct ether_multistep step; 3367 uint32_t crc; 3368 uint32_t mchash[2]; 3369 uint32_t rxcfg; 3370 3371 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3372 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3373 ifp->if_flags &= ~IFF_ALLMULTI; 3374 3375 /* 3376 * Always accept broadcast frames. 3377 */ 3378 rxcfg |= MAC_CFG_BCAST; 3379 3380 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 3381 ifp->if_flags |= IFF_ALLMULTI; 3382 if (ifp->if_flags & IFF_PROMISC) 3383 rxcfg |= MAC_CFG_PROMISC; 3384 else 3385 rxcfg |= MAC_CFG_ALLMULTI; 3386 mchash[0] = mchash[1] = 0xFFFFFFFF; 3387 } else { 3388 /* Program new filter. */ 3389 memset(mchash, 0, sizeof(mchash)); 3390 3391 ETHER_FIRST_MULTI(step, ec, enm); 3392 while (enm != NULL) { 3393 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3394 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3395 ETHER_NEXT_MULTI(step, enm); 3396 } 3397 } 3398 3399 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3400 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3401 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3402 } 3403 3404 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 3405 3406 #ifdef _MODULE 3407 #include "ioconf.c" 3408 #endif 3409 3410 static int 3411 if_alc_modcmd(modcmd_t cmd, void *opaque) 3412 { 3413 int error = 0; 3414 3415 switch (cmd) { 3416 case MODULE_CMD_INIT: 3417 #ifdef _MODULE 3418 error = config_init_component(cfdriver_ioconf_if_alc, 3419 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3420 #endif 3421 return error; 3422 case MODULE_CMD_FINI: 3423 #ifdef _MODULE 3424 error = config_fini_component(cfdriver_ioconf_if_alc, 3425 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 3426 #endif 3427 return error; 3428 default: 3429 return ENOTTY; 3430 } 3431 } 3432