1 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 30 31 #ifdef _KERNEL_OPT 32 #include "vlan.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/callout.h> 46 #include <sys/socket.h> 47 #include <sys/module.h> 48 49 #include <sys/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <net/bpf.h> 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_alcreg.h> 81 82 /* 83 * Devices supported by this driver. 84 */ 85 static struct alc_ident alc_ident_table[] = { 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 87 "Atheros AR8131 PCIe Gigabit Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 89 "Atheros AR8132 PCIe Fast Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 91 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 93 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 95 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 97 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 98 { 0, 0, 0, NULL }, 99 }; 100 101 static int alc_match(device_t, cfdata_t, void *); 102 static void alc_attach(device_t, device_t, void *); 103 static int alc_detach(device_t, int); 104 105 static int alc_init(struct ifnet *); 106 static int alc_init_backend(struct ifnet *, bool); 107 static void alc_start(struct ifnet *); 108 static int alc_ioctl(struct ifnet *, u_long, void *); 109 static void alc_watchdog(struct ifnet *); 110 static int alc_mediachange(struct ifnet *); 111 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 112 113 static void alc_aspm(struct alc_softc *, int); 114 static void alc_disable_l0s_l1(struct alc_softc *); 115 static int alc_dma_alloc(struct alc_softc *); 116 static void alc_dma_free(struct alc_softc *); 117 static int alc_encap(struct alc_softc *, struct mbuf **); 118 static struct alc_ident * 119 alc_find_ident(struct pci_attach_args *); 120 static void alc_get_macaddr(struct alc_softc *); 121 static void alc_init_cmb(struct alc_softc *); 122 static void alc_init_rr_ring(struct alc_softc *); 123 static int alc_init_rx_ring(struct alc_softc *, bool); 124 static void alc_init_smb(struct alc_softc *); 125 static void alc_init_tx_ring(struct alc_softc *); 126 static int alc_intr(void *); 127 static void alc_mac_config(struct alc_softc *); 128 static int alc_miibus_readreg(device_t, int, int); 129 static void alc_miibus_statchg(struct ifnet *); 130 static void alc_miibus_writereg(device_t, int, int, int); 131 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 132 static void alc_phy_down(struct alc_softc *); 133 static void alc_phy_reset(struct alc_softc *); 134 static void alc_reset(struct alc_softc *); 135 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 136 static int alc_rxintr(struct alc_softc *); 137 static void alc_iff(struct alc_softc *); 138 static void alc_rxvlan(struct alc_softc *); 139 static void alc_start_queue(struct alc_softc *); 140 static void alc_stats_clear(struct alc_softc *); 141 static void alc_stats_update(struct alc_softc *); 142 static void alc_stop(struct ifnet *, int); 143 static void alc_stop_mac(struct alc_softc *); 144 static void alc_stop_queue(struct alc_softc *); 145 static void alc_tick(void *); 146 static void alc_txeof(struct alc_softc *); 147 148 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 149 150 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 151 alc_match, alc_attach, alc_detach, NULL); 152 153 int alcdebug = 0; 154 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 155 156 #define ETHER_ALIGN 2 157 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 158 159 static int 160 alc_miibus_readreg(device_t dev, int phy, int reg) 161 { 162 struct alc_softc *sc = device_private(dev); 163 uint32_t v; 164 int i; 165 166 if (phy != sc->alc_phyaddr) 167 return (0); 168 169 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 170 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 171 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 172 DELAY(5); 173 v = CSR_READ_4(sc, ALC_MDIO); 174 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 175 break; 176 } 177 178 if (i == 0) { 179 printf("%s: phy read timeout: phy %d, reg %d\n", 180 device_xname(sc->sc_dev), phy, reg); 181 return (0); 182 } 183 184 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 185 } 186 187 static void 188 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 189 { 190 struct alc_softc *sc = device_private(dev); 191 uint32_t v; 192 int i; 193 194 if (phy != sc->alc_phyaddr) 195 return; 196 197 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 198 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 199 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 200 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 201 DELAY(5); 202 v = CSR_READ_4(sc, ALC_MDIO); 203 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 204 break; 205 } 206 207 if (i == 0) 208 printf("%s: phy write timeout: phy %d, reg %d\n", 209 device_xname(sc->sc_dev), phy, reg); 210 } 211 212 static void 213 alc_miibus_statchg(struct ifnet *ifp) 214 { 215 struct alc_softc *sc = ifp->if_softc; 216 struct mii_data *mii = &sc->sc_miibus; 217 uint32_t reg; 218 219 if ((ifp->if_flags & IFF_RUNNING) == 0) 220 return; 221 222 sc->alc_flags &= ~ALC_FLAG_LINK; 223 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 224 (IFM_ACTIVE | IFM_AVALID)) { 225 switch (IFM_SUBTYPE(mii->mii_media_active)) { 226 case IFM_10_T: 227 case IFM_100_TX: 228 sc->alc_flags |= ALC_FLAG_LINK; 229 break; 230 case IFM_1000_T: 231 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 232 sc->alc_flags |= ALC_FLAG_LINK; 233 break; 234 default: 235 break; 236 } 237 } 238 alc_stop_queue(sc); 239 /* Stop Rx/Tx MACs. */ 240 alc_stop_mac(sc); 241 242 /* Program MACs with resolved speed/duplex/flow-control. */ 243 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 244 alc_start_queue(sc); 245 alc_mac_config(sc); 246 /* Re-enable Tx/Rx MACs. */ 247 reg = CSR_READ_4(sc, ALC_MAC_CFG); 248 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 249 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 250 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 251 } 252 } 253 254 static void 255 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 256 { 257 struct alc_softc *sc = ifp->if_softc; 258 struct mii_data *mii = &sc->sc_miibus; 259 260 mii_pollstat(mii); 261 ifmr->ifm_status = mii->mii_media_status; 262 ifmr->ifm_active = mii->mii_media_active; 263 } 264 265 static int 266 alc_mediachange(struct ifnet *ifp) 267 { 268 struct alc_softc *sc = ifp->if_softc; 269 struct mii_data *mii = &sc->sc_miibus; 270 int error; 271 272 if (mii->mii_instance != 0) { 273 struct mii_softc *miisc; 274 275 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 276 mii_phy_reset(miisc); 277 } 278 error = mii_mediachg(mii); 279 280 return (error); 281 } 282 283 static struct alc_ident * 284 alc_find_ident(struct pci_attach_args *pa) 285 { 286 struct alc_ident *ident; 287 uint16_t vendor, devid; 288 289 vendor = PCI_VENDOR(pa->pa_id); 290 devid = PCI_PRODUCT(pa->pa_id); 291 for (ident = alc_ident_table; ident->name != NULL; ident++) { 292 if (vendor == ident->vendorid && devid == ident->deviceid) 293 return (ident); 294 } 295 296 return (NULL); 297 } 298 299 static int 300 alc_match(device_t dev, cfdata_t match, void *aux) 301 { 302 struct pci_attach_args *pa = aux; 303 304 return alc_find_ident(pa) != NULL; 305 } 306 307 static void 308 alc_get_macaddr(struct alc_softc *sc) 309 { 310 uint32_t ea[2], opt; 311 uint16_t val; 312 int eeprom, i; 313 314 eeprom = 0; 315 opt = CSR_READ_4(sc, ALC_OPT_CFG); 316 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 317 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 318 /* 319 * EEPROM found, let TWSI reload EEPROM configuration. 320 * This will set ethernet address of controller. 321 */ 322 eeprom++; 323 switch (sc->alc_ident->deviceid) { 324 case PCI_PRODUCT_ATTANSIC_AR8131: 325 case PCI_PRODUCT_ATTANSIC_AR8132: 326 if ((opt & OPT_CFG_CLK_ENB) == 0) { 327 opt |= OPT_CFG_CLK_ENB; 328 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 329 CSR_READ_4(sc, ALC_OPT_CFG); 330 DELAY(1000); 331 } 332 break; 333 case PCI_PRODUCT_ATTANSIC_AR8151: 334 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 335 case PCI_PRODUCT_ATTANSIC_AR8152_B: 336 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 337 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 338 ALC_MII_DBG_ADDR, 0x00); 339 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 340 ALC_MII_DBG_DATA); 341 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 342 ALC_MII_DBG_DATA, val & 0xFF7F); 343 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 344 ALC_MII_DBG_ADDR, 0x3B); 345 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 346 ALC_MII_DBG_DATA); 347 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 348 ALC_MII_DBG_DATA, val | 0x0008); 349 DELAY(20); 350 break; 351 } 352 353 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 354 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 355 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 356 CSR_READ_4(sc, ALC_WOL_CFG); 357 358 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 359 TWSI_CFG_SW_LD_START); 360 for (i = 100; i > 0; i--) { 361 DELAY(1000); 362 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 363 TWSI_CFG_SW_LD_START) == 0) 364 break; 365 } 366 if (i == 0) 367 printf("%s: reloading EEPROM timeout!\n", 368 device_xname(sc->sc_dev)); 369 } else { 370 if (alcdebug) 371 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 372 } 373 if (eeprom != 0) { 374 switch (sc->alc_ident->deviceid) { 375 case PCI_PRODUCT_ATTANSIC_AR8131: 376 case PCI_PRODUCT_ATTANSIC_AR8132: 377 if ((opt & OPT_CFG_CLK_ENB) != 0) { 378 opt &= ~OPT_CFG_CLK_ENB; 379 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 380 CSR_READ_4(sc, ALC_OPT_CFG); 381 DELAY(1000); 382 } 383 break; 384 case PCI_PRODUCT_ATTANSIC_AR8151: 385 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 386 case PCI_PRODUCT_ATTANSIC_AR8152_B: 387 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 388 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 389 ALC_MII_DBG_ADDR, 0x00); 390 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 391 ALC_MII_DBG_DATA); 392 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 393 ALC_MII_DBG_DATA, val | 0x0080); 394 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 395 ALC_MII_DBG_ADDR, 0x3B); 396 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 397 ALC_MII_DBG_DATA); 398 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 399 ALC_MII_DBG_DATA, val & 0xFFF7); 400 DELAY(20); 401 break; 402 } 403 } 404 405 ea[0] = CSR_READ_4(sc, ALC_PAR0); 406 ea[1] = CSR_READ_4(sc, ALC_PAR1); 407 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 408 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 409 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 410 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 411 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 412 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 413 } 414 415 static void 416 alc_disable_l0s_l1(struct alc_softc *sc) 417 { 418 uint32_t pmcfg; 419 420 /* Another magic from vendor. */ 421 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 422 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 423 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 424 PM_CFG_SERDES_PD_EX_L1); 425 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 426 PM_CFG_SERDES_L1_ENB; 427 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 428 } 429 430 static void 431 alc_phy_reset(struct alc_softc *sc) 432 { 433 uint16_t data; 434 435 /* Reset magic from Linux. */ 436 CSR_WRITE_2(sc, ALC_GPHY_CFG, 437 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 438 CSR_READ_2(sc, ALC_GPHY_CFG); 439 DELAY(10 * 1000); 440 441 CSR_WRITE_2(sc, ALC_GPHY_CFG, 442 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 443 GPHY_CFG_SEL_ANA_RESET); 444 CSR_READ_2(sc, ALC_GPHY_CFG); 445 DELAY(10 * 1000); 446 447 /* DSP fixup, Vendor magic. */ 448 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 449 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 450 ALC_MII_DBG_ADDR, 0x000A); 451 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 452 ALC_MII_DBG_DATA); 453 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 454 ALC_MII_DBG_DATA, data & 0xDFFF); 455 } 456 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 457 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 458 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 459 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 460 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 461 ALC_MII_DBG_ADDR, 0x003B); 462 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 463 ALC_MII_DBG_DATA); 464 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 465 ALC_MII_DBG_DATA, data & 0xFFF7); 466 DELAY(20 * 1000); 467 } 468 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 469 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 470 ALC_MII_DBG_ADDR, 0x0029); 471 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 472 ALC_MII_DBG_DATA, 0x929D); 473 } 474 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 475 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 476 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 477 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 478 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 479 ALC_MII_DBG_ADDR, 0x0029); 480 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 481 ALC_MII_DBG_DATA, 0xB6DD); 482 } 483 484 /* Load DSP codes, vendor magic. */ 485 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 486 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 487 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 488 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 489 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 490 ALC_MII_DBG_DATA, data); 491 492 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 493 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 494 ANA_SERDES_EN_LCKDT; 495 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 496 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 497 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 498 ALC_MII_DBG_DATA, data); 499 500 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 501 ANA_LONG_CABLE_TH_100_MASK) | 502 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 503 ANA_SHORT_CABLE_TH_100_SHIFT) | 504 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 505 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 506 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 507 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 508 ALC_MII_DBG_DATA, data); 509 510 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 511 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 512 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 513 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 514 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 515 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 516 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 517 ALC_MII_DBG_DATA, data); 518 519 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 520 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 521 ANA_OEN_125M; 522 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 523 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 524 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 525 ALC_MII_DBG_DATA, data); 526 DELAY(1000); 527 } 528 529 static void 530 alc_phy_down(struct alc_softc *sc) 531 { 532 switch (sc->alc_ident->deviceid) { 533 case PCI_PRODUCT_ATTANSIC_AR8151: 534 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 535 /* 536 * GPHY power down caused more problems on AR8151 v2.0. 537 * When driver is reloaded after GPHY power down, 538 * accesses to PHY/MAC registers hung the system. Only 539 * cold boot recovered from it. I'm not sure whether 540 * AR8151 v1.0 also requires this one though. I don't 541 * have AR8151 v1.0 controller in hand. 542 * The only option left is to isolate the PHY and 543 * initiates power down the PHY which in turn saves 544 * more power when driver is unloaded. 545 */ 546 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 547 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 548 break; 549 default: 550 /* Force PHY down. */ 551 CSR_WRITE_2(sc, ALC_GPHY_CFG, 552 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 553 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 554 GPHY_CFG_PWDOWN_HW); 555 DELAY(1000); 556 break; 557 } 558 } 559 560 static void 561 alc_aspm(struct alc_softc *sc, int media) 562 { 563 uint32_t pmcfg; 564 uint16_t linkcfg; 565 566 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 567 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 568 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 569 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 570 PCI_PCIE_LCSR); 571 else 572 linkcfg = 0; 573 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 574 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 575 pmcfg |= PM_CFG_MAC_ASPM_CHK; 576 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 577 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 578 579 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 580 /* Disable extended sync except AR8152 B v1.0 */ 581 linkcfg &= ~0x80; 582 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 583 sc->alc_rev == ATHEROS_AR8152_B_V10) 584 linkcfg |= 0x80; 585 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, 586 linkcfg); 587 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 588 PM_CFG_HOTRST); 589 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 590 PM_CFG_L1_ENTRY_TIMER_SHIFT); 591 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 592 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 593 PM_CFG_PM_REQ_TIMER_SHIFT); 594 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 595 } 596 597 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 598 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 599 pmcfg |= PM_CFG_ASPM_L0S_ENB; 600 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 601 pmcfg |= PM_CFG_ASPM_L1_ENB; 602 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 603 if (sc->alc_ident->deviceid == 604 PCI_PRODUCT_ATTANSIC_AR8152_B) 605 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 606 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 607 PM_CFG_SERDES_PLL_L1_ENB | 608 PM_CFG_SERDES_BUDS_RX_L1_ENB); 609 pmcfg |= PM_CFG_CLK_SWH_L1; 610 if (media == IFM_100_TX || media == IFM_1000_T) { 611 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 612 switch (sc->alc_ident->deviceid) { 613 case PCI_PRODUCT_ATTANSIC_AR8152_B: 614 pmcfg |= (7 << 615 PM_CFG_L1_ENTRY_TIMER_SHIFT); 616 break; 617 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 618 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 619 pmcfg |= (4 << 620 PM_CFG_L1_ENTRY_TIMER_SHIFT); 621 break; 622 default: 623 pmcfg |= (15 << 624 PM_CFG_L1_ENTRY_TIMER_SHIFT); 625 break; 626 } 627 } 628 } else { 629 pmcfg |= PM_CFG_SERDES_L1_ENB | 630 PM_CFG_SERDES_PLL_L1_ENB | 631 PM_CFG_SERDES_BUDS_RX_L1_ENB; 632 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 633 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 634 } 635 } else { 636 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 637 PM_CFG_SERDES_PLL_L1_ENB); 638 pmcfg |= PM_CFG_CLK_SWH_L1; 639 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 640 pmcfg |= PM_CFG_ASPM_L1_ENB; 641 } 642 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 643 } 644 645 static void 646 alc_attach(device_t parent, device_t self, void *aux) 647 { 648 649 struct alc_softc *sc = device_private(self); 650 struct pci_attach_args *pa = aux; 651 pci_chipset_tag_t pc = pa->pa_pc; 652 pci_intr_handle_t ih; 653 const char *intrstr; 654 struct ifnet *ifp; 655 pcireg_t memtype; 656 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 657 uint16_t burst; 658 int base, mii_flags, state, error = 0; 659 uint32_t cap, ctl, val; 660 661 sc->alc_ident = alc_find_ident(pa); 662 663 aprint_naive("\n"); 664 aprint_normal(": %s\n", sc->alc_ident->name); 665 666 sc->sc_dev = self; 667 sc->sc_dmat = pa->pa_dmat; 668 sc->sc_pct = pa->pa_pc; 669 sc->sc_pcitag = pa->pa_tag; 670 671 /* 672 * Allocate IO memory 673 */ 674 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 675 switch (memtype) { 676 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 677 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 678 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 679 break; 680 default: 681 aprint_error_dev(self, "invalid base address register\n"); 682 break; 683 } 684 685 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 686 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 687 aprint_error_dev(self, "could not map mem space\n"); 688 return; 689 } 690 691 if (pci_intr_map(pa, &ih) != 0) { 692 printf(": can't map interrupt\n"); 693 goto fail; 694 } 695 696 /* 697 * Allocate IRQ 698 */ 699 intrstr = pci_intr_string(sc->sc_pct, ih); 700 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc); 701 if (sc->sc_irq_handle == NULL) { 702 printf(": could not establish interrupt"); 703 if (intrstr != NULL) 704 printf(" at %s", intrstr); 705 printf("\n"); 706 goto fail; 707 } 708 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 709 710 /* Set PHY address. */ 711 sc->alc_phyaddr = ALC_PHY_ADDR; 712 713 /* Initialize DMA parameters. */ 714 sc->alc_dma_rd_burst = 0; 715 sc->alc_dma_wr_burst = 0; 716 sc->alc_rcb = DMA_CFG_RCB_64; 717 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 718 &base, NULL)) { 719 sc->alc_flags |= ALC_FLAG_PCIE; 720 sc->alc_expcap = base; 721 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 722 base + PCI_PCIE_DCSR) >> 16; 723 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 724 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 725 if (alcdebug) { 726 printf("%s: Read request size : %u bytes.\n", 727 device_xname(sc->sc_dev), 728 alc_dma_burst[sc->alc_dma_rd_burst]); 729 printf("%s: TLP payload size : %u bytes.\n", 730 device_xname(sc->sc_dev), 731 alc_dma_burst[sc->alc_dma_wr_burst]); 732 } 733 /* Clear data link and flow-control protocol error. */ 734 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 735 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 736 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 737 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 738 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 739 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 740 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 741 PCIE_PHYMISC_FORCE_RCV_DET); 742 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 743 sc->alc_rev == ATHEROS_AR8152_B_V10) { 744 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 745 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 746 PCIE_PHYMISC2_SERDES_TH_MASK); 747 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 748 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 749 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 750 } 751 /* Disable ASPM L0S and L1. */ 752 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 753 base + PCI_PCIE_LCAP) >> 16; 754 if ((cap & 0x00000c00) != 0) { 755 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 756 base + PCI_PCIE_LCSR) >> 16; 757 if ((ctl & 0x08) != 0) 758 sc->alc_rcb = DMA_CFG_RCB_128; 759 if (alcdebug) 760 printf("%s: RCB %u bytes\n", 761 device_xname(sc->sc_dev), 762 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 763 state = ctl & 0x03; 764 if (state & 0x01) 765 sc->alc_flags |= ALC_FLAG_L0S; 766 if (state & 0x02) 767 sc->alc_flags |= ALC_FLAG_L1S; 768 if (alcdebug) 769 printf("%s: ASPM %s %s\n", 770 device_xname(sc->sc_dev), 771 aspm_state[state], 772 state == 0 ? "disabled" : "enabled"); 773 alc_disable_l0s_l1(sc); 774 } else { 775 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 776 } 777 } 778 779 /* Reset PHY. */ 780 alc_phy_reset(sc); 781 782 /* Reset the ethernet controller. */ 783 alc_reset(sc); 784 785 /* 786 * One odd thing is AR8132 uses the same PHY hardware(F1 787 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 788 * the PHY supports 1000Mbps but that's not true. The PHY 789 * used in AR8132 can't establish gigabit link even if it 790 * shows the same PHY model/revision number of AR8131. 791 */ 792 switch (sc->alc_ident->deviceid) { 793 case PCI_PRODUCT_ATTANSIC_AR8152_B: 794 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 795 sc->alc_flags |= ALC_FLAG_APS; 796 /* FALLTHROUGH */ 797 case PCI_PRODUCT_ATTANSIC_AR8132: 798 sc->alc_flags |= ALC_FLAG_FASTETHER; 799 break; 800 case PCI_PRODUCT_ATTANSIC_AR8151: 801 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 802 sc->alc_flags |= ALC_FLAG_APS; 803 /* FALLTHROUGH */ 804 default: 805 break; 806 } 807 sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON; 808 809 /* 810 * It seems that AR813x/AR815x has silicon bug for SMB. In 811 * addition, Atheros said that enabling SMB wouldn't improve 812 * performance. However I think it's bad to access lots of 813 * registers to extract MAC statistics. 814 */ 815 sc->alc_flags |= ALC_FLAG_SMB_BUG; 816 /* 817 * Don't use Tx CMB. It is known to have silicon bug. 818 */ 819 sc->alc_flags |= ALC_FLAG_CMB_BUG; 820 sc->alc_rev = PCI_REVISION(pa->pa_class); 821 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 822 MASTER_CHIP_REV_SHIFT; 823 if (alcdebug) { 824 printf("%s: PCI device revision : 0x%04x\n", 825 device_xname(sc->sc_dev), sc->alc_rev); 826 printf("%s: Chip id/revision : 0x%04x\n", 827 device_xname(sc->sc_dev), sc->alc_chip_rev); 828 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 829 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 830 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 831 } 832 833 error = alc_dma_alloc(sc); 834 if (error) 835 goto fail; 836 837 callout_init(&sc->sc_tick_ch, 0); 838 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 839 840 /* Load station address. */ 841 alc_get_macaddr(sc); 842 843 aprint_normal_dev(self, "Ethernet address %s\n", 844 ether_sprintf(sc->alc_eaddr)); 845 846 ifp = &sc->sc_ec.ec_if; 847 ifp->if_softc = sc; 848 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 849 ifp->if_init = alc_init; 850 ifp->if_ioctl = alc_ioctl; 851 ifp->if_start = alc_start; 852 ifp->if_stop = alc_stop; 853 ifp->if_watchdog = alc_watchdog; 854 ifp->if_baudrate = IF_Gbps(1); 855 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 856 IFQ_SET_READY(&ifp->if_snd); 857 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 858 859 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 860 861 #ifdef ALC_CHECKSUM 862 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 863 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 864 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 865 #endif 866 867 #if NVLAN > 0 868 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 869 #endif 870 871 /* Set up MII bus. */ 872 sc->sc_miibus.mii_ifp = ifp; 873 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 874 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 875 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 876 877 sc->sc_ec.ec_mii = &sc->sc_miibus; 878 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 879 alc_mediastatus); 880 mii_flags = 0; 881 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 882 mii_flags |= MIIF_DOPAUSE; 883 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 884 MII_OFFSET_ANY, mii_flags); 885 886 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 887 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 888 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 889 0, NULL); 890 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 891 } else 892 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 893 894 if_attach(ifp); 895 ether_ifattach(ifp, sc->alc_eaddr); 896 897 if (!pmf_device_register(self, NULL, NULL)) 898 aprint_error_dev(self, "couldn't establish power handler\n"); 899 else 900 pmf_class_network_register(self, ifp); 901 902 return; 903 fail: 904 alc_dma_free(sc); 905 if (sc->sc_irq_handle != NULL) { 906 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 907 sc->sc_irq_handle = NULL; 908 } 909 if (sc->sc_mem_size) { 910 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 911 sc->sc_mem_size = 0; 912 } 913 } 914 915 static int 916 alc_detach(device_t self, int flags) 917 { 918 struct alc_softc *sc = device_private(self); 919 struct ifnet *ifp = &sc->sc_ec.ec_if; 920 int s; 921 922 s = splnet(); 923 alc_stop(ifp, 0); 924 splx(s); 925 926 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 927 928 /* Delete all remaining media. */ 929 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 930 931 ether_ifdetach(ifp); 932 if_detach(ifp); 933 alc_dma_free(sc); 934 935 alc_phy_down(sc); 936 if (sc->sc_irq_handle != NULL) { 937 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 938 sc->sc_irq_handle = NULL; 939 } 940 if (sc->sc_mem_size) { 941 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 942 sc->sc_mem_size = 0; 943 } 944 945 return (0); 946 } 947 948 static int 949 alc_dma_alloc(struct alc_softc *sc) 950 { 951 struct alc_txdesc *txd; 952 struct alc_rxdesc *rxd; 953 int nsegs, error, i; 954 955 /* 956 * Create DMA stuffs for TX ring 957 */ 958 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 959 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 960 if (error) { 961 sc->alc_cdata.alc_tx_ring_map = NULL; 962 return (ENOBUFS); 963 } 964 965 /* Allocate DMA'able memory for TX ring */ 966 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 967 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 968 &nsegs, BUS_DMA_NOWAIT); 969 if (error) { 970 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 971 device_xname(sc->sc_dev)); 972 return error; 973 } 974 975 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 976 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 977 BUS_DMA_NOWAIT); 978 if (error) 979 return (ENOBUFS); 980 981 /* Load the DMA map for Tx ring. */ 982 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 983 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 984 if (error) { 985 printf("%s: could not load DMA'able memory for Tx ring.\n", 986 device_xname(sc->sc_dev)); 987 bus_dmamem_free(sc->sc_dmat, 988 &sc->alc_rdata.alc_tx_ring_seg, 1); 989 return error; 990 } 991 992 sc->alc_rdata.alc_tx_ring_paddr = 993 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 994 995 /* 996 * Create DMA stuffs for RX ring 997 */ 998 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 999 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1000 if (error) 1001 return (ENOBUFS); 1002 1003 /* Allocate DMA'able memory for RX ring */ 1004 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1005 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1006 &nsegs, BUS_DMA_NOWAIT); 1007 if (error) { 1008 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1009 device_xname(sc->sc_dev)); 1010 return error; 1011 } 1012 1013 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1014 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1015 BUS_DMA_NOWAIT); 1016 if (error) 1017 return (ENOBUFS); 1018 1019 /* Load the DMA map for Rx ring. */ 1020 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1021 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1022 if (error) { 1023 printf("%s: could not load DMA'able memory for Rx ring.\n", 1024 device_xname(sc->sc_dev)); 1025 bus_dmamem_free(sc->sc_dmat, 1026 &sc->alc_rdata.alc_rx_ring_seg, 1); 1027 return error; 1028 } 1029 1030 sc->alc_rdata.alc_rx_ring_paddr = 1031 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1032 1033 /* 1034 * Create DMA stuffs for RX return ring 1035 */ 1036 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1037 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1038 if (error) 1039 return (ENOBUFS); 1040 1041 /* Allocate DMA'able memory for RX return ring */ 1042 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1043 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1044 &nsegs, BUS_DMA_NOWAIT); 1045 if (error) { 1046 printf("%s: could not allocate DMA'able memory for Rx " 1047 "return ring.\n", device_xname(sc->sc_dev)); 1048 return error; 1049 } 1050 1051 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1052 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1053 BUS_DMA_NOWAIT); 1054 if (error) 1055 return (ENOBUFS); 1056 1057 /* Load the DMA map for Rx return ring. */ 1058 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1059 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1060 if (error) { 1061 printf("%s: could not load DMA'able memory for Rx return ring." 1062 "\n", device_xname(sc->sc_dev)); 1063 bus_dmamem_free(sc->sc_dmat, 1064 &sc->alc_rdata.alc_rr_ring_seg, 1); 1065 return error; 1066 } 1067 1068 sc->alc_rdata.alc_rr_ring_paddr = 1069 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1070 1071 /* 1072 * Create DMA stuffs for CMB block 1073 */ 1074 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1075 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1076 &sc->alc_cdata.alc_cmb_map); 1077 if (error) 1078 return (ENOBUFS); 1079 1080 /* Allocate DMA'able memory for CMB block */ 1081 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1082 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1083 &nsegs, BUS_DMA_NOWAIT); 1084 if (error) { 1085 printf("%s: could not allocate DMA'able memory for " 1086 "CMB block\n", device_xname(sc->sc_dev)); 1087 return error; 1088 } 1089 1090 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1091 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1092 BUS_DMA_NOWAIT); 1093 if (error) 1094 return (ENOBUFS); 1095 1096 /* Load the DMA map for CMB block. */ 1097 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1098 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1099 BUS_DMA_WAITOK); 1100 if (error) { 1101 printf("%s: could not load DMA'able memory for CMB block\n", 1102 device_xname(sc->sc_dev)); 1103 bus_dmamem_free(sc->sc_dmat, 1104 &sc->alc_rdata.alc_cmb_seg, 1); 1105 return error; 1106 } 1107 1108 sc->alc_rdata.alc_cmb_paddr = 1109 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1110 1111 /* 1112 * Create DMA stuffs for SMB block 1113 */ 1114 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1115 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1116 &sc->alc_cdata.alc_smb_map); 1117 if (error) 1118 return (ENOBUFS); 1119 1120 /* Allocate DMA'able memory for SMB block */ 1121 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1122 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1123 &nsegs, BUS_DMA_NOWAIT); 1124 if (error) { 1125 printf("%s: could not allocate DMA'able memory for " 1126 "SMB block\n", device_xname(sc->sc_dev)); 1127 return error; 1128 } 1129 1130 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1131 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1132 BUS_DMA_NOWAIT); 1133 if (error) 1134 return (ENOBUFS); 1135 1136 /* Load the DMA map for SMB block */ 1137 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1138 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1139 BUS_DMA_WAITOK); 1140 if (error) { 1141 printf("%s: could not load DMA'able memory for SMB block\n", 1142 device_xname(sc->sc_dev)); 1143 bus_dmamem_free(sc->sc_dmat, 1144 &sc->alc_rdata.alc_smb_seg, 1); 1145 return error; 1146 } 1147 1148 sc->alc_rdata.alc_smb_paddr = 1149 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1150 1151 1152 /* Create DMA maps for Tx buffers. */ 1153 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1154 txd = &sc->alc_cdata.alc_txdesc[i]; 1155 txd->tx_m = NULL; 1156 txd->tx_dmamap = NULL; 1157 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1158 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1159 &txd->tx_dmamap); 1160 if (error) { 1161 printf("%s: could not create Tx dmamap.\n", 1162 device_xname(sc->sc_dev)); 1163 return error; 1164 } 1165 } 1166 1167 /* Create DMA maps for Rx buffers. */ 1168 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1169 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1170 if (error) { 1171 printf("%s: could not create spare Rx dmamap.\n", 1172 device_xname(sc->sc_dev)); 1173 return error; 1174 } 1175 1176 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1177 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1178 rxd->rx_m = NULL; 1179 rxd->rx_dmamap = NULL; 1180 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1181 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1182 if (error) { 1183 printf("%s: could not create Rx dmamap.\n", 1184 device_xname(sc->sc_dev)); 1185 return error; 1186 } 1187 } 1188 1189 return (0); 1190 } 1191 1192 1193 static void 1194 alc_dma_free(struct alc_softc *sc) 1195 { 1196 struct alc_txdesc *txd; 1197 struct alc_rxdesc *rxd; 1198 int i; 1199 1200 /* Tx buffers */ 1201 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1202 txd = &sc->alc_cdata.alc_txdesc[i]; 1203 if (txd->tx_dmamap != NULL) { 1204 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1205 txd->tx_dmamap = NULL; 1206 } 1207 } 1208 /* Rx buffers */ 1209 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1210 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1211 if (rxd->rx_dmamap != NULL) { 1212 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1213 rxd->rx_dmamap = NULL; 1214 } 1215 } 1216 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1217 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1218 sc->alc_cdata.alc_rx_sparemap = NULL; 1219 } 1220 1221 /* Tx ring. */ 1222 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1223 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1224 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1225 sc->alc_rdata.alc_tx_ring != NULL) 1226 bus_dmamem_free(sc->sc_dmat, 1227 &sc->alc_rdata.alc_tx_ring_seg, 1); 1228 sc->alc_rdata.alc_tx_ring = NULL; 1229 sc->alc_cdata.alc_tx_ring_map = NULL; 1230 1231 /* Rx ring. */ 1232 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1233 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1234 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1235 sc->alc_rdata.alc_rx_ring != NULL) 1236 bus_dmamem_free(sc->sc_dmat, 1237 &sc->alc_rdata.alc_rx_ring_seg, 1); 1238 sc->alc_rdata.alc_rx_ring = NULL; 1239 sc->alc_cdata.alc_rx_ring_map = NULL; 1240 1241 /* Rx return ring. */ 1242 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1243 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1244 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1245 sc->alc_rdata.alc_rr_ring != NULL) 1246 bus_dmamem_free(sc->sc_dmat, 1247 &sc->alc_rdata.alc_rr_ring_seg, 1); 1248 sc->alc_rdata.alc_rr_ring = NULL; 1249 sc->alc_cdata.alc_rr_ring_map = NULL; 1250 1251 /* CMB block */ 1252 if (sc->alc_cdata.alc_cmb_map != NULL) 1253 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1254 if (sc->alc_cdata.alc_cmb_map != NULL && 1255 sc->alc_rdata.alc_cmb != NULL) 1256 bus_dmamem_free(sc->sc_dmat, 1257 &sc->alc_rdata.alc_cmb_seg, 1); 1258 sc->alc_rdata.alc_cmb = NULL; 1259 sc->alc_cdata.alc_cmb_map = NULL; 1260 1261 /* SMB block */ 1262 if (sc->alc_cdata.alc_smb_map != NULL) 1263 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1264 if (sc->alc_cdata.alc_smb_map != NULL && 1265 sc->alc_rdata.alc_smb != NULL) 1266 bus_dmamem_free(sc->sc_dmat, 1267 &sc->alc_rdata.alc_smb_seg, 1); 1268 sc->alc_rdata.alc_smb = NULL; 1269 sc->alc_cdata.alc_smb_map = NULL; 1270 } 1271 1272 static int 1273 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1274 { 1275 struct alc_txdesc *txd, *txd_last; 1276 struct tx_desc *desc; 1277 struct mbuf *m; 1278 bus_dmamap_t map; 1279 uint32_t cflags, poff, vtag; 1280 int error, idx, nsegs, prod; 1281 #if NVLAN > 0 1282 struct m_tag *mtag; 1283 #endif 1284 1285 m = *m_head; 1286 cflags = vtag = 0; 1287 poff = 0; 1288 1289 prod = sc->alc_cdata.alc_tx_prod; 1290 txd = &sc->alc_cdata.alc_txdesc[prod]; 1291 txd_last = txd; 1292 map = txd->tx_dmamap; 1293 1294 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1295 1296 if (error == EFBIG) { 1297 error = 0; 1298 1299 *m_head = m_pullup(*m_head, MHLEN); 1300 if (*m_head == NULL) { 1301 printf("%s: can't defrag TX mbuf\n", 1302 device_xname(sc->sc_dev)); 1303 return ENOBUFS; 1304 } 1305 1306 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1307 BUS_DMA_NOWAIT); 1308 1309 if (error != 0) { 1310 printf("%s: could not load defragged TX mbuf\n", 1311 device_xname(sc->sc_dev)); 1312 m_freem(*m_head); 1313 *m_head = NULL; 1314 return error; 1315 } 1316 } else if (error) { 1317 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1318 return (error); 1319 } 1320 1321 nsegs = map->dm_nsegs; 1322 1323 if (nsegs == 0) { 1324 m_freem(*m_head); 1325 *m_head = NULL; 1326 return (EIO); 1327 } 1328 1329 /* Check descriptor overrun. */ 1330 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1331 bus_dmamap_unload(sc->sc_dmat, map); 1332 return (ENOBUFS); 1333 } 1334 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1335 BUS_DMASYNC_PREWRITE); 1336 1337 m = *m_head; 1338 desc = NULL; 1339 idx = 0; 1340 #if NVLAN > 0 1341 /* Configure VLAN hardware tag insertion. */ 1342 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1343 vtag = htons(VLAN_TAG_VALUE(mtag)); 1344 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1345 cflags |= TD_INS_VLAN_TAG; 1346 } 1347 #endif 1348 /* Configure Tx checksum offload. */ 1349 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1350 cflags |= TD_CUSTOM_CSUM; 1351 /* Set checksum start offset. */ 1352 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1353 TD_PLOAD_OFFSET_MASK; 1354 } 1355 for (; idx < nsegs; idx++) { 1356 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1357 desc->len = 1358 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1359 desc->flags = htole32(cflags); 1360 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1361 sc->alc_cdata.alc_tx_cnt++; 1362 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1363 } 1364 /* Update producer index. */ 1365 sc->alc_cdata.alc_tx_prod = prod; 1366 1367 /* Finally set EOP on the last descriptor. */ 1368 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1369 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1370 desc->flags |= htole32(TD_EOP); 1371 1372 /* Swap dmamap of the first and the last. */ 1373 txd = &sc->alc_cdata.alc_txdesc[prod]; 1374 map = txd_last->tx_dmamap; 1375 txd_last->tx_dmamap = txd->tx_dmamap; 1376 txd->tx_dmamap = map; 1377 txd->tx_m = m; 1378 1379 return (0); 1380 } 1381 1382 static void 1383 alc_start(struct ifnet *ifp) 1384 { 1385 struct alc_softc *sc = ifp->if_softc; 1386 struct mbuf *m_head; 1387 int enq; 1388 1389 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1390 return; 1391 1392 /* Reclaim transmitted frames. */ 1393 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1394 alc_txeof(sc); 1395 1396 enq = 0; 1397 for (;;) { 1398 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1399 if (m_head == NULL) 1400 break; 1401 1402 /* 1403 * Pack the data into the transmit ring. If we 1404 * don't have room, set the OACTIVE flag and wait 1405 * for the NIC to drain the ring. 1406 */ 1407 if (alc_encap(sc, &m_head)) { 1408 if (m_head == NULL) 1409 break; 1410 ifp->if_flags |= IFF_OACTIVE; 1411 break; 1412 } 1413 enq = 1; 1414 1415 /* 1416 * If there's a BPF listener, bounce a copy of this frame 1417 * to him. 1418 */ 1419 bpf_mtap(ifp, m_head); 1420 } 1421 1422 if (enq) { 1423 /* Sync descriptors. */ 1424 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1425 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1426 BUS_DMASYNC_PREWRITE); 1427 /* Kick. Assume we're using normal Tx priority queue. */ 1428 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1429 (sc->alc_cdata.alc_tx_prod << 1430 MBOX_TD_PROD_LO_IDX_SHIFT) & 1431 MBOX_TD_PROD_LO_IDX_MASK); 1432 /* Set a timeout in case the chip goes out to lunch. */ 1433 ifp->if_timer = ALC_TX_TIMEOUT; 1434 } 1435 } 1436 1437 static void 1438 alc_watchdog(struct ifnet *ifp) 1439 { 1440 struct alc_softc *sc = ifp->if_softc; 1441 1442 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1443 printf("%s: watchdog timeout (missed link)\n", 1444 device_xname(sc->sc_dev)); 1445 ifp->if_oerrors++; 1446 alc_init_backend(ifp, false); 1447 return; 1448 } 1449 1450 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1451 ifp->if_oerrors++; 1452 alc_init_backend(ifp, false); 1453 1454 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1455 alc_start(ifp); 1456 } 1457 1458 static int 1459 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1460 { 1461 struct alc_softc *sc = ifp->if_softc; 1462 int s, error = 0; 1463 1464 s = splnet(); 1465 1466 error = ether_ioctl(ifp, cmd, data); 1467 if (error == ENETRESET) { 1468 if (ifp->if_flags & IFF_RUNNING) 1469 alc_iff(sc); 1470 error = 0; 1471 } 1472 1473 splx(s); 1474 return (error); 1475 } 1476 1477 static void 1478 alc_mac_config(struct alc_softc *sc) 1479 { 1480 struct mii_data *mii; 1481 uint32_t reg; 1482 1483 mii = &sc->sc_miibus; 1484 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1485 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1486 MAC_CFG_SPEED_MASK); 1487 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 1488 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 1489 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 1490 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 1491 /* Reprogram MAC with resolved speed/duplex. */ 1492 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1493 case IFM_10_T: 1494 case IFM_100_TX: 1495 reg |= MAC_CFG_SPEED_10_100; 1496 break; 1497 case IFM_1000_T: 1498 reg |= MAC_CFG_SPEED_1000; 1499 break; 1500 } 1501 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1502 reg |= MAC_CFG_FULL_DUPLEX; 1503 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1504 reg |= MAC_CFG_TX_FC; 1505 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1506 reg |= MAC_CFG_RX_FC; 1507 } 1508 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1509 } 1510 1511 static void 1512 alc_stats_clear(struct alc_softc *sc) 1513 { 1514 struct smb sb, *smb; 1515 uint32_t *reg; 1516 int i; 1517 1518 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1519 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1520 sc->alc_cdata.alc_smb_map->dm_mapsize, 1521 BUS_DMASYNC_POSTREAD); 1522 smb = sc->alc_rdata.alc_smb; 1523 /* Update done, clear. */ 1524 smb->updated = 0; 1525 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1526 sc->alc_cdata.alc_smb_map->dm_mapsize, 1527 BUS_DMASYNC_PREWRITE); 1528 } else { 1529 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1530 reg++) { 1531 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1532 i += sizeof(uint32_t); 1533 } 1534 /* Read Tx statistics. */ 1535 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1536 reg++) { 1537 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1538 i += sizeof(uint32_t); 1539 } 1540 } 1541 } 1542 1543 static void 1544 alc_stats_update(struct alc_softc *sc) 1545 { 1546 struct ifnet *ifp = &sc->sc_ec.ec_if; 1547 struct alc_hw_stats *stat; 1548 struct smb sb, *smb; 1549 uint32_t *reg; 1550 int i; 1551 1552 stat = &sc->alc_stats; 1553 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1554 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1555 sc->alc_cdata.alc_smb_map->dm_mapsize, 1556 BUS_DMASYNC_POSTREAD); 1557 smb = sc->alc_rdata.alc_smb; 1558 if (smb->updated == 0) 1559 return; 1560 } else { 1561 smb = &sb; 1562 /* Read Rx statistics. */ 1563 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1564 reg++) { 1565 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1566 i += sizeof(uint32_t); 1567 } 1568 /* Read Tx statistics. */ 1569 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1570 reg++) { 1571 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1572 i += sizeof(uint32_t); 1573 } 1574 } 1575 1576 /* Rx stats. */ 1577 stat->rx_frames += smb->rx_frames; 1578 stat->rx_bcast_frames += smb->rx_bcast_frames; 1579 stat->rx_mcast_frames += smb->rx_mcast_frames; 1580 stat->rx_pause_frames += smb->rx_pause_frames; 1581 stat->rx_control_frames += smb->rx_control_frames; 1582 stat->rx_crcerrs += smb->rx_crcerrs; 1583 stat->rx_lenerrs += smb->rx_lenerrs; 1584 stat->rx_bytes += smb->rx_bytes; 1585 stat->rx_runts += smb->rx_runts; 1586 stat->rx_fragments += smb->rx_fragments; 1587 stat->rx_pkts_64 += smb->rx_pkts_64; 1588 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1589 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1590 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1591 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1592 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1593 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1594 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1595 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1596 stat->rx_rrs_errs += smb->rx_rrs_errs; 1597 stat->rx_alignerrs += smb->rx_alignerrs; 1598 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1599 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1600 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1601 1602 /* Tx stats. */ 1603 stat->tx_frames += smb->tx_frames; 1604 stat->tx_bcast_frames += smb->tx_bcast_frames; 1605 stat->tx_mcast_frames += smb->tx_mcast_frames; 1606 stat->tx_pause_frames += smb->tx_pause_frames; 1607 stat->tx_excess_defer += smb->tx_excess_defer; 1608 stat->tx_control_frames += smb->tx_control_frames; 1609 stat->tx_deferred += smb->tx_deferred; 1610 stat->tx_bytes += smb->tx_bytes; 1611 stat->tx_pkts_64 += smb->tx_pkts_64; 1612 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1613 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1614 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1615 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1616 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1617 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1618 stat->tx_single_colls += smb->tx_single_colls; 1619 stat->tx_multi_colls += smb->tx_multi_colls; 1620 stat->tx_late_colls += smb->tx_late_colls; 1621 stat->tx_excess_colls += smb->tx_excess_colls; 1622 stat->tx_abort += smb->tx_abort; 1623 stat->tx_underrun += smb->tx_underrun; 1624 stat->tx_desc_underrun += smb->tx_desc_underrun; 1625 stat->tx_lenerrs += smb->tx_lenerrs; 1626 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1627 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1628 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1629 1630 /* Update counters in ifnet. */ 1631 ifp->if_opackets += smb->tx_frames; 1632 1633 ifp->if_collisions += smb->tx_single_colls + 1634 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1635 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1636 1637 /* 1638 * XXX 1639 * tx_pkts_truncated counter looks suspicious. It constantly 1640 * increments with no sign of Tx errors. This may indicate 1641 * the counter name is not correct one so I've removed the 1642 * counter in output errors. 1643 */ 1644 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1645 smb->tx_underrun; 1646 1647 ifp->if_ipackets += smb->rx_frames; 1648 1649 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1650 smb->rx_runts + smb->rx_pkts_truncated + 1651 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1652 smb->rx_alignerrs; 1653 1654 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1655 /* Update done, clear. */ 1656 smb->updated = 0; 1657 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1658 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1659 } 1660 } 1661 1662 static int 1663 alc_intr(void *arg) 1664 { 1665 struct alc_softc *sc = arg; 1666 struct ifnet *ifp = &sc->sc_ec.ec_if; 1667 uint32_t status; 1668 1669 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1670 if ((status & ALC_INTRS) == 0) 1671 return (0); 1672 1673 /* Acknowledge and disable interrupts. */ 1674 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 1675 1676 if (ifp->if_flags & IFF_RUNNING) { 1677 if (status & INTR_RX_PKT) { 1678 int error; 1679 1680 error = alc_rxintr(sc); 1681 if (error) { 1682 alc_init_backend(ifp, false); 1683 return (0); 1684 } 1685 } 1686 1687 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 1688 INTR_TXQ_TO_RST)) { 1689 if (status & INTR_DMA_RD_TO_RST) 1690 printf("%s: DMA read error! -- resetting\n", 1691 device_xname(sc->sc_dev)); 1692 if (status & INTR_DMA_WR_TO_RST) 1693 printf("%s: DMA write error! -- resetting\n", 1694 device_xname(sc->sc_dev)); 1695 if (status & INTR_TXQ_TO_RST) 1696 printf("%s: TxQ reset! -- resetting\n", 1697 device_xname(sc->sc_dev)); 1698 alc_init_backend(ifp, false); 1699 return (0); 1700 } 1701 1702 alc_txeof(sc); 1703 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1704 alc_start(ifp); 1705 } 1706 1707 /* Re-enable interrupts. */ 1708 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 1709 return (1); 1710 } 1711 1712 static void 1713 alc_txeof(struct alc_softc *sc) 1714 { 1715 struct ifnet *ifp = &sc->sc_ec.ec_if; 1716 struct alc_txdesc *txd; 1717 uint32_t cons, prod; 1718 int prog; 1719 1720 if (sc->alc_cdata.alc_tx_cnt == 0) 1721 return; 1722 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1723 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1724 BUS_DMASYNC_POSTREAD); 1725 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 1726 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1727 sc->alc_cdata.alc_cmb_map->dm_mapsize, 1728 BUS_DMASYNC_POSTREAD); 1729 prod = sc->alc_rdata.alc_cmb->cons; 1730 } else 1731 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 1732 /* Assume we're using normal Tx priority queue. */ 1733 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 1734 MBOX_TD_CONS_LO_IDX_SHIFT; 1735 cons = sc->alc_cdata.alc_tx_cons; 1736 /* 1737 * Go through our Tx list and free mbufs for those 1738 * frames which have been transmitted. 1739 */ 1740 for (prog = 0; cons != prod; prog++, 1741 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 1742 if (sc->alc_cdata.alc_tx_cnt <= 0) 1743 break; 1744 prog++; 1745 ifp->if_flags &= ~IFF_OACTIVE; 1746 sc->alc_cdata.alc_tx_cnt--; 1747 txd = &sc->alc_cdata.alc_txdesc[cons]; 1748 if (txd->tx_m != NULL) { 1749 /* Reclaim transmitted mbufs. */ 1750 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1751 m_freem(txd->tx_m); 1752 txd->tx_m = NULL; 1753 } 1754 } 1755 1756 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 1757 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1758 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1759 sc->alc_cdata.alc_tx_cons = cons; 1760 /* 1761 * Unarm watchdog timer only when there is no pending 1762 * frames in Tx queue. 1763 */ 1764 if (sc->alc_cdata.alc_tx_cnt == 0) 1765 ifp->if_timer = 0; 1766 } 1767 1768 static int 1769 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 1770 { 1771 struct mbuf *m; 1772 bus_dmamap_t map; 1773 int error; 1774 1775 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1776 if (m == NULL) 1777 return (ENOBUFS); 1778 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 1779 if (!(m->m_flags & M_EXT)) { 1780 m_freem(m); 1781 return (ENOBUFS); 1782 } 1783 1784 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 1785 1786 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1787 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 1788 1789 if (error != 0) { 1790 if (!error) { 1791 bus_dmamap_unload(sc->sc_dmat, 1792 sc->alc_cdata.alc_rx_sparemap); 1793 error = EFBIG; 1794 printf("%s: too many segments?!\n", 1795 device_xname(sc->sc_dev)); 1796 } 1797 m_freem(m); 1798 1799 if (init) 1800 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 1801 1802 return (error); 1803 } 1804 1805 if (rxd->rx_m != NULL) { 1806 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1807 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1808 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1809 } 1810 map = rxd->rx_dmamap; 1811 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 1812 sc->alc_cdata.alc_rx_sparemap = map; 1813 rxd->rx_m = m; 1814 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 1815 return (0); 1816 } 1817 1818 static int 1819 alc_rxintr(struct alc_softc *sc) 1820 { 1821 struct ifnet *ifp = &sc->sc_ec.ec_if; 1822 struct rx_rdesc *rrd; 1823 uint32_t nsegs, status; 1824 int rr_cons, prog; 1825 1826 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1827 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1828 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1829 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1830 rr_cons = sc->alc_cdata.alc_rr_cons; 1831 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 1832 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 1833 status = le32toh(rrd->status); 1834 if ((status & RRD_VALID) == 0) 1835 break; 1836 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 1837 if (nsegs == 0) { 1838 /* This should not happen! */ 1839 if (alcdebug) 1840 printf("%s: unexpected segment count -- " 1841 "resetting\n", device_xname(sc->sc_dev)); 1842 return (EIO); 1843 } 1844 alc_rxeof(sc, rrd); 1845 /* Clear Rx return status. */ 1846 rrd->status = 0; 1847 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 1848 sc->alc_cdata.alc_rx_cons += nsegs; 1849 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 1850 prog += nsegs; 1851 } 1852 1853 if (prog > 0) { 1854 /* Update the consumer index. */ 1855 sc->alc_cdata.alc_rr_cons = rr_cons; 1856 /* Sync Rx return descriptors. */ 1857 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1858 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1859 BUS_DMASYNC_PREWRITE); 1860 /* 1861 * Sync updated Rx descriptors such that controller see 1862 * modified buffer addresses. 1863 */ 1864 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1865 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1866 BUS_DMASYNC_PREWRITE); 1867 /* 1868 * Let controller know availability of new Rx buffers. 1869 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 1870 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 1871 * only when Rx buffer pre-fetching is required. In 1872 * addition we already set ALC_RX_RD_FREE_THRESH to 1873 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 1874 * it still seems that pre-fetching needs more 1875 * experimentation. 1876 */ 1877 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1878 sc->alc_cdata.alc_rx_cons); 1879 } 1880 1881 return (0); 1882 } 1883 1884 /* Receive a frame. */ 1885 static void 1886 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 1887 { 1888 struct ifnet *ifp = &sc->sc_ec.ec_if; 1889 struct alc_rxdesc *rxd; 1890 struct mbuf *mp, *m; 1891 uint32_t rdinfo, status; 1892 int count, nsegs, rx_cons; 1893 1894 status = le32toh(rrd->status); 1895 rdinfo = le32toh(rrd->rdinfo); 1896 rx_cons = RRD_RD_IDX(rdinfo); 1897 nsegs = RRD_RD_CNT(rdinfo); 1898 1899 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 1900 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 1901 /* 1902 * We want to pass the following frames to upper 1903 * layer regardless of error status of Rx return 1904 * ring. 1905 * 1906 * o IP/TCP/UDP checksum is bad. 1907 * o frame length and protocol specific length 1908 * does not match. 1909 * 1910 * Force network stack compute checksum for 1911 * errored frames. 1912 */ 1913 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 1914 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 1915 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 1916 return; 1917 } 1918 1919 for (count = 0; count < nsegs; count++, 1920 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 1921 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 1922 mp = rxd->rx_m; 1923 /* Add a new receive buffer to the ring. */ 1924 if (alc_newbuf(sc, rxd, false) != 0) { 1925 ifp->if_iqdrops++; 1926 /* Reuse Rx buffers. */ 1927 if (sc->alc_cdata.alc_rxhead != NULL) 1928 m_freem(sc->alc_cdata.alc_rxhead); 1929 break; 1930 } 1931 1932 /* 1933 * Assume we've received a full sized frame. 1934 * Actual size is fixed when we encounter the end of 1935 * multi-segmented frame. 1936 */ 1937 mp->m_len = sc->alc_buf_size; 1938 1939 /* Chain received mbufs. */ 1940 if (sc->alc_cdata.alc_rxhead == NULL) { 1941 sc->alc_cdata.alc_rxhead = mp; 1942 sc->alc_cdata.alc_rxtail = mp; 1943 } else { 1944 mp->m_flags &= ~M_PKTHDR; 1945 sc->alc_cdata.alc_rxprev_tail = 1946 sc->alc_cdata.alc_rxtail; 1947 sc->alc_cdata.alc_rxtail->m_next = mp; 1948 sc->alc_cdata.alc_rxtail = mp; 1949 } 1950 1951 if (count == nsegs - 1) { 1952 /* Last desc. for this frame. */ 1953 m = sc->alc_cdata.alc_rxhead; 1954 m->m_flags |= M_PKTHDR; 1955 /* 1956 * It seems that L1C/L2C controller has no way 1957 * to tell hardware to strip CRC bytes. 1958 */ 1959 m->m_pkthdr.len = 1960 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 1961 if (nsegs > 1) { 1962 /* Set last mbuf size. */ 1963 mp->m_len = sc->alc_cdata.alc_rxlen - 1964 (nsegs - 1) * sc->alc_buf_size; 1965 /* Remove the CRC bytes in chained mbufs. */ 1966 if (mp->m_len <= ETHER_CRC_LEN) { 1967 sc->alc_cdata.alc_rxtail = 1968 sc->alc_cdata.alc_rxprev_tail; 1969 sc->alc_cdata.alc_rxtail->m_len -= 1970 (ETHER_CRC_LEN - mp->m_len); 1971 sc->alc_cdata.alc_rxtail->m_next = NULL; 1972 m_freem(mp); 1973 } else { 1974 mp->m_len -= ETHER_CRC_LEN; 1975 } 1976 } else 1977 m->m_len = m->m_pkthdr.len; 1978 m->m_pkthdr.rcvif = ifp; 1979 #if NVLAN > 0 1980 /* 1981 * Due to hardware bugs, Rx checksum offloading 1982 * was intentionally disabled. 1983 */ 1984 if (status & RRD_VLAN_TAG) { 1985 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 1986 VLAN_INPUT_TAG(ifp, m, ntohs(vtag), ); 1987 } 1988 #endif 1989 1990 bpf_mtap(ifp, m); 1991 1992 { 1993 /* Pass it on. */ 1994 ether_input(ifp, m); 1995 } 1996 } 1997 } 1998 /* Reset mbuf chains. */ 1999 ALC_RXCHAIN_RESET(sc); 2000 } 2001 2002 static void 2003 alc_tick(void *xsc) 2004 { 2005 struct alc_softc *sc = xsc; 2006 struct mii_data *mii = &sc->sc_miibus; 2007 int s; 2008 2009 s = splnet(); 2010 mii_tick(mii); 2011 alc_stats_update(sc); 2012 splx(s); 2013 2014 callout_schedule(&sc->sc_tick_ch, hz); 2015 } 2016 2017 static void 2018 alc_reset(struct alc_softc *sc) 2019 { 2020 uint32_t reg; 2021 int i; 2022 2023 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 2024 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2025 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2026 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2027 DELAY(10); 2028 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2029 break; 2030 } 2031 if (i == 0) 2032 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2033 2034 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2035 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2036 break; 2037 DELAY(10); 2038 } 2039 2040 if (i == 0) 2041 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 2042 reg); 2043 } 2044 2045 static int 2046 alc_init(struct ifnet *ifp) 2047 { 2048 2049 return alc_init_backend(ifp, true); 2050 } 2051 2052 static int 2053 alc_init_backend(struct ifnet *ifp, bool init) 2054 { 2055 struct alc_softc *sc = ifp->if_softc; 2056 struct mii_data *mii; 2057 uint8_t eaddr[ETHER_ADDR_LEN]; 2058 bus_addr_t paddr; 2059 uint32_t reg, rxf_hi, rxf_lo; 2060 int error; 2061 2062 /* 2063 * Cancel any pending I/O. 2064 */ 2065 alc_stop(ifp, 0); 2066 /* 2067 * Reset the chip to a known state. 2068 */ 2069 alc_reset(sc); 2070 2071 /* Initialize Rx descriptors. */ 2072 error = alc_init_rx_ring(sc, init); 2073 if (error != 0) { 2074 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2075 alc_stop(ifp, 0); 2076 return (error); 2077 } 2078 alc_init_rr_ring(sc); 2079 alc_init_tx_ring(sc); 2080 alc_init_cmb(sc); 2081 alc_init_smb(sc); 2082 2083 /* Enable all clocks. */ 2084 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2085 2086 /* Reprogram the station address. */ 2087 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2088 CSR_WRITE_4(sc, ALC_PAR0, 2089 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2090 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2091 /* 2092 * Clear WOL status and disable all WOL feature as WOL 2093 * would interfere Rx operation under normal environments. 2094 */ 2095 CSR_READ_4(sc, ALC_WOL_CFG); 2096 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2097 /* Set Tx descriptor base addresses. */ 2098 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2099 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2100 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2101 /* We don't use high priority ring. */ 2102 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2103 /* Set Tx descriptor counter. */ 2104 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2105 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2106 /* Set Rx descriptor base addresses. */ 2107 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2108 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2109 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2110 /* We use one Rx ring. */ 2111 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2112 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2113 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2114 /* Set Rx descriptor counter. */ 2115 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2116 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2117 2118 /* 2119 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2120 * if it do not fit the buffer size. Rx return descriptor holds 2121 * a counter that indicates how many fragments were made by the 2122 * hardware. The buffer size should be multiple of 8 bytes. 2123 * Since hardware has limit on the size of buffer size, always 2124 * use the maximum value. 2125 * For strict-alignment architectures make sure to reduce buffer 2126 * size by 8 bytes to make room for alignment fixup. 2127 */ 2128 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2129 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2130 2131 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2132 /* Set Rx return descriptor base addresses. */ 2133 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2134 /* We use one Rx return ring. */ 2135 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2136 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2137 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2138 /* Set Rx return descriptor counter. */ 2139 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2140 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2141 paddr = sc->alc_rdata.alc_cmb_paddr; 2142 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2143 paddr = sc->alc_rdata.alc_smb_paddr; 2144 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2145 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2146 2147 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2148 /* Reconfigure SRAM - Vendor magic. */ 2149 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2150 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2151 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2152 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2153 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2154 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2155 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2156 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2157 } 2158 2159 /* Tell hardware that we're ready to load DMA blocks. */ 2160 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2161 2162 /* Configure interrupt moderation timer. */ 2163 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2164 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2165 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2166 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2167 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2168 /* 2169 * We don't want to automatic interrupt clear as task queue 2170 * for the interrupt should know interrupt status. 2171 */ 2172 reg = MASTER_SA_TIMER_ENB; 2173 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2174 reg |= MASTER_IM_RX_TIMER_ENB; 2175 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 2176 reg |= MASTER_IM_TX_TIMER_ENB; 2177 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2178 /* 2179 * Disable interrupt re-trigger timer. We don't want automatic 2180 * re-triggering of un-ACKed interrupts. 2181 */ 2182 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2183 /* Configure CMB. */ 2184 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2185 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2186 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2187 else 2188 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2189 /* 2190 * Hardware can be configured to issue SMB interrupt based 2191 * on programmed interval. Since there is a callout that is 2192 * invoked for every hz in driver we use that instead of 2193 * relying on periodic SMB interrupt. 2194 */ 2195 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2196 /* Clear MAC statistics. */ 2197 alc_stats_clear(sc); 2198 2199 /* 2200 * Always use maximum frame size that controller can support. 2201 * Otherwise received frames that has larger frame length 2202 * than alc(4) MTU would be silently dropped in hardware. This 2203 * would make path-MTU discovery hard as sender wouldn't get 2204 * any responses from receiver. alc(4) supports 2205 * multi-fragmented frames on Rx path so it has no issue on 2206 * assembling fragmented frames. Using maximum frame size also 2207 * removes the need to reinitialize hardware when interface 2208 * MTU configuration was changed. 2209 * 2210 * Be conservative in what you do, be liberal in what you 2211 * accept from others - RFC 793. 2212 */ 2213 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2214 2215 /* Disable header split(?) */ 2216 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2217 2218 /* Configure IPG/IFG parameters. */ 2219 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2220 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2221 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2222 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2223 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2224 /* Set parameters for half-duplex media. */ 2225 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2226 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2227 HDPX_CFG_LCOL_MASK) | 2228 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2229 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2230 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2231 HDPX_CFG_ABEBT_MASK) | 2232 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2233 HDPX_CFG_JAMIPG_MASK)); 2234 /* 2235 * Set TSO/checksum offload threshold. For frames that is 2236 * larger than this threshold, hardware wouldn't do 2237 * TSO/checksum offloading. 2238 */ 2239 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 2240 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2241 TSO_OFFLOAD_THRESH_MASK); 2242 /* Configure TxQ. */ 2243 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2244 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2245 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2246 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2247 reg >>= 1; 2248 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2249 TXQ_CFG_TD_BURST_MASK; 2250 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2251 2252 /* Configure Rx free descriptor pre-fetching. */ 2253 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2254 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 2255 RX_RD_FREE_THRESH_HI_MASK) | 2256 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 2257 RX_RD_FREE_THRESH_LO_MASK)); 2258 2259 /* 2260 * Configure flow control parameters. 2261 * XON : 80% of Rx FIFO 2262 * XOFF : 30% of Rx FIFO 2263 */ 2264 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 2265 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 2266 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2267 rxf_hi = (reg * 8) / 10; 2268 rxf_lo = (reg * 3) / 10; 2269 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2270 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2271 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2272 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2273 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2274 } 2275 2276 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2277 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2278 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2279 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2280 SERDES_PHY_CLK_SLOWDOWN); 2281 2282 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2283 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2284 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2285 2286 /* Configure RxQ. */ 2287 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2288 RXQ_CFG_RD_BURST_MASK; 2289 reg |= RXQ_CFG_RSS_MODE_DIS; 2290 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 2291 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 2292 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2293 2294 /* Configure DMA parameters. */ 2295 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2296 reg |= sc->alc_rcb; 2297 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2298 reg |= DMA_CFG_CMB_ENB; 2299 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2300 reg |= DMA_CFG_SMB_ENB; 2301 else 2302 reg |= DMA_CFG_SMB_DIS; 2303 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 2304 DMA_CFG_RD_BURST_SHIFT; 2305 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 2306 DMA_CFG_WR_BURST_SHIFT; 2307 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2308 DMA_CFG_RD_DELAY_CNT_MASK; 2309 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2310 DMA_CFG_WR_DELAY_CNT_MASK; 2311 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2312 2313 /* 2314 * Configure Tx/Rx MACs. 2315 * - Auto-padding for short frames. 2316 * - Enable CRC generation. 2317 * Actual reconfiguration of MAC for resolved speed/duplex 2318 * is followed after detection of link establishment. 2319 * AR813x/AR815x always does checksum computation regardless 2320 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 2321 * have bug in protocol field in Rx return structure so 2322 * these controllers can't handle fragmented frames. Disable 2323 * Rx checksum offloading until there is a newer controller 2324 * that has sane implementation. 2325 */ 2326 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2327 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2328 MAC_CFG_PREAMBLE_MASK); 2329 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2330 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2331 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2332 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2333 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 2334 reg |= MAC_CFG_SPEED_10_100; 2335 else 2336 reg |= MAC_CFG_SPEED_1000; 2337 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2338 2339 /* Set up the receive filter. */ 2340 alc_iff(sc); 2341 alc_rxvlan(sc); 2342 2343 /* Acknowledge all pending interrupts and clear it. */ 2344 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 2345 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2346 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 2347 2348 sc->alc_flags &= ~ALC_FLAG_LINK; 2349 /* Switch to the current media. */ 2350 mii = &sc->sc_miibus; 2351 mii_mediachg(mii); 2352 2353 callout_schedule(&sc->sc_tick_ch, hz); 2354 2355 ifp->if_flags |= IFF_RUNNING; 2356 ifp->if_flags &= ~IFF_OACTIVE; 2357 2358 return (0); 2359 } 2360 2361 static void 2362 alc_stop(struct ifnet *ifp, int disable) 2363 { 2364 struct alc_softc *sc = ifp->if_softc; 2365 struct alc_txdesc *txd; 2366 struct alc_rxdesc *rxd; 2367 uint32_t reg; 2368 int i; 2369 2370 callout_stop(&sc->sc_tick_ch); 2371 2372 /* 2373 * Mark the interface down and cancel the watchdog timer. 2374 */ 2375 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2376 ifp->if_timer = 0; 2377 2378 sc->alc_flags &= ~ALC_FLAG_LINK; 2379 2380 alc_stats_update(sc); 2381 2382 mii_down(&sc->sc_miibus); 2383 2384 /* Disable interrupts. */ 2385 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 2386 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2387 alc_stop_queue(sc); 2388 2389 /* Disable DMA. */ 2390 reg = CSR_READ_4(sc, ALC_DMA_CFG); 2391 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 2392 reg |= DMA_CFG_SMB_DIS; 2393 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2394 DELAY(1000); 2395 2396 /* Stop Rx/Tx MACs. */ 2397 alc_stop_mac(sc); 2398 2399 /* Disable interrupts which might be touched in taskq handler. */ 2400 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2401 2402 /* Reclaim Rx buffers that have been processed. */ 2403 if (sc->alc_cdata.alc_rxhead != NULL) 2404 m_freem(sc->alc_cdata.alc_rxhead); 2405 ALC_RXCHAIN_RESET(sc); 2406 /* 2407 * Free Tx/Rx mbufs still in the queues. 2408 */ 2409 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2410 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2411 if (rxd->rx_m != NULL) { 2412 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2413 m_freem(rxd->rx_m); 2414 rxd->rx_m = NULL; 2415 } 2416 } 2417 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2418 txd = &sc->alc_cdata.alc_txdesc[i]; 2419 if (txd->tx_m != NULL) { 2420 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2421 m_freem(txd->tx_m); 2422 txd->tx_m = NULL; 2423 } 2424 } 2425 } 2426 2427 static void 2428 alc_stop_mac(struct alc_softc *sc) 2429 { 2430 uint32_t reg; 2431 int i; 2432 2433 /* Disable Rx/Tx MAC. */ 2434 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2435 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2436 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2437 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2438 } 2439 for (i = ALC_TIMEOUT; i > 0; i--) { 2440 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2441 if (reg == 0) 2442 break; 2443 DELAY(10); 2444 } 2445 if (i == 0) 2446 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 2447 device_xname(sc->sc_dev), reg); 2448 } 2449 2450 static void 2451 alc_start_queue(struct alc_softc *sc) 2452 { 2453 uint32_t qcfg[] = { 2454 0, 2455 RXQ_CFG_QUEUE0_ENB, 2456 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 2457 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 2458 RXQ_CFG_ENB 2459 }; 2460 uint32_t cfg; 2461 2462 /* Enable RxQ. */ 2463 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 2464 cfg &= ~RXQ_CFG_ENB; 2465 cfg |= qcfg[1]; 2466 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 2467 /* Enable TxQ. */ 2468 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 2469 cfg |= TXQ_CFG_ENB; 2470 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 2471 } 2472 2473 static void 2474 alc_stop_queue(struct alc_softc *sc) 2475 { 2476 uint32_t reg; 2477 int i; 2478 2479 /* Disable RxQ. */ 2480 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 2481 if ((reg & RXQ_CFG_ENB) != 0) { 2482 reg &= ~RXQ_CFG_ENB; 2483 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2484 } 2485 /* Disable TxQ. */ 2486 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 2487 if ((reg & TXQ_CFG_ENB) != 0) { 2488 reg &= ~TXQ_CFG_ENB; 2489 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 2490 } 2491 for (i = ALC_TIMEOUT; i > 0; i--) { 2492 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2493 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2494 break; 2495 DELAY(10); 2496 } 2497 if (i == 0) 2498 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 2499 device_xname(sc->sc_dev), reg); 2500 } 2501 2502 static void 2503 alc_init_tx_ring(struct alc_softc *sc) 2504 { 2505 struct alc_ring_data *rd; 2506 struct alc_txdesc *txd; 2507 int i; 2508 2509 sc->alc_cdata.alc_tx_prod = 0; 2510 sc->alc_cdata.alc_tx_cons = 0; 2511 sc->alc_cdata.alc_tx_cnt = 0; 2512 2513 rd = &sc->alc_rdata; 2514 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 2515 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2516 txd = &sc->alc_cdata.alc_txdesc[i]; 2517 txd->tx_m = NULL; 2518 } 2519 2520 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2521 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2522 } 2523 2524 static int 2525 alc_init_rx_ring(struct alc_softc *sc, bool init) 2526 { 2527 struct alc_ring_data *rd; 2528 struct alc_rxdesc *rxd; 2529 int i; 2530 2531 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 2532 rd = &sc->alc_rdata; 2533 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 2534 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2535 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2536 rxd->rx_m = NULL; 2537 rxd->rx_desc = &rd->alc_rx_ring[i]; 2538 if (alc_newbuf(sc, rxd, init) != 0) 2539 return (ENOBUFS); 2540 } 2541 2542 /* 2543 * Since controller does not update Rx descriptors, driver 2544 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 2545 * is enough to ensure coherence. 2546 */ 2547 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2548 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2549 /* Let controller know availability of new Rx buffers. */ 2550 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 2551 2552 return (0); 2553 } 2554 2555 static void 2556 alc_init_rr_ring(struct alc_softc *sc) 2557 { 2558 struct alc_ring_data *rd; 2559 2560 sc->alc_cdata.alc_rr_cons = 0; 2561 ALC_RXCHAIN_RESET(sc); 2562 2563 rd = &sc->alc_rdata; 2564 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 2565 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2566 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2567 } 2568 2569 static void 2570 alc_init_cmb(struct alc_softc *sc) 2571 { 2572 struct alc_ring_data *rd; 2573 2574 rd = &sc->alc_rdata; 2575 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 2576 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2577 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2578 } 2579 2580 static void 2581 alc_init_smb(struct alc_softc *sc) 2582 { 2583 struct alc_ring_data *rd; 2584 2585 rd = &sc->alc_rdata; 2586 memset(rd->alc_smb, 0, ALC_SMB_SZ); 2587 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2588 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2589 } 2590 2591 static void 2592 alc_rxvlan(struct alc_softc *sc) 2593 { 2594 uint32_t reg; 2595 2596 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2597 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 2598 reg |= MAC_CFG_VLAN_TAG_STRIP; 2599 else 2600 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2601 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2602 } 2603 2604 static void 2605 alc_iff(struct alc_softc *sc) 2606 { 2607 struct ethercom *ec = &sc->sc_ec; 2608 struct ifnet *ifp = &ec->ec_if; 2609 struct ether_multi *enm; 2610 struct ether_multistep step; 2611 uint32_t crc; 2612 uint32_t mchash[2]; 2613 uint32_t rxcfg; 2614 2615 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 2616 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2617 ifp->if_flags &= ~IFF_ALLMULTI; 2618 2619 /* 2620 * Always accept broadcast frames. 2621 */ 2622 rxcfg |= MAC_CFG_BCAST; 2623 2624 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2625 ifp->if_flags |= IFF_ALLMULTI; 2626 if (ifp->if_flags & IFF_PROMISC) 2627 rxcfg |= MAC_CFG_PROMISC; 2628 else 2629 rxcfg |= MAC_CFG_ALLMULTI; 2630 mchash[0] = mchash[1] = 0xFFFFFFFF; 2631 } else { 2632 /* Program new filter. */ 2633 memset(mchash, 0, sizeof(mchash)); 2634 2635 ETHER_FIRST_MULTI(step, ec, enm); 2636 while (enm != NULL) { 2637 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2638 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2639 ETHER_NEXT_MULTI(step, enm); 2640 } 2641 } 2642 2643 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 2644 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 2645 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 2646 } 2647 2648 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 2649 2650 #ifdef _MODULE 2651 #include "ioconf.c" 2652 #endif 2653 2654 static int 2655 if_alc_modcmd(modcmd_t cmd, void *opaque) 2656 { 2657 int error = 0; 2658 2659 switch (cmd) { 2660 case MODULE_CMD_INIT: 2661 #ifdef _MODULE 2662 error = config_init_component(cfdriver_ioconf_if_alc, 2663 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 2664 #endif 2665 return error; 2666 case MODULE_CMD_FINI: 2667 #ifdef _MODULE 2668 error = config_fini_component(cfdriver_ioconf_if_alc, 2669 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 2670 #endif 2671 return error; 2672 default: 2673 return ENOTTY; 2674 } 2675 } 2676