1 /* $OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 30 31 #ifdef _KERNEL_OPT 32 #include "vlan.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/proc.h> 37 #include <sys/endian.h> 38 #include <sys/systm.h> 39 #include <sys/types.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/queue.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/callout.h> 46 #include <sys/socket.h> 47 #include <sys/module.h> 48 49 #include <sys/bus.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/ip.h> 64 #endif 65 66 #include <net/if_types.h> 67 #include <net/if_vlanvar.h> 68 69 #include <net/bpf.h> 70 71 #include <sys/rnd.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/if_alcreg.h> 81 82 /* 83 * Devices supported by this driver. 84 */ 85 static struct alc_ident alc_ident_table[] = { 86 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8131, 9 * 1024, 87 "Atheros AR8131 PCIe Gigabit Ethernet" }, 88 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8132, 9 * 1024, 89 "Atheros AR8132 PCIe Fast Ethernet" }, 90 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151, 6 * 1024, 91 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 92 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8151_V2, 6 * 1024, 93 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 94 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B, 6 * 1024, 95 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 96 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8152_B2, 6 * 1024, 97 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 98 { 0, 0, 0, NULL }, 99 }; 100 101 static int alc_match(device_t, cfdata_t, void *); 102 static void alc_attach(device_t, device_t, void *); 103 static int alc_detach(device_t, int); 104 105 static int alc_init(struct ifnet *); 106 static int alc_init_backend(struct ifnet *, bool); 107 static void alc_start(struct ifnet *); 108 static int alc_ioctl(struct ifnet *, u_long, void *); 109 static void alc_watchdog(struct ifnet *); 110 static int alc_mediachange(struct ifnet *); 111 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 112 113 static void alc_aspm(struct alc_softc *, int); 114 static void alc_disable_l0s_l1(struct alc_softc *); 115 static int alc_dma_alloc(struct alc_softc *); 116 static void alc_dma_free(struct alc_softc *); 117 static int alc_encap(struct alc_softc *, struct mbuf **); 118 static struct alc_ident * 119 alc_find_ident(struct pci_attach_args *); 120 static void alc_get_macaddr(struct alc_softc *); 121 static void alc_init_cmb(struct alc_softc *); 122 static void alc_init_rr_ring(struct alc_softc *); 123 static int alc_init_rx_ring(struct alc_softc *, bool); 124 static void alc_init_smb(struct alc_softc *); 125 static void alc_init_tx_ring(struct alc_softc *); 126 static int alc_intr(void *); 127 static void alc_mac_config(struct alc_softc *); 128 static int alc_miibus_readreg(device_t, int, int); 129 static void alc_miibus_statchg(struct ifnet *); 130 static void alc_miibus_writereg(device_t, int, int, int); 131 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, bool); 132 static void alc_phy_down(struct alc_softc *); 133 static void alc_phy_reset(struct alc_softc *); 134 static void alc_reset(struct alc_softc *); 135 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 136 static int alc_rxintr(struct alc_softc *); 137 static void alc_iff(struct alc_softc *); 138 static void alc_rxvlan(struct alc_softc *); 139 static void alc_start_queue(struct alc_softc *); 140 static void alc_stats_clear(struct alc_softc *); 141 static void alc_stats_update(struct alc_softc *); 142 static void alc_stop(struct ifnet *, int); 143 static void alc_stop_mac(struct alc_softc *); 144 static void alc_stop_queue(struct alc_softc *); 145 static void alc_tick(void *); 146 static void alc_txeof(struct alc_softc *); 147 148 uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 149 150 CFATTACH_DECL_NEW(alc, sizeof(struct alc_softc), 151 alc_match, alc_attach, alc_detach, NULL); 152 153 int alcdebug = 0; 154 #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) 155 156 #define ETHER_ALIGN 2 157 #define ALC_CSUM_FEATURES (M_CSUM_TCPv4 | M_CSUM_UDPv4) 158 159 static int 160 alc_miibus_readreg(device_t dev, int phy, int reg) 161 { 162 struct alc_softc *sc = device_private(dev); 163 uint32_t v; 164 int i; 165 166 if (phy != sc->alc_phyaddr) 167 return (0); 168 169 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 170 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 171 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 172 DELAY(5); 173 v = CSR_READ_4(sc, ALC_MDIO); 174 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 175 break; 176 } 177 178 if (i == 0) { 179 printf("%s: phy read timeout: phy %d, reg %d\n", 180 device_xname(sc->sc_dev), phy, reg); 181 return (0); 182 } 183 184 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 185 } 186 187 static void 188 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 189 { 190 struct alc_softc *sc = device_private(dev); 191 uint32_t v; 192 int i; 193 194 if (phy != sc->alc_phyaddr) 195 return; 196 197 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 198 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 199 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 200 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 201 DELAY(5); 202 v = CSR_READ_4(sc, ALC_MDIO); 203 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 204 break; 205 } 206 207 if (i == 0) 208 printf("%s: phy write timeout: phy %d, reg %d\n", 209 device_xname(sc->sc_dev), phy, reg); 210 } 211 212 static void 213 alc_miibus_statchg(struct ifnet *ifp) 214 { 215 struct alc_softc *sc = ifp->if_softc; 216 struct mii_data *mii = &sc->sc_miibus; 217 uint32_t reg; 218 219 if ((ifp->if_flags & IFF_RUNNING) == 0) 220 return; 221 222 sc->alc_flags &= ~ALC_FLAG_LINK; 223 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 224 (IFM_ACTIVE | IFM_AVALID)) { 225 switch (IFM_SUBTYPE(mii->mii_media_active)) { 226 case IFM_10_T: 227 case IFM_100_TX: 228 sc->alc_flags |= ALC_FLAG_LINK; 229 break; 230 case IFM_1000_T: 231 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 232 sc->alc_flags |= ALC_FLAG_LINK; 233 break; 234 default: 235 break; 236 } 237 } 238 alc_stop_queue(sc); 239 /* Stop Rx/Tx MACs. */ 240 alc_stop_mac(sc); 241 242 /* Program MACs with resolved speed/duplex/flow-control. */ 243 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 244 alc_start_queue(sc); 245 alc_mac_config(sc); 246 /* Re-enable Tx/Rx MACs. */ 247 reg = CSR_READ_4(sc, ALC_MAC_CFG); 248 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 249 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 250 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 251 } 252 } 253 254 static void 255 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 256 { 257 struct alc_softc *sc = ifp->if_softc; 258 struct mii_data *mii = &sc->sc_miibus; 259 260 mii_pollstat(mii); 261 ifmr->ifm_status = mii->mii_media_status; 262 ifmr->ifm_active = mii->mii_media_active; 263 } 264 265 static int 266 alc_mediachange(struct ifnet *ifp) 267 { 268 struct alc_softc *sc = ifp->if_softc; 269 struct mii_data *mii = &sc->sc_miibus; 270 int error; 271 272 if (mii->mii_instance != 0) { 273 struct mii_softc *miisc; 274 275 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 276 mii_phy_reset(miisc); 277 } 278 error = mii_mediachg(mii); 279 280 return (error); 281 } 282 283 static struct alc_ident * 284 alc_find_ident(struct pci_attach_args *pa) 285 { 286 struct alc_ident *ident; 287 uint16_t vendor, devid; 288 289 vendor = PCI_VENDOR(pa->pa_id); 290 devid = PCI_PRODUCT(pa->pa_id); 291 for (ident = alc_ident_table; ident->name != NULL; ident++) { 292 if (vendor == ident->vendorid && devid == ident->deviceid) 293 return (ident); 294 } 295 296 return (NULL); 297 } 298 299 static int 300 alc_match(device_t dev, cfdata_t match, void *aux) 301 { 302 struct pci_attach_args *pa = aux; 303 304 return alc_find_ident(pa) != NULL; 305 } 306 307 static void 308 alc_get_macaddr(struct alc_softc *sc) 309 { 310 uint32_t ea[2], opt; 311 uint16_t val; 312 int eeprom, i; 313 314 eeprom = 0; 315 opt = CSR_READ_4(sc, ALC_OPT_CFG); 316 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 317 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 318 /* 319 * EEPROM found, let TWSI reload EEPROM configuration. 320 * This will set ethernet address of controller. 321 */ 322 eeprom++; 323 switch (sc->alc_ident->deviceid) { 324 case PCI_PRODUCT_ATTANSIC_AR8131: 325 case PCI_PRODUCT_ATTANSIC_AR8132: 326 if ((opt & OPT_CFG_CLK_ENB) == 0) { 327 opt |= OPT_CFG_CLK_ENB; 328 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 329 CSR_READ_4(sc, ALC_OPT_CFG); 330 DELAY(1000); 331 } 332 break; 333 case PCI_PRODUCT_ATTANSIC_AR8151: 334 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 335 case PCI_PRODUCT_ATTANSIC_AR8152_B: 336 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 337 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 338 ALC_MII_DBG_ADDR, 0x00); 339 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 340 ALC_MII_DBG_DATA); 341 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 342 ALC_MII_DBG_DATA, val & 0xFF7F); 343 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 344 ALC_MII_DBG_ADDR, 0x3B); 345 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 346 ALC_MII_DBG_DATA); 347 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 348 ALC_MII_DBG_DATA, val | 0x0008); 349 DELAY(20); 350 break; 351 } 352 353 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 354 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 355 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 356 CSR_READ_4(sc, ALC_WOL_CFG); 357 358 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 359 TWSI_CFG_SW_LD_START); 360 for (i = 100; i > 0; i--) { 361 DELAY(1000); 362 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 363 TWSI_CFG_SW_LD_START) == 0) 364 break; 365 } 366 if (i == 0) 367 printf("%s: reloading EEPROM timeout!\n", 368 device_xname(sc->sc_dev)); 369 } else { 370 if (alcdebug) 371 printf("%s: EEPROM not found!\n", device_xname(sc->sc_dev)); 372 } 373 if (eeprom != 0) { 374 switch (sc->alc_ident->deviceid) { 375 case PCI_PRODUCT_ATTANSIC_AR8131: 376 case PCI_PRODUCT_ATTANSIC_AR8132: 377 if ((opt & OPT_CFG_CLK_ENB) != 0) { 378 opt &= ~OPT_CFG_CLK_ENB; 379 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 380 CSR_READ_4(sc, ALC_OPT_CFG); 381 DELAY(1000); 382 } 383 break; 384 case PCI_PRODUCT_ATTANSIC_AR8151: 385 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 386 case PCI_PRODUCT_ATTANSIC_AR8152_B: 387 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 388 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 389 ALC_MII_DBG_ADDR, 0x00); 390 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 391 ALC_MII_DBG_DATA); 392 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 393 ALC_MII_DBG_DATA, val | 0x0080); 394 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 395 ALC_MII_DBG_ADDR, 0x3B); 396 val = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 397 ALC_MII_DBG_DATA); 398 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 399 ALC_MII_DBG_DATA, val & 0xFFF7); 400 DELAY(20); 401 break; 402 } 403 } 404 405 ea[0] = CSR_READ_4(sc, ALC_PAR0); 406 ea[1] = CSR_READ_4(sc, ALC_PAR1); 407 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 408 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 409 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 410 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 411 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 412 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 413 } 414 415 static void 416 alc_disable_l0s_l1(struct alc_softc *sc) 417 { 418 uint32_t pmcfg; 419 420 /* Another magic from vendor. */ 421 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 422 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 423 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 424 PM_CFG_SERDES_PD_EX_L1); 425 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 426 PM_CFG_SERDES_L1_ENB; 427 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 428 } 429 430 static void 431 alc_phy_reset(struct alc_softc *sc) 432 { 433 uint16_t data; 434 435 /* Reset magic from Linux. */ 436 CSR_WRITE_2(sc, ALC_GPHY_CFG, 437 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 438 CSR_READ_2(sc, ALC_GPHY_CFG); 439 DELAY(10 * 1000); 440 441 CSR_WRITE_2(sc, ALC_GPHY_CFG, 442 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 443 GPHY_CFG_SEL_ANA_RESET); 444 CSR_READ_2(sc, ALC_GPHY_CFG); 445 DELAY(10 * 1000); 446 447 /* DSP fixup, Vendor magic. */ 448 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 449 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 450 ALC_MII_DBG_ADDR, 0x000A); 451 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 452 ALC_MII_DBG_DATA); 453 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 454 ALC_MII_DBG_DATA, data & 0xDFFF); 455 } 456 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 457 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 458 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 459 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 460 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 461 ALC_MII_DBG_ADDR, 0x003B); 462 data = alc_miibus_readreg(sc->sc_dev, sc->alc_phyaddr, 463 ALC_MII_DBG_DATA); 464 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 465 ALC_MII_DBG_DATA, data & 0xFFF7); 466 DELAY(20 * 1000); 467 } 468 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151) { 469 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 470 ALC_MII_DBG_ADDR, 0x0029); 471 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 472 ALC_MII_DBG_DATA, 0x929D); 473 } 474 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 475 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132 || 476 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 477 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) { 478 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 479 ALC_MII_DBG_ADDR, 0x0029); 480 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 481 ALC_MII_DBG_DATA, 0xB6DD); 482 } 483 484 /* Load DSP codes, vendor magic. */ 485 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 486 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 487 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 488 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 489 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 490 ALC_MII_DBG_DATA, data); 491 492 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 493 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 494 ANA_SERDES_EN_LCKDT; 495 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 496 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 497 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 498 ALC_MII_DBG_DATA, data); 499 500 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 501 ANA_LONG_CABLE_TH_100_MASK) | 502 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 503 ANA_SHORT_CABLE_TH_100_SHIFT) | 504 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 505 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 506 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 507 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 508 ALC_MII_DBG_DATA, data); 509 510 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 511 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 512 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 513 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 514 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 515 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 516 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 517 ALC_MII_DBG_DATA, data); 518 519 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 520 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 521 ANA_OEN_125M; 522 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 523 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 524 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 525 ALC_MII_DBG_DATA, data); 526 DELAY(1000); 527 } 528 529 static void 530 alc_phy_down(struct alc_softc *sc) 531 { 532 switch (sc->alc_ident->deviceid) { 533 case PCI_PRODUCT_ATTANSIC_AR8151: 534 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 535 /* 536 * GPHY power down caused more problems on AR8151 v2.0. 537 * When driver is reloaded after GPHY power down, 538 * accesses to PHY/MAC registers hung the system. Only 539 * cold boot recovered from it. I'm not sure whether 540 * AR8151 v1.0 also requires this one though. I don't 541 * have AR8151 v1.0 controller in hand. 542 * The only option left is to isolate the PHY and 543 * initiates power down the PHY which in turn saves 544 * more power when driver is unloaded. 545 */ 546 alc_miibus_writereg(sc->sc_dev, sc->alc_phyaddr, 547 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 548 break; 549 default: 550 /* Force PHY down. */ 551 CSR_WRITE_2(sc, ALC_GPHY_CFG, 552 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 553 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 554 GPHY_CFG_PWDOWN_HW); 555 DELAY(1000); 556 break; 557 } 558 } 559 560 static void 561 alc_aspm(struct alc_softc *sc, int media) 562 { 563 uint32_t pmcfg; 564 uint16_t linkcfg; 565 566 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 567 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 568 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 569 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 570 PCIE_LCSR); 571 else 572 linkcfg = 0; 573 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 574 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 575 pmcfg |= PM_CFG_MAC_ASPM_CHK; 576 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 577 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 578 579 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 580 /* Disable extended sync except AR8152 B v1.0 */ 581 linkcfg &= ~0x80; 582 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 583 sc->alc_rev == ATHEROS_AR8152_B_V10) 584 linkcfg |= 0x80; 585 CSR_WRITE_2(sc, sc->alc_expcap + PCIE_LCSR, 586 linkcfg); 587 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 588 PM_CFG_HOTRST); 589 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 590 PM_CFG_L1_ENTRY_TIMER_SHIFT); 591 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 592 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 593 PM_CFG_PM_REQ_TIMER_SHIFT); 594 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 595 } 596 597 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 598 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 599 pmcfg |= PM_CFG_ASPM_L0S_ENB; 600 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 601 pmcfg |= PM_CFG_ASPM_L1_ENB; 602 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 603 if (sc->alc_ident->deviceid == 604 PCI_PRODUCT_ATTANSIC_AR8152_B) 605 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 606 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 607 PM_CFG_SERDES_PLL_L1_ENB | 608 PM_CFG_SERDES_BUDS_RX_L1_ENB); 609 pmcfg |= PM_CFG_CLK_SWH_L1; 610 if (media == IFM_100_TX || media == IFM_1000_T) { 611 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 612 switch (sc->alc_ident->deviceid) { 613 case PCI_PRODUCT_ATTANSIC_AR8152_B: 614 pmcfg |= (7 << 615 PM_CFG_L1_ENTRY_TIMER_SHIFT); 616 break; 617 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 618 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 619 pmcfg |= (4 << 620 PM_CFG_L1_ENTRY_TIMER_SHIFT); 621 break; 622 default: 623 pmcfg |= (15 << 624 PM_CFG_L1_ENTRY_TIMER_SHIFT); 625 break; 626 } 627 } 628 } else { 629 pmcfg |= PM_CFG_SERDES_L1_ENB | 630 PM_CFG_SERDES_PLL_L1_ENB | 631 PM_CFG_SERDES_BUDS_RX_L1_ENB; 632 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 633 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 634 } 635 } else { 636 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 637 PM_CFG_SERDES_PLL_L1_ENB); 638 pmcfg |= PM_CFG_CLK_SWH_L1; 639 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 640 pmcfg |= PM_CFG_ASPM_L1_ENB; 641 } 642 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 643 } 644 645 static void 646 alc_attach(device_t parent, device_t self, void *aux) 647 { 648 649 struct alc_softc *sc = device_private(self); 650 struct pci_attach_args *pa = aux; 651 pci_chipset_tag_t pc = pa->pa_pc; 652 pci_intr_handle_t ih; 653 const char *intrstr; 654 struct ifnet *ifp; 655 pcireg_t memtype; 656 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 657 uint16_t burst; 658 int base, mii_flags, state, error = 0; 659 uint32_t cap, ctl, val; 660 char intrbuf[PCI_INTRSTR_LEN]; 661 662 sc->alc_ident = alc_find_ident(pa); 663 664 aprint_naive("\n"); 665 aprint_normal(": %s\n", sc->alc_ident->name); 666 667 sc->sc_dev = self; 668 sc->sc_dmat = pa->pa_dmat; 669 sc->sc_pct = pa->pa_pc; 670 sc->sc_pcitag = pa->pa_tag; 671 672 /* 673 * Allocate IO memory 674 */ 675 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); 676 switch (memtype) { 677 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 678 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M: 679 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 680 break; 681 default: 682 aprint_error_dev(self, "invalid base address register\n"); 683 break; 684 } 685 686 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, 687 &sc->sc_mem_bh, NULL, &sc->sc_mem_size)) { 688 aprint_error_dev(self, "could not map mem space\n"); 689 return; 690 } 691 692 if (pci_intr_map(pa, &ih) != 0) { 693 printf(": can't map interrupt\n"); 694 goto fail; 695 } 696 697 /* 698 * Allocate IRQ 699 */ 700 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf)); 701 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc); 702 if (sc->sc_irq_handle == NULL) { 703 printf(": could not establish interrupt"); 704 if (intrstr != NULL) 705 printf(" at %s", intrstr); 706 printf("\n"); 707 goto fail; 708 } 709 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 710 711 /* Set PHY address. */ 712 sc->alc_phyaddr = ALC_PHY_ADDR; 713 714 /* Initialize DMA parameters. */ 715 sc->alc_dma_rd_burst = 0; 716 sc->alc_dma_wr_burst = 0; 717 sc->alc_rcb = DMA_CFG_RCB_64; 718 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 719 &base, NULL)) { 720 sc->alc_flags |= ALC_FLAG_PCIE; 721 sc->alc_expcap = base; 722 burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 723 base + PCIE_DCSR) >> 16; 724 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; 725 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; 726 if (alcdebug) { 727 printf("%s: Read request size : %u bytes.\n", 728 device_xname(sc->sc_dev), 729 alc_dma_burst[sc->alc_dma_rd_burst]); 730 printf("%s: TLP payload size : %u bytes.\n", 731 device_xname(sc->sc_dev), 732 alc_dma_burst[sc->alc_dma_wr_burst]); 733 } 734 /* Clear data link and flow-control protocol error. */ 735 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 736 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 737 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 738 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 739 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 740 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 741 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 742 PCIE_PHYMISC_FORCE_RCV_DET); 743 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B && 744 sc->alc_rev == ATHEROS_AR8152_B_V10) { 745 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 746 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 747 PCIE_PHYMISC2_SERDES_TH_MASK); 748 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 749 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 750 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 751 } 752 /* Disable ASPM L0S and L1. */ 753 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 754 base + PCIE_LCAP) >> 16; 755 if ((cap & 0x00000c00) != 0) { 756 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 757 base + PCIE_LCSR) >> 16; 758 if ((ctl & 0x08) != 0) 759 sc->alc_rcb = DMA_CFG_RCB_128; 760 if (alcdebug) 761 printf("%s: RCB %u bytes\n", 762 device_xname(sc->sc_dev), 763 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 764 state = ctl & 0x03; 765 if (state & 0x01) 766 sc->alc_flags |= ALC_FLAG_L0S; 767 if (state & 0x02) 768 sc->alc_flags |= ALC_FLAG_L1S; 769 if (alcdebug) 770 printf("%s: ASPM %s %s\n", 771 device_xname(sc->sc_dev), 772 aspm_state[state], 773 state == 0 ? "disabled" : "enabled"); 774 alc_disable_l0s_l1(sc); 775 } else { 776 aprint_debug_dev(sc->sc_dev, "no ASPM support\n"); 777 } 778 } 779 780 /* Reset PHY. */ 781 alc_phy_reset(sc); 782 783 /* Reset the ethernet controller. */ 784 alc_reset(sc); 785 786 /* 787 * One odd thing is AR8132 uses the same PHY hardware(F1 788 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 789 * the PHY supports 1000Mbps but that's not true. The PHY 790 * used in AR8132 can't establish gigabit link even if it 791 * shows the same PHY model/revision number of AR8131. 792 */ 793 switch (sc->alc_ident->deviceid) { 794 case PCI_PRODUCT_ATTANSIC_AR8152_B: 795 case PCI_PRODUCT_ATTANSIC_AR8152_B2: 796 sc->alc_flags |= ALC_FLAG_APS; 797 /* FALLTHROUGH */ 798 case PCI_PRODUCT_ATTANSIC_AR8132: 799 sc->alc_flags |= ALC_FLAG_FASTETHER; 800 break; 801 case PCI_PRODUCT_ATTANSIC_AR8151: 802 case PCI_PRODUCT_ATTANSIC_AR8151_V2: 803 sc->alc_flags |= ALC_FLAG_APS; 804 /* FALLTHROUGH */ 805 default: 806 break; 807 } 808 sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON; 809 810 /* 811 * It seems that AR813x/AR815x has silicon bug for SMB. In 812 * addition, Atheros said that enabling SMB wouldn't improve 813 * performance. However I think it's bad to access lots of 814 * registers to extract MAC statistics. 815 */ 816 sc->alc_flags |= ALC_FLAG_SMB_BUG; 817 /* 818 * Don't use Tx CMB. It is known to have silicon bug. 819 */ 820 sc->alc_flags |= ALC_FLAG_CMB_BUG; 821 sc->alc_rev = PCI_REVISION(pa->pa_class); 822 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 823 MASTER_CHIP_REV_SHIFT; 824 if (alcdebug) { 825 printf("%s: PCI device revision : 0x%04x\n", 826 device_xname(sc->sc_dev), sc->alc_rev); 827 printf("%s: Chip id/revision : 0x%04x\n", 828 device_xname(sc->sc_dev), sc->alc_chip_rev); 829 printf("%s: %u Tx FIFO, %u Rx FIFO\n", device_xname(sc->sc_dev), 830 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 831 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 832 } 833 834 error = alc_dma_alloc(sc); 835 if (error) 836 goto fail; 837 838 callout_init(&sc->sc_tick_ch, 0); 839 callout_setfunc(&sc->sc_tick_ch, alc_tick, sc); 840 841 /* Load station address. */ 842 alc_get_macaddr(sc); 843 844 aprint_normal_dev(self, "Ethernet address %s\n", 845 ether_sprintf(sc->alc_eaddr)); 846 847 ifp = &sc->sc_ec.ec_if; 848 ifp->if_softc = sc; 849 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 850 ifp->if_init = alc_init; 851 ifp->if_ioctl = alc_ioctl; 852 ifp->if_start = alc_start; 853 ifp->if_stop = alc_stop; 854 ifp->if_watchdog = alc_watchdog; 855 ifp->if_baudrate = IF_Gbps(1); 856 IFQ_SET_MAXLEN(&ifp->if_snd, ALC_TX_RING_CNT - 1); 857 IFQ_SET_READY(&ifp->if_snd); 858 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 859 860 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 861 862 #ifdef ALC_CHECKSUM 863 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 864 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 865 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 866 #endif 867 868 #if NVLAN > 0 869 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 870 #endif 871 872 /* Set up MII bus. */ 873 sc->sc_miibus.mii_ifp = ifp; 874 sc->sc_miibus.mii_readreg = alc_miibus_readreg; 875 sc->sc_miibus.mii_writereg = alc_miibus_writereg; 876 sc->sc_miibus.mii_statchg = alc_miibus_statchg; 877 878 sc->sc_ec.ec_mii = &sc->sc_miibus; 879 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange, 880 alc_mediastatus); 881 mii_flags = 0; 882 if ((sc->alc_flags & ALC_FLAG_JUMBO) != 0) 883 mii_flags |= MIIF_DOPAUSE; 884 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, 885 MII_OFFSET_ANY, mii_flags); 886 887 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) { 888 printf("%s: no PHY found!\n", device_xname(sc->sc_dev)); 889 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 890 0, NULL); 891 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); 892 } else 893 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); 894 895 if_attach(ifp); 896 ether_ifattach(ifp, sc->alc_eaddr); 897 898 if (!pmf_device_register(self, NULL, NULL)) 899 aprint_error_dev(self, "couldn't establish power handler\n"); 900 else 901 pmf_class_network_register(self, ifp); 902 903 return; 904 fail: 905 alc_dma_free(sc); 906 if (sc->sc_irq_handle != NULL) { 907 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 908 sc->sc_irq_handle = NULL; 909 } 910 if (sc->sc_mem_size) { 911 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 912 sc->sc_mem_size = 0; 913 } 914 } 915 916 static int 917 alc_detach(device_t self, int flags) 918 { 919 struct alc_softc *sc = device_private(self); 920 struct ifnet *ifp = &sc->sc_ec.ec_if; 921 int s; 922 923 s = splnet(); 924 alc_stop(ifp, 0); 925 splx(s); 926 927 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY); 928 929 /* Delete all remaining media. */ 930 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); 931 932 ether_ifdetach(ifp); 933 if_detach(ifp); 934 alc_dma_free(sc); 935 936 alc_phy_down(sc); 937 if (sc->sc_irq_handle != NULL) { 938 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle); 939 sc->sc_irq_handle = NULL; 940 } 941 if (sc->sc_mem_size) { 942 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); 943 sc->sc_mem_size = 0; 944 } 945 946 return (0); 947 } 948 949 static int 950 alc_dma_alloc(struct alc_softc *sc) 951 { 952 struct alc_txdesc *txd; 953 struct alc_rxdesc *rxd; 954 int nsegs, error, i; 955 956 /* 957 * Create DMA stuffs for TX ring 958 */ 959 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1, 960 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map); 961 if (error) { 962 sc->alc_cdata.alc_tx_ring_map = NULL; 963 return (ENOBUFS); 964 } 965 966 /* Allocate DMA'able memory for TX ring */ 967 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ, 968 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1, 969 &nsegs, BUS_DMA_NOWAIT); 970 if (error) { 971 printf("%s: could not allocate DMA'able memory for Tx ring.\n", 972 device_xname(sc->sc_dev)); 973 return error; 974 } 975 976 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg, 977 nsegs, ALC_TX_RING_SZ, (void **)&sc->alc_rdata.alc_tx_ring, 978 BUS_DMA_NOWAIT); 979 if (error) 980 return (ENOBUFS); 981 982 /* Load the DMA map for Tx ring. */ 983 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 984 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK); 985 if (error) { 986 printf("%s: could not load DMA'able memory for Tx ring.\n", 987 device_xname(sc->sc_dev)); 988 bus_dmamem_free(sc->sc_dmat, 989 &sc->alc_rdata.alc_tx_ring_seg, 1); 990 return error; 991 } 992 993 sc->alc_rdata.alc_tx_ring_paddr = 994 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; 995 996 /* 997 * Create DMA stuffs for RX ring 998 */ 999 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1, 1000 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); 1001 if (error) 1002 return (ENOBUFS); 1003 1004 /* Allocate DMA'able memory for RX ring */ 1005 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, 1006 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, 1007 &nsegs, BUS_DMA_NOWAIT); 1008 if (error) { 1009 printf("%s: could not allocate DMA'able memory for Rx ring.\n", 1010 device_xname(sc->sc_dev)); 1011 return error; 1012 } 1013 1014 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg, 1015 nsegs, ALC_RX_RING_SZ, (void **)&sc->alc_rdata.alc_rx_ring, 1016 BUS_DMA_NOWAIT); 1017 if (error) 1018 return (ENOBUFS); 1019 1020 /* Load the DMA map for Rx ring. */ 1021 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 1022 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK); 1023 if (error) { 1024 printf("%s: could not load DMA'able memory for Rx ring.\n", 1025 device_xname(sc->sc_dev)); 1026 bus_dmamem_free(sc->sc_dmat, 1027 &sc->alc_rdata.alc_rx_ring_seg, 1); 1028 return error; 1029 } 1030 1031 sc->alc_rdata.alc_rx_ring_paddr = 1032 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr; 1033 1034 /* 1035 * Create DMA stuffs for RX return ring 1036 */ 1037 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, 1038 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); 1039 if (error) 1040 return (ENOBUFS); 1041 1042 /* Allocate DMA'able memory for RX return ring */ 1043 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, 1044 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, 1045 &nsegs, BUS_DMA_NOWAIT); 1046 if (error) { 1047 printf("%s: could not allocate DMA'able memory for Rx " 1048 "return ring.\n", device_xname(sc->sc_dev)); 1049 return error; 1050 } 1051 1052 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg, 1053 nsegs, ALC_RR_RING_SZ, (void **)&sc->alc_rdata.alc_rr_ring, 1054 BUS_DMA_NOWAIT); 1055 if (error) 1056 return (ENOBUFS); 1057 1058 /* Load the DMA map for Rx return ring. */ 1059 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 1060 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK); 1061 if (error) { 1062 printf("%s: could not load DMA'able memory for Rx return ring." 1063 "\n", device_xname(sc->sc_dev)); 1064 bus_dmamem_free(sc->sc_dmat, 1065 &sc->alc_rdata.alc_rr_ring_seg, 1); 1066 return error; 1067 } 1068 1069 sc->alc_rdata.alc_rr_ring_paddr = 1070 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; 1071 1072 /* 1073 * Create DMA stuffs for CMB block 1074 */ 1075 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, 1076 ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, 1077 &sc->alc_cdata.alc_cmb_map); 1078 if (error) 1079 return (ENOBUFS); 1080 1081 /* Allocate DMA'able memory for CMB block */ 1082 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, 1083 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, 1084 &nsegs, BUS_DMA_NOWAIT); 1085 if (error) { 1086 printf("%s: could not allocate DMA'able memory for " 1087 "CMB block\n", device_xname(sc->sc_dev)); 1088 return error; 1089 } 1090 1091 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg, 1092 nsegs, ALC_CMB_SZ, (void **)&sc->alc_rdata.alc_cmb, 1093 BUS_DMA_NOWAIT); 1094 if (error) 1095 return (ENOBUFS); 1096 1097 /* Load the DMA map for CMB block. */ 1098 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 1099 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, 1100 BUS_DMA_WAITOK); 1101 if (error) { 1102 printf("%s: could not load DMA'able memory for CMB block\n", 1103 device_xname(sc->sc_dev)); 1104 bus_dmamem_free(sc->sc_dmat, 1105 &sc->alc_rdata.alc_cmb_seg, 1); 1106 return error; 1107 } 1108 1109 sc->alc_rdata.alc_cmb_paddr = 1110 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; 1111 1112 /* 1113 * Create DMA stuffs for SMB block 1114 */ 1115 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, 1116 ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, 1117 &sc->alc_cdata.alc_smb_map); 1118 if (error) 1119 return (ENOBUFS); 1120 1121 /* Allocate DMA'able memory for SMB block */ 1122 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, 1123 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, 1124 &nsegs, BUS_DMA_NOWAIT); 1125 if (error) { 1126 printf("%s: could not allocate DMA'able memory for " 1127 "SMB block\n", device_xname(sc->sc_dev)); 1128 return error; 1129 } 1130 1131 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg, 1132 nsegs, ALC_SMB_SZ, (void **)&sc->alc_rdata.alc_smb, 1133 BUS_DMA_NOWAIT); 1134 if (error) 1135 return (ENOBUFS); 1136 1137 /* Load the DMA map for SMB block */ 1138 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 1139 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, 1140 BUS_DMA_WAITOK); 1141 if (error) { 1142 printf("%s: could not load DMA'able memory for SMB block\n", 1143 device_xname(sc->sc_dev)); 1144 bus_dmamem_free(sc->sc_dmat, 1145 &sc->alc_rdata.alc_smb_seg, 1); 1146 return error; 1147 } 1148 1149 sc->alc_rdata.alc_smb_paddr = 1150 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; 1151 1152 1153 /* Create DMA maps for Tx buffers. */ 1154 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1155 txd = &sc->alc_cdata.alc_txdesc[i]; 1156 txd->tx_m = NULL; 1157 txd->tx_dmamap = NULL; 1158 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE, 1159 ALC_MAXTXSEGS, ALC_TSO_MAXSEGSIZE, 0, BUS_DMA_NOWAIT, 1160 &txd->tx_dmamap); 1161 if (error) { 1162 printf("%s: could not create Tx dmamap.\n", 1163 device_xname(sc->sc_dev)); 1164 return error; 1165 } 1166 } 1167 1168 /* Create DMA maps for Rx buffers. */ 1169 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 1170 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap); 1171 if (error) { 1172 printf("%s: could not create spare Rx dmamap.\n", 1173 device_xname(sc->sc_dev)); 1174 return error; 1175 } 1176 1177 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1178 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1179 rxd->rx_m = NULL; 1180 rxd->rx_dmamap = NULL; 1181 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1182 MCLBYTES, 0, BUS_DMA_NOWAIT, &rxd->rx_dmamap); 1183 if (error) { 1184 printf("%s: could not create Rx dmamap.\n", 1185 device_xname(sc->sc_dev)); 1186 return error; 1187 } 1188 } 1189 1190 return (0); 1191 } 1192 1193 1194 static void 1195 alc_dma_free(struct alc_softc *sc) 1196 { 1197 struct alc_txdesc *txd; 1198 struct alc_rxdesc *rxd; 1199 int i; 1200 1201 /* Tx buffers */ 1202 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1203 txd = &sc->alc_cdata.alc_txdesc[i]; 1204 if (txd->tx_dmamap != NULL) { 1205 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap); 1206 txd->tx_dmamap = NULL; 1207 } 1208 } 1209 /* Rx buffers */ 1210 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1211 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1212 if (rxd->rx_dmamap != NULL) { 1213 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap); 1214 rxd->rx_dmamap = NULL; 1215 } 1216 } 1217 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1218 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap); 1219 sc->alc_cdata.alc_rx_sparemap = NULL; 1220 } 1221 1222 /* Tx ring. */ 1223 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1224 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map); 1225 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1226 sc->alc_rdata.alc_tx_ring != NULL) 1227 bus_dmamem_free(sc->sc_dmat, 1228 &sc->alc_rdata.alc_tx_ring_seg, 1); 1229 sc->alc_rdata.alc_tx_ring = NULL; 1230 sc->alc_cdata.alc_tx_ring_map = NULL; 1231 1232 /* Rx ring. */ 1233 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1234 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); 1235 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1236 sc->alc_rdata.alc_rx_ring != NULL) 1237 bus_dmamem_free(sc->sc_dmat, 1238 &sc->alc_rdata.alc_rx_ring_seg, 1); 1239 sc->alc_rdata.alc_rx_ring = NULL; 1240 sc->alc_cdata.alc_rx_ring_map = NULL; 1241 1242 /* Rx return ring. */ 1243 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1244 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); 1245 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1246 sc->alc_rdata.alc_rr_ring != NULL) 1247 bus_dmamem_free(sc->sc_dmat, 1248 &sc->alc_rdata.alc_rr_ring_seg, 1); 1249 sc->alc_rdata.alc_rr_ring = NULL; 1250 sc->alc_cdata.alc_rr_ring_map = NULL; 1251 1252 /* CMB block */ 1253 if (sc->alc_cdata.alc_cmb_map != NULL) 1254 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map); 1255 if (sc->alc_cdata.alc_cmb_map != NULL && 1256 sc->alc_rdata.alc_cmb != NULL) 1257 bus_dmamem_free(sc->sc_dmat, 1258 &sc->alc_rdata.alc_cmb_seg, 1); 1259 sc->alc_rdata.alc_cmb = NULL; 1260 sc->alc_cdata.alc_cmb_map = NULL; 1261 1262 /* SMB block */ 1263 if (sc->alc_cdata.alc_smb_map != NULL) 1264 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); 1265 if (sc->alc_cdata.alc_smb_map != NULL && 1266 sc->alc_rdata.alc_smb != NULL) 1267 bus_dmamem_free(sc->sc_dmat, 1268 &sc->alc_rdata.alc_smb_seg, 1); 1269 sc->alc_rdata.alc_smb = NULL; 1270 sc->alc_cdata.alc_smb_map = NULL; 1271 } 1272 1273 static int 1274 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1275 { 1276 struct alc_txdesc *txd, *txd_last; 1277 struct tx_desc *desc; 1278 struct mbuf *m; 1279 bus_dmamap_t map; 1280 uint32_t cflags, poff, vtag; 1281 int error, idx, nsegs, prod; 1282 #if NVLAN > 0 1283 struct m_tag *mtag; 1284 #endif 1285 1286 m = *m_head; 1287 cflags = vtag = 0; 1288 poff = 0; 1289 1290 prod = sc->alc_cdata.alc_tx_prod; 1291 txd = &sc->alc_cdata.alc_txdesc[prod]; 1292 txd_last = txd; 1293 map = txd->tx_dmamap; 1294 1295 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, BUS_DMA_NOWAIT); 1296 1297 if (error == EFBIG) { 1298 error = 0; 1299 1300 *m_head = m_pullup(*m_head, MHLEN); 1301 if (*m_head == NULL) { 1302 printf("%s: can't defrag TX mbuf\n", 1303 device_xname(sc->sc_dev)); 1304 return ENOBUFS; 1305 } 1306 1307 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, *m_head, 1308 BUS_DMA_NOWAIT); 1309 1310 if (error != 0) { 1311 printf("%s: could not load defragged TX mbuf\n", 1312 device_xname(sc->sc_dev)); 1313 m_freem(*m_head); 1314 *m_head = NULL; 1315 return error; 1316 } 1317 } else if (error) { 1318 printf("%s: could not load TX mbuf\n", device_xname(sc->sc_dev)); 1319 return (error); 1320 } 1321 1322 nsegs = map->dm_nsegs; 1323 1324 if (nsegs == 0) { 1325 m_freem(*m_head); 1326 *m_head = NULL; 1327 return (EIO); 1328 } 1329 1330 /* Check descriptor overrun. */ 1331 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1332 bus_dmamap_unload(sc->sc_dmat, map); 1333 return (ENOBUFS); 1334 } 1335 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1336 BUS_DMASYNC_PREWRITE); 1337 1338 m = *m_head; 1339 desc = NULL; 1340 idx = 0; 1341 #if NVLAN > 0 1342 /* Configure VLAN hardware tag insertion. */ 1343 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ec, m))) { 1344 vtag = htons(VLAN_TAG_VALUE(mtag)); 1345 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1346 cflags |= TD_INS_VLAN_TAG; 1347 } 1348 #endif 1349 /* Configure Tx checksum offload. */ 1350 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1351 cflags |= TD_CUSTOM_CSUM; 1352 /* Set checksum start offset. */ 1353 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1354 TD_PLOAD_OFFSET_MASK; 1355 } 1356 for (; idx < nsegs; idx++) { 1357 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1358 desc->len = 1359 htole32(TX_BYTES(map->dm_segs[idx].ds_len) | vtag); 1360 desc->flags = htole32(cflags); 1361 desc->addr = htole64(map->dm_segs[idx].ds_addr); 1362 sc->alc_cdata.alc_tx_cnt++; 1363 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1364 } 1365 /* Update producer index. */ 1366 sc->alc_cdata.alc_tx_prod = prod; 1367 1368 /* Finally set EOP on the last descriptor. */ 1369 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1370 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1371 desc->flags |= htole32(TD_EOP); 1372 1373 /* Swap dmamap of the first and the last. */ 1374 txd = &sc->alc_cdata.alc_txdesc[prod]; 1375 map = txd_last->tx_dmamap; 1376 txd_last->tx_dmamap = txd->tx_dmamap; 1377 txd->tx_dmamap = map; 1378 txd->tx_m = m; 1379 1380 return (0); 1381 } 1382 1383 static void 1384 alc_start(struct ifnet *ifp) 1385 { 1386 struct alc_softc *sc = ifp->if_softc; 1387 struct mbuf *m_head; 1388 int enq; 1389 1390 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1391 return; 1392 1393 /* Reclaim transmitted frames. */ 1394 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 1395 alc_txeof(sc); 1396 1397 enq = 0; 1398 for (;;) { 1399 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1400 if (m_head == NULL) 1401 break; 1402 1403 /* 1404 * Pack the data into the transmit ring. If we 1405 * don't have room, set the OACTIVE flag and wait 1406 * for the NIC to drain the ring. 1407 */ 1408 if (alc_encap(sc, &m_head)) { 1409 if (m_head == NULL) 1410 break; 1411 ifp->if_flags |= IFF_OACTIVE; 1412 break; 1413 } 1414 enq = 1; 1415 1416 /* 1417 * If there's a BPF listener, bounce a copy of this frame 1418 * to him. 1419 */ 1420 bpf_mtap(ifp, m_head); 1421 } 1422 1423 if (enq) { 1424 /* Sync descriptors. */ 1425 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1426 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1427 BUS_DMASYNC_PREWRITE); 1428 /* Kick. Assume we're using normal Tx priority queue. */ 1429 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 1430 (sc->alc_cdata.alc_tx_prod << 1431 MBOX_TD_PROD_LO_IDX_SHIFT) & 1432 MBOX_TD_PROD_LO_IDX_MASK); 1433 /* Set a timeout in case the chip goes out to lunch. */ 1434 ifp->if_timer = ALC_TX_TIMEOUT; 1435 } 1436 } 1437 1438 static void 1439 alc_watchdog(struct ifnet *ifp) 1440 { 1441 struct alc_softc *sc = ifp->if_softc; 1442 1443 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 1444 printf("%s: watchdog timeout (missed link)\n", 1445 device_xname(sc->sc_dev)); 1446 ifp->if_oerrors++; 1447 alc_init_backend(ifp, false); 1448 return; 1449 } 1450 1451 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1452 ifp->if_oerrors++; 1453 alc_init_backend(ifp, false); 1454 1455 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1456 alc_start(ifp); 1457 } 1458 1459 static int 1460 alc_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1461 { 1462 struct alc_softc *sc = ifp->if_softc; 1463 int s, error = 0; 1464 1465 s = splnet(); 1466 1467 error = ether_ioctl(ifp, cmd, data); 1468 if (error == ENETRESET) { 1469 if (ifp->if_flags & IFF_RUNNING) 1470 alc_iff(sc); 1471 error = 0; 1472 } 1473 1474 splx(s); 1475 return (error); 1476 } 1477 1478 static void 1479 alc_mac_config(struct alc_softc *sc) 1480 { 1481 struct mii_data *mii; 1482 uint32_t reg; 1483 1484 mii = &sc->sc_miibus; 1485 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1486 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1487 MAC_CFG_SPEED_MASK); 1488 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 1489 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 1490 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 1491 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 1492 /* Reprogram MAC with resolved speed/duplex. */ 1493 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1494 case IFM_10_T: 1495 case IFM_100_TX: 1496 reg |= MAC_CFG_SPEED_10_100; 1497 break; 1498 case IFM_1000_T: 1499 reg |= MAC_CFG_SPEED_1000; 1500 break; 1501 } 1502 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1503 reg |= MAC_CFG_FULL_DUPLEX; 1504 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1505 reg |= MAC_CFG_TX_FC; 1506 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1507 reg |= MAC_CFG_RX_FC; 1508 } 1509 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1510 } 1511 1512 static void 1513 alc_stats_clear(struct alc_softc *sc) 1514 { 1515 struct smb sb, *smb; 1516 uint32_t *reg; 1517 int i; 1518 1519 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1520 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1521 sc->alc_cdata.alc_smb_map->dm_mapsize, 1522 BUS_DMASYNC_POSTREAD); 1523 smb = sc->alc_rdata.alc_smb; 1524 /* Update done, clear. */ 1525 smb->updated = 0; 1526 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1527 sc->alc_cdata.alc_smb_map->dm_mapsize, 1528 BUS_DMASYNC_PREWRITE); 1529 } else { 1530 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1531 reg++) { 1532 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1533 i += sizeof(uint32_t); 1534 } 1535 /* Read Tx statistics. */ 1536 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1537 reg++) { 1538 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1539 i += sizeof(uint32_t); 1540 } 1541 } 1542 } 1543 1544 static void 1545 alc_stats_update(struct alc_softc *sc) 1546 { 1547 struct ifnet *ifp = &sc->sc_ec.ec_if; 1548 struct alc_hw_stats *stat; 1549 struct smb sb, *smb; 1550 uint32_t *reg; 1551 int i; 1552 1553 stat = &sc->alc_stats; 1554 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1555 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1556 sc->alc_cdata.alc_smb_map->dm_mapsize, 1557 BUS_DMASYNC_POSTREAD); 1558 smb = sc->alc_rdata.alc_smb; 1559 if (smb->updated == 0) 1560 return; 1561 } else { 1562 smb = &sb; 1563 /* Read Rx statistics. */ 1564 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 1565 reg++) { 1566 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 1567 i += sizeof(uint32_t); 1568 } 1569 /* Read Tx statistics. */ 1570 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 1571 reg++) { 1572 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 1573 i += sizeof(uint32_t); 1574 } 1575 } 1576 1577 /* Rx stats. */ 1578 stat->rx_frames += smb->rx_frames; 1579 stat->rx_bcast_frames += smb->rx_bcast_frames; 1580 stat->rx_mcast_frames += smb->rx_mcast_frames; 1581 stat->rx_pause_frames += smb->rx_pause_frames; 1582 stat->rx_control_frames += smb->rx_control_frames; 1583 stat->rx_crcerrs += smb->rx_crcerrs; 1584 stat->rx_lenerrs += smb->rx_lenerrs; 1585 stat->rx_bytes += smb->rx_bytes; 1586 stat->rx_runts += smb->rx_runts; 1587 stat->rx_fragments += smb->rx_fragments; 1588 stat->rx_pkts_64 += smb->rx_pkts_64; 1589 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1590 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1591 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1592 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1593 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1594 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1595 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1596 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1597 stat->rx_rrs_errs += smb->rx_rrs_errs; 1598 stat->rx_alignerrs += smb->rx_alignerrs; 1599 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1600 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1601 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1602 1603 /* Tx stats. */ 1604 stat->tx_frames += smb->tx_frames; 1605 stat->tx_bcast_frames += smb->tx_bcast_frames; 1606 stat->tx_mcast_frames += smb->tx_mcast_frames; 1607 stat->tx_pause_frames += smb->tx_pause_frames; 1608 stat->tx_excess_defer += smb->tx_excess_defer; 1609 stat->tx_control_frames += smb->tx_control_frames; 1610 stat->tx_deferred += smb->tx_deferred; 1611 stat->tx_bytes += smb->tx_bytes; 1612 stat->tx_pkts_64 += smb->tx_pkts_64; 1613 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1614 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1615 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1616 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1617 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1618 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1619 stat->tx_single_colls += smb->tx_single_colls; 1620 stat->tx_multi_colls += smb->tx_multi_colls; 1621 stat->tx_late_colls += smb->tx_late_colls; 1622 stat->tx_excess_colls += smb->tx_excess_colls; 1623 stat->tx_abort += smb->tx_abort; 1624 stat->tx_underrun += smb->tx_underrun; 1625 stat->tx_desc_underrun += smb->tx_desc_underrun; 1626 stat->tx_lenerrs += smb->tx_lenerrs; 1627 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1628 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1629 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1630 1631 /* Update counters in ifnet. */ 1632 ifp->if_opackets += smb->tx_frames; 1633 1634 ifp->if_collisions += smb->tx_single_colls + 1635 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1636 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1637 1638 /* 1639 * XXX 1640 * tx_pkts_truncated counter looks suspicious. It constantly 1641 * increments with no sign of Tx errors. This may indicate 1642 * the counter name is not correct one so I've removed the 1643 * counter in output errors. 1644 */ 1645 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1646 smb->tx_underrun; 1647 1648 ifp->if_ipackets += smb->rx_frames; 1649 1650 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1651 smb->rx_runts + smb->rx_pkts_truncated + 1652 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1653 smb->rx_alignerrs; 1654 1655 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 1656 /* Update done, clear. */ 1657 smb->updated = 0; 1658 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 1659 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1660 } 1661 } 1662 1663 static int 1664 alc_intr(void *arg) 1665 { 1666 struct alc_softc *sc = arg; 1667 struct ifnet *ifp = &sc->sc_ec.ec_if; 1668 uint32_t status; 1669 1670 status = CSR_READ_4(sc, ALC_INTR_STATUS); 1671 if ((status & ALC_INTRS) == 0) 1672 return (0); 1673 1674 /* Acknowledge and disable interrupts. */ 1675 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 1676 1677 if (ifp->if_flags & IFF_RUNNING) { 1678 if (status & INTR_RX_PKT) { 1679 int error; 1680 1681 error = alc_rxintr(sc); 1682 if (error) { 1683 alc_init_backend(ifp, false); 1684 return (0); 1685 } 1686 } 1687 1688 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 1689 INTR_TXQ_TO_RST)) { 1690 if (status & INTR_DMA_RD_TO_RST) 1691 printf("%s: DMA read error! -- resetting\n", 1692 device_xname(sc->sc_dev)); 1693 if (status & INTR_DMA_WR_TO_RST) 1694 printf("%s: DMA write error! -- resetting\n", 1695 device_xname(sc->sc_dev)); 1696 if (status & INTR_TXQ_TO_RST) 1697 printf("%s: TxQ reset! -- resetting\n", 1698 device_xname(sc->sc_dev)); 1699 alc_init_backend(ifp, false); 1700 return (0); 1701 } 1702 1703 alc_txeof(sc); 1704 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1705 alc_start(ifp); 1706 } 1707 1708 /* Re-enable interrupts. */ 1709 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 1710 return (1); 1711 } 1712 1713 static void 1714 alc_txeof(struct alc_softc *sc) 1715 { 1716 struct ifnet *ifp = &sc->sc_ec.ec_if; 1717 struct alc_txdesc *txd; 1718 uint32_t cons, prod; 1719 int prog; 1720 1721 if (sc->alc_cdata.alc_tx_cnt == 0) 1722 return; 1723 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 1724 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, 1725 BUS_DMASYNC_POSTREAD); 1726 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 1727 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1728 sc->alc_cdata.alc_cmb_map->dm_mapsize, 1729 BUS_DMASYNC_POSTREAD); 1730 prod = sc->alc_rdata.alc_cmb->cons; 1731 } else 1732 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 1733 /* Assume we're using normal Tx priority queue. */ 1734 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 1735 MBOX_TD_CONS_LO_IDX_SHIFT; 1736 cons = sc->alc_cdata.alc_tx_cons; 1737 /* 1738 * Go through our Tx list and free mbufs for those 1739 * frames which have been transmitted. 1740 */ 1741 for (prog = 0; cons != prod; prog++, 1742 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 1743 if (sc->alc_cdata.alc_tx_cnt <= 0) 1744 break; 1745 prog++; 1746 ifp->if_flags &= ~IFF_OACTIVE; 1747 sc->alc_cdata.alc_tx_cnt--; 1748 txd = &sc->alc_cdata.alc_txdesc[cons]; 1749 if (txd->tx_m != NULL) { 1750 /* Reclaim transmitted mbufs. */ 1751 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 1752 m_freem(txd->tx_m); 1753 txd->tx_m = NULL; 1754 } 1755 } 1756 1757 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 1758 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 1759 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1760 sc->alc_cdata.alc_tx_cons = cons; 1761 /* 1762 * Unarm watchdog timer only when there is no pending 1763 * frames in Tx queue. 1764 */ 1765 if (sc->alc_cdata.alc_tx_cnt == 0) 1766 ifp->if_timer = 0; 1767 } 1768 1769 static int 1770 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, bool init) 1771 { 1772 struct mbuf *m; 1773 bus_dmamap_t map; 1774 int error; 1775 1776 MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA); 1777 if (m == NULL) 1778 return (ENOBUFS); 1779 MCLGET(m, init ? M_WAITOK : M_DONTWAIT); 1780 if (!(m->m_flags & M_EXT)) { 1781 m_freem(m); 1782 return (ENOBUFS); 1783 } 1784 1785 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 1786 1787 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1788 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT); 1789 1790 if (error != 0) { 1791 if (!error) { 1792 bus_dmamap_unload(sc->sc_dmat, 1793 sc->alc_cdata.alc_rx_sparemap); 1794 error = EFBIG; 1795 printf("%s: too many segments?!\n", 1796 device_xname(sc->sc_dev)); 1797 } 1798 m_freem(m); 1799 1800 if (init) 1801 printf("%s: can't load RX mbuf\n", device_xname(sc->sc_dev)); 1802 1803 return (error); 1804 } 1805 1806 if (rxd->rx_m != NULL) { 1807 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, 1808 rxd->rx_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1809 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1810 } 1811 map = rxd->rx_dmamap; 1812 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 1813 sc->alc_cdata.alc_rx_sparemap = map; 1814 rxd->rx_m = m; 1815 rxd->rx_desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); 1816 return (0); 1817 } 1818 1819 static int 1820 alc_rxintr(struct alc_softc *sc) 1821 { 1822 struct ifnet *ifp = &sc->sc_ec.ec_if; 1823 struct rx_rdesc *rrd; 1824 uint32_t nsegs, status; 1825 int rr_cons, prog; 1826 1827 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1828 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1829 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1830 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1831 rr_cons = sc->alc_cdata.alc_rr_cons; 1832 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 1833 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 1834 status = le32toh(rrd->status); 1835 if ((status & RRD_VALID) == 0) 1836 break; 1837 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 1838 if (nsegs == 0) { 1839 /* This should not happen! */ 1840 if (alcdebug) 1841 printf("%s: unexpected segment count -- " 1842 "resetting\n", device_xname(sc->sc_dev)); 1843 return (EIO); 1844 } 1845 alc_rxeof(sc, rrd); 1846 /* Clear Rx return status. */ 1847 rrd->status = 0; 1848 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 1849 sc->alc_cdata.alc_rx_cons += nsegs; 1850 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 1851 prog += nsegs; 1852 } 1853 1854 if (prog > 0) { 1855 /* Update the consumer index. */ 1856 sc->alc_cdata.alc_rr_cons = rr_cons; 1857 /* Sync Rx return descriptors. */ 1858 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 1859 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, 1860 BUS_DMASYNC_PREWRITE); 1861 /* 1862 * Sync updated Rx descriptors such that controller see 1863 * modified buffer addresses. 1864 */ 1865 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 1866 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, 1867 BUS_DMASYNC_PREWRITE); 1868 /* 1869 * Let controller know availability of new Rx buffers. 1870 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 1871 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 1872 * only when Rx buffer pre-fetching is required. In 1873 * addition we already set ALC_RX_RD_FREE_THRESH to 1874 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 1875 * it still seems that pre-fetching needs more 1876 * experimentation. 1877 */ 1878 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1879 sc->alc_cdata.alc_rx_cons); 1880 } 1881 1882 return (0); 1883 } 1884 1885 /* Receive a frame. */ 1886 static void 1887 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 1888 { 1889 struct ifnet *ifp = &sc->sc_ec.ec_if; 1890 struct alc_rxdesc *rxd; 1891 struct mbuf *mp, *m; 1892 uint32_t rdinfo, status; 1893 int count, nsegs, rx_cons; 1894 1895 status = le32toh(rrd->status); 1896 rdinfo = le32toh(rrd->rdinfo); 1897 rx_cons = RRD_RD_IDX(rdinfo); 1898 nsegs = RRD_RD_CNT(rdinfo); 1899 1900 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 1901 if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { 1902 /* 1903 * We want to pass the following frames to upper 1904 * layer regardless of error status of Rx return 1905 * ring. 1906 * 1907 * o IP/TCP/UDP checksum is bad. 1908 * o frame length and protocol specific length 1909 * does not match. 1910 * 1911 * Force network stack compute checksum for 1912 * errored frames. 1913 */ 1914 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 1915 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 1916 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 1917 return; 1918 } 1919 1920 for (count = 0; count < nsegs; count++, 1921 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 1922 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 1923 mp = rxd->rx_m; 1924 /* Add a new receive buffer to the ring. */ 1925 if (alc_newbuf(sc, rxd, false) != 0) { 1926 ifp->if_iqdrops++; 1927 /* Reuse Rx buffers. */ 1928 if (sc->alc_cdata.alc_rxhead != NULL) 1929 m_freem(sc->alc_cdata.alc_rxhead); 1930 break; 1931 } 1932 1933 /* 1934 * Assume we've received a full sized frame. 1935 * Actual size is fixed when we encounter the end of 1936 * multi-segmented frame. 1937 */ 1938 mp->m_len = sc->alc_buf_size; 1939 1940 /* Chain received mbufs. */ 1941 if (sc->alc_cdata.alc_rxhead == NULL) { 1942 sc->alc_cdata.alc_rxhead = mp; 1943 sc->alc_cdata.alc_rxtail = mp; 1944 } else { 1945 mp->m_flags &= ~M_PKTHDR; 1946 sc->alc_cdata.alc_rxprev_tail = 1947 sc->alc_cdata.alc_rxtail; 1948 sc->alc_cdata.alc_rxtail->m_next = mp; 1949 sc->alc_cdata.alc_rxtail = mp; 1950 } 1951 1952 if (count == nsegs - 1) { 1953 /* Last desc. for this frame. */ 1954 m = sc->alc_cdata.alc_rxhead; 1955 m->m_flags |= M_PKTHDR; 1956 /* 1957 * It seems that L1C/L2C controller has no way 1958 * to tell hardware to strip CRC bytes. 1959 */ 1960 m->m_pkthdr.len = 1961 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 1962 if (nsegs > 1) { 1963 /* Set last mbuf size. */ 1964 mp->m_len = sc->alc_cdata.alc_rxlen - 1965 (nsegs - 1) * sc->alc_buf_size; 1966 /* Remove the CRC bytes in chained mbufs. */ 1967 if (mp->m_len <= ETHER_CRC_LEN) { 1968 sc->alc_cdata.alc_rxtail = 1969 sc->alc_cdata.alc_rxprev_tail; 1970 sc->alc_cdata.alc_rxtail->m_len -= 1971 (ETHER_CRC_LEN - mp->m_len); 1972 sc->alc_cdata.alc_rxtail->m_next = NULL; 1973 m_freem(mp); 1974 } else { 1975 mp->m_len -= ETHER_CRC_LEN; 1976 } 1977 } else 1978 m->m_len = m->m_pkthdr.len; 1979 m->m_pkthdr.rcvif = ifp; 1980 #if NVLAN > 0 1981 /* 1982 * Due to hardware bugs, Rx checksum offloading 1983 * was intentionally disabled. 1984 */ 1985 if (status & RRD_VLAN_TAG) { 1986 u_int32_t vtag = RRD_VLAN(le32toh(rrd->vtag)); 1987 VLAN_INPUT_TAG(ifp, m, ntohs(vtag), ); 1988 } 1989 #endif 1990 1991 bpf_mtap(ifp, m); 1992 1993 /* Pass it on. */ 1994 (*ifp->if_input)(ifp, m); 1995 } 1996 } 1997 /* Reset mbuf chains. */ 1998 ALC_RXCHAIN_RESET(sc); 1999 } 2000 2001 static void 2002 alc_tick(void *xsc) 2003 { 2004 struct alc_softc *sc = xsc; 2005 struct mii_data *mii = &sc->sc_miibus; 2006 int s; 2007 2008 s = splnet(); 2009 mii_tick(mii); 2010 alc_stats_update(sc); 2011 splx(s); 2012 2013 callout_schedule(&sc->sc_tick_ch, hz); 2014 } 2015 2016 static void 2017 alc_reset(struct alc_softc *sc) 2018 { 2019 uint32_t reg; 2020 int i; 2021 2022 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 2023 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 2024 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2025 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2026 DELAY(10); 2027 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2028 break; 2029 } 2030 if (i == 0) 2031 printf("%s: master reset timeout!\n", device_xname(sc->sc_dev)); 2032 2033 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2034 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2035 break; 2036 DELAY(10); 2037 } 2038 2039 if (i == 0) 2040 printf("%s: reset timeout(0x%08x)!\n", device_xname(sc->sc_dev), 2041 reg); 2042 } 2043 2044 static int 2045 alc_init(struct ifnet *ifp) 2046 { 2047 2048 return alc_init_backend(ifp, true); 2049 } 2050 2051 static int 2052 alc_init_backend(struct ifnet *ifp, bool init) 2053 { 2054 struct alc_softc *sc = ifp->if_softc; 2055 struct mii_data *mii; 2056 uint8_t eaddr[ETHER_ADDR_LEN]; 2057 bus_addr_t paddr; 2058 uint32_t reg, rxf_hi, rxf_lo; 2059 int error; 2060 2061 /* 2062 * Cancel any pending I/O. 2063 */ 2064 alc_stop(ifp, 0); 2065 /* 2066 * Reset the chip to a known state. 2067 */ 2068 alc_reset(sc); 2069 2070 /* Initialize Rx descriptors. */ 2071 error = alc_init_rx_ring(sc, init); 2072 if (error != 0) { 2073 printf("%s: no memory for Rx buffers.\n", device_xname(sc->sc_dev)); 2074 alc_stop(ifp, 0); 2075 return (error); 2076 } 2077 alc_init_rr_ring(sc); 2078 alc_init_tx_ring(sc); 2079 alc_init_cmb(sc); 2080 alc_init_smb(sc); 2081 2082 /* Enable all clocks. */ 2083 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 2084 2085 /* Reprogram the station address. */ 2086 memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr)); 2087 CSR_WRITE_4(sc, ALC_PAR0, 2088 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2089 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2090 /* 2091 * Clear WOL status and disable all WOL feature as WOL 2092 * would interfere Rx operation under normal environments. 2093 */ 2094 CSR_READ_4(sc, ALC_WOL_CFG); 2095 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2096 /* Set Tx descriptor base addresses. */ 2097 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2098 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2099 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2100 /* We don't use high priority ring. */ 2101 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2102 /* Set Tx descriptor counter. */ 2103 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2104 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2105 /* Set Rx descriptor base addresses. */ 2106 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2107 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2108 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2109 /* We use one Rx ring. */ 2110 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2111 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2112 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2113 /* Set Rx descriptor counter. */ 2114 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2115 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2116 2117 /* 2118 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2119 * if it do not fit the buffer size. Rx return descriptor holds 2120 * a counter that indicates how many fragments were made by the 2121 * hardware. The buffer size should be multiple of 8 bytes. 2122 * Since hardware has limit on the size of buffer size, always 2123 * use the maximum value. 2124 * For strict-alignment architectures make sure to reduce buffer 2125 * size by 8 bytes to make room for alignment fixup. 2126 */ 2127 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2128 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2129 2130 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2131 /* Set Rx return descriptor base addresses. */ 2132 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2133 /* We use one Rx return ring. */ 2134 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2135 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2136 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2137 /* Set Rx return descriptor counter. */ 2138 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2139 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2140 paddr = sc->alc_rdata.alc_cmb_paddr; 2141 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2142 paddr = sc->alc_rdata.alc_smb_paddr; 2143 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2144 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2145 2146 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) { 2147 /* Reconfigure SRAM - Vendor magic. */ 2148 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 2149 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 2150 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 2151 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 2152 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 2153 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 2154 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 2155 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 2156 } 2157 2158 /* Tell hardware that we're ready to load DMA blocks. */ 2159 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2160 2161 /* Configure interrupt moderation timer. */ 2162 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 2163 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 2164 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2165 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2166 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2167 /* 2168 * We don't want to automatic interrupt clear as task queue 2169 * for the interrupt should know interrupt status. 2170 */ 2171 reg = MASTER_SA_TIMER_ENB; 2172 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2173 reg |= MASTER_IM_RX_TIMER_ENB; 2174 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 2175 reg |= MASTER_IM_TX_TIMER_ENB; 2176 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2177 /* 2178 * Disable interrupt re-trigger timer. We don't want automatic 2179 * re-triggering of un-ACKed interrupts. 2180 */ 2181 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2182 /* Configure CMB. */ 2183 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2184 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2185 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2186 else 2187 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2188 /* 2189 * Hardware can be configured to issue SMB interrupt based 2190 * on programmed interval. Since there is a callout that is 2191 * invoked for every hz in driver we use that instead of 2192 * relying on periodic SMB interrupt. 2193 */ 2194 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 2195 /* Clear MAC statistics. */ 2196 alc_stats_clear(sc); 2197 2198 /* 2199 * Always use maximum frame size that controller can support. 2200 * Otherwise received frames that has larger frame length 2201 * than alc(4) MTU would be silently dropped in hardware. This 2202 * would make path-MTU discovery hard as sender wouldn't get 2203 * any responses from receiver. alc(4) supports 2204 * multi-fragmented frames on Rx path so it has no issue on 2205 * assembling fragmented frames. Using maximum frame size also 2206 * removes the need to reinitialize hardware when interface 2207 * MTU configuration was changed. 2208 * 2209 * Be conservative in what you do, be liberal in what you 2210 * accept from others - RFC 793. 2211 */ 2212 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 2213 2214 /* Disable header split(?) */ 2215 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 2216 2217 /* Configure IPG/IFG parameters. */ 2218 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 2219 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2220 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2221 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2222 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2223 /* Set parameters for half-duplex media. */ 2224 CSR_WRITE_4(sc, ALC_HDPX_CFG, 2225 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2226 HDPX_CFG_LCOL_MASK) | 2227 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2228 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2229 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2230 HDPX_CFG_ABEBT_MASK) | 2231 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2232 HDPX_CFG_JAMIPG_MASK)); 2233 /* 2234 * Set TSO/checksum offload threshold. For frames that is 2235 * larger than this threshold, hardware wouldn't do 2236 * TSO/checksum offloading. 2237 */ 2238 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 2239 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 2240 TSO_OFFLOAD_THRESH_MASK); 2241 /* Configure TxQ. */ 2242 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 2243 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 2244 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2245 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2246 reg >>= 1; 2247 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 2248 TXQ_CFG_TD_BURST_MASK; 2249 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 2250 2251 /* Configure Rx free descriptor pre-fetching. */ 2252 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 2253 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 2254 RX_RD_FREE_THRESH_HI_MASK) | 2255 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 2256 RX_RD_FREE_THRESH_LO_MASK)); 2257 2258 /* 2259 * Configure flow control parameters. 2260 * XON : 80% of Rx FIFO 2261 * XOFF : 30% of Rx FIFO 2262 */ 2263 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8131 || 2264 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8132) { 2265 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 2266 rxf_hi = (reg * 8) / 10; 2267 rxf_lo = (reg * 3) / 10; 2268 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 2269 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2270 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2271 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2272 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2273 } 2274 2275 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B || 2276 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2) 2277 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 2278 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 2279 SERDES_PHY_CLK_SLOWDOWN); 2280 2281 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 2282 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 2283 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 2284 2285 /* Configure RxQ. */ 2286 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2287 RXQ_CFG_RD_BURST_MASK; 2288 reg |= RXQ_CFG_RSS_MODE_DIS; 2289 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 2290 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 2291 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2292 2293 /* Configure DMA parameters. */ 2294 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 2295 reg |= sc->alc_rcb; 2296 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2297 reg |= DMA_CFG_CMB_ENB; 2298 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 2299 reg |= DMA_CFG_SMB_ENB; 2300 else 2301 reg |= DMA_CFG_SMB_DIS; 2302 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 2303 DMA_CFG_RD_BURST_SHIFT; 2304 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 2305 DMA_CFG_WR_BURST_SHIFT; 2306 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2307 DMA_CFG_RD_DELAY_CNT_MASK; 2308 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2309 DMA_CFG_WR_DELAY_CNT_MASK; 2310 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2311 2312 /* 2313 * Configure Tx/Rx MACs. 2314 * - Auto-padding for short frames. 2315 * - Enable CRC generation. 2316 * Actual reconfiguration of MAC for resolved speed/duplex 2317 * is followed after detection of link establishment. 2318 * AR813x/AR815x always does checksum computation regardless 2319 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 2320 * have bug in protocol field in Rx return structure so 2321 * these controllers can't handle fragmented frames. Disable 2322 * Rx checksum offloading until there is a newer controller 2323 * that has sane implementation. 2324 */ 2325 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2326 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2327 MAC_CFG_PREAMBLE_MASK); 2328 if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151 || 2329 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8151_V2 || 2330 sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B2) 2331 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2332 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 2333 reg |= MAC_CFG_SPEED_10_100; 2334 else 2335 reg |= MAC_CFG_SPEED_1000; 2336 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2337 2338 /* Set up the receive filter. */ 2339 alc_iff(sc); 2340 alc_rxvlan(sc); 2341 2342 /* Acknowledge all pending interrupts and clear it. */ 2343 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 2344 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2345 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 2346 2347 sc->alc_flags &= ~ALC_FLAG_LINK; 2348 /* Switch to the current media. */ 2349 mii = &sc->sc_miibus; 2350 mii_mediachg(mii); 2351 2352 callout_schedule(&sc->sc_tick_ch, hz); 2353 2354 ifp->if_flags |= IFF_RUNNING; 2355 ifp->if_flags &= ~IFF_OACTIVE; 2356 2357 return (0); 2358 } 2359 2360 static void 2361 alc_stop(struct ifnet *ifp, int disable) 2362 { 2363 struct alc_softc *sc = ifp->if_softc; 2364 struct alc_txdesc *txd; 2365 struct alc_rxdesc *rxd; 2366 uint32_t reg; 2367 int i; 2368 2369 callout_stop(&sc->sc_tick_ch); 2370 2371 /* 2372 * Mark the interface down and cancel the watchdog timer. 2373 */ 2374 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2375 ifp->if_timer = 0; 2376 2377 sc->alc_flags &= ~ALC_FLAG_LINK; 2378 2379 alc_stats_update(sc); 2380 2381 mii_down(&sc->sc_miibus); 2382 2383 /* Disable interrupts. */ 2384 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 2385 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2386 alc_stop_queue(sc); 2387 2388 /* Disable DMA. */ 2389 reg = CSR_READ_4(sc, ALC_DMA_CFG); 2390 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 2391 reg |= DMA_CFG_SMB_DIS; 2392 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 2393 DELAY(1000); 2394 2395 /* Stop Rx/Tx MACs. */ 2396 alc_stop_mac(sc); 2397 2398 /* Disable interrupts which might be touched in taskq handler. */ 2399 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 2400 2401 /* Reclaim Rx buffers that have been processed. */ 2402 if (sc->alc_cdata.alc_rxhead != NULL) 2403 m_freem(sc->alc_cdata.alc_rxhead); 2404 ALC_RXCHAIN_RESET(sc); 2405 /* 2406 * Free Tx/Rx mbufs still in the queues. 2407 */ 2408 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2409 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2410 if (rxd->rx_m != NULL) { 2411 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 2412 m_freem(rxd->rx_m); 2413 rxd->rx_m = NULL; 2414 } 2415 } 2416 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2417 txd = &sc->alc_cdata.alc_txdesc[i]; 2418 if (txd->tx_m != NULL) { 2419 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap); 2420 m_freem(txd->tx_m); 2421 txd->tx_m = NULL; 2422 } 2423 } 2424 } 2425 2426 static void 2427 alc_stop_mac(struct alc_softc *sc) 2428 { 2429 uint32_t reg; 2430 int i; 2431 2432 /* Disable Rx/Tx MAC. */ 2433 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2434 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2435 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2436 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2437 } 2438 for (i = ALC_TIMEOUT; i > 0; i--) { 2439 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2440 if (reg == 0) 2441 break; 2442 DELAY(10); 2443 } 2444 if (i == 0) 2445 printf("%s: could not disable Rx/Tx MAC(0x%08x)!\n", 2446 device_xname(sc->sc_dev), reg); 2447 } 2448 2449 static void 2450 alc_start_queue(struct alc_softc *sc) 2451 { 2452 uint32_t qcfg[] = { 2453 0, 2454 RXQ_CFG_QUEUE0_ENB, 2455 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 2456 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 2457 RXQ_CFG_ENB 2458 }; 2459 uint32_t cfg; 2460 2461 /* Enable RxQ. */ 2462 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 2463 cfg &= ~RXQ_CFG_ENB; 2464 cfg |= qcfg[1]; 2465 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 2466 /* Enable TxQ. */ 2467 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 2468 cfg |= TXQ_CFG_ENB; 2469 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 2470 } 2471 2472 static void 2473 alc_stop_queue(struct alc_softc *sc) 2474 { 2475 uint32_t reg; 2476 int i; 2477 2478 /* Disable RxQ. */ 2479 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 2480 if ((reg & RXQ_CFG_ENB) != 0) { 2481 reg &= ~RXQ_CFG_ENB; 2482 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 2483 } 2484 /* Disable TxQ. */ 2485 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 2486 if ((reg & TXQ_CFG_ENB) != 0) { 2487 reg &= ~TXQ_CFG_ENB; 2488 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 2489 } 2490 for (i = ALC_TIMEOUT; i > 0; i--) { 2491 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 2492 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 2493 break; 2494 DELAY(10); 2495 } 2496 if (i == 0) 2497 printf("%s: could not disable RxQ/TxQ (0x%08x)!\n", 2498 device_xname(sc->sc_dev), reg); 2499 } 2500 2501 static void 2502 alc_init_tx_ring(struct alc_softc *sc) 2503 { 2504 struct alc_ring_data *rd; 2505 struct alc_txdesc *txd; 2506 int i; 2507 2508 sc->alc_cdata.alc_tx_prod = 0; 2509 sc->alc_cdata.alc_tx_cons = 0; 2510 sc->alc_cdata.alc_tx_cnt = 0; 2511 2512 rd = &sc->alc_rdata; 2513 memset(rd->alc_tx_ring, 0, ALC_TX_RING_SZ); 2514 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2515 txd = &sc->alc_cdata.alc_txdesc[i]; 2516 txd->tx_m = NULL; 2517 } 2518 2519 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, 2520 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2521 } 2522 2523 static int 2524 alc_init_rx_ring(struct alc_softc *sc, bool init) 2525 { 2526 struct alc_ring_data *rd; 2527 struct alc_rxdesc *rxd; 2528 int i; 2529 2530 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 2531 rd = &sc->alc_rdata; 2532 memset(rd->alc_rx_ring, 0, ALC_RX_RING_SZ); 2533 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2534 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2535 rxd->rx_m = NULL; 2536 rxd->rx_desc = &rd->alc_rx_ring[i]; 2537 if (alc_newbuf(sc, rxd, init) != 0) 2538 return (ENOBUFS); 2539 } 2540 2541 /* 2542 * Since controller does not update Rx descriptors, driver 2543 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 2544 * is enough to ensure coherence. 2545 */ 2546 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0, 2547 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2548 /* Let controller know availability of new Rx buffers. */ 2549 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 2550 2551 return (0); 2552 } 2553 2554 static void 2555 alc_init_rr_ring(struct alc_softc *sc) 2556 { 2557 struct alc_ring_data *rd; 2558 2559 sc->alc_cdata.alc_rr_cons = 0; 2560 ALC_RXCHAIN_RESET(sc); 2561 2562 rd = &sc->alc_rdata; 2563 memset(rd->alc_rr_ring, 0, ALC_RR_RING_SZ); 2564 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0, 2565 sc->alc_cdata.alc_rr_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2566 } 2567 2568 static void 2569 alc_init_cmb(struct alc_softc *sc) 2570 { 2571 struct alc_ring_data *rd; 2572 2573 rd = &sc->alc_rdata; 2574 memset(rd->alc_cmb, 0, ALC_CMB_SZ); 2575 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, 2576 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2577 } 2578 2579 static void 2580 alc_init_smb(struct alc_softc *sc) 2581 { 2582 struct alc_ring_data *rd; 2583 2584 rd = &sc->alc_rdata; 2585 memset(rd->alc_smb, 0, ALC_SMB_SZ); 2586 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, 2587 sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2588 } 2589 2590 static void 2591 alc_rxvlan(struct alc_softc *sc) 2592 { 2593 uint32_t reg; 2594 2595 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2596 if (sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) 2597 reg |= MAC_CFG_VLAN_TAG_STRIP; 2598 else 2599 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2600 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2601 } 2602 2603 static void 2604 alc_iff(struct alc_softc *sc) 2605 { 2606 struct ethercom *ec = &sc->sc_ec; 2607 struct ifnet *ifp = &ec->ec_if; 2608 struct ether_multi *enm; 2609 struct ether_multistep step; 2610 uint32_t crc; 2611 uint32_t mchash[2]; 2612 uint32_t rxcfg; 2613 2614 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 2615 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2616 ifp->if_flags &= ~IFF_ALLMULTI; 2617 2618 /* 2619 * Always accept broadcast frames. 2620 */ 2621 rxcfg |= MAC_CFG_BCAST; 2622 2623 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 2624 ifp->if_flags |= IFF_ALLMULTI; 2625 if (ifp->if_flags & IFF_PROMISC) 2626 rxcfg |= MAC_CFG_PROMISC; 2627 else 2628 rxcfg |= MAC_CFG_ALLMULTI; 2629 mchash[0] = mchash[1] = 0xFFFFFFFF; 2630 } else { 2631 /* Program new filter. */ 2632 memset(mchash, 0, sizeof(mchash)); 2633 2634 ETHER_FIRST_MULTI(step, ec, enm); 2635 while (enm != NULL) { 2636 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2637 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2638 ETHER_NEXT_MULTI(step, enm); 2639 } 2640 } 2641 2642 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 2643 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 2644 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 2645 } 2646 2647 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci"); 2648 2649 #ifdef _MODULE 2650 #include "ioconf.c" 2651 #endif 2652 2653 static int 2654 if_alc_modcmd(modcmd_t cmd, void *opaque) 2655 { 2656 int error = 0; 2657 2658 switch (cmd) { 2659 case MODULE_CMD_INIT: 2660 #ifdef _MODULE 2661 error = config_init_component(cfdriver_ioconf_if_alc, 2662 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 2663 #endif 2664 return error; 2665 case MODULE_CMD_FINI: 2666 #ifdef _MODULE 2667 error = config_fini_component(cfdriver_ioconf_if_alc, 2668 cfattach_ioconf_if_alc, cfdata_ioconf_if_alc); 2669 #endif 2670 return error; 2671 default: 2672 return ENOTTY; 2673 } 2674 } 2675