1 /* $NetBSD: icp_pci.c,v 1.20 2010/11/13 13:52:05 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Niklas Hallqvist. 46 * 4. The name of the author may not be used to endorse or promote products 47 * derived from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 50 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 51 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 52 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 53 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 54 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 58 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 * 60 * from OpenBSD: icp_pci.c,v 1.11 2001/06/12 15:40:30 niklas Exp 61 */ 62 63 /* 64 * This driver would not have written if it was not for the hardware donations 65 * from both ICP-Vortex and �ko.neT. I want to thank them for their support. 66 * 67 * Re-worked for NetBSD by Andrew Doran. Test hardware kindly supplied by 68 * Intel. 69 */ 70 71 #include <sys/cdefs.h> 72 __KERNEL_RCSID(0, "$NetBSD: icp_pci.c,v 1.20 2010/11/13 13:52:05 uebayasi Exp $"); 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 #include <sys/kernel.h> 78 #include <sys/queue.h> 79 #include <sys/buf.h> 80 #include <sys/endian.h> 81 #include <sys/conf.h> 82 83 #include <sys/bus.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcidevs.h> 88 89 #include <dev/ic/icpreg.h> 90 #include <dev/ic/icpvar.h> 91 92 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 93 #define ICP_PCI_PRODUCT_FC 0x200 94 95 /* Mapping registers for various areas */ 96 #define ICP_PCI_DPMEM 0x10 97 #define ICP_PCINEW_IOMEM 0x10 98 #define ICP_PCINEW_IO 0x14 99 #define ICP_PCINEW_DPMEM 0x18 100 101 /* PCI SRAM structure */ 102 #define ICP_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 103 #define ICP_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 104 #define ICP_SWITCH_SUPPORT 0x06 /* u_int8_t, see ICP_NEED_DEINIT */ 105 #define ICP_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 106 #define ICP_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 107 #define ICP_SRAM_SZ 0x40 108 109 /* DPRAM PCI controllers */ 110 #define ICP_DPR_IF 0x00 /* interface area */ 111 #define ICP_6SR (0xff0 - ICP_SRAM_SZ) 112 #define ICP_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 113 #define ICP_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 114 #define ICP_EVENT 0xff8 /* u_int8_t, release event */ 115 #define ICP_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 116 #define ICP_DPRAM_SZ 0x1000 117 118 /* PLX register structure (new PCI controllers) */ 119 #define ICP_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 120 #define ICP_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 121 #define ICP_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 122 #define ICP_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 123 #define ICP_PLX_SERVICE 0x46 /* u_int16_t, service */ 124 #define ICP_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 125 #define ICP_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 126 #define ICP_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 127 #define ICP_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 128 #define ICP_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 129 #define ICP_PLX_SZ 0x80 130 131 /* DPRAM new PCI controllers */ 132 #define ICP_IC 0x00 /* interface */ 133 #define ICP_PCINEW_6SR (0x4000 - ICP_SRAM_SZ) 134 /* SRAM structure */ 135 #define ICP_PCINEW_SZ 0x4000 136 137 /* i960 register structure (PCI MPR controllers) */ 138 #define ICP_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 139 #define ICP_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 140 #define ICP_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 141 #define ICP_MPR_SERVICE 0x16 /* u_int16_t, service */ 142 #define ICP_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 143 #define ICP_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 144 #define ICP_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 145 #define ICP_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 146 #define ICP_SEVERITY 0xefc /* u_int8_t, event severity */ 147 #define ICP_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 148 #define ICP_I960_SZ 0x1000 149 150 /* DPRAM PCI MPR controllers */ 151 #define ICP_I960R 0x00 /* 4KB i960 registers */ 152 #define ICP_MPR_IC ICP_I960_SZ 153 /* interface area */ 154 #define ICP_MPR_6SR (ICP_I960_SZ + 0x3000 - ICP_SRAM_SZ) 155 /* SRAM structure */ 156 #define ICP_MPR_SZ 0x4000 157 158 int icp_pci_match(device_t, cfdata_t, void *); 159 void icp_pci_attach(device_t, device_t, void *); 160 void icp_pci_enable_intr(struct icp_softc *); 161 int icp_pci_find_class(struct pci_attach_args *); 162 163 void icp_pci_copy_cmd(struct icp_softc *, struct icp_ccb *); 164 u_int8_t icp_pci_get_status(struct icp_softc *); 165 void icp_pci_intr(struct icp_softc *, struct icp_intr_ctx *); 166 void icp_pci_release_event(struct icp_softc *, struct icp_ccb *); 167 void icp_pci_set_sema0(struct icp_softc *); 168 int icp_pci_test_busy(struct icp_softc *); 169 170 void icp_pcinew_copy_cmd(struct icp_softc *, struct icp_ccb *); 171 u_int8_t icp_pcinew_get_status(struct icp_softc *); 172 void icp_pcinew_intr(struct icp_softc *, struct icp_intr_ctx *); 173 void icp_pcinew_release_event(struct icp_softc *, struct icp_ccb *); 174 void icp_pcinew_set_sema0(struct icp_softc *); 175 int icp_pcinew_test_busy(struct icp_softc *); 176 177 void icp_mpr_copy_cmd(struct icp_softc *, struct icp_ccb *); 178 u_int8_t icp_mpr_get_status(struct icp_softc *); 179 void icp_mpr_intr(struct icp_softc *, struct icp_intr_ctx *); 180 void icp_mpr_release_event(struct icp_softc *, struct icp_ccb *); 181 void icp_mpr_set_sema0(struct icp_softc *); 182 int icp_mpr_test_busy(struct icp_softc *); 183 184 CFATTACH_DECL(icp_pci, sizeof(struct icp_softc), 185 icp_pci_match, icp_pci_attach, NULL, NULL); 186 187 struct icp_pci_ident { 188 u_short gpi_vendor; 189 u_short gpi_product; 190 u_short gpi_class; 191 } const icp_pci_ident[] = { 192 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_60x0, ICP_PCI }, 193 { PCI_VENDOR_VORTEX, PCI_PRODUCT_VORTEX_GDT_6000B, ICP_PCI }, 194 195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID1, ICP_MPR }, 196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GDT_RAID2, ICP_MPR }, 197 }; 198 199 int 200 icp_pci_find_class(struct pci_attach_args *pa) 201 { 202 const struct icp_pci_ident *gpi, *maxgpi; 203 204 gpi = icp_pci_ident; 205 maxgpi = gpi + sizeof(icp_pci_ident) / sizeof(icp_pci_ident[0]); 206 207 for (; gpi < maxgpi; gpi++) 208 if (PCI_VENDOR(pa->pa_id) == gpi->gpi_vendor && 209 PCI_PRODUCT(pa->pa_id) == gpi->gpi_product) 210 return (gpi->gpi_class); 211 212 /* 213 * ICP-Vortex only make RAID controllers, so we employ a heuristic 214 * to match unlisted boards. 215 */ 216 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) 217 return (PCI_PRODUCT(pa->pa_id) < 0x100 ? ICP_PCINEW : ICP_MPR); 218 219 return (-1); 220 } 221 222 int 223 icp_pci_match(device_t parent, cfdata_t match, void *aux) 224 { 225 struct pci_attach_args *pa; 226 227 pa = aux; 228 229 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 230 return (0); 231 232 return (icp_pci_find_class(pa) != -1); 233 } 234 235 void 236 icp_pci_attach(device_t parent, device_t self, void *aux) 237 { 238 struct pci_attach_args *pa; 239 struct icp_softc *icp; 240 bus_space_tag_t dpmemt, iomemt, iot; 241 bus_space_handle_t dpmemh, iomemh, ioh; 242 bus_addr_t dpmembase, iomembase, iobase; 243 bus_size_t dpmemsize, iomemsize, iosize; 244 u_int32_t status; 245 #define DPMEM_MAPPED 1 246 #define IOMEM_MAPPED 2 247 #define IO_MAPPED 4 248 #define INTR_ESTABLISHED 8 249 int retries; 250 u_int8_t protocol; 251 pci_intr_handle_t ih; 252 const char *intrstr; 253 254 pa = aux; 255 status = 0; 256 icp = device_private(self); 257 icp->icp_class = icp_pci_find_class(pa); 258 259 aprint_naive(": RAID controller\n"); 260 aprint_normal(": "); 261 262 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 263 PCI_PRODUCT(pa->pa_id) >= ICP_PCI_PRODUCT_FC) 264 icp->icp_class |= ICP_FC; 265 266 if (pci_mapreg_map(pa, 267 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : ICP_PCI_DPMEM, 268 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 269 &dpmemh, &dpmembase, &dpmemsize)) { 270 if (pci_mapreg_map(pa, 271 ICP_CLASS(icp) == ICP_PCINEW ? ICP_PCINEW_DPMEM : 272 ICP_PCI_DPMEM, 273 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 274 &dpmemt, &dpmemh, &dpmembase, &dpmemsize)) { 275 aprint_error("cannot map DPMEM\n"); 276 goto bail_out; 277 } 278 } 279 status |= DPMEM_MAPPED; 280 icp->icp_dpmemt = dpmemt; 281 icp->icp_dpmemh = dpmemh; 282 icp->icp_dpmembase = dpmembase; 283 icp->icp_dmat = pa->pa_dmat; 284 285 /* 286 * The ICP_PCINEW series also has two other regions to map. 287 */ 288 if (ICP_CLASS(icp) == ICP_PCINEW) { 289 if (pci_mapreg_map(pa, ICP_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 290 0, &iomemt, &iomemh, &iomembase, &iomemsize)) { 291 aprint_error("cannot map memory mapped I/O ports\n"); 292 goto bail_out; 293 } 294 status |= IOMEM_MAPPED; 295 296 if (pci_mapreg_map(pa, ICP_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 297 &iot, &ioh, &iobase, &iosize)) { 298 aprint_error("cannot map I/O ports\n"); 299 goto bail_out; 300 } 301 status |= IO_MAPPED; 302 icp->icp_iot = iot; 303 icp->icp_ioh = ioh; 304 icp->icp_iobase = iobase; 305 } 306 307 switch (ICP_CLASS(icp)) { 308 case ICP_PCI: 309 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 310 ICP_DPR_IF_SZ >> 2); 311 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 312 aprint_error("cannot write to DPMEM\n"); 313 goto bail_out; 314 } 315 316 #if 0 317 /* disable board interrupts, deinit services */ 318 icph_writeb(0xff, &dp6_ptr->io.irqdel); 319 icph_writeb(0x00, &dp6_ptr->io.irqen); 320 icph_writeb(0x00, &dp6_ptr->u.ic.S_Status); 321 icph_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 322 323 icph_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 324 icph_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 325 icph_writeb(0, &dp6_ptr->io.event); 326 retries = INIT_RETRIES; 327 icph_delay(20); 328 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 329 if (--retries == 0) { 330 printk("initialization error (DEINIT failed)\n"); 331 icph_munmap(ha->brd); 332 return 0; 333 } 334 icph_delay(1); 335 } 336 prot_ver = (unchar)icph_readl(&dp6_ptr->u.ic.S_Info[0]); 337 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 338 icph_writeb(0xff, &dp6_ptr->io.irqdel); 339 if (prot_ver != PROTOCOL_VERSION) { 340 printk("illegal protocol version\n"); 341 icph_munmap(ha->brd); 342 return 0; 343 } 344 345 ha->type = ICP_PCI; 346 ha->ic_all_size = sizeof(dp6_ptr->u); 347 348 /* special command to controller BIOS */ 349 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 350 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 351 icph_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 352 icph_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 353 icph_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 354 icph_writeb(0, &dp6_ptr->io.event); 355 retries = INIT_RETRIES; 356 icph_delay(20); 357 while (icph_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 358 if (--retries == 0) { 359 printk("initialization error\n"); 360 icph_munmap(ha->brd); 361 return 0; 362 } 363 icph_delay(1); 364 } 365 icph_writeb(0, &dp6_ptr->u.ic.S_Status); 366 icph_writeb(0xff, &dp6_ptr->io.irqdel); 367 #endif 368 369 icp->icp_ic_all_size = ICP_DPRAM_SZ; 370 371 icp->icp_copy_cmd = icp_pci_copy_cmd; 372 icp->icp_get_status = icp_pci_get_status; 373 icp->icp_intr = icp_pci_intr; 374 icp->icp_release_event = icp_pci_release_event; 375 icp->icp_set_sema0 = icp_pci_set_sema0; 376 icp->icp_test_busy = icp_pci_test_busy; 377 378 break; 379 380 case ICP_PCINEW: 381 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 382 ICP_DPR_IF_SZ >> 2); 383 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 384 aprint_error("cannot write to DPMEM\n"); 385 goto bail_out; 386 } 387 388 #if 0 389 /* disable board interrupts, deinit services */ 390 outb(0x00,PTR2USHORT(&ha->plx->control1)); 391 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 392 393 icph_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 394 icph_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 395 396 icph_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 397 icph_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 398 399 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 400 401 retries = INIT_RETRIES; 402 icph_delay(20); 403 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 404 if (--retries == 0) { 405 printk("initialization error (DEINIT failed)\n"); 406 icph_munmap(ha->brd); 407 return 0; 408 } 409 icph_delay(1); 410 } 411 prot_ver = (unchar)icph_readl(&dp6c_ptr->u.ic.S_Info[0]); 412 icph_writeb(0, &dp6c_ptr->u.ic.Status); 413 if (prot_ver != PROTOCOL_VERSION) { 414 printk("illegal protocol version\n"); 415 icph_munmap(ha->brd); 416 return 0; 417 } 418 419 ha->type = ICP_PCINEW; 420 ha->ic_all_size = sizeof(dp6c_ptr->u); 421 422 /* special command to controller BIOS */ 423 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 424 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 425 icph_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 426 icph_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 427 icph_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 428 429 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 430 431 retries = INIT_RETRIES; 432 icph_delay(20); 433 while (icph_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 434 if (--retries == 0) { 435 printk("initialization error\n"); 436 icph_munmap(ha->brd); 437 return 0; 438 } 439 icph_delay(1); 440 } 441 icph_writeb(0, &dp6c_ptr->u.ic.S_Status); 442 #endif 443 444 icp->icp_ic_all_size = ICP_PCINEW_SZ; 445 446 icp->icp_copy_cmd = icp_pcinew_copy_cmd; 447 icp->icp_get_status = icp_pcinew_get_status; 448 icp->icp_intr = icp_pcinew_intr; 449 icp->icp_release_event = icp_pcinew_release_event; 450 icp->icp_set_sema0 = icp_pcinew_set_sema0; 451 icp->icp_test_busy = icp_pcinew_test_busy; 452 453 break; 454 455 case ICP_MPR: 456 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC, ICP_MPR_MAGIC); 457 if (bus_space_read_4(dpmemt, dpmemh, ICP_MPR_IC) != 458 ICP_MPR_MAGIC) { 459 aprint_error( 460 "cannot access DPMEM at 0x%lx (shadowed?)\n", 461 (u_long)dpmembase); 462 goto bail_out; 463 } 464 465 /* 466 * XXX Here the Linux driver has a weird remapping logic I 467 * don't understand. My controller does not need it, and I 468 * cannot see what purpose it serves, therefore I did not 469 * do anything similar. 470 */ 471 472 bus_space_set_region_4(dpmemt, dpmemh, ICP_I960_SZ, 0, 473 ICP_DPR_IF_SZ >> 2); 474 475 /* Disable everything. */ 476 bus_space_write_1(dpmemt, dpmemh, ICP_EDOOR_EN, 477 bus_space_read_1(dpmemt, dpmemh, ICP_EDOOR_EN) | 4); 478 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_EDOOR, 0xff); 479 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 480 0); 481 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_CMD_INDEX, 482 0); 483 484 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 485 htole32(dpmembase)); 486 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 487 0xff); 488 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 489 490 DELAY(20); 491 retries = 1000000; 492 while (bus_space_read_1(dpmemt, dpmemh, 493 ICP_MPR_IC + ICP_S_STATUS) != 0xff) { 494 if (--retries == 0) { 495 aprint_error("DEINIT failed\n"); 496 goto bail_out; 497 } 498 DELAY(1); 499 } 500 501 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 502 ICP_MPR_IC + ICP_S_INFO); 503 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 504 0); 505 if (protocol != ICP_PROTOCOL_VERSION) { 506 aprint_error("unsupported protocol %d\n", protocol); 507 goto bail_out; 508 } 509 510 /* special commnd to controller BIOS */ 511 bus_space_write_4(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_INFO, 0); 512 bus_space_write_4(dpmemt, dpmemh, 513 ICP_MPR_IC + ICP_S_INFO + sizeof(u_int32_t), 0); 514 bus_space_write_4(dpmemt, dpmemh, 515 ICP_MPR_IC + ICP_S_INFO + 2 * sizeof(u_int32_t), 1); 516 bus_space_write_4(dpmemt, dpmemh, 517 ICP_MPR_IC + ICP_S_INFO + 3 * sizeof(u_int32_t), 0); 518 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_CMD_INDX, 519 0xfe); 520 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_LDOOR, 1); 521 522 DELAY(20); 523 retries = 1000000; 524 while (bus_space_read_1(dpmemt, dpmemh, 525 ICP_MPR_IC + ICP_S_STATUS) != 0xfe) { 526 if (--retries == 0) { 527 aprint_error("initialization error\n"); 528 goto bail_out; 529 } 530 DELAY(1); 531 } 532 533 bus_space_write_1(dpmemt, dpmemh, ICP_MPR_IC + ICP_S_STATUS, 534 0); 535 536 icp->icp_copy_cmd = icp_mpr_copy_cmd; 537 icp->icp_get_status = icp_mpr_get_status; 538 icp->icp_intr = icp_mpr_intr; 539 icp->icp_release_event = icp_mpr_release_event; 540 icp->icp_set_sema0 = icp_mpr_set_sema0; 541 icp->icp_test_busy = icp_mpr_test_busy; 542 break; 543 } 544 545 if (pci_intr_map(pa, &ih)) { 546 aprint_error("couldn't map interrupt\n"); 547 goto bail_out; 548 } 549 intrstr = pci_intr_string(pa->pa_pc, ih); 550 icp->icp_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, icp_intr, icp); 551 if (icp->icp_ih == NULL) { 552 aprint_error("couldn't establish interrupt"); 553 if (intrstr != NULL) 554 aprint_error(" at %s", intrstr); 555 aprint_error("\n"); 556 goto bail_out; 557 } 558 status |= INTR_ESTABLISHED; 559 560 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) 561 aprint_normal("Intel Storage RAID controller\n"); 562 else 563 aprint_normal("ICP-Vortex RAID controller\n"); 564 565 icp->icp_pci_bus = pa->pa_bus; 566 icp->icp_pci_device = pa->pa_device; 567 icp->icp_pci_device_id = PCI_PRODUCT(pa->pa_id); 568 icp->icp_pci_subdevice_id = pci_conf_read(pa->pa_pc, pa->pa_tag, 569 PCI_SUBSYS_ID_REG); 570 571 if (icp_init(icp, intrstr)) 572 goto bail_out; 573 574 icp_pci_enable_intr(icp); 575 return; 576 577 bail_out: 578 if ((status & DPMEM_MAPPED) != 0) 579 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 580 if ((status & IOMEM_MAPPED) != 0) 581 bus_space_unmap(iomemt, iomemh, iomembase); 582 if ((status & IO_MAPPED) != 0) 583 bus_space_unmap(iot, ioh, iosize); 584 if ((status & INTR_ESTABLISHED) != 0) 585 pci_intr_disestablish(pa->pa_pc, icp->icp_ih); 586 } 587 588 /* 589 * Enable interrupts. 590 */ 591 void 592 icp_pci_enable_intr(struct icp_softc *icp) 593 { 594 595 switch (ICP_CLASS(icp)) { 596 case ICP_PCI: 597 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQDEL, 598 1); 599 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 600 ICP_CMD_INDEX, 0); 601 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_IRQEN, 602 1); 603 break; 604 605 case ICP_PCINEW: 606 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_EDOOR_REG, 607 0xff); 608 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_CONTROL1, 3); 609 break; 610 611 case ICP_MPR: 612 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, 613 ICP_MPR_EDOOR, 0xff); 614 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_EDOOR_EN, 615 bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 616 ICP_EDOOR_EN) & ~4); 617 break; 618 } 619 } 620 621 /* 622 * "Old" PCI controller-specific functions. 623 */ 624 625 void 626 icp_pci_copy_cmd(struct icp_softc *icp, struct icp_ccb *ccb) 627 { 628 629 /* XXX Not yet implemented */ 630 } 631 632 u_int8_t 633 icp_pci_get_status(struct icp_softc *icp) 634 { 635 636 /* XXX Not yet implemented */ 637 return (0); 638 } 639 640 void 641 icp_pci_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 642 { 643 644 /* XXX Not yet implemented */ 645 } 646 647 void 648 icp_pci_release_event(struct icp_softc *icp, 649 struct icp_ccb *ccb) 650 { 651 652 /* XXX Not yet implemented */ 653 } 654 655 void 656 icp_pci_set_sema0(struct icp_softc *icp) 657 { 658 659 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_SEMA0, 1); 660 } 661 662 int 663 icp_pci_test_busy(struct icp_softc *icp) 664 { 665 666 /* XXX Not yet implemented */ 667 return (0); 668 } 669 670 /* 671 * "New" PCI controller-specific functions. 672 */ 673 674 void 675 icp_pcinew_copy_cmd(struct icp_softc *icp, 676 struct icp_ccb *ccb) 677 { 678 679 /* XXX Not yet implemented */ 680 } 681 682 u_int8_t 683 icp_pcinew_get_status(struct icp_softc *icp) 684 { 685 686 /* XXX Not yet implemented */ 687 return (0); 688 } 689 690 void 691 icp_pcinew_intr(struct icp_softc *icp, 692 struct icp_intr_ctx *ctx) 693 { 694 695 /* XXX Not yet implemented */ 696 } 697 698 void 699 icp_pcinew_release_event(struct icp_softc *icp, 700 struct icp_ccb *ccb) 701 { 702 703 /* XXX Not yet implemented */ 704 } 705 706 void 707 icp_pcinew_set_sema0(struct icp_softc *icp) 708 { 709 710 bus_space_write_1(icp->icp_iot, icp->icp_ioh, ICP_SEMA0_REG, 1); 711 } 712 713 int 714 icp_pcinew_test_busy(struct icp_softc *icp) 715 { 716 717 /* XXX Not yet implemented */ 718 return (0); 719 } 720 721 /* 722 * MPR PCI controller-specific functions 723 */ 724 725 void 726 icp_mpr_copy_cmd(struct icp_softc *icp, struct icp_ccb *ic) 727 { 728 729 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 730 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_OFFSET, 731 ICP_DPR_CMD); 732 bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh, 733 ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_SERV_ID, 734 ic->ic_service); 735 bus_space_write_region_4(icp->icp_dpmemt, icp->icp_dpmemh, 736 ICP_MPR_IC + ICP_DPR_CMD, (u_int32_t *)&ic->ic_cmd, 737 ic->ic_cmdlen >> 2); 738 } 739 740 u_int8_t 741 icp_mpr_get_status(struct icp_softc *icp) 742 { 743 744 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 745 ICP_MPR_EDOOR)); 746 } 747 748 void 749 icp_mpr_intr(struct icp_softc *icp, struct icp_intr_ctx *ctx) 750 { 751 752 if ((ctx->istatus & 0x80) != 0) { /* error flag */ 753 ctx->istatus &= ~0x80; 754 ctx->cmd_status = bus_space_read_2(icp->icp_dpmemt, 755 icp->icp_dpmemh, ICP_MPR_STATUS); 756 } else 757 ctx->cmd_status = ICP_S_OK; 758 759 ctx->service = bus_space_read_2(icp->icp_dpmemt, icp->icp_dpmemh, 760 ICP_MPR_SERVICE); 761 ctx->info = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 762 ICP_MPR_INFO); 763 ctx->info2 = bus_space_read_4(icp->icp_dpmemt, icp->icp_dpmemh, 764 ICP_MPR_INFO + sizeof(u_int32_t)); 765 766 if (ctx->istatus == ICP_ASYNCINDEX) { 767 if (ctx->service != ICP_SCREENSERVICE && 768 (icp->icp_fw_vers & 0xff) >= 0x1a) { 769 int i; 770 771 icp->icp_evt.severity = 772 bus_space_read_1(icp->icp_dpmemt, 773 icp->icp_dpmemh, ICP_SEVERITY); 774 for (i = 0; 775 i < sizeof(icp->icp_evt.event_string); i++) { 776 icp->icp_evt.event_string[i] = 777 bus_space_read_1(icp->icp_dpmemt, 778 icp->icp_dpmemh, ICP_EVT_BUF + i); 779 if (icp->icp_evt.event_string[i] == '\0') 780 break; 781 } 782 } 783 } 784 785 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_EDOOR, 786 0xff); 787 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA1, 0); 788 } 789 790 void 791 icp_mpr_release_event(struct icp_softc *icp, struct icp_ccb *ic) 792 { 793 794 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_LDOOR, 1); 795 } 796 797 void 798 icp_mpr_set_sema0(struct icp_softc *icp) 799 { 800 801 bus_space_write_1(icp->icp_dpmemt, icp->icp_dpmemh, ICP_MPR_SEMA0, 1); 802 } 803 804 int 805 icp_mpr_test_busy(struct icp_softc *icp) 806 { 807 808 return (bus_space_read_1(icp->icp_dpmemt, icp->icp_dpmemh, 809 ICP_MPR_SEMA0) & 1); 810 } 811