1 /* $NetBSD: ichsmb.c,v 1.56 2018/03/02 08:25:53 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.56 2018/03/02 08:25:53 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 64 struct i2c_controller sc_i2c_tag; 65 kmutex_t sc_i2c_mutex; 66 struct { 67 i2c_op_t op; 68 void * buf; 69 size_t len; 70 int flags; 71 volatile int error; 72 } sc_i2c_xfer; 73 device_t sc_i2c_device; 74 }; 75 76 static int ichsmb_match(device_t, cfdata_t, void *); 77 static void ichsmb_attach(device_t, device_t, void *); 78 static int ichsmb_detach(device_t, int); 79 static int ichsmb_rescan(device_t, const char *, const int *); 80 static void ichsmb_chdet(device_t, device_t); 81 82 static int ichsmb_i2c_acquire_bus(void *, int); 83 static void ichsmb_i2c_release_bus(void *, int); 84 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 85 size_t, void *, size_t, int); 86 87 static int ichsmb_intr(void *); 88 89 #include "ioconf.h" 90 91 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 92 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 93 ichsmb_chdet, 0); 94 95 96 static int 97 ichsmb_match(device_t parent, cfdata_t match, void *aux) 98 { 99 struct pci_attach_args *pa = aux; 100 101 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 102 switch (PCI_PRODUCT(pa->pa_id)) { 103 case PCI_PRODUCT_INTEL_6300ESB_SMB: 104 case PCI_PRODUCT_INTEL_63XXESB_SMB: 105 case PCI_PRODUCT_INTEL_82801AA_SMB: 106 case PCI_PRODUCT_INTEL_82801AB_SMB: 107 case PCI_PRODUCT_INTEL_82801BA_SMB: 108 case PCI_PRODUCT_INTEL_82801CA_SMB: 109 case PCI_PRODUCT_INTEL_82801DB_SMB: 110 case PCI_PRODUCT_INTEL_82801E_SMB: 111 case PCI_PRODUCT_INTEL_82801EB_SMB: 112 case PCI_PRODUCT_INTEL_82801FB_SMB: 113 case PCI_PRODUCT_INTEL_82801G_SMB: 114 case PCI_PRODUCT_INTEL_82801H_SMB: 115 case PCI_PRODUCT_INTEL_82801I_SMB: 116 case PCI_PRODUCT_INTEL_82801JD_SMB: 117 case PCI_PRODUCT_INTEL_82801JI_SMB: 118 case PCI_PRODUCT_INTEL_3400_SMB: 119 case PCI_PRODUCT_INTEL_6SERIES_SMB: 120 case PCI_PRODUCT_INTEL_7SERIES_SMB: 121 case PCI_PRODUCT_INTEL_8SERIES_SMB: 122 case PCI_PRODUCT_INTEL_9SERIES_SMB: 123 case PCI_PRODUCT_INTEL_100SERIES_SMB: 124 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 125 case PCI_PRODUCT_INTEL_2HS_SMB: 126 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 127 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 128 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 129 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 130 case PCI_PRODUCT_INTEL_APL_SMB: 131 case PCI_PRODUCT_INTEL_GLK_SMB: 132 case PCI_PRODUCT_INTEL_C600_SMBUS: 133 case PCI_PRODUCT_INTEL_C600_SMB_0: 134 case PCI_PRODUCT_INTEL_C600_SMB_1: 135 case PCI_PRODUCT_INTEL_C600_SMB_2: 136 case PCI_PRODUCT_INTEL_C610_SMB: 137 case PCI_PRODUCT_INTEL_C620_SMB: 138 case PCI_PRODUCT_INTEL_C620_SMB_S: 139 case PCI_PRODUCT_INTEL_EP80579_SMB: 140 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 141 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 142 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 143 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 144 return 1; 145 } 146 } 147 return 0; 148 } 149 150 static void 151 ichsmb_attach(device_t parent, device_t self, void *aux) 152 { 153 struct ichsmb_softc *sc = device_private(self); 154 struct pci_attach_args *pa = aux; 155 pcireg_t conf; 156 pci_intr_handle_t ih; 157 const char *intrstr = NULL; 158 char intrbuf[PCI_INTRSTR_LEN]; 159 int flags; 160 161 sc->sc_dev = self; 162 sc->sc_pc = pa->pa_pc; 163 164 pci_aprint_devinfo(pa, NULL); 165 166 /* Read configuration */ 167 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 168 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 169 170 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 171 aprint_error_dev(self, "SMBus disabled\n"); 172 goto out; 173 } 174 175 /* Map I/O space */ 176 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 177 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 178 aprint_error_dev(self, "can't map I/O space\n"); 179 goto out; 180 } 181 182 sc->sc_poll = 1; 183 sc->sc_ih = NULL; 184 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 185 /* No PCI IRQ */ 186 aprint_normal_dev(self, "interrupting at SMI\n"); 187 } else { 188 /* Install interrupt handler */ 189 if (pci_intr_map(pa, &ih) == 0) { 190 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 191 sizeof(intrbuf)); 192 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, 193 IPL_BIO, ichsmb_intr, sc, device_xname(sc->sc_dev)); 194 if (sc->sc_ih != NULL) { 195 aprint_normal_dev(self, "interrupting at %s\n", 196 intrstr); 197 sc->sc_poll = 0; 198 } 199 } 200 if (sc->sc_poll) 201 aprint_normal_dev(self, "polling\n"); 202 } 203 204 sc->sc_i2c_device = NULL; 205 flags = 0; 206 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 207 ichsmb_rescan(self, "i2cbus", &flags); 208 209 out: if (!pmf_device_register(self, NULL, NULL)) 210 aprint_error_dev(self, "couldn't establish power handler\n"); 211 } 212 213 static int 214 ichsmb_rescan(device_t self, const char *ifattr, const int *flags) 215 { 216 struct ichsmb_softc *sc = device_private(self); 217 struct i2cbus_attach_args iba; 218 219 if (!ifattr_match(ifattr, "i2cbus")) 220 return 0; 221 222 if (sc->sc_i2c_device) 223 return 0; 224 225 /* Attach I2C bus */ 226 sc->sc_i2c_tag.ic_cookie = sc; 227 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 228 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 229 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 230 231 memset(&iba, 0, sizeof(iba)); 232 iba.iba_type = I2C_TYPE_SMBUS; 233 iba.iba_tag = &sc->sc_i2c_tag; 234 sc->sc_i2c_device = config_found_ia(self, ifattr, &iba, iicbus_print); 235 236 return 0; 237 } 238 239 static int 240 ichsmb_detach(device_t self, int flags) 241 { 242 struct ichsmb_softc *sc = device_private(self); 243 int error; 244 245 if (sc->sc_i2c_device) { 246 error = config_detach(sc->sc_i2c_device, flags); 247 if (error) 248 return error; 249 } 250 251 mutex_destroy(&sc->sc_i2c_mutex); 252 253 if (sc->sc_ih) 254 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 255 256 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 257 258 return 0; 259 } 260 261 static void 262 ichsmb_chdet(device_t self, device_t child) 263 { 264 struct ichsmb_softc *sc = device_private(self); 265 266 if (sc->sc_i2c_device == child) 267 sc->sc_i2c_device = NULL; 268 } 269 270 static int 271 ichsmb_i2c_acquire_bus(void *cookie, int flags) 272 { 273 struct ichsmb_softc *sc = cookie; 274 275 if (cold) 276 return 0; 277 278 mutex_enter(&sc->sc_i2c_mutex); 279 return 0; 280 } 281 282 static void 283 ichsmb_i2c_release_bus(void *cookie, int flags) 284 { 285 struct ichsmb_softc *sc = cookie; 286 287 if (cold) 288 return; 289 290 mutex_exit(&sc->sc_i2c_mutex); 291 } 292 293 static int 294 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 295 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 296 { 297 struct ichsmb_softc *sc = cookie; 298 const uint8_t *b; 299 uint8_t ctl = 0, st; 300 int retries; 301 char fbuf[64]; 302 303 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 304 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 305 len, flags)); 306 307 /* Clear status bits */ 308 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 309 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 310 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 311 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 312 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 313 314 /* Wait for bus to be idle */ 315 for (retries = 100; retries > 0; retries--) { 316 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 317 if (!(st & LPCIB_SMB_HS_BUSY)) 318 break; 319 DELAY(ICHIIC_DELAY); 320 } 321 #ifdef ICHIIC_DEBUG 322 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 323 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 324 #endif 325 if (st & LPCIB_SMB_HS_BUSY) 326 return (1); 327 328 if (cold || sc->sc_poll) 329 flags |= I2C_F_POLL; 330 331 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 332 (cmdlen == 0 && len > 1)) 333 return (1); 334 335 /* Setup transfer */ 336 sc->sc_i2c_xfer.op = op; 337 sc->sc_i2c_xfer.buf = buf; 338 sc->sc_i2c_xfer.len = len; 339 sc->sc_i2c_xfer.flags = flags; 340 sc->sc_i2c_xfer.error = 0; 341 342 /* Set slave address and transfer direction */ 343 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 344 LPCIB_SMB_TXSLVA_ADDR(addr) | 345 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 346 347 b = (const uint8_t *)cmdbuf; 348 if (cmdlen > 0) 349 /* Set command byte */ 350 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 351 352 if (I2C_OP_WRITE_P(op)) { 353 /* Write data */ 354 b = buf; 355 if (cmdlen == 0 && len == 1) 356 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 357 LPCIB_SMB_HCMD, b[0]); 358 else if (len > 0) 359 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 360 LPCIB_SMB_HD0, b[0]); 361 if (len > 1) 362 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 363 LPCIB_SMB_HD1, b[1]); 364 } 365 366 /* Set SMBus command */ 367 if (cmdlen == 0) { 368 if (len == 0) 369 ctl = LPCIB_SMB_HC_CMD_QUICK; 370 else 371 ctl = LPCIB_SMB_HC_CMD_BYTE; 372 } else if (len == 1) 373 ctl = LPCIB_SMB_HC_CMD_BDATA; 374 else if (len == 2) 375 ctl = LPCIB_SMB_HC_CMD_WDATA; 376 377 if ((flags & I2C_F_POLL) == 0) 378 ctl |= LPCIB_SMB_HC_INTREN; 379 380 /* Start transaction */ 381 ctl |= LPCIB_SMB_HC_START; 382 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 383 384 if (flags & I2C_F_POLL) { 385 /* Poll for completion */ 386 DELAY(ICHIIC_DELAY); 387 for (retries = 1000; retries > 0; retries--) { 388 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 389 LPCIB_SMB_HS); 390 if ((st & LPCIB_SMB_HS_BUSY) == 0) 391 break; 392 DELAY(ICHIIC_DELAY); 393 } 394 if (st & LPCIB_SMB_HS_BUSY) 395 goto timeout; 396 ichsmb_intr(sc); 397 } else { 398 /* Wait for interrupt */ 399 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 400 goto timeout; 401 } 402 403 if (sc->sc_i2c_xfer.error) 404 return (1); 405 406 return (0); 407 408 timeout: 409 /* 410 * Transfer timeout. Kill the transaction and clear status bits. 411 */ 412 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 413 aprint_error_dev(sc->sc_dev, 414 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 415 "flags 0x%02x: timeout, status %s\n", 416 op, addr, cmdlen, len, flags, fbuf); 417 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 418 LPCIB_SMB_HC_KILL); 419 DELAY(ICHIIC_DELAY); 420 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 421 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 422 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 423 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 424 fbuf); 425 } 426 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 427 return (1); 428 } 429 430 static int 431 ichsmb_intr(void *arg) 432 { 433 struct ichsmb_softc *sc = arg; 434 uint8_t st; 435 uint8_t *b; 436 size_t len; 437 #ifdef ICHIIC_DEBUG 438 char fbuf[64]; 439 #endif 440 441 /* Read status */ 442 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 443 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 444 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 445 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 446 /* Interrupt was not for us */ 447 return (0); 448 449 #ifdef ICHIIC_DEBUG 450 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 451 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 452 #endif 453 454 /* Clear status bits */ 455 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 456 457 /* Check for errors */ 458 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 459 sc->sc_i2c_xfer.error = 1; 460 goto done; 461 } 462 463 if (st & LPCIB_SMB_HS_INTR) { 464 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 465 goto done; 466 467 /* Read data */ 468 b = sc->sc_i2c_xfer.buf; 469 len = sc->sc_i2c_xfer.len; 470 if (len > 0) 471 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 472 LPCIB_SMB_HD0); 473 if (len > 1) 474 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 475 LPCIB_SMB_HD1); 476 } 477 478 done: 479 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 480 wakeup(sc); 481 return (1); 482 } 483 484 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 485 486 #ifdef _MODULE 487 #include "ioconf.c" 488 #endif 489 490 static int 491 ichsmb_modcmd(modcmd_t cmd, void *opaque) 492 { 493 int error = 0; 494 495 switch (cmd) { 496 case MODULE_CMD_INIT: 497 #ifdef _MODULE 498 error = config_init_component(cfdriver_ioconf_ichsmb, 499 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 500 #endif 501 break; 502 case MODULE_CMD_FINI: 503 #ifdef _MODULE 504 error = config_fini_component(cfdriver_ioconf_ichsmb, 505 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 506 #endif 507 break; 508 default: 509 #ifdef _MODULE 510 error = ENOTTY; 511 #endif 512 break; 513 } 514 515 return error; 516 } 517