1 /* $NetBSD: ichsmb.c,v 1.75 2021/10/27 18:50:57 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.44 2020/10/07 11:23:05 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.75 2021/10/27 18:50:57 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/module.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/ic/i82801lpcreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #ifdef ICHIIC_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define ICHIIC_DELAY 100 52 #define ICHIIC_TIMEOUT 1 53 54 struct ichsmb_softc { 55 device_t sc_dev; 56 57 bus_space_tag_t sc_iot; 58 bus_space_handle_t sc_ioh; 59 bus_size_t sc_size; 60 pci_chipset_tag_t sc_pc; 61 void * sc_ih; 62 int sc_poll; 63 pci_intr_handle_t *sc_pihp; 64 65 kmutex_t sc_exec_lock; 66 kcondvar_t sc_exec_wait; 67 68 struct i2c_controller sc_i2c_tag; 69 struct { 70 i2c_op_t op; 71 void * buf; 72 size_t len; 73 int flags; 74 int error; 75 bool done; 76 } sc_i2c_xfer; 77 device_t sc_i2c_device; 78 }; 79 80 static int ichsmb_match(device_t, cfdata_t, void *); 81 static void ichsmb_attach(device_t, device_t, void *); 82 static int ichsmb_detach(device_t, int); 83 static int ichsmb_rescan(device_t, const char *, const int *); 84 static void ichsmb_chdet(device_t, device_t); 85 86 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 87 size_t, void *, size_t, int); 88 89 static int ichsmb_intr(void *); 90 91 #include "ioconf.h" 92 93 CFATTACH_DECL3_NEW(ichsmb, sizeof(struct ichsmb_softc), 94 ichsmb_match, ichsmb_attach, ichsmb_detach, NULL, ichsmb_rescan, 95 ichsmb_chdet, DVF_DETACH_SHUTDOWN); 96 97 98 static int 99 ichsmb_match(device_t parent, cfdata_t match, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 103 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 104 switch (PCI_PRODUCT(pa->pa_id)) { 105 case PCI_PRODUCT_INTEL_6300ESB_SMB: 106 case PCI_PRODUCT_INTEL_63XXESB_SMB: 107 case PCI_PRODUCT_INTEL_82801AA_SMB: 108 case PCI_PRODUCT_INTEL_82801AB_SMB: 109 case PCI_PRODUCT_INTEL_82801BA_SMB: 110 case PCI_PRODUCT_INTEL_82801CA_SMB: 111 case PCI_PRODUCT_INTEL_82801DB_SMB: 112 case PCI_PRODUCT_INTEL_82801E_SMB: 113 case PCI_PRODUCT_INTEL_82801EB_SMB: 114 case PCI_PRODUCT_INTEL_82801FB_SMB: 115 case PCI_PRODUCT_INTEL_82801G_SMB: 116 case PCI_PRODUCT_INTEL_82801H_SMB: 117 case PCI_PRODUCT_INTEL_82801I_SMB: 118 case PCI_PRODUCT_INTEL_82801JD_SMB: 119 case PCI_PRODUCT_INTEL_82801JI_SMB: 120 case PCI_PRODUCT_INTEL_3400_SMB: 121 case PCI_PRODUCT_INTEL_6SERIES_SMB: 122 case PCI_PRODUCT_INTEL_7SERIES_SMB: 123 case PCI_PRODUCT_INTEL_8SERIES_SMB: 124 case PCI_PRODUCT_INTEL_9SERIES_SMB: 125 case PCI_PRODUCT_INTEL_100SERIES_SMB: 126 case PCI_PRODUCT_INTEL_100SERIES_LP_SMB: 127 case PCI_PRODUCT_INTEL_2HS_SMB: 128 case PCI_PRODUCT_INTEL_3HS_SMB: 129 case PCI_PRODUCT_INTEL_3HS_U_SMB: 130 case PCI_PRODUCT_INTEL_4HS_H_SMB: 131 case PCI_PRODUCT_INTEL_4HS_V_SMB: 132 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 133 case PCI_PRODUCT_INTEL_CORE5G_M_SMB: 134 case PCI_PRODUCT_INTEL_CMTLK_SMB: 135 case PCI_PRODUCT_INTEL_BAYTRAIL_PCU_SMB: 136 case PCI_PRODUCT_INTEL_BSW_PCU_SMB: 137 case PCI_PRODUCT_INTEL_APL_SMB: 138 case PCI_PRODUCT_INTEL_GLK_SMB: 139 case PCI_PRODUCT_INTEL_EHL_SMB: 140 case PCI_PRODUCT_INTEL_JSL_SMB: 141 case PCI_PRODUCT_INTEL_C600_SMBUS: 142 case PCI_PRODUCT_INTEL_C600_SMB_0: 143 case PCI_PRODUCT_INTEL_C600_SMB_1: 144 case PCI_PRODUCT_INTEL_C600_SMB_2: 145 case PCI_PRODUCT_INTEL_C610_SMB: 146 case PCI_PRODUCT_INTEL_C620_SMB: 147 case PCI_PRODUCT_INTEL_C620_SMB_S: 148 case PCI_PRODUCT_INTEL_EP80579_SMB: 149 case PCI_PRODUCT_INTEL_DH89XXCC_SMB: 150 case PCI_PRODUCT_INTEL_DH89XXCL_SMB: 151 case PCI_PRODUCT_INTEL_C2000_PCU_SMBUS: 152 case PCI_PRODUCT_INTEL_C3K_SMBUS_LEGACY: 153 case PCI_PRODUCT_INTEL_495_YU_SMB: 154 case PCI_PRODUCT_INTEL_5HS_H_SMB: 155 case PCI_PRODUCT_INTEL_5HS_LP_SMB: 156 return 1; 157 } 158 } 159 return 0; 160 } 161 162 static void 163 ichsmb_attach(device_t parent, device_t self, void *aux) 164 { 165 struct ichsmb_softc *sc = device_private(self); 166 struct pci_attach_args *pa = aux; 167 pcireg_t conf; 168 const char *intrstr = NULL; 169 char intrbuf[PCI_INTRSTR_LEN]; 170 171 sc->sc_dev = self; 172 sc->sc_pc = pa->pa_pc; 173 174 pci_aprint_devinfo(pa, NULL); 175 176 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 177 cv_init(&sc->sc_exec_wait, device_xname(self)); 178 179 /* Read configuration */ 180 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 181 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 182 183 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 184 aprint_error_dev(self, "SMBus disabled\n"); 185 goto out; 186 } 187 188 /* Map I/O space */ 189 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 190 &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) { 191 aprint_error_dev(self, "can't map I/O space\n"); 192 goto out; 193 } 194 195 sc->sc_poll = 1; 196 sc->sc_ih = NULL; 197 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 198 /* No PCI IRQ */ 199 aprint_normal_dev(self, "interrupting at SMI\n"); 200 } else { 201 /* Install interrupt handler */ 202 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) { 203 intrstr = pci_intr_string(pa->pa_pc, sc->sc_pihp[0], 204 intrbuf, sizeof(intrbuf)); 205 pci_intr_setattr(pa->pa_pc, &sc->sc_pihp[0], 206 PCI_INTR_MPSAFE, true); 207 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, 208 sc->sc_pihp[0], IPL_BIO, ichsmb_intr, sc, 209 device_xname(sc->sc_dev)); 210 if (sc->sc_ih != NULL) { 211 aprint_normal_dev(self, "interrupting at %s\n", 212 intrstr); 213 sc->sc_poll = 0; 214 } else { 215 pci_intr_release(pa->pa_pc, sc->sc_pihp, 1); 216 sc->sc_pihp = NULL; 217 } 218 } 219 if (sc->sc_poll) 220 aprint_normal_dev(self, "polling\n"); 221 } 222 223 sc->sc_i2c_device = NULL; 224 ichsmb_rescan(self, NULL, NULL); 225 226 out: if (!pmf_device_register(self, NULL, NULL)) 227 aprint_error_dev(self, "couldn't establish power handler\n"); 228 } 229 230 static int 231 ichsmb_rescan(device_t self, const char *ifattr, const int *locators) 232 { 233 struct ichsmb_softc *sc = device_private(self); 234 struct i2cbus_attach_args iba; 235 236 if (sc->sc_i2c_device != NULL) 237 return 0; 238 239 /* Attach I2C bus */ 240 iic_tag_init(&sc->sc_i2c_tag); 241 sc->sc_i2c_tag.ic_cookie = sc; 242 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 243 244 memset(&iba, 0, sizeof(iba)); 245 iba.iba_tag = &sc->sc_i2c_tag; 246 sc->sc_i2c_device = config_found(self, &iba, iicbus_print, CFARGS_NONE); 247 248 return 0; 249 } 250 251 static int 252 ichsmb_detach(device_t self, int flags) 253 { 254 struct ichsmb_softc *sc = device_private(self); 255 int error; 256 257 if (sc->sc_i2c_device) { 258 error = config_detach(sc->sc_i2c_device, flags); 259 if (error) 260 return error; 261 } 262 263 iic_tag_fini(&sc->sc_i2c_tag); 264 265 if (sc->sc_ih) { 266 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 267 sc->sc_ih = NULL; 268 } 269 270 if (sc->sc_pihp) { 271 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 272 sc->sc_pihp = NULL; 273 } 274 275 if (sc->sc_size != 0) 276 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); 277 278 mutex_destroy(&sc->sc_exec_lock); 279 cv_destroy(&sc->sc_exec_wait); 280 281 return 0; 282 } 283 284 static void 285 ichsmb_chdet(device_t self, device_t child) 286 { 287 struct ichsmb_softc *sc = device_private(self); 288 289 if (sc->sc_i2c_device == child) 290 sc->sc_i2c_device = NULL; 291 } 292 293 static int 294 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 295 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 296 { 297 struct ichsmb_softc *sc = cookie; 298 const uint8_t *b; 299 uint8_t ctl = 0, st; 300 int retries; 301 char fbuf[64]; 302 303 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 304 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 305 len, flags)); 306 307 mutex_enter(&sc->sc_exec_lock); 308 309 /* Clear status bits */ 310 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 311 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 312 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 313 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 314 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 315 316 /* Wait for bus to be idle */ 317 for (retries = 100; retries > 0; retries--) { 318 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 319 if (!(st & LPCIB_SMB_HS_BUSY)) 320 break; 321 DELAY(ICHIIC_DELAY); 322 } 323 #ifdef ICHIIC_DEBUG 324 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 325 printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf); 326 #endif 327 if (st & LPCIB_SMB_HS_BUSY) { 328 mutex_exit(&sc->sc_exec_lock); 329 return (EBUSY); 330 } 331 332 if (sc->sc_poll) 333 flags |= I2C_F_POLL; 334 335 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 336 (cmdlen == 0 && len > 1)) { 337 mutex_exit(&sc->sc_exec_lock); 338 return (EINVAL); 339 } 340 341 /* Setup transfer */ 342 sc->sc_i2c_xfer.op = op; 343 sc->sc_i2c_xfer.buf = buf; 344 sc->sc_i2c_xfer.len = len; 345 sc->sc_i2c_xfer.flags = flags; 346 sc->sc_i2c_xfer.error = 0; 347 sc->sc_i2c_xfer.done = false; 348 349 /* Set slave address and transfer direction */ 350 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 351 LPCIB_SMB_TXSLVA_ADDR(addr) | 352 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 353 354 b = (const uint8_t *)cmdbuf; 355 if (cmdlen > 0) 356 /* Set command byte */ 357 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 358 359 if (I2C_OP_WRITE_P(op)) { 360 /* Write data */ 361 b = buf; 362 if (cmdlen == 0 && len == 1) 363 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 364 LPCIB_SMB_HCMD, b[0]); 365 else if (len > 0) 366 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 367 LPCIB_SMB_HD0, b[0]); 368 if (len > 1) 369 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 370 LPCIB_SMB_HD1, b[1]); 371 } 372 373 /* Set SMBus command */ 374 if (cmdlen == 0) { 375 if (len == 0) 376 ctl = LPCIB_SMB_HC_CMD_QUICK; 377 else 378 ctl = LPCIB_SMB_HC_CMD_BYTE; 379 } else if (len == 1) 380 ctl = LPCIB_SMB_HC_CMD_BDATA; 381 else if (len == 2) 382 ctl = LPCIB_SMB_HC_CMD_WDATA; 383 384 if ((flags & I2C_F_POLL) == 0) 385 ctl |= LPCIB_SMB_HC_INTREN; 386 387 /* Start transaction */ 388 ctl |= LPCIB_SMB_HC_START; 389 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 390 391 if (flags & I2C_F_POLL) { 392 /* Poll for completion */ 393 DELAY(ICHIIC_DELAY); 394 for (retries = 1000; retries > 0; retries--) { 395 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 396 LPCIB_SMB_HS); 397 if ((st & LPCIB_SMB_HS_BUSY) == 0) 398 break; 399 DELAY(ICHIIC_DELAY); 400 } 401 if (st & LPCIB_SMB_HS_BUSY) 402 goto timeout; 403 ichsmb_intr(sc); 404 } else { 405 /* Wait for interrupt */ 406 while (! sc->sc_i2c_xfer.done) { 407 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 408 ICHIIC_TIMEOUT * hz)) 409 goto timeout; 410 } 411 } 412 413 int error = sc->sc_i2c_xfer.error; 414 mutex_exit(&sc->sc_exec_lock); 415 416 return (error); 417 418 timeout: 419 /* 420 * Transfer timeout. Kill the transaction and clear status bits. 421 */ 422 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 423 LPCIB_SMB_HC_KILL); 424 DELAY(ICHIIC_DELAY); 425 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 426 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 427 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 428 aprint_error_dev(sc->sc_dev, "abort failed, status %s\n", 429 fbuf); 430 } 431 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 432 mutex_exit(&sc->sc_exec_lock); 433 return (ETIMEDOUT); 434 } 435 436 static int 437 ichsmb_intr(void *arg) 438 { 439 struct ichsmb_softc *sc = arg; 440 uint8_t st; 441 uint8_t *b; 442 size_t len; 443 #ifdef ICHIIC_DEBUG 444 char fbuf[64]; 445 #endif 446 447 /* Read status */ 448 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 449 450 /* Clear status bits */ 451 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 452 453 /* XXX Ignore SMBALERT# for now */ 454 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 455 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 456 LPCIB_SMB_HS_BDONE)) == 0) 457 /* Interrupt was not for us */ 458 return (0); 459 460 #ifdef ICHIIC_DEBUG 461 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 462 printf("%s: intr st %s\n", device_xname(sc->sc_dev), fbuf); 463 #endif 464 465 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 466 mutex_enter(&sc->sc_exec_lock); 467 468 /* Check for errors */ 469 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 470 sc->sc_i2c_xfer.error = EIO; 471 goto done; 472 } 473 474 if (st & LPCIB_SMB_HS_INTR) { 475 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 476 goto done; 477 478 /* Read data */ 479 b = sc->sc_i2c_xfer.buf; 480 len = sc->sc_i2c_xfer.len; 481 if (len > 0) 482 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 483 LPCIB_SMB_HD0); 484 if (len > 1) 485 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 486 LPCIB_SMB_HD1); 487 } 488 489 done: 490 sc->sc_i2c_xfer.done = true; 491 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 492 cv_signal(&sc->sc_exec_wait); 493 mutex_exit(&sc->sc_exec_lock); 494 } 495 return (1); 496 } 497 498 MODULE(MODULE_CLASS_DRIVER, ichsmb, "pci,iic"); 499 500 #ifdef _MODULE 501 #include "ioconf.c" 502 #endif 503 504 static int 505 ichsmb_modcmd(modcmd_t cmd, void *opaque) 506 { 507 int error = 0; 508 509 switch (cmd) { 510 case MODULE_CMD_INIT: 511 #ifdef _MODULE 512 error = config_init_component(cfdriver_ioconf_ichsmb, 513 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 514 #endif 515 break; 516 case MODULE_CMD_FINI: 517 #ifdef _MODULE 518 error = config_fini_component(cfdriver_ioconf_ichsmb, 519 cfattach_ioconf_ichsmb, cfdata_ioconf_ichsmb); 520 #endif 521 break; 522 default: 523 #ifdef _MODULE 524 error = ENOTTY; 525 #endif 526 break; 527 } 528 529 return error; 530 } 531