1 /* $NetBSD: ichsmb.c,v 1.33 2013/11/07 15:55:08 msaitoh Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.33 2013/11/07 15:55:08 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 case PCI_PRODUCT_INTEL_7SERIES_SMB: 112 case PCI_PRODUCT_INTEL_8SERIES_SMB: 113 case PCI_PRODUCT_INTEL_CORE4G_M_SMB: 114 case PCI_PRODUCT_INTEL_C600_SMBUS: 115 case PCI_PRODUCT_INTEL_C600_SMB_0: 116 case PCI_PRODUCT_INTEL_C600_SMB_1: 117 case PCI_PRODUCT_INTEL_C600_SMB_2: 118 return 1; 119 } 120 } 121 return 0; 122 } 123 124 static void 125 ichsmb_attach(device_t parent, device_t self, void *aux) 126 { 127 struct ichsmb_softc *sc = device_private(self); 128 struct pci_attach_args *pa = aux; 129 struct i2cbus_attach_args iba; 130 pcireg_t conf; 131 bus_size_t iosize; 132 pci_intr_handle_t ih; 133 const char *intrstr = NULL; 134 135 sc->sc_dev = self; 136 137 pci_aprint_devinfo(pa, NULL); 138 139 /* Read configuration */ 140 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 141 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 142 143 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 144 aprint_error_dev(self, "SMBus disabled\n"); 145 return; 146 } 147 148 /* Map I/O space */ 149 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 150 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 151 aprint_error_dev(self, "can't map I/O space\n"); 152 return; 153 } 154 155 sc->sc_poll = 1; 156 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 157 /* No PCI IRQ */ 158 aprint_normal_dev(self, "interrupting at SMI\n"); 159 } else { 160 /* Install interrupt handler */ 161 if (pci_intr_map(pa, &ih) == 0) { 162 intrstr = pci_intr_string(pa->pa_pc, ih); 163 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 164 ichsmb_intr, sc); 165 if (sc->sc_ih != NULL) { 166 aprint_normal_dev(self, "interrupting at %s\n", 167 intrstr); 168 sc->sc_poll = 0; 169 } 170 } 171 if (sc->sc_poll) 172 aprint_normal_dev(self, "polling\n"); 173 } 174 175 /* Attach I2C bus */ 176 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 177 sc->sc_i2c_tag.ic_cookie = sc; 178 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 179 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 180 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 181 182 memset(&iba, 0, sizeof(iba)); 183 iba.iba_type = I2C_TYPE_SMBUS; 184 iba.iba_tag = &sc->sc_i2c_tag; 185 config_found(self, &iba, iicbus_print); 186 187 if (!pmf_device_register(self, NULL, NULL)) 188 aprint_error_dev(self, "couldn't establish power handler\n"); 189 } 190 191 static int 192 ichsmb_i2c_acquire_bus(void *cookie, int flags) 193 { 194 struct ichsmb_softc *sc = cookie; 195 196 if (cold) 197 return 0; 198 199 mutex_enter(&sc->sc_i2c_mutex); 200 return 0; 201 } 202 203 static void 204 ichsmb_i2c_release_bus(void *cookie, int flags) 205 { 206 struct ichsmb_softc *sc = cookie; 207 208 if (cold) 209 return; 210 211 mutex_exit(&sc->sc_i2c_mutex); 212 } 213 214 static int 215 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 216 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 217 { 218 struct ichsmb_softc *sc = cookie; 219 const uint8_t *b; 220 uint8_t ctl = 0, st; 221 int retries; 222 char fbuf[64]; 223 224 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 225 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 226 len, flags)); 227 228 /* Clear status bits */ 229 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 230 LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR | 231 LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED); 232 bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1, 233 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 234 235 /* Wait for bus to be idle */ 236 for (retries = 100; retries > 0; retries--) { 237 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 238 if (!(st & LPCIB_SMB_HS_BUSY)) 239 break; 240 DELAY(ICHIIC_DELAY); 241 } 242 #ifdef ICHIIC_DEBUG 243 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 244 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 245 #endif 246 if (st & LPCIB_SMB_HS_BUSY) 247 return (1); 248 249 if (cold || sc->sc_poll) 250 flags |= I2C_F_POLL; 251 252 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 253 (cmdlen == 0 && len > 1)) 254 return (1); 255 256 /* Setup transfer */ 257 sc->sc_i2c_xfer.op = op; 258 sc->sc_i2c_xfer.buf = buf; 259 sc->sc_i2c_xfer.len = len; 260 sc->sc_i2c_xfer.flags = flags; 261 sc->sc_i2c_xfer.error = 0; 262 263 /* Set slave address and transfer direction */ 264 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 265 LPCIB_SMB_TXSLVA_ADDR(addr) | 266 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 267 268 b = (const uint8_t *)cmdbuf; 269 if (cmdlen > 0) 270 /* Set command byte */ 271 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 272 273 if (I2C_OP_WRITE_P(op)) { 274 /* Write data */ 275 b = buf; 276 if (cmdlen == 0 && len == 1) 277 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 278 LPCIB_SMB_HCMD, b[0]); 279 else if (len > 0) 280 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 281 LPCIB_SMB_HD0, b[0]); 282 if (len > 1) 283 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 284 LPCIB_SMB_HD1, b[1]); 285 } 286 287 /* Set SMBus command */ 288 if (cmdlen == 0) { 289 if (len == 0) 290 ctl = LPCIB_SMB_HC_CMD_QUICK; 291 else 292 ctl = LPCIB_SMB_HC_CMD_BYTE; 293 } else if (len == 1) 294 ctl = LPCIB_SMB_HC_CMD_BDATA; 295 else if (len == 2) 296 ctl = LPCIB_SMB_HC_CMD_WDATA; 297 298 if ((flags & I2C_F_POLL) == 0) 299 ctl |= LPCIB_SMB_HC_INTREN; 300 301 /* Start transaction */ 302 ctl |= LPCIB_SMB_HC_START; 303 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 304 305 if (flags & I2C_F_POLL) { 306 /* Poll for completion */ 307 DELAY(ICHIIC_DELAY); 308 for (retries = 1000; retries > 0; retries--) { 309 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 310 LPCIB_SMB_HS); 311 if ((st & LPCIB_SMB_HS_BUSY) == 0) 312 break; 313 DELAY(ICHIIC_DELAY); 314 } 315 if (st & LPCIB_SMB_HS_BUSY) 316 goto timeout; 317 ichsmb_intr(sc); 318 } else { 319 /* Wait for interrupt */ 320 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 321 goto timeout; 322 } 323 324 if (sc->sc_i2c_xfer.error) 325 return (1); 326 327 return (0); 328 329 timeout: 330 /* 331 * Transfer timeout. Kill the transaction and clear status bits. 332 */ 333 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 334 aprint_error_dev(sc->sc_dev, 335 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 336 "flags 0x%02x: timeout, status 0x%s\n", 337 op, addr, cmdlen, len, flags, fbuf); 338 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 339 LPCIB_SMB_HC_KILL); 340 DELAY(ICHIIC_DELAY); 341 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 342 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 343 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 344 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 345 fbuf); 346 } 347 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 348 return (1); 349 } 350 351 static int 352 ichsmb_intr(void *arg) 353 { 354 struct ichsmb_softc *sc = arg; 355 uint8_t st; 356 uint8_t *b; 357 size_t len; 358 #ifdef ICHIIC_DEBUG 359 char fbuf[64]; 360 #endif 361 362 /* Read status */ 363 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 364 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 365 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 366 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 367 /* Interrupt was not for us */ 368 return (0); 369 370 #ifdef ICHIIC_DEBUG 371 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 372 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 373 #endif 374 375 /* Clear status bits */ 376 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 377 378 /* Check for errors */ 379 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 380 sc->sc_i2c_xfer.error = 1; 381 goto done; 382 } 383 384 if (st & LPCIB_SMB_HS_INTR) { 385 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 386 goto done; 387 388 /* Read data */ 389 b = sc->sc_i2c_xfer.buf; 390 len = sc->sc_i2c_xfer.len; 391 if (len > 0) 392 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 393 LPCIB_SMB_HD0); 394 if (len > 1) 395 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 396 LPCIB_SMB_HD1); 397 } 398 399 done: 400 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 401 wakeup(sc); 402 return (1); 403 } 404