1 /* $NetBSD: geodeide.c,v 1.14 2007/02/09 21:55:27 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for the IDE part of the AMD Geode CS5530A companion chip 35 * and AMD Geode SC1100. 36 * Docs available from AMD's web site 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: geodeide.c,v 1.14 2007/02/09 21:55:27 ad Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/pciidereg.h> 50 #include <dev/pci/pciidevar.h> 51 52 #include <dev/pci/pciide_geode_reg.h> 53 54 static void geodeide_chip_map(struct pciide_softc *, 55 struct pci_attach_args *); 56 static void geodeide_setup_channel(struct ata_channel *); 57 static int geodeide_dma_init(void *, int, int, void *, size_t, int); 58 59 static int geodeide_match(struct device *, struct cfdata *, void *); 60 static void geodeide_attach(struct device *, struct device *, void *); 61 62 CFATTACH_DECL(geodeide, sizeof(struct pciide_softc), 63 geodeide_match, geodeide_attach, NULL, NULL); 64 65 static const struct pciide_product_desc pciide_geode_products[] = { 66 { PCI_PRODUCT_CYRIX_CX5530_IDE, 67 0, 68 "AMD Geode CX5530 IDE controller", 69 geodeide_chip_map, 70 }, 71 { PCI_PRODUCT_NS_SC1100_IDE, 72 0, 73 "AMD Geode SC1100 IDE controller", 74 geodeide_chip_map, 75 }, 76 { 0, 77 0, 78 NULL, 79 NULL, 80 }, 81 }; 82 83 static int 84 geodeide_match(struct device *parent, struct cfdata *match, 85 void *aux) 86 { 87 struct pci_attach_args *pa = aux; 88 89 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYRIX || 90 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS) && 91 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 92 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 93 pciide_lookup_product(pa->pa_id, pciide_geode_products)) 94 return(2); 95 return (0); 96 } 97 98 static void 99 geodeide_attach(struct device *parent, struct device *self, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 struct pciide_softc *sc = (void *)self; 103 104 pciide_common_attach(sc, pa, 105 pciide_lookup_product(pa->pa_id, pciide_geode_products)); 106 } 107 108 static void 109 geodeide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 110 { 111 struct pciide_channel *cp; 112 int channel; 113 bus_size_t cmdsize, ctlsize; 114 115 if (pciide_chipen(sc, pa) == 0) 116 return; 117 118 aprint_verbose("%s: bus-master DMA support present", 119 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 120 pciide_mapreg_dma(sc, pa); 121 aprint_verbose("\n"); 122 if (sc->sc_dma_ok) { 123 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 124 sc->sc_wdcdev.irqack = pciide_irqack; 125 /* 126 * XXXJRT What chip revisions actually need the DMA 127 * alignment work-around? 128 */ 129 sc->sc_wdcdev.dma_init = geodeide_dma_init; 130 } 131 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 132 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 133 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 134 /* 135 * The 5530 is utterly swamped by UDMA mode 2, so limit to mode 1 136 * so that the chip is able to perform the other functions it has 137 * while IDE UDMA is going on. 138 */ 139 if (sc->sc_pp->ide_product == PCI_PRODUCT_CYRIX_CX5530_IDE) { 140 sc->sc_wdcdev.sc_atac.atac_udma_cap = 1; 141 } 142 sc->sc_wdcdev.sc_atac.atac_set_modes = geodeide_setup_channel; 143 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 144 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 145 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 146 147 /* 148 * Soekris Engineering Issue #0003: 149 * "The SC1100 built in busmaster IDE controller is pretty 150 * standard, but have two bugs: data transfers need to be 151 * dword aligned and it cannot do an exact 64Kbyte data 152 * transfer." 153 */ 154 if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SC1100_IDE) { 155 if (sc->sc_dma_boundary == 0x10000) 156 sc->sc_dma_boundary -= PAGE_SIZE; 157 158 if (sc->sc_dma_maxsegsz == 0x10000) 159 sc->sc_dma_maxsegsz -= PAGE_SIZE; 160 } 161 162 wdc_allocate_regs(&sc->sc_wdcdev); 163 164 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 165 channel++) { 166 cp = &sc->pciide_channels[channel]; 167 /* controller is compat-only */ 168 if (pciide_chansetup(sc, channel, 0) == 0) 169 continue; 170 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 171 } 172 } 173 174 static void 175 geodeide_setup_channel(struct ata_channel *chp) 176 { 177 struct ata_drive_datas *drvp; 178 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 179 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 180 int channel = chp->ch_channel; 181 int drive, s; 182 u_int32_t dma_timing; 183 u_int8_t idedma_ctl; 184 const int32_t *geode_pio; 185 const int32_t *geode_dma; 186 const int32_t *geode_udma; 187 bus_size_t dmaoff, piooff; 188 189 switch (sc->sc_pp->ide_product) { 190 case PCI_PRODUCT_CYRIX_CX5530_IDE: 191 geode_pio = geode_cs5530_pio; 192 geode_dma = geode_cs5530_dma; 193 geode_udma = geode_cs5530_udma; 194 break; 195 196 case PCI_PRODUCT_NS_SC1100_IDE: 197 default: /* XXX gcc */ 198 geode_pio = geode_sc1100_pio; 199 geode_dma = geode_sc1100_dma; 200 geode_udma = geode_sc1100_udma; 201 break; 202 } 203 204 /* setup DMA if needed */ 205 pciide_channel_dma_setup(cp); 206 207 idedma_ctl = 0; 208 209 /* Per drive settings */ 210 for (drive = 0; drive < 2; drive++) { 211 drvp = &chp->ch_drive[drive]; 212 /* If no drive, skip */ 213 if ((drvp->drive_flags & DRIVE) == 0) 214 continue; 215 216 switch (sc->sc_pp->ide_product) { 217 case PCI_PRODUCT_CYRIX_CX5530_IDE: 218 dmaoff = CS5530_DMA_REG(channel, drive); 219 piooff = CS5530_PIO_REG(channel, drive); 220 dma_timing = CS5530_DMA_REG_PIO_FORMAT; 221 break; 222 223 case PCI_PRODUCT_NS_SC1100_IDE: 224 default: /* XXX gcc */ 225 dmaoff = SC1100_DMA_REG(channel, drive); 226 piooff = SC1100_PIO_REG(channel, drive); 227 dma_timing = 0; 228 break; 229 } 230 231 /* add timing values, setup DMA if needed */ 232 if (drvp->drive_flags & DRIVE_UDMA) { 233 /* Use Ultra-DMA */ 234 dma_timing |= geode_udma[drvp->UDMA_mode]; 235 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 236 } else if (drvp->drive_flags & DRIVE_DMA) { 237 /* use Multiword DMA */ 238 dma_timing |= geode_dma[drvp->DMA_mode]; 239 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 240 } else { 241 /* PIO only */ 242 s = splbio(); 243 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 244 splx(s); 245 } 246 247 switch (sc->sc_pp->ide_product) { 248 case PCI_PRODUCT_CYRIX_CX5530_IDE: 249 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 250 dmaoff, dma_timing); 251 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 252 piooff, geode_pio[drvp->PIO_mode]); 253 break; 254 255 case PCI_PRODUCT_NS_SC1100_IDE: 256 pci_conf_write(sc->sc_pc, sc->sc_tag, dmaoff, 257 dma_timing); 258 pci_conf_write(sc->sc_pc, sc->sc_tag, piooff, 259 geode_pio[drvp->PIO_mode]); 260 break; 261 } 262 } 263 264 if (idedma_ctl != 0) { 265 /* Add software bits in status register */ 266 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 267 idedma_ctl); 268 } 269 } 270 271 static int 272 geodeide_dma_init(void *v, int channel, int drive, void *databuf, 273 size_t datalen, int flags) 274 { 275 276 /* 277 * If the buffer is not properly aligned, we can't allow DMA 278 * and need to fall back to PIO. 279 */ 280 if (((uintptr_t)databuf) & 0xf) 281 return (EINVAL); 282 283 return (pciide_dma_init(v, channel, drive, databuf, datalen, flags)); 284 } 285