1 /* $NetBSD: cz.c,v 1.35 2006/03/05 17:33:33 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only use RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: cz.c,v 1.35 2006/03/05 17:33:33 christos Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/tty.h> 84 #include <sys/conf.h> 85 #include <sys/time.h> 86 #include <sys/kernel.h> 87 #include <sys/fcntl.h> 88 #include <sys/syslog.h> 89 90 #include <sys/callout.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/czreg.h> 96 97 #include <dev/pci/plx9060reg.h> 98 #include <dev/pci/plx9060var.h> 99 100 #include <dev/microcode/cyclades-z/cyzfirm.h> 101 102 #define CZ_DRIVER_VERSION 0x20000411 103 104 #define CZ_POLL_MS 20 105 106 /* These are the interrupts we always use. */ 107 #define CZ_INTERRUPTS \ 108 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 109 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 110 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 111 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 112 113 /* 114 * cztty_softc: 115 * 116 * Per-channel (TTY) state. 117 */ 118 struct cztty_softc { 119 struct cz_softc *sc_parent; 120 struct tty *sc_tty; 121 122 struct callout sc_diag_ch; 123 124 int sc_channel; /* Also used to flag unattached chan */ 125 #define CZTTY_CHANNEL_DEAD -1 126 127 bus_space_tag_t sc_chan_st; /* channel space tag */ 128 bus_space_handle_t sc_chan_sh; /* channel space handle */ 129 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 130 131 u_int sc_overflows, 132 sc_parity_errors, 133 sc_framing_errors, 134 sc_errors; 135 136 int sc_swflags; 137 138 u_int32_t sc_rs_control_dtr, 139 sc_chanctl_hw_flow, 140 sc_chanctl_comm_baud, 141 sc_chanctl_rs_control, 142 sc_chanctl_comm_data_l, 143 sc_chanctl_comm_parity; 144 }; 145 146 /* 147 * cz_softc: 148 * 149 * Per-board state. 150 */ 151 struct cz_softc { 152 struct device cz_dev; /* generic device info */ 153 struct plx9060_config cz_plx; /* PLX 9060 config info */ 154 bus_space_tag_t cz_win_st; /* window space tag */ 155 bus_space_handle_t cz_win_sh; /* window space handle */ 156 struct callout cz_callout; /* callout for polling-mode */ 157 158 void *cz_ih; /* interrupt handle */ 159 160 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 161 int cz_nchannels; /* number of channels */ 162 int cz_nopenchan; /* number of open channels */ 163 struct cztty_softc *cz_ports; /* our array of ports */ 164 165 bus_addr_t cz_fwctl; /* offset of firmware control */ 166 }; 167 168 static int cz_wait_pci_doorbell(struct cz_softc *, const char *); 169 170 static int cz_load_firmware(struct cz_softc *); 171 172 static int cz_intr(void *); 173 static void cz_poll(void *); 174 static int cztty_transmit(struct cztty_softc *, struct tty *); 175 static int cztty_receive(struct cztty_softc *, struct tty *); 176 177 static struct cztty_softc *cztty_getttysoftc(dev_t dev); 178 static int cztty_attached_ttys; 179 static int cz_timeout_ticks; 180 181 static void czttystart(struct tty *tp); 182 static int czttyparam(struct tty *tp, struct termios *t); 183 static void cztty_shutdown(struct cztty_softc *sc); 184 static void cztty_modem(struct cztty_softc *sc, int onoff); 185 static void cztty_break(struct cztty_softc *sc, int onoff); 186 static void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 187 static int cztty_to_tiocm(struct cztty_softc *sc); 188 static void cztty_diag(void *arg); 189 190 extern struct cfdriver cz_cd; 191 192 /* 193 * Macros to read and write the PLX. 194 */ 195 #define CZ_PLX_READ(cz, reg) \ 196 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 197 #define CZ_PLX_WRITE(cz, reg, val) \ 198 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 199 (reg), (val)) 200 201 /* 202 * Macros to read and write the FPGA. We must already be in the FPGA 203 * window for this. 204 */ 205 #define CZ_FPGA_READ(cz, reg) \ 206 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 207 #define CZ_FPGA_WRITE(cz, reg, val) \ 208 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 209 210 /* 211 * Macros to read and write the firmware control structures in board RAM. 212 */ 213 #define CZ_FWCTL_READ(cz, off) \ 214 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 215 (cz)->cz_fwctl + (off)) 216 217 #define CZ_FWCTL_WRITE(cz, off, val) \ 218 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 219 (cz)->cz_fwctl + (off), (val)) 220 221 /* 222 * Convenience macros for cztty routines. PLX window MUST be to RAM. 223 */ 224 #define CZTTY_CHAN_READ(sc, off) \ 225 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 226 227 #define CZTTY_CHAN_WRITE(sc, off, val) \ 228 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 229 (off), (val)) 230 231 #define CZTTY_BUF_READ(sc, off) \ 232 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 233 234 #define CZTTY_BUF_WRITE(sc, off, val) \ 235 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 236 (off), (val)) 237 238 /* 239 * Convenience macros. 240 */ 241 #define CZ_WIN_RAM(cz) \ 242 do { \ 243 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 244 delay(100); \ 245 } while (0) 246 247 #define CZ_WIN_FPGA(cz) \ 248 do { \ 249 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 250 delay(100); \ 251 } while (0) 252 253 /***************************************************************************** 254 * Cyclades-Z controller code starts here... 255 *****************************************************************************/ 256 257 /* 258 * cz_match: 259 * 260 * Determine if the given PCI device is a Cyclades-Z board. 261 */ 262 static int 263 cz_match(struct device *parent, 264 struct cfdata *match, 265 void *aux) 266 { 267 struct pci_attach_args *pa = aux; 268 269 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 270 switch (PCI_PRODUCT(pa->pa_id)) { 271 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 272 return (1); 273 } 274 } 275 276 return (0); 277 } 278 279 /* 280 * cz_attach: 281 * 282 * A Cyclades-Z board was found; attach it. 283 */ 284 static void 285 cz_attach(struct device *parent, 286 struct device *self, 287 void *aux) 288 { 289 extern const struct cdevsw cz_cdevsw; /* XXX */ 290 struct cz_softc *cz = (void *) self; 291 struct pci_attach_args *pa = aux; 292 pci_intr_handle_t ih; 293 const char *intrstr = NULL; 294 struct cztty_softc *sc; 295 struct tty *tp; 296 int i; 297 298 aprint_naive(": Multi-port serial controller\n"); 299 aprint_normal(": Cyclades-Z multiport serial\n"); 300 301 cz->cz_plx.plx_pc = pa->pa_pc; 302 cz->cz_plx.plx_tag = pa->pa_tag; 303 304 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 305 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 306 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 307 aprint_error("%s: unable to map PLX registers\n", 308 cz->cz_dev.dv_xname); 309 return; 310 } 311 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 312 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 313 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 314 aprint_error("%s: unable to map device window\n", 315 cz->cz_dev.dv_xname); 316 return; 317 } 318 319 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 320 cz->cz_nopenchan = 0; 321 322 /* 323 * Make sure that the board is completely stopped. 324 */ 325 CZ_WIN_FPGA(cz); 326 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 327 328 /* 329 * Load the board's firmware. 330 */ 331 if (cz_load_firmware(cz) != 0) 332 return; 333 334 /* 335 * Now that we're ready to roll, map and establish the interrupt 336 * handler. 337 */ 338 if (pci_intr_map(pa, &ih) != 0) { 339 /* 340 * The common case is for Cyclades-Z boards to run 341 * in polling mode, and thus not have an interrupt 342 * mapped for them. Don't bother reporting that 343 * the interrupt is not mappable, since this isn't 344 * really an error. 345 */ 346 cz->cz_ih = NULL; 347 goto polling_mode; 348 } else { 349 intrstr = pci_intr_string(pa->pa_pc, ih); 350 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 351 cz_intr, cz); 352 } 353 if (cz->cz_ih == NULL) { 354 aprint_error("%s: unable to establish interrupt", 355 cz->cz_dev.dv_xname); 356 if (intrstr != NULL) 357 aprint_normal(" at %s", intrstr); 358 aprint_normal("\n"); 359 /* We will fall-back on polling mode. */ 360 } else 361 aprint_normal("%s: interrupting at %s\n", 362 cz->cz_dev.dv_xname, intrstr); 363 364 polling_mode: 365 if (cz->cz_ih == NULL) { 366 callout_init(&cz->cz_callout); 367 if (cz_timeout_ticks == 0) 368 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 369 aprint_normal("%s: polling mode, %d ms interval (%d tick%s)\n", 370 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 371 cz_timeout_ticks == 1 ? "" : "s"); 372 } 373 374 /* 375 * Allocate sufficient pointers for the children and 376 * attach them. Set all ports to a reasonable initial 377 * configuration while we're at it: 378 * 379 * disabled 380 * 8N1 381 * default baud rate 382 * hardware flow control. 383 */ 384 CZ_WIN_RAM(cz); 385 386 if (cz->cz_nchannels == 0) { 387 /* No channels? No more work to do! */ 388 return; 389 } 390 391 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 392 M_DEVBUF, M_WAITOK|M_ZERO); 393 cztty_attached_ttys += cz->cz_nchannels; 394 395 for (i = 0; i < cz->cz_nchannels; i++) { 396 sc = &cz->cz_ports[i]; 397 398 sc->sc_channel = i; 399 sc->sc_chan_st = cz->cz_win_st; 400 sc->sc_parent = cz; 401 402 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 403 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 404 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 405 aprint_error( 406 "%s: unable to subregion channel %d control\n", 407 cz->cz_dev.dv_xname, i); 408 sc->sc_channel = CZTTY_CHANNEL_DEAD; 409 continue; 410 } 411 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 412 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 413 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 414 aprint_error( 415 "%s: unable to subregion channel %d buffer\n", 416 cz->cz_dev.dv_xname, i); 417 sc->sc_channel = CZTTY_CHANNEL_DEAD; 418 continue; 419 } 420 421 callout_init(&sc->sc_diag_ch); 422 423 tp = ttymalloc(); 424 tp->t_dev = makedev(cdevsw_lookup_major(&cz_cdevsw), 425 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 426 tp->t_oproc = czttystart; 427 tp->t_param = czttyparam; 428 tty_attach(tp); 429 430 sc->sc_tty = tp; 431 432 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 433 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 434 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 435 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 436 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 437 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 438 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 439 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 440 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 441 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 442 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 443 } 444 } 445 446 CFATTACH_DECL(cz, sizeof(struct cz_softc), 447 cz_match, cz_attach, NULL, NULL); 448 449 #if 0 450 /* 451 * cz_reset_board: 452 * 453 * Reset the board via the PLX. 454 */ 455 static void 456 cz_reset_board(struct cz_softc *cz) 457 { 458 u_int32_t reg; 459 460 reg = CZ_PLX_READ(cz, PLX_CONTROL); 461 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 462 delay(1000); 463 464 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 465 delay(1000); 466 467 /* Now reload the PLX from its EEPROM. */ 468 reg = CZ_PLX_READ(cz, PLX_CONTROL); 469 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 470 delay(1000); 471 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 472 } 473 #endif 474 475 /* 476 * cz_load_firmware: 477 * 478 * Load the ZFIRM firmware into the board's RAM and start it 479 * running. 480 */ 481 static int 482 cz_load_firmware(struct cz_softc *cz) 483 { 484 const struct zfirm_header *zfh; 485 const struct zfirm_config *zfc; 486 const struct zfirm_block *zfb, *zblocks; 487 const u_int8_t *cp; 488 const char *board; 489 u_int32_t fid; 490 int i, j, nconfigs, nblocks, nbytes; 491 492 zfh = (const struct zfirm_header *) cycladesz_firmware; 493 494 /* Find the config header. */ 495 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 496 aprint_error("%s: bad ZFIRM config offset: 0x%x\n", 497 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 498 return (EIO); 499 } 500 zfc = (const struct zfirm_config *)(cycladesz_firmware + 501 le32toh(zfh->zfh_configoff)); 502 nconfigs = le32toh(zfh->zfh_nconfig); 503 504 /* Locate the correct configuration for our board. */ 505 for (i = 0; i < nconfigs; i++, zfc++) { 506 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 507 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 508 break; 509 } 510 if (i == nconfigs) { 511 aprint_error("%s: unable to locate config header\n", 512 cz->cz_dev.dv_xname); 513 return (EIO); 514 } 515 516 nblocks = le32toh(zfc->zfc_nblocks); 517 zblocks = (const struct zfirm_block *)(cycladesz_firmware + 518 le32toh(zfh->zfh_blockoff)); 519 520 /* 521 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 522 * necessary. 523 */ 524 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 525 #if 0 526 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 527 #endif 528 ) { 529 #ifdef CZ_DEBUG 530 aprint_debug("%s: Loading FPGA...", cz->cz_dev.dv_xname); 531 #endif 532 CZ_WIN_FPGA(cz); 533 for (i = 0; i < nblocks; i++) { 534 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 535 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 536 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 537 nbytes = le32toh(zfb->zfb_size); 538 cp = &cycladesz_firmware[ 539 le32toh(zfb->zfb_fileoff)]; 540 for (j = 0; j < nbytes; j++, cp++) { 541 bus_space_write_1(cz->cz_win_st, 542 cz->cz_win_sh, 0, *cp); 543 /* FPGA needs 30-100us to settle. */ 544 delay(10); 545 } 546 } 547 } 548 #ifdef CZ_DEBUG 549 aprint_debug("done\n"); 550 #endif 551 } 552 553 /* Now load the firmware. */ 554 CZ_WIN_RAM(cz); 555 556 for (i = 0; i < nblocks; i++) { 557 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 558 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 559 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 560 const u_int32_t *lp; 561 u_int32_t ro = le32toh(zfb->zfb_ramoff); 562 nbytes = le32toh(zfb->zfb_size); 563 lp = (const u_int32_t *) 564 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 565 for (j = 0; j < nbytes; j += 4, lp++) { 566 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 567 ro + j, le32toh(*lp)); 568 delay(10); 569 } 570 } 571 } 572 573 /* Now restart the MIPS. */ 574 CZ_WIN_FPGA(cz); 575 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 576 577 /* Wait for the MIPS to start, then report the results. */ 578 CZ_WIN_RAM(cz); 579 580 #ifdef CZ_DEBUG 581 aprint_debug("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 582 #endif 583 for (i = 0; i < 100; i++) { 584 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 585 ZFIRM_SIG_OFF); 586 if (fid == ZFIRM_SIG) { 587 /* MIPS has booted. */ 588 break; 589 } else if (fid == ZFIRM_HLT) { 590 /* 591 * The MIPS has halted, usually due to a power 592 * shortage on the expansion module. 593 */ 594 aprint_error("%s: MIPS halted; possible power supply " 595 "problem\n", cz->cz_dev.dv_xname); 596 return (EIO); 597 } else { 598 #ifdef CZ_DEBUG 599 if ((i % 8) == 0) 600 aprint_debug("."); 601 #endif 602 delay(250000); 603 } 604 } 605 #ifdef CZ_DEBUG 606 aprint_debug("\n"); 607 #endif 608 if (i == 100) { 609 CZ_WIN_FPGA(cz); 610 aprint_error( 611 "%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 612 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 613 aprint_error("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 614 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 615 CZ_FPGA_READ(cz, FPGA_VERSION)); 616 return (EIO); 617 } 618 619 /* 620 * Locate the firmware control structures. 621 */ 622 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 623 ZFIRM_CTRLADDR_OFF); 624 #ifdef CZ_DEBUG 625 aprint_debug("%s: FWCTL structure at offset 0x%08lx\n", 626 cz->cz_dev.dv_xname, cz->cz_fwctl); 627 #endif 628 629 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 630 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 631 632 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 633 634 switch (cz->cz_mailbox0) { 635 case MAILBOX0_8Zo_V1: 636 board = "Cyclades-8Zo ver. 1"; 637 break; 638 639 case MAILBOX0_8Zo_V2: 640 board = "Cyclades-8Zo ver. 2"; 641 break; 642 643 case MAILBOX0_Ze_V1: 644 board = "Cyclades-Ze"; 645 break; 646 647 default: 648 board = "unknown Cyclades Z-series"; 649 break; 650 } 651 652 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 653 aprint_normal("%s: %s, ", cz->cz_dev.dv_xname, board); 654 if (cz->cz_nchannels == 0) 655 aprint_normal("no channels attached, "); 656 else 657 aprint_normal("%d channels (ttyCZ%04d..ttyCZ%04d), ", 658 cz->cz_nchannels, cztty_attached_ttys, 659 cztty_attached_ttys + (cz->cz_nchannels - 1)); 660 aprint_normal("firmware %x.%x.%x\n", 661 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 662 663 return (0); 664 } 665 666 /* 667 * cz_poll: 668 * 669 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 670 * ms. 671 */ 672 static void 673 cz_poll(void *arg) 674 { 675 int s = spltty(); 676 struct cz_softc *cz = arg; 677 678 cz_intr(cz); 679 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 680 681 splx(s); 682 } 683 684 /* 685 * cz_intr: 686 * 687 * Interrupt service routine. 688 * 689 * We either are receiving an interrupt directly from the board, or we are 690 * in polling mode and it's time to poll. 691 */ 692 static int 693 cz_intr(void *arg) 694 { 695 int rval = 0; 696 u_int command, channel, param; 697 struct cz_softc *cz = arg; 698 struct cztty_softc *sc; 699 struct tty *tp; 700 701 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 702 rval = 1; 703 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 704 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 705 706 /* now clear this interrupt, posslibly enabling another */ 707 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 708 709 if (cz->cz_ports == NULL) { 710 #ifdef CZ_DEBUG 711 printf("%s: interrupt on channel %d, but no channels\n", 712 cz->cz_dev.dv_xname, channel); 713 #endif 714 continue; 715 } 716 717 sc = &cz->cz_ports[channel]; 718 719 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 720 break; 721 722 tp = sc->sc_tty; 723 724 switch (command) { 725 case C_CM_TXFEMPTY: /* transmit cases */ 726 case C_CM_TXBEMPTY: 727 case C_CM_TXLOWWM: 728 case C_CM_INTBACK: 729 if (!ISSET(tp->t_state, TS_ISOPEN)) { 730 #ifdef CZ_DEBUG 731 printf("%s: tx intr on closed channel %d\n", 732 cz->cz_dev.dv_xname, channel); 733 #endif 734 break; 735 } 736 737 if (cztty_transmit(sc, tp)) { 738 /* 739 * Do wakeup stuff here. 740 */ 741 ttwakeup(tp); 742 wakeup(tp); 743 } 744 break; 745 746 case C_CM_RXNNDT: /* receive cases */ 747 case C_CM_RXHIWM: 748 case C_CM_INTBACK2: /* from restart ?? */ 749 #if 0 750 case C_CM_ICHAR: 751 #endif 752 if (!ISSET(tp->t_state, TS_ISOPEN)) { 753 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 754 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 755 break; 756 } 757 758 if (cztty_receive(sc, tp)) { 759 /* 760 * Do wakeup stuff here. 761 */ 762 ttwakeup(tp); 763 wakeup(tp); 764 } 765 break; 766 767 case C_CM_MDCD: 768 if (!ISSET(tp->t_state, TS_ISOPEN)) 769 break; 770 771 (void) (*tp->t_linesw->l_modem)(tp, 772 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 773 CHNCTL_RS_STATUS))); 774 break; 775 776 case C_CM_MDSR: 777 case C_CM_MRI: 778 case C_CM_MCTS: 779 case C_CM_MRTS: 780 break; 781 782 case C_CM_IOCTLW: 783 break; 784 785 case C_CM_PR_ERROR: 786 sc->sc_parity_errors++; 787 goto error_common; 788 789 case C_CM_FR_ERROR: 790 sc->sc_framing_errors++; 791 goto error_common; 792 793 case C_CM_OVR_ERROR: 794 sc->sc_overflows++; 795 error_common: 796 if (sc->sc_errors++ == 0) 797 callout_reset(&sc->sc_diag_ch, 60 * hz, 798 cztty_diag, sc); 799 break; 800 801 case C_CM_RXBRK: 802 if (!ISSET(tp->t_state, TS_ISOPEN)) 803 break; 804 805 /* 806 * A break is a \000 character with TTY_FE error 807 * flags set. So TTY_FE by itself works. 808 */ 809 (*tp->t_linesw->l_rint)(TTY_FE, tp); 810 ttwakeup(tp); 811 wakeup(tp); 812 break; 813 814 default: 815 #ifdef CZ_DEBUG 816 printf("%s: channel %d: Unknown interrupt 0x%x\n", 817 cz->cz_dev.dv_xname, sc->sc_channel, command); 818 #endif 819 break; 820 } 821 } 822 823 return (rval); 824 } 825 826 /* 827 * cz_wait_pci_doorbell: 828 * 829 * Wait for the pci doorbell to be clear - wait for pending 830 * activity to drain. 831 */ 832 static int 833 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 834 { 835 int error; 836 837 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 838 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 839 if ((error != 0) && (error != EWOULDBLOCK)) 840 return (error); 841 } 842 return (0); 843 } 844 845 /***************************************************************************** 846 * Cyclades-Z TTY code starts here... 847 *****************************************************************************/ 848 849 #define CZTTYDIALOUT_MASK 0x80000 850 851 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 852 #define CZTTY_CZ(sc) ((sc)->sc_parent) 853 854 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 855 856 static struct cztty_softc * 857 cztty_getttysoftc(dev_t dev) 858 { 859 int i, j, k = 0, u = minor(dev) & ~CZTTYDIALOUT_MASK; 860 struct cz_softc *cz = NULL; 861 862 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 863 k = j; 864 cz = device_lookup(&cz_cd, i); 865 if (cz == NULL) 866 continue; 867 if (cz->cz_ports == NULL) 868 continue; 869 j += cz->cz_nchannels; 870 if (j > u) 871 break; 872 } 873 874 if (i >= cz_cd.cd_ndevs) 875 return (NULL); 876 else 877 return (&cz->cz_ports[u - k]); 878 } 879 880 /* 881 * czttytty: 882 * 883 * Return a pointer to our tty. 884 */ 885 static struct tty * 886 czttytty(dev_t dev) 887 { 888 struct cztty_softc *sc = CZTTY_SOFTC(dev); 889 890 #ifdef DIAGNOSTIC 891 if (sc == NULL) 892 panic("czttytty"); 893 #endif 894 895 return (sc->sc_tty); 896 } 897 898 /* 899 * cztty_shutdown: 900 * 901 * Shut down a port. 902 */ 903 static void 904 cztty_shutdown(struct cztty_softc *sc) 905 { 906 struct cz_softc *cz = CZTTY_CZ(sc); 907 struct tty *tp = sc->sc_tty; 908 int s; 909 910 s = spltty(); 911 912 /* Clear any break condition set with TIOCSBRK. */ 913 cztty_break(sc, 0); 914 915 /* 916 * Hang up if necessary. Wait a bit, so the other side has time to 917 * notice even if we immediately open the port again. 918 */ 919 if (ISSET(tp->t_cflag, HUPCL)) { 920 cztty_modem(sc, 0); 921 (void) tsleep(tp, TTIPRI, ttclos, hz); 922 } 923 924 /* Disable the channel. */ 925 cz_wait_pci_doorbell(cz, "czdis"); 926 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 927 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 928 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 929 930 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 931 #ifdef CZ_DEBUG 932 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 933 #endif 934 callout_stop(&cz->cz_callout); 935 } 936 937 splx(s); 938 } 939 940 /* 941 * czttyopen: 942 * 943 * Open a Cyclades-Z serial port. 944 */ 945 static int 946 czttyopen(dev_t dev, int flags, int mode, struct lwp *l) 947 { 948 struct cztty_softc *sc = CZTTY_SOFTC(dev); 949 struct cz_softc *cz; 950 struct tty *tp; 951 int s, error; 952 953 if (sc == NULL) 954 return (ENXIO); 955 956 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 957 return (ENXIO); 958 959 cz = CZTTY_CZ(sc); 960 tp = sc->sc_tty; 961 962 if (ISSET(tp->t_state, TS_ISOPEN) && 963 ISSET(tp->t_state, TS_XCLUDE) && 964 suser(l->l_proc->p_ucred, &l->l_proc->p_acflag) != 0) 965 return (EBUSY); 966 967 s = spltty(); 968 969 /* 970 * Do the following iff this is a first open. 971 */ 972 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 973 struct termios t; 974 975 tp->t_dev = dev; 976 977 /* If we're turning things on, enable interrupts */ 978 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 979 #ifdef CZ_DEBUG 980 printf("%s: Enabling polling.\n", 981 cz->cz_dev.dv_xname); 982 #endif 983 callout_reset(&cz->cz_callout, cz_timeout_ticks, 984 cz_poll, cz); 985 } 986 987 /* 988 * Enable the channel. Don't actually ring the 989 * doorbell here; czttyparam() will do it for us. 990 */ 991 cz_wait_pci_doorbell(cz, "czopen"); 992 993 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 994 995 /* 996 * Initialize the termios status to the defaults. Add in the 997 * sticky bits from TIOCSFLAGS. 998 */ 999 t.c_ispeed = 0; 1000 t.c_ospeed = TTYDEF_SPEED; 1001 t.c_cflag = TTYDEF_CFLAG; 1002 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1003 SET(t.c_cflag, CLOCAL); 1004 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1005 SET(t.c_cflag, CRTSCTS); 1006 1007 /* 1008 * Reset the input and output rings. Do this before 1009 * we call czttyparam(), as that function enables 1010 * the channel. 1011 */ 1012 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1013 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1014 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1015 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1016 1017 /* Make sure czttyparam() will see changes. */ 1018 tp->t_ospeed = 0; 1019 (void) czttyparam(tp, &t); 1020 tp->t_iflag = TTYDEF_IFLAG; 1021 tp->t_oflag = TTYDEF_OFLAG; 1022 tp->t_lflag = TTYDEF_LFLAG; 1023 ttychars(tp); 1024 ttsetwater(tp); 1025 1026 /* 1027 * Turn on DTR. We must always do this, even if carrier is not 1028 * present, because otherwise we'd have to use TIOCSDTR 1029 * immediately after setting CLOCAL, which applications do not 1030 * expect. We always assert DTR while the device is open 1031 * unless explicitly requested to deassert it. 1032 */ 1033 cztty_modem(sc, 1); 1034 } 1035 1036 splx(s); 1037 1038 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1039 if (error) 1040 goto bad; 1041 1042 error = (*tp->t_linesw->l_open)(dev, tp); 1043 if (error) 1044 goto bad; 1045 1046 return (0); 1047 1048 bad: 1049 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1050 /* 1051 * We failed to open the device, and nobody else had it opened. 1052 * Clean up the state as appropriate. 1053 */ 1054 cztty_shutdown(sc); 1055 } 1056 1057 return (error); 1058 } 1059 1060 /* 1061 * czttyclose: 1062 * 1063 * Close a Cyclades-Z serial port. 1064 */ 1065 static int 1066 czttyclose(dev_t dev, int flags, int mode, struct lwp *l) 1067 { 1068 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1069 struct tty *tp = sc->sc_tty; 1070 1071 /* XXX This is for cons.c. */ 1072 if (!ISSET(tp->t_state, TS_ISOPEN)) 1073 return (0); 1074 1075 (*tp->t_linesw->l_close)(tp, flags); 1076 ttyclose(tp); 1077 1078 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1079 /* 1080 * Although we got a last close, the device may still be in 1081 * use; e.g. if this was the dialout node, and there are still 1082 * processes waiting for carrier on the non-dialout node. 1083 */ 1084 cztty_shutdown(sc); 1085 } 1086 1087 return (0); 1088 } 1089 1090 /* 1091 * czttyread: 1092 * 1093 * Read from a Cyclades-Z serial port. 1094 */ 1095 static int 1096 czttyread(dev_t dev, struct uio *uio, int flags) 1097 { 1098 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1099 struct tty *tp = sc->sc_tty; 1100 1101 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1102 } 1103 1104 /* 1105 * czttywrite: 1106 * 1107 * Write to a Cyclades-Z serial port. 1108 */ 1109 static int 1110 czttywrite(dev_t dev, struct uio *uio, int flags) 1111 { 1112 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1113 struct tty *tp = sc->sc_tty; 1114 1115 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1116 } 1117 1118 /* 1119 * czttypoll: 1120 * 1121 * Poll a Cyclades-Z serial port. 1122 */ 1123 static int 1124 czttypoll(dev_t dev, int events, struct lwp *l) 1125 { 1126 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1127 struct tty *tp = sc->sc_tty; 1128 1129 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1130 } 1131 1132 /* 1133 * czttyioctl: 1134 * 1135 * Perform a control operation on a Cyclades-Z serial port. 1136 */ 1137 static int 1138 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct lwp *l) 1139 { 1140 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1141 struct tty *tp = sc->sc_tty; 1142 struct proc *p = l->l_proc; 1143 int s, error; 1144 1145 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1146 if (error != EPASSTHROUGH) 1147 return (error); 1148 1149 error = ttioctl(tp, cmd, data, flag, l); 1150 if (error != EPASSTHROUGH) 1151 return (error); 1152 1153 error = 0; 1154 1155 s = spltty(); 1156 1157 switch (cmd) { 1158 case TIOCSBRK: 1159 cztty_break(sc, 1); 1160 break; 1161 1162 case TIOCCBRK: 1163 cztty_break(sc, 0); 1164 break; 1165 1166 case TIOCGFLAGS: 1167 *(int *)data = sc->sc_swflags; 1168 break; 1169 1170 case TIOCSFLAGS: 1171 error = suser(p->p_ucred, &p->p_acflag); 1172 if (error) 1173 break; 1174 sc->sc_swflags = *(int *)data; 1175 break; 1176 1177 case TIOCSDTR: 1178 cztty_modem(sc, 1); 1179 break; 1180 1181 case TIOCCDTR: 1182 cztty_modem(sc, 0); 1183 break; 1184 1185 case TIOCMSET: 1186 case TIOCMBIS: 1187 case TIOCMBIC: 1188 tiocm_to_cztty(sc, cmd, *(int *)data); 1189 break; 1190 1191 case TIOCMGET: 1192 *(int *)data = cztty_to_tiocm(sc); 1193 break; 1194 1195 default: 1196 error = EPASSTHROUGH; 1197 break; 1198 } 1199 1200 splx(s); 1201 1202 return (error); 1203 } 1204 1205 /* 1206 * cztty_break: 1207 * 1208 * Set or clear BREAK on a port. 1209 */ 1210 static void 1211 cztty_break(struct cztty_softc *sc, int onoff) 1212 { 1213 struct cz_softc *cz = CZTTY_CZ(sc); 1214 1215 cz_wait_pci_doorbell(cz, "czbreak"); 1216 1217 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1218 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1219 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1220 } 1221 1222 /* 1223 * cztty_modem: 1224 * 1225 * Set or clear DTR on a port. 1226 */ 1227 static void 1228 cztty_modem(struct cztty_softc *sc, int onoff) 1229 { 1230 struct cz_softc *cz = CZTTY_CZ(sc); 1231 1232 if (sc->sc_rs_control_dtr == 0) 1233 return; 1234 1235 cz_wait_pci_doorbell(cz, "czmod"); 1236 1237 if (onoff) 1238 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1239 else 1240 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1241 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1242 1243 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1244 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1245 } 1246 1247 /* 1248 * tiocm_to_cztty: 1249 * 1250 * Process TIOCM* ioctls. 1251 */ 1252 static void 1253 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1254 { 1255 struct cz_softc *cz = CZTTY_CZ(sc); 1256 u_int32_t czttybits; 1257 1258 czttybits = 0; 1259 if (ISSET(ttybits, TIOCM_DTR)) 1260 SET(czttybits, C_RS_DTR); 1261 if (ISSET(ttybits, TIOCM_RTS)) 1262 SET(czttybits, C_RS_RTS); 1263 1264 cz_wait_pci_doorbell(cz, "cztiocm"); 1265 1266 switch (how) { 1267 case TIOCMBIC: 1268 CLR(sc->sc_chanctl_rs_control, czttybits); 1269 break; 1270 1271 case TIOCMBIS: 1272 SET(sc->sc_chanctl_rs_control, czttybits); 1273 break; 1274 1275 case TIOCMSET: 1276 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1277 SET(sc->sc_chanctl_rs_control, czttybits); 1278 break; 1279 } 1280 1281 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1282 1283 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1284 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1285 } 1286 1287 /* 1288 * cztty_to_tiocm: 1289 * 1290 * Process the TIOCMGET ioctl. 1291 */ 1292 static int 1293 cztty_to_tiocm(struct cztty_softc *sc) 1294 { 1295 struct cz_softc *cz = CZTTY_CZ(sc); 1296 u_int32_t rs_status, op_mode; 1297 int ttybits = 0; 1298 1299 cz_wait_pci_doorbell(cz, "cztty"); 1300 1301 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1302 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1303 1304 if (ISSET(rs_status, C_RS_RTS)) 1305 SET(ttybits, TIOCM_RTS); 1306 if (ISSET(rs_status, C_RS_CTS)) 1307 SET(ttybits, TIOCM_CTS); 1308 if (ISSET(rs_status, C_RS_DCD)) 1309 SET(ttybits, TIOCM_CAR); 1310 if (ISSET(rs_status, C_RS_DTR)) 1311 SET(ttybits, TIOCM_DTR); 1312 if (ISSET(rs_status, C_RS_RI)) 1313 SET(ttybits, TIOCM_RNG); 1314 if (ISSET(rs_status, C_RS_DSR)) 1315 SET(ttybits, TIOCM_DSR); 1316 1317 if (ISSET(op_mode, C_CH_ENABLE)) 1318 SET(ttybits, TIOCM_LE); 1319 1320 return (ttybits); 1321 } 1322 1323 /* 1324 * czttyparam: 1325 * 1326 * Set Cyclades-Z serial port parameters from termios. 1327 * 1328 * XXX Should just copy the whole termios after making 1329 * XXX sure all the changes could be done. 1330 */ 1331 static int 1332 czttyparam(struct tty *tp, struct termios *t) 1333 { 1334 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1335 struct cz_softc *cz = CZTTY_CZ(sc); 1336 u_int32_t rs_status; 1337 int ospeed, cflag; 1338 1339 ospeed = t->c_ospeed; 1340 cflag = t->c_cflag; 1341 1342 /* Check requested parameters. */ 1343 if (ospeed < 0) 1344 return (EINVAL); 1345 if (t->c_ispeed && t->c_ispeed != ospeed) 1346 return (EINVAL); 1347 1348 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1349 SET(cflag, CLOCAL); 1350 CLR(cflag, HUPCL); 1351 } 1352 1353 /* 1354 * If there were no changes, don't do anything. This avoids dropping 1355 * input and improves performance when all we did was frob things like 1356 * VMIN and VTIME. 1357 */ 1358 if (tp->t_ospeed == ospeed && 1359 tp->t_cflag == cflag) 1360 return (0); 1361 1362 /* Data bits. */ 1363 sc->sc_chanctl_comm_data_l = 0; 1364 switch (t->c_cflag & CSIZE) { 1365 case CS5: 1366 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1367 break; 1368 1369 case CS6: 1370 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1371 break; 1372 1373 case CS7: 1374 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1375 break; 1376 1377 case CS8: 1378 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1379 break; 1380 } 1381 1382 /* Stop bits. */ 1383 if (t->c_cflag & CSTOPB) { 1384 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1385 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1386 else 1387 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1388 } else 1389 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1390 1391 /* Parity. */ 1392 if (t->c_cflag & PARENB) { 1393 if (t->c_cflag & PARODD) 1394 sc->sc_chanctl_comm_parity = C_PR_ODD; 1395 else 1396 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1397 } else 1398 sc->sc_chanctl_comm_parity = C_PR_NONE; 1399 1400 /* 1401 * Initialize flow control pins depending on the current flow control 1402 * mode. 1403 */ 1404 if (ISSET(t->c_cflag, CRTSCTS)) { 1405 sc->sc_rs_control_dtr = C_RS_DTR; 1406 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1407 } else if (ISSET(t->c_cflag, MDMBUF)) { 1408 sc->sc_rs_control_dtr = 0; 1409 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1410 } else { 1411 /* 1412 * If no flow control, then always set RTS. This will make 1413 * the other side happy if it mistakenly thinks we're doing 1414 * RTS/CTS flow control. 1415 */ 1416 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1417 sc->sc_chanctl_hw_flow = 0; 1418 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1419 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1420 else 1421 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1422 } 1423 1424 /* Baud rate. */ 1425 sc->sc_chanctl_comm_baud = ospeed; 1426 1427 /* Copy to tty. */ 1428 tp->t_ispeed = 0; 1429 tp->t_ospeed = t->c_ospeed; 1430 tp->t_cflag = t->c_cflag; 1431 1432 /* 1433 * Now load the channel control structure. 1434 */ 1435 1436 cz_wait_pci_doorbell(cz, "czparam"); 1437 1438 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1439 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1440 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1441 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1442 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1443 1444 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1445 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1446 1447 cz_wait_pci_doorbell(cz, "czparam"); 1448 1449 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1450 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1451 1452 cz_wait_pci_doorbell(cz, "czparam"); 1453 1454 /* 1455 * Update the tty layer's idea of the carrier bit, in case we changed 1456 * CLOCAL. We don't hang up here; we only do that by explicit 1457 * request. 1458 */ 1459 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1460 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1461 1462 return (0); 1463 } 1464 1465 /* 1466 * czttystart: 1467 * 1468 * Start or restart transmission. 1469 */ 1470 static void 1471 czttystart(struct tty *tp) 1472 { 1473 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1474 int s; 1475 1476 s = spltty(); 1477 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1478 goto out; 1479 1480 if (tp->t_outq.c_cc <= tp->t_lowat) { 1481 if (ISSET(tp->t_state, TS_ASLEEP)) { 1482 CLR(tp->t_state, TS_ASLEEP); 1483 wakeup(&tp->t_outq); 1484 } 1485 selwakeup(&tp->t_wsel); 1486 if (tp->t_outq.c_cc == 0) 1487 goto out; 1488 } 1489 1490 cztty_transmit(sc, tp); 1491 out: 1492 splx(s); 1493 } 1494 1495 /* 1496 * czttystop: 1497 * 1498 * Stop output, e.g., for ^S or output flush. 1499 */ 1500 static void 1501 czttystop(struct tty *tp, int flag) 1502 { 1503 1504 /* 1505 * XXX We don't do anything here, yet. Mostly, I don't know 1506 * XXX exactly how this should be implemented on this device. 1507 * XXX We've given a big chunk of data to the MIPS already, 1508 * XXX and I don't know how we request the MIPS to stop sending 1509 * XXX the data. So, punt for now. --thorpej 1510 */ 1511 } 1512 1513 /* 1514 * cztty_diag: 1515 * 1516 * Issue a scheduled diagnostic message. 1517 */ 1518 static void 1519 cztty_diag(void *arg) 1520 { 1521 struct cztty_softc *sc = arg; 1522 struct cz_softc *cz = CZTTY_CZ(sc); 1523 u_int overflows, parity_errors, framing_errors; 1524 int s; 1525 1526 s = spltty(); 1527 1528 overflows = sc->sc_overflows; 1529 sc->sc_overflows = 0; 1530 1531 parity_errors = sc->sc_parity_errors; 1532 sc->sc_parity_errors = 0; 1533 1534 framing_errors = sc->sc_framing_errors; 1535 sc->sc_framing_errors = 0; 1536 1537 sc->sc_errors = 0; 1538 1539 splx(s); 1540 1541 log(LOG_WARNING, 1542 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1543 cz->cz_dev.dv_xname, sc->sc_channel, 1544 overflows, overflows == 1 ? "" : "s", 1545 parity_errors, 1546 framing_errors, framing_errors == 1 ? "" : "s"); 1547 } 1548 1549 const struct cdevsw cz_cdevsw = { 1550 czttyopen, czttyclose, czttyread, czttywrite, czttyioctl, 1551 czttystop, czttytty, czttypoll, nommap, ttykqfilter, D_TTY 1552 }; 1553 1554 /* 1555 * tx and rx ring buffer size macros: 1556 * 1557 * The transmitter and receiver both use ring buffers. For each one, there 1558 * is a get (consumer) and a put (producer) offset. The get value is the 1559 * next byte to be read from the ring, and the put is the next one to be 1560 * put into the ring. get == put means the ring is empty. 1561 * 1562 * For each ring, the firmware controls one of (get, put) and this driver 1563 * controls the other. For transmission, this driver updates put to point 1564 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1565 * for receive, the driver controls put, and this driver controls get. 1566 */ 1567 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1568 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1569 1570 /* 1571 * cztty_transmit() 1572 * 1573 * Look at the tty for this port and start sending. 1574 */ 1575 static int 1576 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1577 { 1578 struct cz_softc *cz = CZTTY_CZ(sc); 1579 u_int move, get, put, size, address; 1580 #ifdef HOSTRAMCODE 1581 int error, done = 0; 1582 #else 1583 int done = 0; 1584 #endif 1585 1586 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1587 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1588 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1589 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1590 1591 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1592 #ifdef HOSTRAMCODE 1593 if (0) { 1594 move = min(tp->t_outq.c_cc, move); 1595 error = q_to_b(&tp->t_outq, 0, move); 1596 if (error != move) { 1597 printf("%s: channel %d: error moving to " 1598 "transmit buf\n", cz->cz_dev.dv_xname, 1599 sc->sc_channel); 1600 move = error; 1601 } 1602 } else { 1603 #endif 1604 move = min(ndqb(&tp->t_outq, 0), move); 1605 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1606 address + put, tp->t_outq.c_cf, move); 1607 ndflush(&tp->t_outq, move); 1608 #ifdef HOSTRAMCODE 1609 } 1610 #endif 1611 1612 put = ((put + move) % size); 1613 done = 1; 1614 } 1615 if (done) { 1616 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1617 } 1618 return (done); 1619 } 1620 1621 static int 1622 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1623 { 1624 struct cz_softc *cz = CZTTY_CZ(sc); 1625 u_int get, put, size, address; 1626 int done = 0, ch; 1627 1628 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1629 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1630 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1631 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1632 1633 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1634 #ifdef HOSTRAMCODE 1635 if (hostram) 1636 ch = ((char *)fifoaddr)[get]; 1637 } else { 1638 #endif 1639 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1640 address + get); 1641 #ifdef HOSTRAMCODE 1642 } 1643 #endif 1644 (*tp->t_linesw->l_rint)(ch, tp); 1645 get = (get + 1) % size; 1646 done = 1; 1647 } 1648 if (done) { 1649 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1650 } 1651 return (done); 1652 } 1653