1 /* $NetBSD: cz.c,v 1.49 2008/06/08 12:43:52 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only use RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: cz.c,v 1.49 2008/06/08 12:43:52 tsutsui Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/tty.h> 84 #include <sys/conf.h> 85 #include <sys/time.h> 86 #include <sys/kernel.h> 87 #include <sys/fcntl.h> 88 #include <sys/syslog.h> 89 #include <sys/kauth.h> 90 91 #include <sys/callout.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/czreg.h> 97 98 #include <dev/pci/plx9060reg.h> 99 #include <dev/pci/plx9060var.h> 100 101 #include <dev/microcode/cyclades-z/cyzfirm.h> 102 103 #define CZ_DRIVER_VERSION 0x20000411 104 105 #define CZ_POLL_MS 20 106 107 /* These are the interrupts we always use. */ 108 #define CZ_INTERRUPTS \ 109 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 110 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 111 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 112 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 113 114 /* 115 * cztty_softc: 116 * 117 * Per-channel (TTY) state. 118 */ 119 struct cztty_softc { 120 struct cz_softc *sc_parent; 121 struct tty *sc_tty; 122 123 callout_t sc_diag_ch; 124 125 int sc_channel; /* Also used to flag unattached chan */ 126 #define CZTTY_CHANNEL_DEAD -1 127 128 bus_space_tag_t sc_chan_st; /* channel space tag */ 129 bus_space_handle_t sc_chan_sh; /* channel space handle */ 130 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 131 132 u_int sc_overflows, 133 sc_parity_errors, 134 sc_framing_errors, 135 sc_errors; 136 137 int sc_swflags; 138 139 u_int32_t sc_rs_control_dtr, 140 sc_chanctl_hw_flow, 141 sc_chanctl_comm_baud, 142 sc_chanctl_rs_control, 143 sc_chanctl_comm_data_l, 144 sc_chanctl_comm_parity; 145 }; 146 147 /* 148 * cz_softc: 149 * 150 * Per-board state. 151 */ 152 struct cz_softc { 153 struct device cz_dev; /* generic device info */ 154 struct plx9060_config cz_plx; /* PLX 9060 config info */ 155 bus_space_tag_t cz_win_st; /* window space tag */ 156 bus_space_handle_t cz_win_sh; /* window space handle */ 157 callout_t cz_callout; /* callout for polling-mode */ 158 159 void *cz_ih; /* interrupt handle */ 160 161 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 162 int cz_nchannels; /* number of channels */ 163 int cz_nopenchan; /* number of open channels */ 164 struct cztty_softc *cz_ports; /* our array of ports */ 165 166 bus_addr_t cz_fwctl; /* offset of firmware control */ 167 }; 168 169 static int cz_wait_pci_doorbell(struct cz_softc *, const char *); 170 171 static int cz_load_firmware(struct cz_softc *); 172 173 static int cz_intr(void *); 174 static void cz_poll(void *); 175 static int cztty_transmit(struct cztty_softc *, struct tty *); 176 static int cztty_receive(struct cztty_softc *, struct tty *); 177 178 static struct cztty_softc *cztty_getttysoftc(dev_t dev); 179 static int cztty_attached_ttys; 180 static int cz_timeout_ticks; 181 182 static void czttystart(struct tty *tp); 183 static int czttyparam(struct tty *tp, struct termios *t); 184 static void cztty_shutdown(struct cztty_softc *sc); 185 static void cztty_modem(struct cztty_softc *sc, int onoff); 186 static void cztty_break(struct cztty_softc *sc, int onoff); 187 static void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 188 static int cztty_to_tiocm(struct cztty_softc *sc); 189 static void cztty_diag(void *arg); 190 191 extern struct cfdriver cz_cd; 192 193 /* 194 * Macros to read and write the PLX. 195 */ 196 #define CZ_PLX_READ(cz, reg) \ 197 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 198 #define CZ_PLX_WRITE(cz, reg, val) \ 199 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 200 (reg), (val)) 201 202 /* 203 * Macros to read and write the FPGA. We must already be in the FPGA 204 * window for this. 205 */ 206 #define CZ_FPGA_READ(cz, reg) \ 207 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 208 #define CZ_FPGA_WRITE(cz, reg, val) \ 209 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 210 211 /* 212 * Macros to read and write the firmware control structures in board RAM. 213 */ 214 #define CZ_FWCTL_READ(cz, off) \ 215 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 216 (cz)->cz_fwctl + (off)) 217 218 #define CZ_FWCTL_WRITE(cz, off, val) \ 219 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 220 (cz)->cz_fwctl + (off), (val)) 221 222 /* 223 * Convenience macros for cztty routines. PLX window MUST be to RAM. 224 */ 225 #define CZTTY_CHAN_READ(sc, off) \ 226 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 227 228 #define CZTTY_CHAN_WRITE(sc, off, val) \ 229 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 230 (off), (val)) 231 232 #define CZTTY_BUF_READ(sc, off) \ 233 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 234 235 #define CZTTY_BUF_WRITE(sc, off, val) \ 236 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 237 (off), (val)) 238 239 /* 240 * Convenience macros. 241 */ 242 #define CZ_WIN_RAM(cz) \ 243 do { \ 244 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 245 delay(100); \ 246 } while (0) 247 248 #define CZ_WIN_FPGA(cz) \ 249 do { \ 250 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 251 delay(100); \ 252 } while (0) 253 254 /***************************************************************************** 255 * Cyclades-Z controller code starts here... 256 *****************************************************************************/ 257 258 /* 259 * cz_match: 260 * 261 * Determine if the given PCI device is a Cyclades-Z board. 262 */ 263 static int 264 cz_match(struct device *parent, 265 struct cfdata *match, 266 void *aux) 267 { 268 struct pci_attach_args *pa = aux; 269 270 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 271 switch (PCI_PRODUCT(pa->pa_id)) { 272 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 273 return (1); 274 } 275 } 276 277 return (0); 278 } 279 280 /* 281 * cz_attach: 282 * 283 * A Cyclades-Z board was found; attach it. 284 */ 285 static void 286 cz_attach(struct device *parent, 287 struct device *self, 288 void *aux) 289 { 290 extern const struct cdevsw cz_cdevsw; /* XXX */ 291 struct cz_softc *cz = (void *) self; 292 struct pci_attach_args *pa = aux; 293 pci_intr_handle_t ih; 294 const char *intrstr = NULL; 295 struct cztty_softc *sc; 296 struct tty *tp; 297 int i; 298 299 aprint_naive(": Multi-port serial controller\n"); 300 aprint_normal(": Cyclades-Z multiport serial\n"); 301 302 cz->cz_plx.plx_pc = pa->pa_pc; 303 cz->cz_plx.plx_tag = pa->pa_tag; 304 305 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 306 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 307 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 308 aprint_error_dev(&cz->cz_dev, "unable to map PLX registers\n"); 309 return; 310 } 311 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 312 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 313 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 314 aprint_error_dev(&cz->cz_dev, "unable to map device window\n"); 315 return; 316 } 317 318 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 319 cz->cz_nopenchan = 0; 320 321 /* 322 * Make sure that the board is completely stopped. 323 */ 324 CZ_WIN_FPGA(cz); 325 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 326 327 /* 328 * Load the board's firmware. 329 */ 330 if (cz_load_firmware(cz) != 0) 331 return; 332 333 /* 334 * Now that we're ready to roll, map and establish the interrupt 335 * handler. 336 */ 337 if (pci_intr_map(pa, &ih) != 0) { 338 /* 339 * The common case is for Cyclades-Z boards to run 340 * in polling mode, and thus not have an interrupt 341 * mapped for them. Don't bother reporting that 342 * the interrupt is not mappable, since this isn't 343 * really an error. 344 */ 345 cz->cz_ih = NULL; 346 goto polling_mode; 347 } else { 348 intrstr = pci_intr_string(pa->pa_pc, ih); 349 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 350 cz_intr, cz); 351 } 352 if (cz->cz_ih == NULL) { 353 aprint_error_dev(&cz->cz_dev, "unable to establish interrupt"); 354 if (intrstr != NULL) 355 aprint_normal(" at %s", intrstr); 356 aprint_normal("\n"); 357 /* We will fall-back on polling mode. */ 358 } else 359 aprint_normal_dev(&cz->cz_dev, "interrupting at %s\n", 360 intrstr); 361 362 polling_mode: 363 if (cz->cz_ih == NULL) { 364 callout_init(&cz->cz_callout, 0); 365 if (cz_timeout_ticks == 0) 366 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 367 aprint_normal_dev(&cz->cz_dev, "polling mode, %d ms interval (%d tick%s)\n", 368 CZ_POLL_MS, cz_timeout_ticks, 369 cz_timeout_ticks == 1 ? "" : "s"); 370 } 371 372 /* 373 * Allocate sufficient pointers for the children and 374 * attach them. Set all ports to a reasonable initial 375 * configuration while we're at it: 376 * 377 * disabled 378 * 8N1 379 * default baud rate 380 * hardware flow control. 381 */ 382 CZ_WIN_RAM(cz); 383 384 if (cz->cz_nchannels == 0) { 385 /* No channels? No more work to do! */ 386 return; 387 } 388 389 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 390 M_DEVBUF, M_WAITOK|M_ZERO); 391 cztty_attached_ttys += cz->cz_nchannels; 392 393 for (i = 0; i < cz->cz_nchannels; i++) { 394 sc = &cz->cz_ports[i]; 395 396 sc->sc_channel = i; 397 sc->sc_chan_st = cz->cz_win_st; 398 sc->sc_parent = cz; 399 400 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 401 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 402 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 403 aprint_error_dev(&cz->cz_dev, 404 "unable to subregion channel %d control\n", i); 405 sc->sc_channel = CZTTY_CHANNEL_DEAD; 406 continue; 407 } 408 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 409 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 410 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 411 aprint_error_dev(&cz->cz_dev, 412 "unable to subregion channel %d buffer\n", i); 413 sc->sc_channel = CZTTY_CHANNEL_DEAD; 414 continue; 415 } 416 417 callout_init(&sc->sc_diag_ch, 0); 418 419 tp = ttymalloc(); 420 tp->t_dev = makedev(cdevsw_lookup_major(&cz_cdevsw), 421 (device_unit(&cz->cz_dev) * ZFIRM_MAX_CHANNELS) + i); 422 tp->t_oproc = czttystart; 423 tp->t_param = czttyparam; 424 tty_attach(tp); 425 426 sc->sc_tty = tp; 427 428 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 429 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 430 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 431 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 432 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 433 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 434 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 435 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 436 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 437 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 438 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 439 } 440 } 441 442 CFATTACH_DECL(cz, sizeof(struct cz_softc), 443 cz_match, cz_attach, NULL, NULL); 444 445 #if 0 446 /* 447 * cz_reset_board: 448 * 449 * Reset the board via the PLX. 450 */ 451 static void 452 cz_reset_board(struct cz_softc *cz) 453 { 454 u_int32_t reg; 455 456 reg = CZ_PLX_READ(cz, PLX_CONTROL); 457 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 458 delay(1000); 459 460 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 461 delay(1000); 462 463 /* Now reload the PLX from its EEPROM. */ 464 reg = CZ_PLX_READ(cz, PLX_CONTROL); 465 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 466 delay(1000); 467 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 468 } 469 #endif 470 471 /* 472 * cz_load_firmware: 473 * 474 * Load the ZFIRM firmware into the board's RAM and start it 475 * running. 476 */ 477 static int 478 cz_load_firmware(struct cz_softc *cz) 479 { 480 const struct zfirm_header *zfh; 481 const struct zfirm_config *zfc; 482 const struct zfirm_block *zfb, *zblocks; 483 const u_int8_t *cp; 484 const char *board; 485 u_int32_t fid; 486 int i, j, nconfigs, nblocks, nbytes; 487 488 zfh = (const struct zfirm_header *) cycladesz_firmware; 489 490 /* Find the config header. */ 491 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 492 aprint_error_dev(&cz->cz_dev, "bad ZFIRM config offset: 0x%x\n", 493 le32toh(zfh->zfh_configoff)); 494 return (EIO); 495 } 496 zfc = (const struct zfirm_config *)(cycladesz_firmware + 497 le32toh(zfh->zfh_configoff)); 498 nconfigs = le32toh(zfh->zfh_nconfig); 499 500 /* Locate the correct configuration for our board. */ 501 for (i = 0; i < nconfigs; i++, zfc++) { 502 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 503 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 504 break; 505 } 506 if (i == nconfigs) { 507 aprint_error_dev(&cz->cz_dev, "unable to locate config header\n"); 508 return (EIO); 509 } 510 511 nblocks = le32toh(zfc->zfc_nblocks); 512 zblocks = (const struct zfirm_block *)(cycladesz_firmware + 513 le32toh(zfh->zfh_blockoff)); 514 515 /* 516 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 517 * necessary. 518 */ 519 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 520 #if 0 521 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 522 #endif 523 ) { 524 #ifdef CZ_DEBUG 525 aprint_debug_dev(&cz->cz_dev, "Loading FPGA..."); 526 #endif 527 CZ_WIN_FPGA(cz); 528 for (i = 0; i < nblocks; i++) { 529 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 530 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 531 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 532 nbytes = le32toh(zfb->zfb_size); 533 cp = &cycladesz_firmware[ 534 le32toh(zfb->zfb_fileoff)]; 535 for (j = 0; j < nbytes; j++, cp++) { 536 bus_space_write_1(cz->cz_win_st, 537 cz->cz_win_sh, 0, *cp); 538 /* FPGA needs 30-100us to settle. */ 539 delay(10); 540 } 541 } 542 } 543 #ifdef CZ_DEBUG 544 aprint_debug("done\n"); 545 #endif 546 } 547 548 /* Now load the firmware. */ 549 CZ_WIN_RAM(cz); 550 551 for (i = 0; i < nblocks; i++) { 552 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 553 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 554 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 555 const u_int32_t *lp; 556 u_int32_t ro = le32toh(zfb->zfb_ramoff); 557 nbytes = le32toh(zfb->zfb_size); 558 lp = (const u_int32_t *) 559 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 560 for (j = 0; j < nbytes; j += 4, lp++) { 561 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 562 ro + j, le32toh(*lp)); 563 delay(10); 564 } 565 } 566 } 567 568 /* Now restart the MIPS. */ 569 CZ_WIN_FPGA(cz); 570 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 571 572 /* Wait for the MIPS to start, then report the results. */ 573 CZ_WIN_RAM(cz); 574 575 #ifdef CZ_DEBUG 576 aprint_debug_dev(&cz->cz_dev, "waiting for MIPS to start"); 577 #endif 578 for (i = 0; i < 100; i++) { 579 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 580 ZFIRM_SIG_OFF); 581 if (fid == ZFIRM_SIG) { 582 /* MIPS has booted. */ 583 break; 584 } else if (fid == ZFIRM_HLT) { 585 /* 586 * The MIPS has halted, usually due to a power 587 * shortage on the expansion module. 588 */ 589 aprint_error_dev(&cz->cz_dev, "MIPS halted; possible power supply " 590 "problem\n"); 591 return (EIO); 592 } else { 593 #ifdef CZ_DEBUG 594 if ((i % 8) == 0) 595 aprint_debug("."); 596 #endif 597 delay(250000); 598 } 599 } 600 #ifdef CZ_DEBUG 601 aprint_debug("\n"); 602 #endif 603 if (i == 100) { 604 CZ_WIN_FPGA(cz); 605 aprint_error_dev(&cz->cz_dev, 606 "MIPS failed to start; wanted 0x%08x got 0x%08x\n", 607 ZFIRM_SIG, fid); 608 aprint_error_dev(&cz->cz_dev, "FPGA ID 0x%08x, FPGA version 0x%08x\n", 609 CZ_FPGA_READ(cz, FPGA_ID), 610 CZ_FPGA_READ(cz, FPGA_VERSION)); 611 return (EIO); 612 } 613 614 /* 615 * Locate the firmware control structures. 616 */ 617 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 618 ZFIRM_CTRLADDR_OFF); 619 #ifdef CZ_DEBUG 620 aprint_debug_dev(&cz->cz_dev, "FWCTL structure at offset 0x%08lx\n", 621 cz->cz_fwctl); 622 #endif 623 624 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 625 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 626 627 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 628 629 switch (cz->cz_mailbox0) { 630 case MAILBOX0_8Zo_V1: 631 board = "Cyclades-8Zo ver. 1"; 632 break; 633 634 case MAILBOX0_8Zo_V2: 635 board = "Cyclades-8Zo ver. 2"; 636 break; 637 638 case MAILBOX0_Ze_V1: 639 board = "Cyclades-Ze"; 640 break; 641 642 default: 643 board = "unknown Cyclades Z-series"; 644 break; 645 } 646 647 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 648 aprint_normal_dev(&cz->cz_dev, "%s, ", board); 649 if (cz->cz_nchannels == 0) 650 aprint_normal("no channels attached, "); 651 else 652 aprint_normal("%d channels (ttyCZ%04d..ttyCZ%04d), ", 653 cz->cz_nchannels, cztty_attached_ttys, 654 cztty_attached_ttys + (cz->cz_nchannels - 1)); 655 aprint_normal("firmware %x.%x.%x\n", 656 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 657 658 return (0); 659 } 660 661 /* 662 * cz_poll: 663 * 664 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 665 * ms. 666 */ 667 static void 668 cz_poll(void *arg) 669 { 670 int s = spltty(); 671 struct cz_softc *cz = arg; 672 673 cz_intr(cz); 674 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 675 676 splx(s); 677 } 678 679 /* 680 * cz_intr: 681 * 682 * Interrupt service routine. 683 * 684 * We either are receiving an interrupt directly from the board, or we are 685 * in polling mode and it's time to poll. 686 */ 687 static int 688 cz_intr(void *arg) 689 { 690 int rval = 0; 691 u_int command, channel, param; 692 struct cz_softc *cz = arg; 693 struct cztty_softc *sc; 694 struct tty *tp; 695 696 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 697 rval = 1; 698 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 699 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 700 701 /* now clear this interrupt, posslibly enabling another */ 702 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 703 704 if (cz->cz_ports == NULL) { 705 #ifdef CZ_DEBUG 706 printf("%s: interrupt on channel %d, but no channels\n", 707 device_xname(&cz->cz_dev), channel); 708 #endif 709 continue; 710 } 711 712 sc = &cz->cz_ports[channel]; 713 714 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 715 break; 716 717 tp = sc->sc_tty; 718 719 switch (command) { 720 case C_CM_TXFEMPTY: /* transmit cases */ 721 case C_CM_TXBEMPTY: 722 case C_CM_TXLOWWM: 723 case C_CM_INTBACK: 724 if (!ISSET(tp->t_state, TS_ISOPEN)) { 725 #ifdef CZ_DEBUG 726 printf("%s: tx intr on closed channel %d\n", 727 device_xname(&cz->cz_dev), channel); 728 #endif 729 break; 730 } 731 732 if (cztty_transmit(sc, tp)) { 733 /* 734 * Do wakeup stuff here. 735 */ 736 mutex_spin_enter(&tty_lock); /* XXX */ 737 ttwakeup(tp); 738 mutex_spin_exit(&tty_lock); /* XXX */ 739 wakeup(tp); 740 } 741 break; 742 743 case C_CM_RXNNDT: /* receive cases */ 744 case C_CM_RXHIWM: 745 case C_CM_INTBACK2: /* from restart ?? */ 746 #if 0 747 case C_CM_ICHAR: 748 #endif 749 if (!ISSET(tp->t_state, TS_ISOPEN)) { 750 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 751 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 752 break; 753 } 754 755 if (cztty_receive(sc, tp)) { 756 /* 757 * Do wakeup stuff here. 758 */ 759 mutex_spin_enter(&tty_lock); /* XXX */ 760 ttwakeup(tp); 761 mutex_spin_exit(&tty_lock); /* XXX */ 762 wakeup(tp); 763 } 764 break; 765 766 case C_CM_MDCD: 767 if (!ISSET(tp->t_state, TS_ISOPEN)) 768 break; 769 770 (void) (*tp->t_linesw->l_modem)(tp, 771 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 772 CHNCTL_RS_STATUS))); 773 break; 774 775 case C_CM_MDSR: 776 case C_CM_MRI: 777 case C_CM_MCTS: 778 case C_CM_MRTS: 779 break; 780 781 case C_CM_IOCTLW: 782 break; 783 784 case C_CM_PR_ERROR: 785 sc->sc_parity_errors++; 786 goto error_common; 787 788 case C_CM_FR_ERROR: 789 sc->sc_framing_errors++; 790 goto error_common; 791 792 case C_CM_OVR_ERROR: 793 sc->sc_overflows++; 794 error_common: 795 if (sc->sc_errors++ == 0) 796 callout_reset(&sc->sc_diag_ch, 60 * hz, 797 cztty_diag, sc); 798 break; 799 800 case C_CM_RXBRK: 801 if (!ISSET(tp->t_state, TS_ISOPEN)) 802 break; 803 804 /* 805 * A break is a \000 character with TTY_FE error 806 * flags set. So TTY_FE by itself works. 807 */ 808 (*tp->t_linesw->l_rint)(TTY_FE, tp); 809 mutex_spin_enter(&tty_lock); /* XXX */ 810 ttwakeup(tp); 811 mutex_spin_exit(&tty_lock); /* XXX */ 812 wakeup(tp); 813 break; 814 815 default: 816 #ifdef CZ_DEBUG 817 printf("%s: channel %d: Unknown interrupt 0x%x\n", 818 device_xname(&cz->cz_dev), sc->sc_channel, command); 819 #endif 820 break; 821 } 822 } 823 824 return (rval); 825 } 826 827 /* 828 * cz_wait_pci_doorbell: 829 * 830 * Wait for the pci doorbell to be clear - wait for pending 831 * activity to drain. 832 */ 833 static int 834 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 835 { 836 int error; 837 838 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 839 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 840 if ((error != 0) && (error != EWOULDBLOCK)) 841 return (error); 842 } 843 return (0); 844 } 845 846 /***************************************************************************** 847 * Cyclades-Z TTY code starts here... 848 *****************************************************************************/ 849 850 #define CZTTYDIALOUT_MASK 0x80000 851 852 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 853 #define CZTTY_CZ(sc) ((sc)->sc_parent) 854 855 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 856 857 static struct cztty_softc * 858 cztty_getttysoftc(dev_t dev) 859 { 860 int i, j, k = 0, u = minor(dev) & ~CZTTYDIALOUT_MASK; 861 struct cz_softc *cz = NULL; 862 863 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 864 k = j; 865 cz = device_lookup_private(&cz_cd, i); 866 if (cz == NULL) 867 continue; 868 if (cz->cz_ports == NULL) 869 continue; 870 j += cz->cz_nchannels; 871 if (j > u) 872 break; 873 } 874 875 if (i >= cz_cd.cd_ndevs) 876 return (NULL); 877 else 878 return (&cz->cz_ports[u - k]); 879 } 880 881 /* 882 * czttytty: 883 * 884 * Return a pointer to our tty. 885 */ 886 static struct tty * 887 czttytty(dev_t dev) 888 { 889 struct cztty_softc *sc = CZTTY_SOFTC(dev); 890 891 #ifdef DIAGNOSTIC 892 if (sc == NULL) 893 panic("czttytty"); 894 #endif 895 896 return (sc->sc_tty); 897 } 898 899 /* 900 * cztty_shutdown: 901 * 902 * Shut down a port. 903 */ 904 static void 905 cztty_shutdown(struct cztty_softc *sc) 906 { 907 struct cz_softc *cz = CZTTY_CZ(sc); 908 struct tty *tp = sc->sc_tty; 909 int s; 910 911 s = spltty(); 912 913 /* Clear any break condition set with TIOCSBRK. */ 914 cztty_break(sc, 0); 915 916 /* 917 * Hang up if necessary. Wait a bit, so the other side has time to 918 * notice even if we immediately open the port again. 919 */ 920 if (ISSET(tp->t_cflag, HUPCL)) { 921 cztty_modem(sc, 0); 922 (void) tsleep(tp, TTIPRI, ttclos, hz); 923 } 924 925 /* Disable the channel. */ 926 cz_wait_pci_doorbell(cz, "czdis"); 927 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 928 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 929 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 930 931 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 932 #ifdef CZ_DEBUG 933 printf("%s: Disabling polling\n", device_xname(&cz->cz_dev)); 934 #endif 935 callout_stop(&cz->cz_callout); 936 } 937 938 splx(s); 939 } 940 941 /* 942 * czttyopen: 943 * 944 * Open a Cyclades-Z serial port. 945 */ 946 static int 947 czttyopen(dev_t dev, int flags, int mode, struct lwp *l) 948 { 949 struct cztty_softc *sc = CZTTY_SOFTC(dev); 950 struct cz_softc *cz; 951 struct tty *tp; 952 int s, error; 953 954 if (sc == NULL) 955 return (ENXIO); 956 957 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 958 return (ENXIO); 959 960 cz = CZTTY_CZ(sc); 961 tp = sc->sc_tty; 962 963 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 964 return (EBUSY); 965 966 s = spltty(); 967 968 /* 969 * Do the following iff this is a first open. 970 */ 971 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 972 struct termios t; 973 974 tp->t_dev = dev; 975 976 /* If we're turning things on, enable interrupts */ 977 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 978 #ifdef CZ_DEBUG 979 printf("%s: Enabling polling.\n", 980 device_xname(&cz->cz_dev)); 981 #endif 982 callout_reset(&cz->cz_callout, cz_timeout_ticks, 983 cz_poll, cz); 984 } 985 986 /* 987 * Enable the channel. Don't actually ring the 988 * doorbell here; czttyparam() will do it for us. 989 */ 990 cz_wait_pci_doorbell(cz, "czopen"); 991 992 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 993 994 /* 995 * Initialize the termios status to the defaults. Add in the 996 * sticky bits from TIOCSFLAGS. 997 */ 998 t.c_ispeed = 0; 999 t.c_ospeed = TTYDEF_SPEED; 1000 t.c_cflag = TTYDEF_CFLAG; 1001 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1002 SET(t.c_cflag, CLOCAL); 1003 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1004 SET(t.c_cflag, CRTSCTS); 1005 1006 /* 1007 * Reset the input and output rings. Do this before 1008 * we call czttyparam(), as that function enables 1009 * the channel. 1010 */ 1011 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1012 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1013 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1014 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1015 1016 /* Make sure czttyparam() will see changes. */ 1017 tp->t_ospeed = 0; 1018 (void) czttyparam(tp, &t); 1019 tp->t_iflag = TTYDEF_IFLAG; 1020 tp->t_oflag = TTYDEF_OFLAG; 1021 tp->t_lflag = TTYDEF_LFLAG; 1022 ttychars(tp); 1023 ttsetwater(tp); 1024 1025 /* 1026 * Turn on DTR. We must always do this, even if carrier is not 1027 * present, because otherwise we'd have to use TIOCSDTR 1028 * immediately after setting CLOCAL, which applications do not 1029 * expect. We always assert DTR while the device is open 1030 * unless explicitly requested to deassert it. 1031 */ 1032 cztty_modem(sc, 1); 1033 } 1034 1035 splx(s); 1036 1037 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1038 if (error) 1039 goto bad; 1040 1041 error = (*tp->t_linesw->l_open)(dev, tp); 1042 if (error) 1043 goto bad; 1044 1045 return (0); 1046 1047 bad: 1048 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1049 /* 1050 * We failed to open the device, and nobody else had it opened. 1051 * Clean up the state as appropriate. 1052 */ 1053 cztty_shutdown(sc); 1054 } 1055 1056 return (error); 1057 } 1058 1059 /* 1060 * czttyclose: 1061 * 1062 * Close a Cyclades-Z serial port. 1063 */ 1064 static int 1065 czttyclose(dev_t dev, int flags, int mode, struct lwp *l) 1066 { 1067 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1068 struct tty *tp = sc->sc_tty; 1069 1070 /* XXX This is for cons.c. */ 1071 if (!ISSET(tp->t_state, TS_ISOPEN)) 1072 return (0); 1073 1074 (*tp->t_linesw->l_close)(tp, flags); 1075 ttyclose(tp); 1076 1077 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1078 /* 1079 * Although we got a last close, the device may still be in 1080 * use; e.g. if this was the dialout node, and there are still 1081 * processes waiting for carrier on the non-dialout node. 1082 */ 1083 cztty_shutdown(sc); 1084 } 1085 1086 return (0); 1087 } 1088 1089 /* 1090 * czttyread: 1091 * 1092 * Read from a Cyclades-Z serial port. 1093 */ 1094 static int 1095 czttyread(dev_t dev, struct uio *uio, int flags) 1096 { 1097 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1098 struct tty *tp = sc->sc_tty; 1099 1100 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1101 } 1102 1103 /* 1104 * czttywrite: 1105 * 1106 * Write to a Cyclades-Z serial port. 1107 */ 1108 static int 1109 czttywrite(dev_t dev, struct uio *uio, int flags) 1110 { 1111 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1112 struct tty *tp = sc->sc_tty; 1113 1114 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1115 } 1116 1117 /* 1118 * czttypoll: 1119 * 1120 * Poll a Cyclades-Z serial port. 1121 */ 1122 static int 1123 czttypoll(dev_t dev, int events, struct lwp *l) 1124 { 1125 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1126 struct tty *tp = sc->sc_tty; 1127 1128 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1129 } 1130 1131 /* 1132 * czttyioctl: 1133 * 1134 * Perform a control operation on a Cyclades-Z serial port. 1135 */ 1136 static int 1137 czttyioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1138 { 1139 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1140 struct tty *tp = sc->sc_tty; 1141 int s, error; 1142 1143 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1144 if (error != EPASSTHROUGH) 1145 return (error); 1146 1147 error = ttioctl(tp, cmd, data, flag, l); 1148 if (error != EPASSTHROUGH) 1149 return (error); 1150 1151 error = 0; 1152 1153 s = spltty(); 1154 1155 switch (cmd) { 1156 case TIOCSBRK: 1157 cztty_break(sc, 1); 1158 break; 1159 1160 case TIOCCBRK: 1161 cztty_break(sc, 0); 1162 break; 1163 1164 case TIOCGFLAGS: 1165 *(int *)data = sc->sc_swflags; 1166 break; 1167 1168 case TIOCSFLAGS: 1169 error = kauth_authorize_device_tty(l->l_cred, 1170 KAUTH_DEVICE_TTY_PRIVSET, tp); 1171 if (error) 1172 break; 1173 sc->sc_swflags = *(int *)data; 1174 break; 1175 1176 case TIOCSDTR: 1177 cztty_modem(sc, 1); 1178 break; 1179 1180 case TIOCCDTR: 1181 cztty_modem(sc, 0); 1182 break; 1183 1184 case TIOCMSET: 1185 case TIOCMBIS: 1186 case TIOCMBIC: 1187 tiocm_to_cztty(sc, cmd, *(int *)data); 1188 break; 1189 1190 case TIOCMGET: 1191 *(int *)data = cztty_to_tiocm(sc); 1192 break; 1193 1194 default: 1195 error = EPASSTHROUGH; 1196 break; 1197 } 1198 1199 splx(s); 1200 1201 return (error); 1202 } 1203 1204 /* 1205 * cztty_break: 1206 * 1207 * Set or clear BREAK on a port. 1208 */ 1209 static void 1210 cztty_break(struct cztty_softc *sc, int onoff) 1211 { 1212 struct cz_softc *cz = CZTTY_CZ(sc); 1213 1214 cz_wait_pci_doorbell(cz, "czbreak"); 1215 1216 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1217 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1218 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1219 } 1220 1221 /* 1222 * cztty_modem: 1223 * 1224 * Set or clear DTR on a port. 1225 */ 1226 static void 1227 cztty_modem(struct cztty_softc *sc, int onoff) 1228 { 1229 struct cz_softc *cz = CZTTY_CZ(sc); 1230 1231 if (sc->sc_rs_control_dtr == 0) 1232 return; 1233 1234 cz_wait_pci_doorbell(cz, "czmod"); 1235 1236 if (onoff) 1237 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1238 else 1239 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1240 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1241 1242 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1243 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1244 } 1245 1246 /* 1247 * tiocm_to_cztty: 1248 * 1249 * Process TIOCM* ioctls. 1250 */ 1251 static void 1252 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1253 { 1254 struct cz_softc *cz = CZTTY_CZ(sc); 1255 u_int32_t czttybits; 1256 1257 czttybits = 0; 1258 if (ISSET(ttybits, TIOCM_DTR)) 1259 SET(czttybits, C_RS_DTR); 1260 if (ISSET(ttybits, TIOCM_RTS)) 1261 SET(czttybits, C_RS_RTS); 1262 1263 cz_wait_pci_doorbell(cz, "cztiocm"); 1264 1265 switch (how) { 1266 case TIOCMBIC: 1267 CLR(sc->sc_chanctl_rs_control, czttybits); 1268 break; 1269 1270 case TIOCMBIS: 1271 SET(sc->sc_chanctl_rs_control, czttybits); 1272 break; 1273 1274 case TIOCMSET: 1275 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1276 SET(sc->sc_chanctl_rs_control, czttybits); 1277 break; 1278 } 1279 1280 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1281 1282 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1283 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1284 } 1285 1286 /* 1287 * cztty_to_tiocm: 1288 * 1289 * Process the TIOCMGET ioctl. 1290 */ 1291 static int 1292 cztty_to_tiocm(struct cztty_softc *sc) 1293 { 1294 struct cz_softc *cz = CZTTY_CZ(sc); 1295 u_int32_t rs_status, op_mode; 1296 int ttybits = 0; 1297 1298 cz_wait_pci_doorbell(cz, "cztty"); 1299 1300 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1301 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1302 1303 if (ISSET(rs_status, C_RS_RTS)) 1304 SET(ttybits, TIOCM_RTS); 1305 if (ISSET(rs_status, C_RS_CTS)) 1306 SET(ttybits, TIOCM_CTS); 1307 if (ISSET(rs_status, C_RS_DCD)) 1308 SET(ttybits, TIOCM_CAR); 1309 if (ISSET(rs_status, C_RS_DTR)) 1310 SET(ttybits, TIOCM_DTR); 1311 if (ISSET(rs_status, C_RS_RI)) 1312 SET(ttybits, TIOCM_RNG); 1313 if (ISSET(rs_status, C_RS_DSR)) 1314 SET(ttybits, TIOCM_DSR); 1315 1316 if (ISSET(op_mode, C_CH_ENABLE)) 1317 SET(ttybits, TIOCM_LE); 1318 1319 return (ttybits); 1320 } 1321 1322 /* 1323 * czttyparam: 1324 * 1325 * Set Cyclades-Z serial port parameters from termios. 1326 * 1327 * XXX Should just copy the whole termios after making 1328 * XXX sure all the changes could be done. 1329 */ 1330 static int 1331 czttyparam(struct tty *tp, struct termios *t) 1332 { 1333 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1334 struct cz_softc *cz = CZTTY_CZ(sc); 1335 u_int32_t rs_status; 1336 int ospeed, cflag; 1337 1338 ospeed = t->c_ospeed; 1339 cflag = t->c_cflag; 1340 1341 /* Check requested parameters. */ 1342 if (ospeed < 0) 1343 return (EINVAL); 1344 if (t->c_ispeed && t->c_ispeed != ospeed) 1345 return (EINVAL); 1346 1347 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1348 SET(cflag, CLOCAL); 1349 CLR(cflag, HUPCL); 1350 } 1351 1352 /* 1353 * If there were no changes, don't do anything. This avoids dropping 1354 * input and improves performance when all we did was frob things like 1355 * VMIN and VTIME. 1356 */ 1357 if (tp->t_ospeed == ospeed && 1358 tp->t_cflag == cflag) 1359 return (0); 1360 1361 /* Data bits. */ 1362 sc->sc_chanctl_comm_data_l = 0; 1363 switch (t->c_cflag & CSIZE) { 1364 case CS5: 1365 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1366 break; 1367 1368 case CS6: 1369 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1370 break; 1371 1372 case CS7: 1373 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1374 break; 1375 1376 case CS8: 1377 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1378 break; 1379 } 1380 1381 /* Stop bits. */ 1382 if (t->c_cflag & CSTOPB) { 1383 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1384 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1385 else 1386 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1387 } else 1388 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1389 1390 /* Parity. */ 1391 if (t->c_cflag & PARENB) { 1392 if (t->c_cflag & PARODD) 1393 sc->sc_chanctl_comm_parity = C_PR_ODD; 1394 else 1395 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1396 } else 1397 sc->sc_chanctl_comm_parity = C_PR_NONE; 1398 1399 /* 1400 * Initialize flow control pins depending on the current flow control 1401 * mode. 1402 */ 1403 if (ISSET(t->c_cflag, CRTSCTS)) { 1404 sc->sc_rs_control_dtr = C_RS_DTR; 1405 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1406 } else if (ISSET(t->c_cflag, MDMBUF)) { 1407 sc->sc_rs_control_dtr = 0; 1408 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1409 } else { 1410 /* 1411 * If no flow control, then always set RTS. This will make 1412 * the other side happy if it mistakenly thinks we're doing 1413 * RTS/CTS flow control. 1414 */ 1415 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1416 sc->sc_chanctl_hw_flow = 0; 1417 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1418 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1419 else 1420 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1421 } 1422 1423 /* Baud rate. */ 1424 sc->sc_chanctl_comm_baud = ospeed; 1425 1426 /* Copy to tty. */ 1427 tp->t_ispeed = 0; 1428 tp->t_ospeed = t->c_ospeed; 1429 tp->t_cflag = t->c_cflag; 1430 1431 /* 1432 * Now load the channel control structure. 1433 */ 1434 1435 cz_wait_pci_doorbell(cz, "czparam"); 1436 1437 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1438 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1439 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1440 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1441 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1442 1443 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1444 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1445 1446 cz_wait_pci_doorbell(cz, "czparam"); 1447 1448 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1449 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1450 1451 cz_wait_pci_doorbell(cz, "czparam"); 1452 1453 /* 1454 * Update the tty layer's idea of the carrier bit, in case we changed 1455 * CLOCAL. We don't hang up here; we only do that by explicit 1456 * request. 1457 */ 1458 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1459 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1460 1461 return (0); 1462 } 1463 1464 /* 1465 * czttystart: 1466 * 1467 * Start or restart transmission. 1468 */ 1469 static void 1470 czttystart(struct tty *tp) 1471 { 1472 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1473 int s; 1474 1475 s = spltty(); 1476 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1477 goto out; 1478 if (!ttypull(tp)) 1479 goto out; 1480 cztty_transmit(sc, tp); 1481 out: 1482 splx(s); 1483 } 1484 1485 /* 1486 * czttystop: 1487 * 1488 * Stop output, e.g., for ^S or output flush. 1489 */ 1490 static void 1491 czttystop(struct tty *tp, int flag) 1492 { 1493 1494 /* 1495 * XXX We don't do anything here, yet. Mostly, I don't know 1496 * XXX exactly how this should be implemented on this device. 1497 * XXX We've given a big chunk of data to the MIPS already, 1498 * XXX and I don't know how we request the MIPS to stop sending 1499 * XXX the data. So, punt for now. --thorpej 1500 */ 1501 } 1502 1503 /* 1504 * cztty_diag: 1505 * 1506 * Issue a scheduled diagnostic message. 1507 */ 1508 static void 1509 cztty_diag(void *arg) 1510 { 1511 struct cztty_softc *sc = arg; 1512 struct cz_softc *cz = CZTTY_CZ(sc); 1513 u_int overflows, parity_errors, framing_errors; 1514 int s; 1515 1516 s = spltty(); 1517 1518 overflows = sc->sc_overflows; 1519 sc->sc_overflows = 0; 1520 1521 parity_errors = sc->sc_parity_errors; 1522 sc->sc_parity_errors = 0; 1523 1524 framing_errors = sc->sc_framing_errors; 1525 sc->sc_framing_errors = 0; 1526 1527 sc->sc_errors = 0; 1528 1529 splx(s); 1530 1531 log(LOG_WARNING, 1532 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1533 device_xname(&cz->cz_dev), sc->sc_channel, 1534 overflows, overflows == 1 ? "" : "s", 1535 parity_errors, 1536 framing_errors, framing_errors == 1 ? "" : "s"); 1537 } 1538 1539 const struct cdevsw cz_cdevsw = { 1540 czttyopen, czttyclose, czttyread, czttywrite, czttyioctl, 1541 czttystop, czttytty, czttypoll, nommap, ttykqfilter, D_TTY 1542 }; 1543 1544 /* 1545 * tx and rx ring buffer size macros: 1546 * 1547 * The transmitter and receiver both use ring buffers. For each one, there 1548 * is a get (consumer) and a put (producer) offset. The get value is the 1549 * next byte to be read from the ring, and the put is the next one to be 1550 * put into the ring. get == put means the ring is empty. 1551 * 1552 * For each ring, the firmware controls one of (get, put) and this driver 1553 * controls the other. For transmission, this driver updates put to point 1554 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1555 * for receive, the driver controls put, and this driver controls get. 1556 */ 1557 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1558 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1559 1560 /* 1561 * cztty_transmit() 1562 * 1563 * Look at the tty for this port and start sending. 1564 */ 1565 static int 1566 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1567 { 1568 struct cz_softc *cz = CZTTY_CZ(sc); 1569 u_int move, get, put, size, address; 1570 #ifdef HOSTRAMCODE 1571 int error, done = 0; 1572 #else 1573 int done = 0; 1574 #endif 1575 1576 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1577 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1578 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1579 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1580 1581 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1582 #ifdef HOSTRAMCODE 1583 if (0) { 1584 move = min(tp->t_outq.c_cc, move); 1585 error = q_to_b(&tp->t_outq, 0, move); 1586 if (error != move) { 1587 printf("%s: channel %d: error moving to " 1588 "transmit buf\n", device_xname(&cz->cz_dev), 1589 sc->sc_channel); 1590 move = error; 1591 } 1592 } else { 1593 #endif 1594 move = min(ndqb(&tp->t_outq, 0), move); 1595 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1596 address + put, tp->t_outq.c_cf, move); 1597 ndflush(&tp->t_outq, move); 1598 #ifdef HOSTRAMCODE 1599 } 1600 #endif 1601 1602 put = ((put + move) % size); 1603 done = 1; 1604 } 1605 if (done) { 1606 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1607 } 1608 return (done); 1609 } 1610 1611 static int 1612 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1613 { 1614 struct cz_softc *cz = CZTTY_CZ(sc); 1615 u_int get, put, size, address; 1616 int done = 0, ch; 1617 1618 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1619 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1620 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1621 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1622 1623 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1624 #ifdef HOSTRAMCODE 1625 if (hostram) { 1626 ch = ((char *)fifoaddr)[get]; 1627 } else { 1628 #endif 1629 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1630 address + get); 1631 #ifdef HOSTRAMCODE 1632 } 1633 #endif 1634 (*tp->t_linesw->l_rint)(ch, tp); 1635 get = (get + 1) % size; 1636 done = 1; 1637 } 1638 if (done) { 1639 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1640 } 1641 return (done); 1642 } 1643