1 /* $NetBSD: cz.c,v 1.17 2001/11/13 07:48:41 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only utilize RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: cz.c,v 1.17 2001/11/13 07:48:41 lukem Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/tty.h> 84 #include <sys/conf.h> 85 #include <sys/time.h> 86 #include <sys/kernel.h> 87 #include <sys/fcntl.h> 88 #include <sys/syslog.h> 89 90 #include <sys/callout.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/czreg.h> 96 97 #include <dev/pci/plx9060reg.h> 98 #include <dev/pci/plx9060var.h> 99 100 #include <dev/microcode/cyclades-z/cyzfirm.h> 101 102 #define CZ_DRIVER_VERSION 0x20000411 103 104 #define CZ_POLL_MS 20 105 106 /* These are the interrupts we always use. */ 107 #define CZ_INTERRUPTS \ 108 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 109 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 110 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 111 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 112 113 /* 114 * cztty_softc: 115 * 116 * Per-channel (TTY) state. 117 */ 118 struct cztty_softc { 119 struct cz_softc *sc_parent; 120 struct tty *sc_tty; 121 122 struct callout sc_diag_ch; 123 124 int sc_channel; /* Also used to flag unattached chan */ 125 #define CZTTY_CHANNEL_DEAD -1 126 127 bus_space_tag_t sc_chan_st; /* channel space tag */ 128 bus_space_handle_t sc_chan_sh; /* channel space handle */ 129 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 130 131 u_int sc_overflows, 132 sc_parity_errors, 133 sc_framing_errors, 134 sc_errors; 135 136 int sc_swflags; 137 138 u_int32_t sc_rs_control_dtr, 139 sc_chanctl_hw_flow, 140 sc_chanctl_comm_baud, 141 sc_chanctl_rs_control, 142 sc_chanctl_comm_data_l, 143 sc_chanctl_comm_parity; 144 }; 145 146 /* 147 * cz_softc: 148 * 149 * Per-board state. 150 */ 151 struct cz_softc { 152 struct device cz_dev; /* generic device info */ 153 struct plx9060_config cz_plx; /* PLX 9060 config info */ 154 bus_space_tag_t cz_win_st; /* window space tag */ 155 bus_space_handle_t cz_win_sh; /* window space handle */ 156 struct callout cz_callout; /* callout for polling-mode */ 157 158 void *cz_ih; /* interrupt handle */ 159 160 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 161 int cz_nchannels; /* number of channels */ 162 int cz_nopenchan; /* number of open channels */ 163 struct cztty_softc *cz_ports; /* our array of ports */ 164 165 bus_addr_t cz_fwctl; /* offset of firmware control */ 166 }; 167 168 int cz_match(struct device *, struct cfdata *, void *); 169 void cz_attach(struct device *, struct device *, void *); 170 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 171 172 struct cfattach cz_ca = { 173 sizeof(struct cz_softc), cz_match, cz_attach 174 }; 175 176 void cz_reset_board(struct cz_softc *); 177 int cz_load_firmware(struct cz_softc *); 178 179 int cz_intr(void *); 180 void cz_poll(void *); 181 int cztty_transmit(struct cztty_softc *, struct tty *); 182 int cztty_receive(struct cztty_softc *, struct tty *); 183 184 struct cztty_softc * cztty_getttysoftc(dev_t dev); 185 int cztty_findmajor(void); 186 int cztty_major; 187 int cztty_attached_ttys; 188 int cz_timeout_ticks; 189 190 cdev_decl(cztty); 191 192 void czttystart(struct tty *tp); 193 int czttyparam(struct tty *tp, struct termios *t); 194 void cztty_shutdown(struct cztty_softc *sc); 195 void cztty_modem(struct cztty_softc *sc, int onoff); 196 void cztty_break(struct cztty_softc *sc, int onoff); 197 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 198 int cztty_to_tiocm(struct cztty_softc *sc); 199 void cztty_diag(void *arg); 200 201 extern struct cfdriver cz_cd; 202 203 /* Macros to clear/set/test flags. */ 204 #define SET(t, f) (t) |= (f) 205 #define CLR(t, f) (t) &= ~(f) 206 #define ISSET(t, f) ((t) & (f)) 207 208 /* 209 * Macros to read and write the PLX. 210 */ 211 #define CZ_PLX_READ(cz, reg) \ 212 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 213 #define CZ_PLX_WRITE(cz, reg, val) \ 214 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 215 (reg), (val)) 216 217 /* 218 * Macros to read and write the FPGA. We must already be in the FPGA 219 * window for this. 220 */ 221 #define CZ_FPGA_READ(cz, reg) \ 222 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 223 #define CZ_FPGA_WRITE(cz, reg, val) \ 224 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 225 226 /* 227 * Macros to read and write the firmware control structures in board RAM. 228 */ 229 #define CZ_FWCTL_READ(cz, off) \ 230 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 231 (cz)->cz_fwctl + (off)) 232 233 #define CZ_FWCTL_WRITE(cz, off, val) \ 234 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 235 (cz)->cz_fwctl + (off), (val)) 236 237 /* 238 * Convenience macros for cztty routines. PLX window MUST be to RAM. 239 */ 240 #define CZTTY_CHAN_READ(sc, off) \ 241 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 242 243 #define CZTTY_CHAN_WRITE(sc, off, val) \ 244 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 245 (off), (val)) 246 247 #define CZTTY_BUF_READ(sc, off) \ 248 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 249 250 #define CZTTY_BUF_WRITE(sc, off, val) \ 251 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 252 (off), (val)) 253 254 /* 255 * Convenience macros. 256 */ 257 #define CZ_WIN_RAM(cz) \ 258 do { \ 259 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 260 delay(100); \ 261 } while (0) 262 263 #define CZ_WIN_FPGA(cz) \ 264 do { \ 265 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 266 delay(100); \ 267 } while (0) 268 269 /***************************************************************************** 270 * Cyclades-Z controller code starts here... 271 *****************************************************************************/ 272 273 /* 274 * cz_match: 275 * 276 * Determine if the given PCI device is a Cyclades-Z board. 277 */ 278 int 279 cz_match(struct device *parent, 280 struct cfdata *match, 281 void *aux) 282 { 283 struct pci_attach_args *pa = aux; 284 285 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 286 switch (PCI_PRODUCT(pa->pa_id)) { 287 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 288 return (1); 289 } 290 } 291 292 return (0); 293 } 294 295 /* 296 * cz_attach: 297 * 298 * A Cyclades-Z board was found; attach it. 299 */ 300 void 301 cz_attach(struct device *parent, 302 struct device *self, 303 void *aux) 304 { 305 struct cz_softc *cz = (void *) self; 306 struct pci_attach_args *pa = aux; 307 pci_intr_handle_t ih; 308 const char *intrstr = NULL; 309 struct cztty_softc *sc; 310 struct tty *tp; 311 int i; 312 313 printf(": Cyclades-Z multiport serial\n"); 314 315 cz->cz_plx.plx_pc = pa->pa_pc; 316 cz->cz_plx.plx_tag = pa->pa_tag; 317 318 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 319 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 320 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 321 printf("%s: unable to map PLX registers\n", 322 cz->cz_dev.dv_xname); 323 return; 324 } 325 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 326 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 327 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 328 printf("%s: unable to map device window\n", 329 cz->cz_dev.dv_xname); 330 return; 331 } 332 333 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 334 cz->cz_nopenchan = 0; 335 336 /* 337 * Make sure that the board is completely stopped. 338 */ 339 CZ_WIN_FPGA(cz); 340 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 341 342 /* 343 * Load the board's firmware. 344 */ 345 if (cz_load_firmware(cz) != 0) 346 return; 347 348 /* 349 * Now that we're ready to roll, map and establish the interrupt 350 * handler. 351 */ 352 if (pci_intr_map(pa, &ih) != 0) { 353 /* 354 * The common case is for Cyclades-Z boards to run 355 * in polling mode, and thus not have an interrupt 356 * mapped for them. Don't bother reporting that 357 * the interrupt is not mappable, since this isn't 358 * really an error. 359 */ 360 cz->cz_ih = NULL; 361 goto polling_mode; 362 } else { 363 intrstr = pci_intr_string(pa->pa_pc, ih); 364 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 365 cz_intr, cz); 366 } 367 if (cz->cz_ih == NULL) { 368 printf("%s: unable to establish interrupt", 369 cz->cz_dev.dv_xname); 370 if (intrstr != NULL) 371 printf(" at %s", intrstr); 372 printf("\n"); 373 /* We will fall-back on polling mode. */ 374 } else 375 printf("%s: interrupting at %s\n", 376 cz->cz_dev.dv_xname, intrstr); 377 378 polling_mode: 379 if (cz->cz_ih == NULL) { 380 callout_init(&cz->cz_callout); 381 if (cz_timeout_ticks == 0) 382 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 383 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 384 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 385 cz_timeout_ticks == 1 ? "" : "s"); 386 } 387 388 if (cztty_major == 0) 389 cztty_major = cztty_findmajor(); 390 /* 391 * Allocate sufficient pointers for the children and 392 * attach them. Set all ports to a reasonable initial 393 * configuration while we're at it: 394 * 395 * disabled 396 * 8N1 397 * default baud rate 398 * hardware flow control. 399 */ 400 CZ_WIN_RAM(cz); 401 402 if (cz->cz_nchannels == 0) { 403 /* No channels? No more work to do! */ 404 return; 405 } 406 407 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 408 M_DEVBUF, M_WAITOK); 409 cztty_attached_ttys += cz->cz_nchannels; 410 memset(cz->cz_ports, 0, 411 sizeof(struct cztty_softc) * cz->cz_nchannels); 412 413 for (i = 0; i < cz->cz_nchannels; i++) { 414 sc = &cz->cz_ports[i]; 415 416 sc->sc_channel = i; 417 sc->sc_chan_st = cz->cz_win_st; 418 sc->sc_parent = cz; 419 420 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 421 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 422 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 423 printf("%s: unable to subregion channel %d control\n", 424 cz->cz_dev.dv_xname, i); 425 sc->sc_channel = CZTTY_CHANNEL_DEAD; 426 continue; 427 } 428 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 429 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 430 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 431 printf("%s: unable to subregion channel %d buffer\n", 432 cz->cz_dev.dv_xname, i); 433 sc->sc_channel = CZTTY_CHANNEL_DEAD; 434 continue; 435 } 436 437 callout_init(&sc->sc_diag_ch); 438 439 tp = ttymalloc(); 440 tp->t_dev = makedev(cztty_major, 441 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 442 tp->t_oproc = czttystart; 443 tp->t_param = czttyparam; 444 tty_attach(tp); 445 446 sc->sc_tty = tp; 447 448 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 449 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 450 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 451 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 452 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 453 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 454 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 455 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 456 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 457 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 458 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 459 } 460 } 461 462 /* 463 * cz_reset_board: 464 * 465 * Reset the board via the PLX. 466 */ 467 void 468 cz_reset_board(struct cz_softc *cz) 469 { 470 u_int32_t reg; 471 472 reg = CZ_PLX_READ(cz, PLX_CONTROL); 473 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 474 delay(1000); 475 476 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 477 delay(1000); 478 479 /* Now reload the PLX from its EEPROM. */ 480 reg = CZ_PLX_READ(cz, PLX_CONTROL); 481 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 482 delay(1000); 483 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 484 } 485 486 /* 487 * cz_load_firmware: 488 * 489 * Load the ZFIRM firmware into the board's RAM and start it 490 * running. 491 */ 492 int 493 cz_load_firmware(struct cz_softc *cz) 494 { 495 struct zfirm_header *zfh; 496 struct zfirm_config *zfc; 497 struct zfirm_block *zfb, *zblocks; 498 const u_int8_t *cp; 499 const char *board; 500 u_int32_t fid; 501 int i, j, nconfigs, nblocks, nbytes; 502 503 zfh = (struct zfirm_header *) cycladesz_firmware; 504 505 /* Find the config header. */ 506 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 507 printf("%s: bad ZFIRM config offset: 0x%x\n", 508 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 509 return (EIO); 510 } 511 zfc = (struct zfirm_config *)(cycladesz_firmware + 512 le32toh(zfh->zfh_configoff)); 513 nconfigs = le32toh(zfh->zfh_nconfig); 514 515 /* Locate the correct configuration for our board. */ 516 for (i = 0; i < nconfigs; i++, zfc++) { 517 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 518 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 519 break; 520 } 521 if (i == nconfigs) { 522 printf("%s: unable to locate config header\n", 523 cz->cz_dev.dv_xname); 524 return (EIO); 525 } 526 527 nblocks = le32toh(zfc->zfc_nblocks); 528 zblocks = (struct zfirm_block *)(cycladesz_firmware + 529 le32toh(zfh->zfh_blockoff)); 530 531 /* 532 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 533 * necessary. 534 */ 535 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 536 #if 0 537 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 538 #endif 539 ) { 540 #ifdef CZ_DEBUG 541 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 542 #endif 543 CZ_WIN_FPGA(cz); 544 for (i = 0; i < nblocks; i++) { 545 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 546 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 547 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 548 nbytes = le32toh(zfb->zfb_size); 549 cp = &cycladesz_firmware[ 550 le32toh(zfb->zfb_fileoff)]; 551 for (j = 0; j < nbytes; j++, cp++) { 552 bus_space_write_1(cz->cz_win_st, 553 cz->cz_win_sh, 0, *cp); 554 /* FPGA needs 30-100us to settle. */ 555 delay(10); 556 } 557 } 558 } 559 #ifdef CZ_DEBUG 560 printf("done\n"); 561 #endif 562 } 563 564 /* Now load the firmware. */ 565 CZ_WIN_RAM(cz); 566 567 for (i = 0; i < nblocks; i++) { 568 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 569 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 570 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 571 const u_int32_t *lp; 572 u_int32_t ro = le32toh(zfb->zfb_ramoff); 573 nbytes = le32toh(zfb->zfb_size); 574 lp = (const u_int32_t *) 575 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 576 for (j = 0; j < nbytes; j += 4, lp++) { 577 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 578 ro + j, le32toh(*lp)); 579 delay(10); 580 } 581 } 582 } 583 584 /* Now restart the MIPS. */ 585 CZ_WIN_FPGA(cz); 586 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 587 588 /* Wait for the MIPS to start, then report the results. */ 589 CZ_WIN_RAM(cz); 590 591 #ifdef CZ_DEBUG 592 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 593 #endif 594 for (i = 0; i < 100; i++) { 595 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 596 ZFIRM_SIG_OFF); 597 if (fid == ZFIRM_SIG) { 598 /* MIPS has booted. */ 599 break; 600 } else if (fid == ZFIRM_HLT) { 601 /* 602 * The MIPS has halted, usually due to a power 603 * shortage on the expansion module. 604 */ 605 printf("%s: MIPS halted; possible power supply " 606 "problem\n", cz->cz_dev.dv_xname); 607 return (EIO); 608 } else { 609 #ifdef CZ_DEBUG 610 if ((i % 8) == 0) 611 printf("."); 612 #endif 613 delay(250000); 614 } 615 } 616 #ifdef CZ_DEBUG 617 printf("\n"); 618 #endif 619 if (i == 100) { 620 CZ_WIN_FPGA(cz); 621 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 622 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 623 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 624 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 625 CZ_FPGA_READ(cz, FPGA_VERSION)); 626 return (EIO); 627 } 628 629 /* 630 * Locate the firmware control structures. 631 */ 632 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 633 ZFIRM_CTRLADDR_OFF); 634 #ifdef CZ_DEBUG 635 printf("%s: FWCTL structure at offset 0x%08lx\n", 636 cz->cz_dev.dv_xname, cz->cz_fwctl); 637 #endif 638 639 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 640 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 641 642 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 643 644 switch (cz->cz_mailbox0) { 645 case MAILBOX0_8Zo_V1: 646 board = "Cyclades-8Zo ver. 1"; 647 break; 648 649 case MAILBOX0_8Zo_V2: 650 board = "Cyclades-8Zo ver. 2"; 651 break; 652 653 case MAILBOX0_Ze_V1: 654 board = "Cyclades-Ze"; 655 break; 656 657 default: 658 board = "unknown Cyclades Z-series"; 659 break; 660 } 661 662 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 663 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 664 if (cz->cz_nchannels == 0) 665 printf("no channels attached, "); 666 else 667 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 668 cz->cz_nchannels, cztty_attached_ttys, 669 cztty_attached_ttys + (cz->cz_nchannels - 1)); 670 printf("firmware %x.%x.%x\n", 671 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 672 673 return (0); 674 } 675 676 /* 677 * cz_poll: 678 * 679 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 680 * ms. 681 */ 682 void 683 cz_poll(void *arg) 684 { 685 int s = spltty(); 686 struct cz_softc *cz = arg; 687 688 cz_intr(cz); 689 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 690 691 splx(s); 692 } 693 694 /* 695 * cz_intr: 696 * 697 * Interrupt service routine. 698 * 699 * We either are receiving an interrupt directly from the board, or we are 700 * in polling mode and it's time to poll. 701 */ 702 int 703 cz_intr(void *arg) 704 { 705 int rval = 0; 706 u_int command, channel, param; 707 struct cz_softc *cz = arg; 708 struct cztty_softc *sc; 709 struct tty *tp; 710 711 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 712 rval = 1; 713 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 714 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 715 716 /* now clear this interrupt, posslibly enabling another */ 717 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 718 719 if (cz->cz_ports == NULL) { 720 #ifdef CZ_DEBUG 721 printf("%s: interrupt on channel %d, but no channels\n", 722 cz->cz_dev.dv_xname, channel); 723 #endif 724 continue; 725 } 726 727 sc = &cz->cz_ports[channel]; 728 729 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 730 break; 731 732 tp = sc->sc_tty; 733 734 switch (command) { 735 case C_CM_TXFEMPTY: /* transmit cases */ 736 case C_CM_TXBEMPTY: 737 case C_CM_TXLOWWM: 738 case C_CM_INTBACK: 739 if (!ISSET(tp->t_state, TS_ISOPEN)) { 740 #ifdef CZ_DEBUG 741 printf("%s: tx intr on closed channel %d\n", 742 cz->cz_dev.dv_xname, channel); 743 #endif 744 break; 745 } 746 747 if (cztty_transmit(sc, tp)) { 748 /* 749 * Do wakeup stuff here. 750 */ 751 ttwakeup(tp); 752 wakeup(tp); 753 } 754 break; 755 756 case C_CM_RXNNDT: /* receive cases */ 757 case C_CM_RXHIWM: 758 case C_CM_INTBACK2: /* from restart ?? */ 759 #if 0 760 case C_CM_ICHAR: 761 #endif 762 if (!ISSET(tp->t_state, TS_ISOPEN)) { 763 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 764 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 765 break; 766 } 767 768 if (cztty_receive(sc, tp)) { 769 /* 770 * Do wakeup stuff here. 771 */ 772 ttwakeup(tp); 773 wakeup(tp); 774 } 775 break; 776 777 case C_CM_MDCD: 778 if (!ISSET(tp->t_state, TS_ISOPEN)) 779 break; 780 781 (void) (*tp->t_linesw->l_modem)(tp, 782 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 783 CHNCTL_RS_STATUS))); 784 break; 785 786 case C_CM_MDSR: 787 case C_CM_MRI: 788 case C_CM_MCTS: 789 case C_CM_MRTS: 790 break; 791 792 case C_CM_IOCTLW: 793 break; 794 795 case C_CM_PR_ERROR: 796 sc->sc_parity_errors++; 797 goto error_common; 798 799 case C_CM_FR_ERROR: 800 sc->sc_framing_errors++; 801 goto error_common; 802 803 case C_CM_OVR_ERROR: 804 sc->sc_overflows++; 805 error_common: 806 if (sc->sc_errors++ == 0) 807 callout_reset(&sc->sc_diag_ch, 60 * hz, 808 cztty_diag, sc); 809 break; 810 811 case C_CM_RXBRK: 812 if (!ISSET(tp->t_state, TS_ISOPEN)) 813 break; 814 815 /* 816 * A break is a \000 character with TTY_FE error 817 * flags set. So TTY_FE by itself works. 818 */ 819 (*tp->t_linesw->l_rint)(TTY_FE, tp); 820 ttwakeup(tp); 821 wakeup(tp); 822 break; 823 824 default: 825 #ifdef CZ_DEBUG 826 printf("%s: channel %d: Unknown interrupt 0x%x\n", 827 cz->cz_dev.dv_xname, sc->sc_channel, command); 828 #endif 829 break; 830 } 831 } 832 833 return (rval); 834 } 835 836 /* 837 * cz_wait_pci_doorbell: 838 * 839 * Wait for the pci doorbell to be clear - wait for pending 840 * activity to drain. 841 */ 842 int 843 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 844 { 845 int error; 846 847 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 848 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 849 if ((error != 0) && (error != EWOULDBLOCK)) 850 return (error); 851 } 852 return (0); 853 } 854 855 /***************************************************************************** 856 * Cyclades-Z TTY code starts here... 857 *****************************************************************************/ 858 859 #define CZTTYDIALOUT_MASK 0x80000 860 861 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 862 #define CZTTY_CZ(sc) ((sc)->sc_parent) 863 864 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 865 866 struct cztty_softc * 867 cztty_getttysoftc(dev_t dev) 868 { 869 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 870 struct cz_softc *cz; 871 872 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 873 k = j; 874 cz = device_lookup(&cz_cd, i); 875 if (cz == NULL) 876 continue; 877 if (cz->cz_ports == NULL) 878 continue; 879 j += cz->cz_nchannels; 880 if (j > u) 881 break; 882 } 883 884 if (i >= cz_cd.cd_ndevs) 885 return (NULL); 886 else 887 return (&cz->cz_ports[u - k]); 888 } 889 890 int 891 cztty_findmajor(void) 892 { 893 int maj; 894 895 for (maj = 0; maj < nchrdev; maj++) { 896 if (cdevsw[maj].d_open == czttyopen) 897 break; 898 } 899 900 return (maj == nchrdev) ? 0 : maj; 901 } 902 903 /* 904 * czttytty: 905 * 906 * Return a pointer to our tty. 907 */ 908 struct tty * 909 czttytty(dev_t dev) 910 { 911 struct cztty_softc *sc = CZTTY_SOFTC(dev); 912 913 #ifdef DIAGNOSTIC 914 if (sc == NULL) 915 panic("czttytty"); 916 #endif 917 918 return (sc->sc_tty); 919 } 920 921 /* 922 * cztty_shutdown: 923 * 924 * Shut down a port. 925 */ 926 void 927 cztty_shutdown(struct cztty_softc *sc) 928 { 929 struct cz_softc *cz = CZTTY_CZ(sc); 930 struct tty *tp = sc->sc_tty; 931 int s; 932 933 s = spltty(); 934 935 /* Clear any break condition set with TIOCSBRK. */ 936 cztty_break(sc, 0); 937 938 /* 939 * Hang up if necessary. Wait a bit, so the other side has time to 940 * notice even if we immediately open the port again. 941 */ 942 if (ISSET(tp->t_cflag, HUPCL)) { 943 cztty_modem(sc, 0); 944 (void) tsleep(tp, TTIPRI, ttclos, hz); 945 } 946 947 /* Disable the channel. */ 948 cz_wait_pci_doorbell(cz, "czdis"); 949 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 950 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 951 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 952 953 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 954 #ifdef CZ_DEBUG 955 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 956 #endif 957 callout_stop(&cz->cz_callout); 958 } 959 960 splx(s); 961 } 962 963 /* 964 * czttyopen: 965 * 966 * Open a Cyclades-Z serial port. 967 */ 968 int 969 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 970 { 971 struct cztty_softc *sc = CZTTY_SOFTC(dev); 972 struct cz_softc *cz; 973 struct tty *tp; 974 int s, error; 975 976 if (sc == NULL) 977 return (ENXIO); 978 979 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 980 return (ENXIO); 981 982 cz = CZTTY_CZ(sc); 983 tp = sc->sc_tty; 984 985 if (ISSET(tp->t_state, TS_ISOPEN) && 986 ISSET(tp->t_state, TS_XCLUDE) && 987 p->p_ucred->cr_uid != 0) 988 return (EBUSY); 989 990 s = spltty(); 991 992 /* 993 * Do the following iff this is a first open. 994 */ 995 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 996 struct termios t; 997 998 tp->t_dev = dev; 999 1000 /* If we're turning things on, enable interrupts */ 1001 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 1002 #ifdef CZ_DEBUG 1003 printf("%s: Enabling polling.\n", 1004 cz->cz_dev.dv_xname); 1005 #endif 1006 callout_reset(&cz->cz_callout, cz_timeout_ticks, 1007 cz_poll, cz); 1008 } 1009 1010 /* 1011 * Enable the channel. Don't actually ring the 1012 * doorbell here; czttyparam() will do it for us. 1013 */ 1014 cz_wait_pci_doorbell(cz, "czopen"); 1015 1016 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1017 1018 /* 1019 * Initialize the termios status to the defaults. Add in the 1020 * sticky bits from TIOCSFLAGS. 1021 */ 1022 t.c_ispeed = 0; 1023 t.c_ospeed = TTYDEF_SPEED; 1024 t.c_cflag = TTYDEF_CFLAG; 1025 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1026 SET(t.c_cflag, CLOCAL); 1027 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1028 SET(t.c_cflag, CRTSCTS); 1029 1030 /* 1031 * Reset the input and output rings. Do this before 1032 * we call czttyparam(), as that function enables 1033 * the channel. 1034 */ 1035 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1036 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1037 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1038 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1039 1040 /* Make sure czttyparam() will see changes. */ 1041 tp->t_ospeed = 0; 1042 (void) czttyparam(tp, &t); 1043 tp->t_iflag = TTYDEF_IFLAG; 1044 tp->t_oflag = TTYDEF_OFLAG; 1045 tp->t_lflag = TTYDEF_LFLAG; 1046 ttychars(tp); 1047 ttsetwater(tp); 1048 1049 /* 1050 * Turn on DTR. We must always do this, even if carrier is not 1051 * present, because otherwise we'd have to use TIOCSDTR 1052 * immediately after setting CLOCAL, which applications do not 1053 * expect. We always assert DTR while the device is open 1054 * unless explicitly requested to deassert it. 1055 */ 1056 cztty_modem(sc, 1); 1057 } 1058 1059 splx(s); 1060 1061 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1062 if (error) 1063 goto bad; 1064 1065 error = (*tp->t_linesw->l_open)(dev, tp); 1066 if (error) 1067 goto bad; 1068 1069 return (0); 1070 1071 bad: 1072 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1073 /* 1074 * We failed to open the device, and nobody else had it opened. 1075 * Clean up the state as appropriate. 1076 */ 1077 cztty_shutdown(sc); 1078 } 1079 1080 return (error); 1081 } 1082 1083 /* 1084 * czttyclose: 1085 * 1086 * Close a Cyclades-Z serial port. 1087 */ 1088 int 1089 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1090 { 1091 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1092 struct tty *tp = sc->sc_tty; 1093 1094 /* XXX This is for cons.c. */ 1095 if (!ISSET(tp->t_state, TS_ISOPEN)) 1096 return (0); 1097 1098 (*tp->t_linesw->l_close)(tp, flags); 1099 ttyclose(tp); 1100 1101 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1102 /* 1103 * Although we got a last close, the device may still be in 1104 * use; e.g. if this was the dialout node, and there are still 1105 * processes waiting for carrier on the non-dialout node. 1106 */ 1107 cztty_shutdown(sc); 1108 } 1109 1110 return (0); 1111 } 1112 1113 /* 1114 * czttyread: 1115 * 1116 * Read from a Cyclades-Z serial port. 1117 */ 1118 int 1119 czttyread(dev_t dev, struct uio *uio, int flags) 1120 { 1121 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1122 struct tty *tp = sc->sc_tty; 1123 1124 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1125 } 1126 1127 /* 1128 * czttywrite: 1129 * 1130 * Write to a Cyclades-Z serial port. 1131 */ 1132 int 1133 czttywrite(dev_t dev, struct uio *uio, int flags) 1134 { 1135 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1136 struct tty *tp = sc->sc_tty; 1137 1138 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1139 } 1140 1141 /* 1142 * czttypoll: 1143 * 1144 * Poll a Cyclades-Z serial port. 1145 */ 1146 int 1147 czttypoll(dev, events, p) 1148 dev_t dev; 1149 int events; 1150 struct proc *p; 1151 { 1152 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1153 struct tty *tp = sc->sc_tty; 1154 1155 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1156 } 1157 1158 /* 1159 * czttyioctl: 1160 * 1161 * Perform a control operation on a Cyclades-Z serial port. 1162 */ 1163 int 1164 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1165 { 1166 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1167 struct tty *tp = sc->sc_tty; 1168 int s, error; 1169 1170 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 1171 if (error >= 0) 1172 return (error); 1173 1174 error = ttioctl(tp, cmd, data, flag, p); 1175 if (error >= 0) 1176 return (error); 1177 1178 error = 0; 1179 1180 s = spltty(); 1181 1182 switch (cmd) { 1183 case TIOCSBRK: 1184 cztty_break(sc, 1); 1185 break; 1186 1187 case TIOCCBRK: 1188 cztty_break(sc, 0); 1189 break; 1190 1191 case TIOCGFLAGS: 1192 *(int *)data = sc->sc_swflags; 1193 break; 1194 1195 case TIOCSFLAGS: 1196 error = suser(p->p_ucred, &p->p_acflag); 1197 if (error) 1198 break; 1199 sc->sc_swflags = *(int *)data; 1200 break; 1201 1202 case TIOCSDTR: 1203 cztty_modem(sc, 1); 1204 break; 1205 1206 case TIOCCDTR: 1207 cztty_modem(sc, 0); 1208 break; 1209 1210 case TIOCMSET: 1211 case TIOCMBIS: 1212 case TIOCMBIC: 1213 tiocm_to_cztty(sc, cmd, *(int *)data); 1214 break; 1215 1216 case TIOCMGET: 1217 *(int *)data = cztty_to_tiocm(sc); 1218 break; 1219 1220 default: 1221 error = ENOTTY; 1222 break; 1223 } 1224 1225 splx(s); 1226 1227 return (error); 1228 } 1229 1230 /* 1231 * cztty_break: 1232 * 1233 * Set or clear BREAK on a port. 1234 */ 1235 void 1236 cztty_break(struct cztty_softc *sc, int onoff) 1237 { 1238 struct cz_softc *cz = CZTTY_CZ(sc); 1239 1240 cz_wait_pci_doorbell(cz, "czbreak"); 1241 1242 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1243 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1244 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1245 } 1246 1247 /* 1248 * cztty_modem: 1249 * 1250 * Set or clear DTR on a port. 1251 */ 1252 void 1253 cztty_modem(struct cztty_softc *sc, int onoff) 1254 { 1255 struct cz_softc *cz = CZTTY_CZ(sc); 1256 1257 if (sc->sc_rs_control_dtr == 0) 1258 return; 1259 1260 cz_wait_pci_doorbell(cz, "czmod"); 1261 1262 if (onoff) 1263 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1264 else 1265 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1266 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1267 1268 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1269 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1270 } 1271 1272 /* 1273 * tiocm_to_cztty: 1274 * 1275 * Process TIOCM* ioctls. 1276 */ 1277 void 1278 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1279 { 1280 struct cz_softc *cz = CZTTY_CZ(sc); 1281 u_int32_t czttybits; 1282 1283 czttybits = 0; 1284 if (ISSET(ttybits, TIOCM_DTR)) 1285 SET(czttybits, C_RS_DTR); 1286 if (ISSET(ttybits, TIOCM_RTS)) 1287 SET(czttybits, C_RS_RTS); 1288 1289 cz_wait_pci_doorbell(cz, "cztiocm"); 1290 1291 switch (how) { 1292 case TIOCMBIC: 1293 CLR(sc->sc_chanctl_rs_control, czttybits); 1294 break; 1295 1296 case TIOCMBIS: 1297 SET(sc->sc_chanctl_rs_control, czttybits); 1298 break; 1299 1300 case TIOCMSET: 1301 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1302 SET(sc->sc_chanctl_rs_control, czttybits); 1303 break; 1304 } 1305 1306 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1307 1308 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1309 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1310 } 1311 1312 /* 1313 * cztty_to_tiocm: 1314 * 1315 * Process the TIOCMGET ioctl. 1316 */ 1317 int 1318 cztty_to_tiocm(struct cztty_softc *sc) 1319 { 1320 struct cz_softc *cz = CZTTY_CZ(sc); 1321 u_int32_t rs_status, op_mode; 1322 int ttybits = 0; 1323 1324 cz_wait_pci_doorbell(cz, "cztty"); 1325 1326 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1327 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1328 1329 if (ISSET(rs_status, C_RS_RTS)) 1330 SET(ttybits, TIOCM_RTS); 1331 if (ISSET(rs_status, C_RS_CTS)) 1332 SET(ttybits, TIOCM_CTS); 1333 if (ISSET(rs_status, C_RS_DCD)) 1334 SET(ttybits, TIOCM_CAR); 1335 if (ISSET(rs_status, C_RS_DTR)) 1336 SET(ttybits, TIOCM_DTR); 1337 if (ISSET(rs_status, C_RS_RI)) 1338 SET(ttybits, TIOCM_RNG); 1339 if (ISSET(rs_status, C_RS_DSR)) 1340 SET(ttybits, TIOCM_DSR); 1341 1342 if (ISSET(op_mode, C_CH_ENABLE)) 1343 SET(ttybits, TIOCM_LE); 1344 1345 return (ttybits); 1346 } 1347 1348 /* 1349 * czttyparam: 1350 * 1351 * Set Cyclades-Z serial port parameters from termios. 1352 * 1353 * XXX Should just copy the whole termios after making 1354 * XXX sure all the changes could be done. 1355 */ 1356 int 1357 czttyparam(struct tty *tp, struct termios *t) 1358 { 1359 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1360 struct cz_softc *cz = CZTTY_CZ(sc); 1361 u_int32_t rs_status; 1362 int ospeed, cflag; 1363 1364 ospeed = t->c_ospeed; 1365 cflag = t->c_cflag; 1366 1367 /* Check requested parameters. */ 1368 if (ospeed < 0) 1369 return (EINVAL); 1370 if (t->c_ispeed && t->c_ispeed != ospeed) 1371 return (EINVAL); 1372 1373 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1374 SET(cflag, CLOCAL); 1375 CLR(cflag, HUPCL); 1376 } 1377 1378 /* 1379 * If there were no changes, don't do anything. This avoids dropping 1380 * input and improves performance when all we did was frob things like 1381 * VMIN and VTIME. 1382 */ 1383 if (tp->t_ospeed == ospeed && 1384 tp->t_cflag == cflag) 1385 return (0); 1386 1387 /* Data bits. */ 1388 sc->sc_chanctl_comm_data_l = 0; 1389 switch (t->c_cflag & CSIZE) { 1390 case CS5: 1391 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1392 break; 1393 1394 case CS6: 1395 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1396 break; 1397 1398 case CS7: 1399 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1400 break; 1401 1402 case CS8: 1403 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1404 break; 1405 } 1406 1407 /* Stop bits. */ 1408 if (t->c_cflag & CSTOPB) { 1409 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1410 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1411 else 1412 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1413 } else 1414 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1415 1416 /* Parity. */ 1417 if (t->c_cflag & PARENB) { 1418 if (t->c_cflag & PARODD) 1419 sc->sc_chanctl_comm_parity = C_PR_ODD; 1420 else 1421 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1422 } else 1423 sc->sc_chanctl_comm_parity = C_PR_NONE; 1424 1425 /* 1426 * Initialize flow control pins depending on the current flow control 1427 * mode. 1428 */ 1429 if (ISSET(t->c_cflag, CRTSCTS)) { 1430 sc->sc_rs_control_dtr = C_RS_DTR; 1431 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1432 } else if (ISSET(t->c_cflag, MDMBUF)) { 1433 sc->sc_rs_control_dtr = 0; 1434 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1435 } else { 1436 /* 1437 * If no flow control, then always set RTS. This will make 1438 * the other side happy if it mistakenly thinks we're doing 1439 * RTS/CTS flow control. 1440 */ 1441 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1442 sc->sc_chanctl_hw_flow = 0; 1443 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1444 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1445 else 1446 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1447 } 1448 1449 /* Baud rate. */ 1450 sc->sc_chanctl_comm_baud = ospeed; 1451 1452 /* Copy to tty. */ 1453 tp->t_ispeed = 0; 1454 tp->t_ospeed = t->c_ospeed; 1455 tp->t_cflag = t->c_cflag; 1456 1457 /* 1458 * Now load the channel control structure. 1459 */ 1460 1461 cz_wait_pci_doorbell(cz, "czparam"); 1462 1463 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1464 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1465 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1466 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1467 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1468 1469 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1470 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1471 1472 cz_wait_pci_doorbell(cz, "czparam"); 1473 1474 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1475 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1476 1477 cz_wait_pci_doorbell(cz, "czparam"); 1478 1479 /* 1480 * Update the tty layer's idea of the carrier bit, in case we changed 1481 * CLOCAL. We don't hang up here; we only do that by explicit 1482 * request. 1483 */ 1484 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1485 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1486 1487 return (0); 1488 } 1489 1490 /* 1491 * czttystart: 1492 * 1493 * Start or restart transmission. 1494 */ 1495 void 1496 czttystart(struct tty *tp) 1497 { 1498 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1499 int s; 1500 1501 s = spltty(); 1502 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1503 goto out; 1504 1505 if (tp->t_outq.c_cc <= tp->t_lowat) { 1506 if (ISSET(tp->t_state, TS_ASLEEP)) { 1507 CLR(tp->t_state, TS_ASLEEP); 1508 wakeup(&tp->t_outq); 1509 } 1510 selwakeup(&tp->t_wsel); 1511 if (tp->t_outq.c_cc == 0) 1512 goto out; 1513 } 1514 1515 cztty_transmit(sc, tp); 1516 out: 1517 splx(s); 1518 } 1519 1520 /* 1521 * czttystop: 1522 * 1523 * Stop output, e.g., for ^S or output flush. 1524 */ 1525 void 1526 czttystop(struct tty *tp, int flag) 1527 { 1528 1529 /* 1530 * XXX We don't do anything here, yet. Mostly, I don't know 1531 * XXX exactly how this should be implemented on this device. 1532 * XXX We've given a big chunk of data to the MIPS already, 1533 * XXX and I don't know how we request the MIPS to stop sending 1534 * XXX the data. So, punt for now. --thorpej 1535 */ 1536 } 1537 1538 /* 1539 * cztty_diag: 1540 * 1541 * Issue a scheduled diagnostic message. 1542 */ 1543 void 1544 cztty_diag(void *arg) 1545 { 1546 struct cztty_softc *sc = arg; 1547 struct cz_softc *cz = CZTTY_CZ(sc); 1548 u_int overflows, parity_errors, framing_errors; 1549 int s; 1550 1551 s = spltty(); 1552 1553 overflows = sc->sc_overflows; 1554 sc->sc_overflows = 0; 1555 1556 parity_errors = sc->sc_parity_errors; 1557 sc->sc_parity_errors = 0; 1558 1559 framing_errors = sc->sc_framing_errors; 1560 sc->sc_framing_errors = 0; 1561 1562 sc->sc_errors = 0; 1563 1564 splx(s); 1565 1566 log(LOG_WARNING, 1567 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1568 cz->cz_dev.dv_xname, sc->sc_channel, 1569 overflows, overflows == 1 ? "" : "s", 1570 parity_errors, 1571 framing_errors, framing_errors == 1 ? "" : "s"); 1572 } 1573 1574 /* 1575 * tx and rx ring buffer size macros: 1576 * 1577 * The transmitter and receiver both use ring buffers. For each one, there 1578 * is a get (consumer) and a put (producer) offset. The get value is the 1579 * next byte to be read from the ring, and the put is the next one to be 1580 * put into the ring. get == put means the ring is empty. 1581 * 1582 * For each ring, the firmware controls one of (get, put) and this driver 1583 * controls the other. For transmission, this driver updates put to point 1584 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1585 * for receive, the driver controls put, and this driver controls get. 1586 */ 1587 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1588 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1589 1590 /* 1591 * cztty_transmit() 1592 * 1593 * Look at the tty for this port and start sending. 1594 */ 1595 int 1596 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1597 { 1598 struct cz_softc *cz = CZTTY_CZ(sc); 1599 u_int move, get, put, size, address; 1600 #ifdef HOSTRAMCODE 1601 int error, done = 0; 1602 #else 1603 int done = 0; 1604 #endif 1605 1606 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1607 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1608 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1609 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1610 1611 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1612 #ifdef HOSTRAMCODE 1613 if (0) { 1614 move = min(tp->t_outq.c_cc, move); 1615 error = q_to_b(&tp->t_outq, 0, move); 1616 if (error != move) { 1617 printf("%s: channel %d: error moving to " 1618 "transmit buf\n", cz->cz_dev.dv_xname, 1619 sc->sc_channel); 1620 move = error; 1621 } 1622 } else { 1623 #endif 1624 move = min(ndqb(&tp->t_outq, 0), move); 1625 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1626 address + put, tp->t_outq.c_cf, move); 1627 ndflush(&tp->t_outq, move); 1628 #ifdef HOSTRAMCODE 1629 } 1630 #endif 1631 1632 put = ((put + move) % size); 1633 done = 1; 1634 } 1635 if (done) { 1636 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1637 } 1638 return (done); 1639 } 1640 1641 int 1642 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1643 { 1644 struct cz_softc *cz = CZTTY_CZ(sc); 1645 u_int get, put, size, address; 1646 int done = 0, ch; 1647 1648 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1649 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1650 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1651 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1652 1653 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1654 #ifdef HOSTRAMCODE 1655 if (hostram) 1656 ch = ((char *)fifoaddr)[get]; 1657 } else { 1658 #endif 1659 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1660 address + get); 1661 #ifdef HOSTRAMCODE 1662 } 1663 #endif 1664 (*tp->t_linesw->l_rint)(ch, tp); 1665 get = (get + 1) % size; 1666 done = 1; 1667 } 1668 if (done) { 1669 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1670 } 1671 return (done); 1672 } 1673