1 /* $NetBSD: cz.c,v 1.47 2007/11/19 18:51:49 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only use RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: cz.c,v 1.47 2007/11/19 18:51:49 ad Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/tty.h> 84 #include <sys/conf.h> 85 #include <sys/time.h> 86 #include <sys/kernel.h> 87 #include <sys/fcntl.h> 88 #include <sys/syslog.h> 89 #include <sys/kauth.h> 90 91 #include <sys/callout.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/czreg.h> 97 98 #include <dev/pci/plx9060reg.h> 99 #include <dev/pci/plx9060var.h> 100 101 #include <dev/microcode/cyclades-z/cyzfirm.h> 102 103 #define CZ_DRIVER_VERSION 0x20000411 104 105 #define CZ_POLL_MS 20 106 107 /* These are the interrupts we always use. */ 108 #define CZ_INTERRUPTS \ 109 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 110 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 111 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 112 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 113 114 /* 115 * cztty_softc: 116 * 117 * Per-channel (TTY) state. 118 */ 119 struct cztty_softc { 120 struct cz_softc *sc_parent; 121 struct tty *sc_tty; 122 123 callout_t sc_diag_ch; 124 125 int sc_channel; /* Also used to flag unattached chan */ 126 #define CZTTY_CHANNEL_DEAD -1 127 128 bus_space_tag_t sc_chan_st; /* channel space tag */ 129 bus_space_handle_t sc_chan_sh; /* channel space handle */ 130 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 131 132 u_int sc_overflows, 133 sc_parity_errors, 134 sc_framing_errors, 135 sc_errors; 136 137 int sc_swflags; 138 139 u_int32_t sc_rs_control_dtr, 140 sc_chanctl_hw_flow, 141 sc_chanctl_comm_baud, 142 sc_chanctl_rs_control, 143 sc_chanctl_comm_data_l, 144 sc_chanctl_comm_parity; 145 }; 146 147 /* 148 * cz_softc: 149 * 150 * Per-board state. 151 */ 152 struct cz_softc { 153 struct device cz_dev; /* generic device info */ 154 struct plx9060_config cz_plx; /* PLX 9060 config info */ 155 bus_space_tag_t cz_win_st; /* window space tag */ 156 bus_space_handle_t cz_win_sh; /* window space handle */ 157 callout_t cz_callout; /* callout for polling-mode */ 158 159 void *cz_ih; /* interrupt handle */ 160 161 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 162 int cz_nchannels; /* number of channels */ 163 int cz_nopenchan; /* number of open channels */ 164 struct cztty_softc *cz_ports; /* our array of ports */ 165 166 bus_addr_t cz_fwctl; /* offset of firmware control */ 167 }; 168 169 static int cz_wait_pci_doorbell(struct cz_softc *, const char *); 170 171 static int cz_load_firmware(struct cz_softc *); 172 173 static int cz_intr(void *); 174 static void cz_poll(void *); 175 static int cztty_transmit(struct cztty_softc *, struct tty *); 176 static int cztty_receive(struct cztty_softc *, struct tty *); 177 178 static struct cztty_softc *cztty_getttysoftc(dev_t dev); 179 static int cztty_attached_ttys; 180 static int cz_timeout_ticks; 181 182 static void czttystart(struct tty *tp); 183 static int czttyparam(struct tty *tp, struct termios *t); 184 static void cztty_shutdown(struct cztty_softc *sc); 185 static void cztty_modem(struct cztty_softc *sc, int onoff); 186 static void cztty_break(struct cztty_softc *sc, int onoff); 187 static void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 188 static int cztty_to_tiocm(struct cztty_softc *sc); 189 static void cztty_diag(void *arg); 190 191 extern struct cfdriver cz_cd; 192 193 /* 194 * Macros to read and write the PLX. 195 */ 196 #define CZ_PLX_READ(cz, reg) \ 197 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 198 #define CZ_PLX_WRITE(cz, reg, val) \ 199 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 200 (reg), (val)) 201 202 /* 203 * Macros to read and write the FPGA. We must already be in the FPGA 204 * window for this. 205 */ 206 #define CZ_FPGA_READ(cz, reg) \ 207 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 208 #define CZ_FPGA_WRITE(cz, reg, val) \ 209 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 210 211 /* 212 * Macros to read and write the firmware control structures in board RAM. 213 */ 214 #define CZ_FWCTL_READ(cz, off) \ 215 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 216 (cz)->cz_fwctl + (off)) 217 218 #define CZ_FWCTL_WRITE(cz, off, val) \ 219 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 220 (cz)->cz_fwctl + (off), (val)) 221 222 /* 223 * Convenience macros for cztty routines. PLX window MUST be to RAM. 224 */ 225 #define CZTTY_CHAN_READ(sc, off) \ 226 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 227 228 #define CZTTY_CHAN_WRITE(sc, off, val) \ 229 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 230 (off), (val)) 231 232 #define CZTTY_BUF_READ(sc, off) \ 233 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 234 235 #define CZTTY_BUF_WRITE(sc, off, val) \ 236 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 237 (off), (val)) 238 239 /* 240 * Convenience macros. 241 */ 242 #define CZ_WIN_RAM(cz) \ 243 do { \ 244 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 245 delay(100); \ 246 } while (0) 247 248 #define CZ_WIN_FPGA(cz) \ 249 do { \ 250 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 251 delay(100); \ 252 } while (0) 253 254 /***************************************************************************** 255 * Cyclades-Z controller code starts here... 256 *****************************************************************************/ 257 258 /* 259 * cz_match: 260 * 261 * Determine if the given PCI device is a Cyclades-Z board. 262 */ 263 static int 264 cz_match(struct device *parent, 265 struct cfdata *match, 266 void *aux) 267 { 268 struct pci_attach_args *pa = aux; 269 270 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 271 switch (PCI_PRODUCT(pa->pa_id)) { 272 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 273 return (1); 274 } 275 } 276 277 return (0); 278 } 279 280 /* 281 * cz_attach: 282 * 283 * A Cyclades-Z board was found; attach it. 284 */ 285 static void 286 cz_attach(struct device *parent, 287 struct device *self, 288 void *aux) 289 { 290 extern const struct cdevsw cz_cdevsw; /* XXX */ 291 struct cz_softc *cz = (void *) self; 292 struct pci_attach_args *pa = aux; 293 pci_intr_handle_t ih; 294 const char *intrstr = NULL; 295 struct cztty_softc *sc; 296 struct tty *tp; 297 int i; 298 299 aprint_naive(": Multi-port serial controller\n"); 300 aprint_normal(": Cyclades-Z multiport serial\n"); 301 302 cz->cz_plx.plx_pc = pa->pa_pc; 303 cz->cz_plx.plx_tag = pa->pa_tag; 304 305 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 306 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 307 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 308 aprint_error("%s: unable to map PLX registers\n", 309 cz->cz_dev.dv_xname); 310 return; 311 } 312 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 313 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 314 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 315 aprint_error("%s: unable to map device window\n", 316 cz->cz_dev.dv_xname); 317 return; 318 } 319 320 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 321 cz->cz_nopenchan = 0; 322 323 /* 324 * Make sure that the board is completely stopped. 325 */ 326 CZ_WIN_FPGA(cz); 327 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 328 329 /* 330 * Load the board's firmware. 331 */ 332 if (cz_load_firmware(cz) != 0) 333 return; 334 335 /* 336 * Now that we're ready to roll, map and establish the interrupt 337 * handler. 338 */ 339 if (pci_intr_map(pa, &ih) != 0) { 340 /* 341 * The common case is for Cyclades-Z boards to run 342 * in polling mode, and thus not have an interrupt 343 * mapped for them. Don't bother reporting that 344 * the interrupt is not mappable, since this isn't 345 * really an error. 346 */ 347 cz->cz_ih = NULL; 348 goto polling_mode; 349 } else { 350 intrstr = pci_intr_string(pa->pa_pc, ih); 351 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 352 cz_intr, cz); 353 } 354 if (cz->cz_ih == NULL) { 355 aprint_error("%s: unable to establish interrupt", 356 cz->cz_dev.dv_xname); 357 if (intrstr != NULL) 358 aprint_normal(" at %s", intrstr); 359 aprint_normal("\n"); 360 /* We will fall-back on polling mode. */ 361 } else 362 aprint_normal("%s: interrupting at %s\n", 363 cz->cz_dev.dv_xname, intrstr); 364 365 polling_mode: 366 if (cz->cz_ih == NULL) { 367 callout_init(&cz->cz_callout, 0); 368 if (cz_timeout_ticks == 0) 369 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 370 aprint_normal("%s: polling mode, %d ms interval (%d tick%s)\n", 371 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 372 cz_timeout_ticks == 1 ? "" : "s"); 373 } 374 375 /* 376 * Allocate sufficient pointers for the children and 377 * attach them. Set all ports to a reasonable initial 378 * configuration while we're at it: 379 * 380 * disabled 381 * 8N1 382 * default baud rate 383 * hardware flow control. 384 */ 385 CZ_WIN_RAM(cz); 386 387 if (cz->cz_nchannels == 0) { 388 /* No channels? No more work to do! */ 389 return; 390 } 391 392 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 393 M_DEVBUF, M_WAITOK|M_ZERO); 394 cztty_attached_ttys += cz->cz_nchannels; 395 396 for (i = 0; i < cz->cz_nchannels; i++) { 397 sc = &cz->cz_ports[i]; 398 399 sc->sc_channel = i; 400 sc->sc_chan_st = cz->cz_win_st; 401 sc->sc_parent = cz; 402 403 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 404 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 405 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 406 aprint_error( 407 "%s: unable to subregion channel %d control\n", 408 cz->cz_dev.dv_xname, i); 409 sc->sc_channel = CZTTY_CHANNEL_DEAD; 410 continue; 411 } 412 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 413 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 414 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 415 aprint_error( 416 "%s: unable to subregion channel %d buffer\n", 417 cz->cz_dev.dv_xname, i); 418 sc->sc_channel = CZTTY_CHANNEL_DEAD; 419 continue; 420 } 421 422 callout_init(&sc->sc_diag_ch, 0); 423 424 tp = ttymalloc(); 425 tp->t_dev = makedev(cdevsw_lookup_major(&cz_cdevsw), 426 (device_unit(&cz->cz_dev) * ZFIRM_MAX_CHANNELS) + i); 427 tp->t_oproc = czttystart; 428 tp->t_param = czttyparam; 429 tty_attach(tp); 430 431 sc->sc_tty = tp; 432 433 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 434 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 435 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 436 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 437 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 438 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 439 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 440 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 441 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 442 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 443 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 444 } 445 } 446 447 CFATTACH_DECL(cz, sizeof(struct cz_softc), 448 cz_match, cz_attach, NULL, NULL); 449 450 #if 0 451 /* 452 * cz_reset_board: 453 * 454 * Reset the board via the PLX. 455 */ 456 static void 457 cz_reset_board(struct cz_softc *cz) 458 { 459 u_int32_t reg; 460 461 reg = CZ_PLX_READ(cz, PLX_CONTROL); 462 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 463 delay(1000); 464 465 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 466 delay(1000); 467 468 /* Now reload the PLX from its EEPROM. */ 469 reg = CZ_PLX_READ(cz, PLX_CONTROL); 470 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 471 delay(1000); 472 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 473 } 474 #endif 475 476 /* 477 * cz_load_firmware: 478 * 479 * Load the ZFIRM firmware into the board's RAM and start it 480 * running. 481 */ 482 static int 483 cz_load_firmware(struct cz_softc *cz) 484 { 485 const struct zfirm_header *zfh; 486 const struct zfirm_config *zfc; 487 const struct zfirm_block *zfb, *zblocks; 488 const u_int8_t *cp; 489 const char *board; 490 u_int32_t fid; 491 int i, j, nconfigs, nblocks, nbytes; 492 493 zfh = (const struct zfirm_header *) cycladesz_firmware; 494 495 /* Find the config header. */ 496 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 497 aprint_error("%s: bad ZFIRM config offset: 0x%x\n", 498 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 499 return (EIO); 500 } 501 zfc = (const struct zfirm_config *)(cycladesz_firmware + 502 le32toh(zfh->zfh_configoff)); 503 nconfigs = le32toh(zfh->zfh_nconfig); 504 505 /* Locate the correct configuration for our board. */ 506 for (i = 0; i < nconfigs; i++, zfc++) { 507 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 508 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 509 break; 510 } 511 if (i == nconfigs) { 512 aprint_error("%s: unable to locate config header\n", 513 cz->cz_dev.dv_xname); 514 return (EIO); 515 } 516 517 nblocks = le32toh(zfc->zfc_nblocks); 518 zblocks = (const struct zfirm_block *)(cycladesz_firmware + 519 le32toh(zfh->zfh_blockoff)); 520 521 /* 522 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 523 * necessary. 524 */ 525 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 526 #if 0 527 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 528 #endif 529 ) { 530 #ifdef CZ_DEBUG 531 aprint_debug("%s: Loading FPGA...", cz->cz_dev.dv_xname); 532 #endif 533 CZ_WIN_FPGA(cz); 534 for (i = 0; i < nblocks; i++) { 535 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 536 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 537 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 538 nbytes = le32toh(zfb->zfb_size); 539 cp = &cycladesz_firmware[ 540 le32toh(zfb->zfb_fileoff)]; 541 for (j = 0; j < nbytes; j++, cp++) { 542 bus_space_write_1(cz->cz_win_st, 543 cz->cz_win_sh, 0, *cp); 544 /* FPGA needs 30-100us to settle. */ 545 delay(10); 546 } 547 } 548 } 549 #ifdef CZ_DEBUG 550 aprint_debug("done\n"); 551 #endif 552 } 553 554 /* Now load the firmware. */ 555 CZ_WIN_RAM(cz); 556 557 for (i = 0; i < nblocks; i++) { 558 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 559 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 560 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 561 const u_int32_t *lp; 562 u_int32_t ro = le32toh(zfb->zfb_ramoff); 563 nbytes = le32toh(zfb->zfb_size); 564 lp = (const u_int32_t *) 565 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 566 for (j = 0; j < nbytes; j += 4, lp++) { 567 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 568 ro + j, le32toh(*lp)); 569 delay(10); 570 } 571 } 572 } 573 574 /* Now restart the MIPS. */ 575 CZ_WIN_FPGA(cz); 576 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 577 578 /* Wait for the MIPS to start, then report the results. */ 579 CZ_WIN_RAM(cz); 580 581 #ifdef CZ_DEBUG 582 aprint_debug("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 583 #endif 584 for (i = 0; i < 100; i++) { 585 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 586 ZFIRM_SIG_OFF); 587 if (fid == ZFIRM_SIG) { 588 /* MIPS has booted. */ 589 break; 590 } else if (fid == ZFIRM_HLT) { 591 /* 592 * The MIPS has halted, usually due to a power 593 * shortage on the expansion module. 594 */ 595 aprint_error("%s: MIPS halted; possible power supply " 596 "problem\n", cz->cz_dev.dv_xname); 597 return (EIO); 598 } else { 599 #ifdef CZ_DEBUG 600 if ((i % 8) == 0) 601 aprint_debug("."); 602 #endif 603 delay(250000); 604 } 605 } 606 #ifdef CZ_DEBUG 607 aprint_debug("\n"); 608 #endif 609 if (i == 100) { 610 CZ_WIN_FPGA(cz); 611 aprint_error( 612 "%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 613 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 614 aprint_error("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 615 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 616 CZ_FPGA_READ(cz, FPGA_VERSION)); 617 return (EIO); 618 } 619 620 /* 621 * Locate the firmware control structures. 622 */ 623 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 624 ZFIRM_CTRLADDR_OFF); 625 #ifdef CZ_DEBUG 626 aprint_debug("%s: FWCTL structure at offset 0x%08lx\n", 627 cz->cz_dev.dv_xname, cz->cz_fwctl); 628 #endif 629 630 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 631 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 632 633 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 634 635 switch (cz->cz_mailbox0) { 636 case MAILBOX0_8Zo_V1: 637 board = "Cyclades-8Zo ver. 1"; 638 break; 639 640 case MAILBOX0_8Zo_V2: 641 board = "Cyclades-8Zo ver. 2"; 642 break; 643 644 case MAILBOX0_Ze_V1: 645 board = "Cyclades-Ze"; 646 break; 647 648 default: 649 board = "unknown Cyclades Z-series"; 650 break; 651 } 652 653 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 654 aprint_normal("%s: %s, ", cz->cz_dev.dv_xname, board); 655 if (cz->cz_nchannels == 0) 656 aprint_normal("no channels attached, "); 657 else 658 aprint_normal("%d channels (ttyCZ%04d..ttyCZ%04d), ", 659 cz->cz_nchannels, cztty_attached_ttys, 660 cztty_attached_ttys + (cz->cz_nchannels - 1)); 661 aprint_normal("firmware %x.%x.%x\n", 662 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 663 664 return (0); 665 } 666 667 /* 668 * cz_poll: 669 * 670 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 671 * ms. 672 */ 673 static void 674 cz_poll(void *arg) 675 { 676 int s = spltty(); 677 struct cz_softc *cz = arg; 678 679 cz_intr(cz); 680 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 681 682 splx(s); 683 } 684 685 /* 686 * cz_intr: 687 * 688 * Interrupt service routine. 689 * 690 * We either are receiving an interrupt directly from the board, or we are 691 * in polling mode and it's time to poll. 692 */ 693 static int 694 cz_intr(void *arg) 695 { 696 int rval = 0; 697 u_int command, channel, param; 698 struct cz_softc *cz = arg; 699 struct cztty_softc *sc; 700 struct tty *tp; 701 702 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 703 rval = 1; 704 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 705 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 706 707 /* now clear this interrupt, posslibly enabling another */ 708 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 709 710 if (cz->cz_ports == NULL) { 711 #ifdef CZ_DEBUG 712 printf("%s: interrupt on channel %d, but no channels\n", 713 cz->cz_dev.dv_xname, channel); 714 #endif 715 continue; 716 } 717 718 sc = &cz->cz_ports[channel]; 719 720 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 721 break; 722 723 tp = sc->sc_tty; 724 725 switch (command) { 726 case C_CM_TXFEMPTY: /* transmit cases */ 727 case C_CM_TXBEMPTY: 728 case C_CM_TXLOWWM: 729 case C_CM_INTBACK: 730 if (!ISSET(tp->t_state, TS_ISOPEN)) { 731 #ifdef CZ_DEBUG 732 printf("%s: tx intr on closed channel %d\n", 733 cz->cz_dev.dv_xname, channel); 734 #endif 735 break; 736 } 737 738 if (cztty_transmit(sc, tp)) { 739 /* 740 * Do wakeup stuff here. 741 */ 742 mutex_spin_enter(&tty_lock); /* XXX */ 743 ttwakeup(tp); 744 mutex_spin_exit(&tty_lock); /* XXX */ 745 wakeup(tp); 746 } 747 break; 748 749 case C_CM_RXNNDT: /* receive cases */ 750 case C_CM_RXHIWM: 751 case C_CM_INTBACK2: /* from restart ?? */ 752 #if 0 753 case C_CM_ICHAR: 754 #endif 755 if (!ISSET(tp->t_state, TS_ISOPEN)) { 756 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 757 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 758 break; 759 } 760 761 if (cztty_receive(sc, tp)) { 762 /* 763 * Do wakeup stuff here. 764 */ 765 mutex_spin_enter(&tty_lock); /* XXX */ 766 ttwakeup(tp); 767 mutex_spin_exit(&tty_lock); /* XXX */ 768 wakeup(tp); 769 } 770 break; 771 772 case C_CM_MDCD: 773 if (!ISSET(tp->t_state, TS_ISOPEN)) 774 break; 775 776 (void) (*tp->t_linesw->l_modem)(tp, 777 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 778 CHNCTL_RS_STATUS))); 779 break; 780 781 case C_CM_MDSR: 782 case C_CM_MRI: 783 case C_CM_MCTS: 784 case C_CM_MRTS: 785 break; 786 787 case C_CM_IOCTLW: 788 break; 789 790 case C_CM_PR_ERROR: 791 sc->sc_parity_errors++; 792 goto error_common; 793 794 case C_CM_FR_ERROR: 795 sc->sc_framing_errors++; 796 goto error_common; 797 798 case C_CM_OVR_ERROR: 799 sc->sc_overflows++; 800 error_common: 801 if (sc->sc_errors++ == 0) 802 callout_reset(&sc->sc_diag_ch, 60 * hz, 803 cztty_diag, sc); 804 break; 805 806 case C_CM_RXBRK: 807 if (!ISSET(tp->t_state, TS_ISOPEN)) 808 break; 809 810 /* 811 * A break is a \000 character with TTY_FE error 812 * flags set. So TTY_FE by itself works. 813 */ 814 (*tp->t_linesw->l_rint)(TTY_FE, tp); 815 mutex_spin_enter(&tty_lock); /* XXX */ 816 ttwakeup(tp); 817 mutex_spin_exit(&tty_lock); /* XXX */ 818 wakeup(tp); 819 break; 820 821 default: 822 #ifdef CZ_DEBUG 823 printf("%s: channel %d: Unknown interrupt 0x%x\n", 824 cz->cz_dev.dv_xname, sc->sc_channel, command); 825 #endif 826 break; 827 } 828 } 829 830 return (rval); 831 } 832 833 /* 834 * cz_wait_pci_doorbell: 835 * 836 * Wait for the pci doorbell to be clear - wait for pending 837 * activity to drain. 838 */ 839 static int 840 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 841 { 842 int error; 843 844 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 845 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 846 if ((error != 0) && (error != EWOULDBLOCK)) 847 return (error); 848 } 849 return (0); 850 } 851 852 /***************************************************************************** 853 * Cyclades-Z TTY code starts here... 854 *****************************************************************************/ 855 856 #define CZTTYDIALOUT_MASK 0x80000 857 858 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 859 #define CZTTY_CZ(sc) ((sc)->sc_parent) 860 861 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 862 863 static struct cztty_softc * 864 cztty_getttysoftc(dev_t dev) 865 { 866 int i, j, k = 0, u = minor(dev) & ~CZTTYDIALOUT_MASK; 867 struct cz_softc *cz = NULL; 868 869 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 870 k = j; 871 cz = device_lookup(&cz_cd, i); 872 if (cz == NULL) 873 continue; 874 if (cz->cz_ports == NULL) 875 continue; 876 j += cz->cz_nchannels; 877 if (j > u) 878 break; 879 } 880 881 if (i >= cz_cd.cd_ndevs) 882 return (NULL); 883 else 884 return (&cz->cz_ports[u - k]); 885 } 886 887 /* 888 * czttytty: 889 * 890 * Return a pointer to our tty. 891 */ 892 static struct tty * 893 czttytty(dev_t dev) 894 { 895 struct cztty_softc *sc = CZTTY_SOFTC(dev); 896 897 #ifdef DIAGNOSTIC 898 if (sc == NULL) 899 panic("czttytty"); 900 #endif 901 902 return (sc->sc_tty); 903 } 904 905 /* 906 * cztty_shutdown: 907 * 908 * Shut down a port. 909 */ 910 static void 911 cztty_shutdown(struct cztty_softc *sc) 912 { 913 struct cz_softc *cz = CZTTY_CZ(sc); 914 struct tty *tp = sc->sc_tty; 915 int s; 916 917 s = spltty(); 918 919 /* Clear any break condition set with TIOCSBRK. */ 920 cztty_break(sc, 0); 921 922 /* 923 * Hang up if necessary. Wait a bit, so the other side has time to 924 * notice even if we immediately open the port again. 925 */ 926 if (ISSET(tp->t_cflag, HUPCL)) { 927 cztty_modem(sc, 0); 928 (void) tsleep(tp, TTIPRI, ttclos, hz); 929 } 930 931 /* Disable the channel. */ 932 cz_wait_pci_doorbell(cz, "czdis"); 933 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 934 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 935 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 936 937 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 938 #ifdef CZ_DEBUG 939 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 940 #endif 941 callout_stop(&cz->cz_callout); 942 } 943 944 splx(s); 945 } 946 947 /* 948 * czttyopen: 949 * 950 * Open a Cyclades-Z serial port. 951 */ 952 static int 953 czttyopen(dev_t dev, int flags, int mode, struct lwp *l) 954 { 955 struct cztty_softc *sc = CZTTY_SOFTC(dev); 956 struct cz_softc *cz; 957 struct tty *tp; 958 int s, error; 959 960 if (sc == NULL) 961 return (ENXIO); 962 963 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 964 return (ENXIO); 965 966 cz = CZTTY_CZ(sc); 967 tp = sc->sc_tty; 968 969 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 970 return (EBUSY); 971 972 s = spltty(); 973 974 /* 975 * Do the following iff this is a first open. 976 */ 977 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 978 struct termios t; 979 980 tp->t_dev = dev; 981 982 /* If we're turning things on, enable interrupts */ 983 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 984 #ifdef CZ_DEBUG 985 printf("%s: Enabling polling.\n", 986 cz->cz_dev.dv_xname); 987 #endif 988 callout_reset(&cz->cz_callout, cz_timeout_ticks, 989 cz_poll, cz); 990 } 991 992 /* 993 * Enable the channel. Don't actually ring the 994 * doorbell here; czttyparam() will do it for us. 995 */ 996 cz_wait_pci_doorbell(cz, "czopen"); 997 998 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 999 1000 /* 1001 * Initialize the termios status to the defaults. Add in the 1002 * sticky bits from TIOCSFLAGS. 1003 */ 1004 t.c_ispeed = 0; 1005 t.c_ospeed = TTYDEF_SPEED; 1006 t.c_cflag = TTYDEF_CFLAG; 1007 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1008 SET(t.c_cflag, CLOCAL); 1009 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1010 SET(t.c_cflag, CRTSCTS); 1011 1012 /* 1013 * Reset the input and output rings. Do this before 1014 * we call czttyparam(), as that function enables 1015 * the channel. 1016 */ 1017 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1018 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1019 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1020 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1021 1022 /* Make sure czttyparam() will see changes. */ 1023 tp->t_ospeed = 0; 1024 (void) czttyparam(tp, &t); 1025 tp->t_iflag = TTYDEF_IFLAG; 1026 tp->t_oflag = TTYDEF_OFLAG; 1027 tp->t_lflag = TTYDEF_LFLAG; 1028 ttychars(tp); 1029 ttsetwater(tp); 1030 1031 /* 1032 * Turn on DTR. We must always do this, even if carrier is not 1033 * present, because otherwise we'd have to use TIOCSDTR 1034 * immediately after setting CLOCAL, which applications do not 1035 * expect. We always assert DTR while the device is open 1036 * unless explicitly requested to deassert it. 1037 */ 1038 cztty_modem(sc, 1); 1039 } 1040 1041 splx(s); 1042 1043 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1044 if (error) 1045 goto bad; 1046 1047 error = (*tp->t_linesw->l_open)(dev, tp); 1048 if (error) 1049 goto bad; 1050 1051 return (0); 1052 1053 bad: 1054 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1055 /* 1056 * We failed to open the device, and nobody else had it opened. 1057 * Clean up the state as appropriate. 1058 */ 1059 cztty_shutdown(sc); 1060 } 1061 1062 return (error); 1063 } 1064 1065 /* 1066 * czttyclose: 1067 * 1068 * Close a Cyclades-Z serial port. 1069 */ 1070 static int 1071 czttyclose(dev_t dev, int flags, int mode, struct lwp *l) 1072 { 1073 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1074 struct tty *tp = sc->sc_tty; 1075 1076 /* XXX This is for cons.c. */ 1077 if (!ISSET(tp->t_state, TS_ISOPEN)) 1078 return (0); 1079 1080 (*tp->t_linesw->l_close)(tp, flags); 1081 ttyclose(tp); 1082 1083 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1084 /* 1085 * Although we got a last close, the device may still be in 1086 * use; e.g. if this was the dialout node, and there are still 1087 * processes waiting for carrier on the non-dialout node. 1088 */ 1089 cztty_shutdown(sc); 1090 } 1091 1092 return (0); 1093 } 1094 1095 /* 1096 * czttyread: 1097 * 1098 * Read from a Cyclades-Z serial port. 1099 */ 1100 static int 1101 czttyread(dev_t dev, struct uio *uio, int flags) 1102 { 1103 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1104 struct tty *tp = sc->sc_tty; 1105 1106 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1107 } 1108 1109 /* 1110 * czttywrite: 1111 * 1112 * Write to a Cyclades-Z serial port. 1113 */ 1114 static int 1115 czttywrite(dev_t dev, struct uio *uio, int flags) 1116 { 1117 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1118 struct tty *tp = sc->sc_tty; 1119 1120 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1121 } 1122 1123 /* 1124 * czttypoll: 1125 * 1126 * Poll a Cyclades-Z serial port. 1127 */ 1128 static int 1129 czttypoll(dev_t dev, int events, struct lwp *l) 1130 { 1131 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1132 struct tty *tp = sc->sc_tty; 1133 1134 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1135 } 1136 1137 /* 1138 * czttyioctl: 1139 * 1140 * Perform a control operation on a Cyclades-Z serial port. 1141 */ 1142 static int 1143 czttyioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1144 { 1145 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1146 struct tty *tp = sc->sc_tty; 1147 int s, error; 1148 1149 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1150 if (error != EPASSTHROUGH) 1151 return (error); 1152 1153 error = ttioctl(tp, cmd, data, flag, l); 1154 if (error != EPASSTHROUGH) 1155 return (error); 1156 1157 error = 0; 1158 1159 s = spltty(); 1160 1161 switch (cmd) { 1162 case TIOCSBRK: 1163 cztty_break(sc, 1); 1164 break; 1165 1166 case TIOCCBRK: 1167 cztty_break(sc, 0); 1168 break; 1169 1170 case TIOCGFLAGS: 1171 *(int *)data = sc->sc_swflags; 1172 break; 1173 1174 case TIOCSFLAGS: 1175 error = kauth_authorize_device_tty(l->l_cred, 1176 KAUTH_DEVICE_TTY_PRIVSET, tp); 1177 if (error) 1178 break; 1179 sc->sc_swflags = *(int *)data; 1180 break; 1181 1182 case TIOCSDTR: 1183 cztty_modem(sc, 1); 1184 break; 1185 1186 case TIOCCDTR: 1187 cztty_modem(sc, 0); 1188 break; 1189 1190 case TIOCMSET: 1191 case TIOCMBIS: 1192 case TIOCMBIC: 1193 tiocm_to_cztty(sc, cmd, *(int *)data); 1194 break; 1195 1196 case TIOCMGET: 1197 *(int *)data = cztty_to_tiocm(sc); 1198 break; 1199 1200 default: 1201 error = EPASSTHROUGH; 1202 break; 1203 } 1204 1205 splx(s); 1206 1207 return (error); 1208 } 1209 1210 /* 1211 * cztty_break: 1212 * 1213 * Set or clear BREAK on a port. 1214 */ 1215 static void 1216 cztty_break(struct cztty_softc *sc, int onoff) 1217 { 1218 struct cz_softc *cz = CZTTY_CZ(sc); 1219 1220 cz_wait_pci_doorbell(cz, "czbreak"); 1221 1222 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1223 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1224 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1225 } 1226 1227 /* 1228 * cztty_modem: 1229 * 1230 * Set or clear DTR on a port. 1231 */ 1232 static void 1233 cztty_modem(struct cztty_softc *sc, int onoff) 1234 { 1235 struct cz_softc *cz = CZTTY_CZ(sc); 1236 1237 if (sc->sc_rs_control_dtr == 0) 1238 return; 1239 1240 cz_wait_pci_doorbell(cz, "czmod"); 1241 1242 if (onoff) 1243 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1244 else 1245 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1246 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1247 1248 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1249 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1250 } 1251 1252 /* 1253 * tiocm_to_cztty: 1254 * 1255 * Process TIOCM* ioctls. 1256 */ 1257 static void 1258 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1259 { 1260 struct cz_softc *cz = CZTTY_CZ(sc); 1261 u_int32_t czttybits; 1262 1263 czttybits = 0; 1264 if (ISSET(ttybits, TIOCM_DTR)) 1265 SET(czttybits, C_RS_DTR); 1266 if (ISSET(ttybits, TIOCM_RTS)) 1267 SET(czttybits, C_RS_RTS); 1268 1269 cz_wait_pci_doorbell(cz, "cztiocm"); 1270 1271 switch (how) { 1272 case TIOCMBIC: 1273 CLR(sc->sc_chanctl_rs_control, czttybits); 1274 break; 1275 1276 case TIOCMBIS: 1277 SET(sc->sc_chanctl_rs_control, czttybits); 1278 break; 1279 1280 case TIOCMSET: 1281 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1282 SET(sc->sc_chanctl_rs_control, czttybits); 1283 break; 1284 } 1285 1286 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1287 1288 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1289 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1290 } 1291 1292 /* 1293 * cztty_to_tiocm: 1294 * 1295 * Process the TIOCMGET ioctl. 1296 */ 1297 static int 1298 cztty_to_tiocm(struct cztty_softc *sc) 1299 { 1300 struct cz_softc *cz = CZTTY_CZ(sc); 1301 u_int32_t rs_status, op_mode; 1302 int ttybits = 0; 1303 1304 cz_wait_pci_doorbell(cz, "cztty"); 1305 1306 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1307 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1308 1309 if (ISSET(rs_status, C_RS_RTS)) 1310 SET(ttybits, TIOCM_RTS); 1311 if (ISSET(rs_status, C_RS_CTS)) 1312 SET(ttybits, TIOCM_CTS); 1313 if (ISSET(rs_status, C_RS_DCD)) 1314 SET(ttybits, TIOCM_CAR); 1315 if (ISSET(rs_status, C_RS_DTR)) 1316 SET(ttybits, TIOCM_DTR); 1317 if (ISSET(rs_status, C_RS_RI)) 1318 SET(ttybits, TIOCM_RNG); 1319 if (ISSET(rs_status, C_RS_DSR)) 1320 SET(ttybits, TIOCM_DSR); 1321 1322 if (ISSET(op_mode, C_CH_ENABLE)) 1323 SET(ttybits, TIOCM_LE); 1324 1325 return (ttybits); 1326 } 1327 1328 /* 1329 * czttyparam: 1330 * 1331 * Set Cyclades-Z serial port parameters from termios. 1332 * 1333 * XXX Should just copy the whole termios after making 1334 * XXX sure all the changes could be done. 1335 */ 1336 static int 1337 czttyparam(struct tty *tp, struct termios *t) 1338 { 1339 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1340 struct cz_softc *cz = CZTTY_CZ(sc); 1341 u_int32_t rs_status; 1342 int ospeed, cflag; 1343 1344 ospeed = t->c_ospeed; 1345 cflag = t->c_cflag; 1346 1347 /* Check requested parameters. */ 1348 if (ospeed < 0) 1349 return (EINVAL); 1350 if (t->c_ispeed && t->c_ispeed != ospeed) 1351 return (EINVAL); 1352 1353 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1354 SET(cflag, CLOCAL); 1355 CLR(cflag, HUPCL); 1356 } 1357 1358 /* 1359 * If there were no changes, don't do anything. This avoids dropping 1360 * input and improves performance when all we did was frob things like 1361 * VMIN and VTIME. 1362 */ 1363 if (tp->t_ospeed == ospeed && 1364 tp->t_cflag == cflag) 1365 return (0); 1366 1367 /* Data bits. */ 1368 sc->sc_chanctl_comm_data_l = 0; 1369 switch (t->c_cflag & CSIZE) { 1370 case CS5: 1371 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1372 break; 1373 1374 case CS6: 1375 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1376 break; 1377 1378 case CS7: 1379 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1380 break; 1381 1382 case CS8: 1383 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1384 break; 1385 } 1386 1387 /* Stop bits. */ 1388 if (t->c_cflag & CSTOPB) { 1389 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1390 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1391 else 1392 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1393 } else 1394 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1395 1396 /* Parity. */ 1397 if (t->c_cflag & PARENB) { 1398 if (t->c_cflag & PARODD) 1399 sc->sc_chanctl_comm_parity = C_PR_ODD; 1400 else 1401 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1402 } else 1403 sc->sc_chanctl_comm_parity = C_PR_NONE; 1404 1405 /* 1406 * Initialize flow control pins depending on the current flow control 1407 * mode. 1408 */ 1409 if (ISSET(t->c_cflag, CRTSCTS)) { 1410 sc->sc_rs_control_dtr = C_RS_DTR; 1411 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1412 } else if (ISSET(t->c_cflag, MDMBUF)) { 1413 sc->sc_rs_control_dtr = 0; 1414 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1415 } else { 1416 /* 1417 * If no flow control, then always set RTS. This will make 1418 * the other side happy if it mistakenly thinks we're doing 1419 * RTS/CTS flow control. 1420 */ 1421 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1422 sc->sc_chanctl_hw_flow = 0; 1423 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1424 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1425 else 1426 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1427 } 1428 1429 /* Baud rate. */ 1430 sc->sc_chanctl_comm_baud = ospeed; 1431 1432 /* Copy to tty. */ 1433 tp->t_ispeed = 0; 1434 tp->t_ospeed = t->c_ospeed; 1435 tp->t_cflag = t->c_cflag; 1436 1437 /* 1438 * Now load the channel control structure. 1439 */ 1440 1441 cz_wait_pci_doorbell(cz, "czparam"); 1442 1443 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1444 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1445 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1446 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1447 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1448 1449 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1450 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1451 1452 cz_wait_pci_doorbell(cz, "czparam"); 1453 1454 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1455 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1456 1457 cz_wait_pci_doorbell(cz, "czparam"); 1458 1459 /* 1460 * Update the tty layer's idea of the carrier bit, in case we changed 1461 * CLOCAL. We don't hang up here; we only do that by explicit 1462 * request. 1463 */ 1464 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1465 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1466 1467 return (0); 1468 } 1469 1470 /* 1471 * czttystart: 1472 * 1473 * Start or restart transmission. 1474 */ 1475 static void 1476 czttystart(struct tty *tp) 1477 { 1478 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1479 int s; 1480 1481 s = spltty(); 1482 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1483 goto out; 1484 if (!ttypull(tp)) 1485 goto out; 1486 cztty_transmit(sc, tp); 1487 out: 1488 splx(s); 1489 } 1490 1491 /* 1492 * czttystop: 1493 * 1494 * Stop output, e.g., for ^S or output flush. 1495 */ 1496 static void 1497 czttystop(struct tty *tp, int flag) 1498 { 1499 1500 /* 1501 * XXX We don't do anything here, yet. Mostly, I don't know 1502 * XXX exactly how this should be implemented on this device. 1503 * XXX We've given a big chunk of data to the MIPS already, 1504 * XXX and I don't know how we request the MIPS to stop sending 1505 * XXX the data. So, punt for now. --thorpej 1506 */ 1507 } 1508 1509 /* 1510 * cztty_diag: 1511 * 1512 * Issue a scheduled diagnostic message. 1513 */ 1514 static void 1515 cztty_diag(void *arg) 1516 { 1517 struct cztty_softc *sc = arg; 1518 struct cz_softc *cz = CZTTY_CZ(sc); 1519 u_int overflows, parity_errors, framing_errors; 1520 int s; 1521 1522 s = spltty(); 1523 1524 overflows = sc->sc_overflows; 1525 sc->sc_overflows = 0; 1526 1527 parity_errors = sc->sc_parity_errors; 1528 sc->sc_parity_errors = 0; 1529 1530 framing_errors = sc->sc_framing_errors; 1531 sc->sc_framing_errors = 0; 1532 1533 sc->sc_errors = 0; 1534 1535 splx(s); 1536 1537 log(LOG_WARNING, 1538 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1539 cz->cz_dev.dv_xname, sc->sc_channel, 1540 overflows, overflows == 1 ? "" : "s", 1541 parity_errors, 1542 framing_errors, framing_errors == 1 ? "" : "s"); 1543 } 1544 1545 const struct cdevsw cz_cdevsw = { 1546 czttyopen, czttyclose, czttyread, czttywrite, czttyioctl, 1547 czttystop, czttytty, czttypoll, nommap, ttykqfilter, D_TTY 1548 }; 1549 1550 /* 1551 * tx and rx ring buffer size macros: 1552 * 1553 * The transmitter and receiver both use ring buffers. For each one, there 1554 * is a get (consumer) and a put (producer) offset. The get value is the 1555 * next byte to be read from the ring, and the put is the next one to be 1556 * put into the ring. get == put means the ring is empty. 1557 * 1558 * For each ring, the firmware controls one of (get, put) and this driver 1559 * controls the other. For transmission, this driver updates put to point 1560 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1561 * for receive, the driver controls put, and this driver controls get. 1562 */ 1563 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1564 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1565 1566 /* 1567 * cztty_transmit() 1568 * 1569 * Look at the tty for this port and start sending. 1570 */ 1571 static int 1572 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1573 { 1574 struct cz_softc *cz = CZTTY_CZ(sc); 1575 u_int move, get, put, size, address; 1576 #ifdef HOSTRAMCODE 1577 int error, done = 0; 1578 #else 1579 int done = 0; 1580 #endif 1581 1582 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1583 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1584 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1585 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1586 1587 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1588 #ifdef HOSTRAMCODE 1589 if (0) { 1590 move = min(tp->t_outq.c_cc, move); 1591 error = q_to_b(&tp->t_outq, 0, move); 1592 if (error != move) { 1593 printf("%s: channel %d: error moving to " 1594 "transmit buf\n", cz->cz_dev.dv_xname, 1595 sc->sc_channel); 1596 move = error; 1597 } 1598 } else { 1599 #endif 1600 move = min(ndqb(&tp->t_outq, 0), move); 1601 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1602 address + put, tp->t_outq.c_cf, move); 1603 ndflush(&tp->t_outq, move); 1604 #ifdef HOSTRAMCODE 1605 } 1606 #endif 1607 1608 put = ((put + move) % size); 1609 done = 1; 1610 } 1611 if (done) { 1612 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1613 } 1614 return (done); 1615 } 1616 1617 static int 1618 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1619 { 1620 struct cz_softc *cz = CZTTY_CZ(sc); 1621 u_int get, put, size, address; 1622 int done = 0, ch; 1623 1624 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1625 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1626 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1627 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1628 1629 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1630 #ifdef HOSTRAMCODE 1631 if (hostram) { 1632 ch = ((char *)fifoaddr)[get]; 1633 } else { 1634 #endif 1635 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1636 address + get); 1637 #ifdef HOSTRAMCODE 1638 } 1639 #endif 1640 (*tp->t_linesw->l_rint)(ch, tp); 1641 get = (get + 1) % size; 1642 done = 1; 1643 } 1644 if (done) { 1645 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1646 } 1647 return (done); 1648 } 1649