1 /* $NetBSD: cz.c,v 1.11 2000/11/02 00:01:45 eeh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only utilize RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/proc.h> 78 #include <sys/device.h> 79 #include <sys/malloc.h> 80 #include <sys/tty.h> 81 #include <sys/conf.h> 82 #include <sys/time.h> 83 #include <sys/kernel.h> 84 #include <sys/fcntl.h> 85 #include <sys/syslog.h> 86 87 #include <sys/callout.h> 88 89 #include <dev/pci/pcireg.h> 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/czreg.h> 93 94 #include <dev/pci/plx9060reg.h> 95 #include <dev/pci/plx9060var.h> 96 97 #include <dev/microcode/cyclades-z/cyzfirm.h> 98 99 #define CZ_DRIVER_VERSION 0x20000411 100 101 #define CZ_POLL_MS 20 102 103 /* These are the interrupts we always use. */ 104 #define CZ_INTERRUPTS \ 105 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 106 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 107 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 108 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 109 110 /* 111 * cztty_softc: 112 * 113 * Per-channel (TTY) state. 114 */ 115 struct cztty_softc { 116 struct cz_softc *sc_parent; 117 struct tty *sc_tty; 118 119 struct callout sc_diag_ch; 120 121 int sc_channel; /* Also used to flag unattached chan */ 122 #define CZTTY_CHANNEL_DEAD -1 123 124 bus_space_tag_t sc_chan_st; /* channel space tag */ 125 bus_space_handle_t sc_chan_sh; /* channel space handle */ 126 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 127 128 u_int sc_overflows, 129 sc_parity_errors, 130 sc_framing_errors, 131 sc_errors; 132 133 int sc_swflags; 134 135 u_int32_t sc_rs_control_dtr, 136 sc_chanctl_hw_flow, 137 sc_chanctl_comm_baud, 138 sc_chanctl_rs_control, 139 sc_chanctl_comm_data_l, 140 sc_chanctl_comm_parity; 141 }; 142 143 /* 144 * cz_softc: 145 * 146 * Per-board state. 147 */ 148 struct cz_softc { 149 struct device cz_dev; /* generic device info */ 150 struct plx9060_config cz_plx; /* PLX 9060 config info */ 151 bus_space_tag_t cz_win_st; /* window space tag */ 152 bus_space_handle_t cz_win_sh; /* window space handle */ 153 struct callout cz_callout; /* callout for polling-mode */ 154 155 void *cz_ih; /* interrupt handle */ 156 157 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 158 int cz_nchannels; /* number of channels */ 159 int cz_nopenchan; /* number of open channels */ 160 struct cztty_softc *cz_ports; /* our array of ports */ 161 162 bus_addr_t cz_fwctl; /* offset of firmware control */ 163 }; 164 165 int cz_match(struct device *, struct cfdata *, void *); 166 void cz_attach(struct device *, struct device *, void *); 167 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 168 169 struct cfattach cz_ca = { 170 sizeof(struct cz_softc), cz_match, cz_attach 171 }; 172 173 void cz_reset_board(struct cz_softc *); 174 int cz_load_firmware(struct cz_softc *); 175 176 int cz_intr(void *); 177 void cz_poll(void *); 178 int cztty_transmit(struct cztty_softc *, struct tty *); 179 int cztty_receive(struct cztty_softc *, struct tty *); 180 181 struct cztty_softc * cztty_getttysoftc(dev_t dev); 182 int cztty_findmajor(void); 183 int cztty_major; 184 int cztty_attached_ttys; 185 int cz_timeout_ticks; 186 187 cdev_decl(cztty); 188 189 void czttystart(struct tty *tp); 190 int czttyparam(struct tty *tp, struct termios *t); 191 void cztty_shutdown(struct cztty_softc *sc); 192 void cztty_modem(struct cztty_softc *sc, int onoff); 193 void cztty_break(struct cztty_softc *sc, int onoff); 194 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 195 int cztty_to_tiocm(struct cztty_softc *sc); 196 void cztty_diag(void *arg); 197 198 extern struct cfdriver cz_cd; 199 200 /* Macros to clear/set/test flags. */ 201 #define SET(t, f) (t) |= (f) 202 #define CLR(t, f) (t) &= ~(f) 203 #define ISSET(t, f) ((t) & (f)) 204 205 /* 206 * Macros to read and write the PLX. 207 */ 208 #define CZ_PLX_READ(cz, reg) \ 209 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 210 #define CZ_PLX_WRITE(cz, reg, val) \ 211 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 212 (reg), (val)) 213 214 /* 215 * Macros to read and write the FPGA. We must already be in the FPGA 216 * window for this. 217 */ 218 #define CZ_FPGA_READ(cz, reg) \ 219 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 220 #define CZ_FPGA_WRITE(cz, reg, val) \ 221 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 222 223 /* 224 * Macros to read and write the firmware control structures in board RAM. 225 */ 226 #define CZ_FWCTL_READ(cz, off) \ 227 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 228 (cz)->cz_fwctl + (off)) 229 230 #define CZ_FWCTL_WRITE(cz, off, val) \ 231 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 232 (cz)->cz_fwctl + (off), (val)) 233 234 /* 235 * Convenience macros for cztty routines. PLX window MUST be to RAM. 236 */ 237 #define CZTTY_CHAN_READ(sc, off) \ 238 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 239 240 #define CZTTY_CHAN_WRITE(sc, off, val) \ 241 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 242 (off), (val)) 243 244 #define CZTTY_BUF_READ(sc, off) \ 245 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 246 247 #define CZTTY_BUF_WRITE(sc, off, val) \ 248 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 249 (off), (val)) 250 251 /* 252 * Convenience macros. 253 */ 254 #define CZ_WIN_RAM(cz) \ 255 do { \ 256 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 257 delay(100); \ 258 } while (0) 259 260 #define CZ_WIN_FPGA(cz) \ 261 do { \ 262 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 263 delay(100); \ 264 } while (0) 265 266 /***************************************************************************** 267 * Cyclades-Z controller code starts here... 268 *****************************************************************************/ 269 270 /* 271 * cz_match: 272 * 273 * Determine if the given PCI device is a Cyclades-Z board. 274 */ 275 int 276 cz_match(struct device *parent, 277 struct cfdata *match, 278 void *aux) 279 { 280 struct pci_attach_args *pa = aux; 281 282 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 283 switch (PCI_PRODUCT(pa->pa_id)) { 284 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 285 return (1); 286 } 287 } 288 289 return (0); 290 } 291 292 /* 293 * cz_attach: 294 * 295 * A Cyclades-Z board was found; attach it. 296 */ 297 void 298 cz_attach(struct device *parent, 299 struct device *self, 300 void *aux) 301 { 302 struct cz_softc *cz = (void *) self; 303 struct pci_attach_args *pa = aux; 304 pci_intr_handle_t ih; 305 const char *intrstr = NULL; 306 struct cztty_softc *sc; 307 struct tty *tp; 308 int i; 309 310 printf(": Cyclades-Z multiport serial\n"); 311 312 cz->cz_plx.plx_pc = pa->pa_pc; 313 cz->cz_plx.plx_tag = pa->pa_tag; 314 315 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 316 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 317 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 318 printf("%s: unable to map PLX registers\n", 319 cz->cz_dev.dv_xname); 320 return; 321 } 322 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 323 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 324 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 325 printf("%s: unable to map device window\n", 326 cz->cz_dev.dv_xname); 327 return; 328 } 329 330 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 331 cz->cz_nopenchan = 0; 332 333 /* 334 * Make sure that the board is completely stopped. 335 */ 336 CZ_WIN_FPGA(cz); 337 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 338 339 /* 340 * Load the board's firmware. 341 */ 342 if (cz_load_firmware(cz) != 0) 343 return; 344 345 /* 346 * Now that we're ready to roll, map and establish the interrupt 347 * handler. 348 */ 349 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 350 pa->pa_intrline, &ih) != 0) { 351 /* 352 * The common case is for Cyclades-Z boards to run 353 * in polling mode, and thus not have an interrupt 354 * mapped for them. Don't bother reporting that 355 * the interrupt is not mappable, since this isn't 356 * really an error. 357 */ 358 cz->cz_ih = NULL; 359 goto polling_mode; 360 } else { 361 intrstr = pci_intr_string(pa->pa_pc, ih); 362 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 363 cz_intr, cz); 364 } 365 if (cz->cz_ih == NULL) { 366 printf("%s: unable to establish interrupt", 367 cz->cz_dev.dv_xname); 368 if (intrstr != NULL) 369 printf(" at %s", intrstr); 370 printf("\n"); 371 /* We will fall-back on polling mode. */ 372 } else 373 printf("%s: interrupting at %s\n", 374 cz->cz_dev.dv_xname, intrstr); 375 376 polling_mode: 377 if (cz->cz_ih == NULL) { 378 callout_init(&cz->cz_callout); 379 if (cz_timeout_ticks == 0) 380 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 381 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 382 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 383 cz_timeout_ticks == 1 ? "" : "s"); 384 } 385 386 if (cztty_major == 0) 387 cztty_major = cztty_findmajor(); 388 /* 389 * Allocate sufficient pointers for the children and 390 * attach them. Set all ports to a reasonable initial 391 * configuration while we're at it: 392 * 393 * disabled 394 * 8N1 395 * default baud rate 396 * hardware flow control. 397 */ 398 CZ_WIN_RAM(cz); 399 400 if (cz->cz_nchannels == 0) { 401 /* No channels? No more work to do! */ 402 return; 403 } 404 405 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 406 M_DEVBUF, M_WAITOK); 407 cztty_attached_ttys += cz->cz_nchannels; 408 memset(cz->cz_ports, 0, 409 sizeof(struct cztty_softc) * cz->cz_nchannels); 410 411 for (i = 0; i < cz->cz_nchannels; i++) { 412 sc = &cz->cz_ports[i]; 413 414 sc->sc_channel = i; 415 sc->sc_chan_st = cz->cz_win_st; 416 sc->sc_parent = cz; 417 418 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 419 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 420 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 421 printf("%s: unable to subregion channel %d control\n", 422 cz->cz_dev.dv_xname, i); 423 sc->sc_channel = CZTTY_CHANNEL_DEAD; 424 continue; 425 } 426 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 427 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 428 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 429 printf("%s: unable to subregion channel %d buffer\n", 430 cz->cz_dev.dv_xname, i); 431 sc->sc_channel = CZTTY_CHANNEL_DEAD; 432 continue; 433 } 434 435 callout_init(&sc->sc_diag_ch); 436 437 tp = ttymalloc(); 438 tp->t_dev = makedev(cztty_major, 439 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 440 tp->t_oproc = czttystart; 441 tp->t_param = czttyparam; 442 tty_attach(tp); 443 444 sc->sc_tty = tp; 445 446 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 447 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 448 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 449 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 450 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 451 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 452 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 453 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 454 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 455 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 456 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 457 } 458 } 459 460 /* 461 * cz_reset_board: 462 * 463 * Reset the board via the PLX. 464 */ 465 void 466 cz_reset_board(struct cz_softc *cz) 467 { 468 u_int32_t reg; 469 470 reg = CZ_PLX_READ(cz, PLX_CONTROL); 471 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 472 delay(1000); 473 474 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 475 delay(1000); 476 477 /* Now reload the PLX from its EEPROM. */ 478 reg = CZ_PLX_READ(cz, PLX_CONTROL); 479 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 480 delay(1000); 481 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 482 } 483 484 /* 485 * cz_load_firmware: 486 * 487 * Load the ZFIRM firmware into the board's RAM and start it 488 * running. 489 */ 490 int 491 cz_load_firmware(struct cz_softc *cz) 492 { 493 struct zfirm_header *zfh; 494 struct zfirm_config *zfc; 495 struct zfirm_block *zfb, *zblocks; 496 const u_int8_t *cp; 497 const char *board; 498 u_int32_t fid; 499 int i, j, nconfigs, nblocks, nbytes; 500 501 zfh = (struct zfirm_header *) cycladesz_firmware; 502 503 /* Find the config header. */ 504 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 505 printf("%s: bad ZFIRM config offset: 0x%x\n", 506 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 507 return (EIO); 508 } 509 zfc = (struct zfirm_config *)(cycladesz_firmware + 510 le32toh(zfh->zfh_configoff)); 511 nconfigs = le32toh(zfh->zfh_nconfig); 512 513 /* Locate the correct configuration for our board. */ 514 for (i = 0; i < nconfigs; i++, zfc++) { 515 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 516 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 517 break; 518 } 519 if (i == nconfigs) { 520 printf("%s: unable to locate config header\n", 521 cz->cz_dev.dv_xname); 522 return (EIO); 523 } 524 525 nblocks = le32toh(zfc->zfc_nblocks); 526 zblocks = (struct zfirm_block *)(cycladesz_firmware + 527 le32toh(zfh->zfh_blockoff)); 528 529 /* 530 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 531 * necessary. 532 */ 533 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 534 #if 0 535 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 536 #endif 537 ) { 538 #ifdef CZ_DEBUG 539 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 540 #endif 541 CZ_WIN_FPGA(cz); 542 for (i = 0; i < nblocks; i++) { 543 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 544 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 545 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 546 nbytes = le32toh(zfb->zfb_size); 547 cp = &cycladesz_firmware[ 548 le32toh(zfb->zfb_fileoff)]; 549 for (j = 0; j < nbytes; j++, cp++) { 550 bus_space_write_1(cz->cz_win_st, 551 cz->cz_win_sh, 0, *cp); 552 /* FPGA needs 30-100us to settle. */ 553 delay(10); 554 } 555 } 556 } 557 #ifdef CZ_DEBUG 558 printf("done\n"); 559 #endif 560 } 561 562 /* Now load the firmware. */ 563 CZ_WIN_RAM(cz); 564 565 for (i = 0; i < nblocks; i++) { 566 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 567 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 568 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 569 const u_int32_t *lp; 570 u_int32_t ro = le32toh(zfb->zfb_ramoff); 571 nbytes = le32toh(zfb->zfb_size); 572 lp = (const u_int32_t *) 573 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 574 for (j = 0; j < nbytes; j += 4, lp++) { 575 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 576 ro + j, le32toh(*lp)); 577 delay(10); 578 } 579 } 580 } 581 582 /* Now restart the MIPS. */ 583 CZ_WIN_FPGA(cz); 584 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 585 586 /* Wait for the MIPS to start, then report the results. */ 587 CZ_WIN_RAM(cz); 588 589 #ifdef CZ_DEBUG 590 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 591 #endif 592 for (i = 0; i < 100; i++) { 593 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 594 ZFIRM_SIG_OFF); 595 if (fid == ZFIRM_SIG) { 596 /* MIPS has booted. */ 597 break; 598 } else if (fid == ZFIRM_HLT) { 599 /* 600 * The MIPS has halted, usually due to a power 601 * shortage on the expansion module. 602 */ 603 printf("%s: MIPS halted; possible power supply " 604 "problem\n", cz->cz_dev.dv_xname); 605 return (EIO); 606 } else { 607 #ifdef CZ_DEBUG 608 if ((i % 8) == 0) 609 printf("."); 610 #endif 611 delay(250000); 612 } 613 } 614 #ifdef CZ_DEBUG 615 printf("\n"); 616 #endif 617 if (i == 100) { 618 CZ_WIN_FPGA(cz); 619 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 620 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 621 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 622 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 623 CZ_FPGA_READ(cz, FPGA_VERSION)); 624 return (EIO); 625 } 626 627 /* 628 * Locate the firmware control structures. 629 */ 630 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 631 ZFIRM_CTRLADDR_OFF); 632 #ifdef CZ_DEBUG 633 printf("%s: FWCTL structure at offset 0x%08lx\n", 634 cz->cz_dev.dv_xname, cz->cz_fwctl); 635 #endif 636 637 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 638 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 639 640 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 641 642 switch (cz->cz_mailbox0) { 643 case MAILBOX0_8Zo_V1: 644 board = "Cyclades-8Zo ver. 1"; 645 break; 646 647 case MAILBOX0_8Zo_V2: 648 board = "Cyclades-8Zo ver. 2"; 649 break; 650 651 case MAILBOX0_Ze_V1: 652 board = "Cyclades-Ze"; 653 break; 654 655 default: 656 board = "unknown Cyclades Z-series"; 657 break; 658 } 659 660 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 661 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 662 if (cz->cz_nchannels == 0) 663 printf("no channels attached, "); 664 else 665 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 666 cz->cz_nchannels, cztty_attached_ttys, 667 cztty_attached_ttys + (cz->cz_nchannels - 1)); 668 printf("firmware %x.%x.%x\n", 669 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 670 671 return (0); 672 } 673 674 /* 675 * cz_poll: 676 * 677 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 678 * ms. 679 */ 680 void 681 cz_poll(void *arg) 682 { 683 int s = spltty(); 684 struct cz_softc *cz = arg; 685 686 cz_intr(cz); 687 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 688 689 splx(s); 690 } 691 692 /* 693 * cz_intr: 694 * 695 * Interrupt service routine. 696 * 697 * We either are receiving an interrupt directly from the board, or we are 698 * in polling mode and it's time to poll. 699 */ 700 int 701 cz_intr(void *arg) 702 { 703 int rval = 0; 704 u_int command, channel, param; 705 struct cz_softc *cz = arg; 706 struct cztty_softc *sc; 707 struct tty *tp; 708 709 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 710 rval = 1; 711 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 712 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 713 714 /* now clear this interrupt, posslibly enabling another */ 715 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 716 717 if (cz->cz_ports == NULL) { 718 #ifdef CZ_DEBUG 719 printf("%s: interrupt on channel %d, but no channels\n", 720 cz->cz_dev.dv_xname, channel); 721 #endif 722 continue; 723 } 724 725 sc = &cz->cz_ports[channel]; 726 727 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 728 break; 729 730 tp = sc->sc_tty; 731 732 switch (command) { 733 case C_CM_TXFEMPTY: /* transmit cases */ 734 case C_CM_TXBEMPTY: 735 case C_CM_TXLOWWM: 736 case C_CM_INTBACK: 737 if (!ISSET(tp->t_state, TS_ISOPEN)) { 738 #ifdef CZ_DEBUG 739 printf("%s: tx intr on closed channel %d\n", 740 cz->cz_dev.dv_xname, channel); 741 #endif 742 break; 743 } 744 745 if (cztty_transmit(sc, tp)) { 746 /* 747 * Do wakeup stuff here. 748 */ 749 ttwakeup(tp); 750 wakeup(tp); 751 } 752 break; 753 754 case C_CM_RXNNDT: /* receive cases */ 755 case C_CM_RXHIWM: 756 case C_CM_INTBACK2: /* from restart ?? */ 757 #if 0 758 case C_CM_ICHAR: 759 #endif 760 if (!ISSET(tp->t_state, TS_ISOPEN)) { 761 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 762 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 763 break; 764 } 765 766 if (cztty_receive(sc, tp)) { 767 /* 768 * Do wakeup stuff here. 769 */ 770 ttwakeup(tp); 771 wakeup(tp); 772 } 773 break; 774 775 case C_CM_MDCD: 776 if (!ISSET(tp->t_state, TS_ISOPEN)) 777 break; 778 779 (void) (*tp->t_linesw->l_modem)(tp, 780 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 781 CHNCTL_RS_STATUS))); 782 break; 783 784 case C_CM_MDSR: 785 case C_CM_MRI: 786 case C_CM_MCTS: 787 case C_CM_MRTS: 788 break; 789 790 case C_CM_IOCTLW: 791 break; 792 793 case C_CM_PR_ERROR: 794 sc->sc_parity_errors++; 795 goto error_common; 796 797 case C_CM_FR_ERROR: 798 sc->sc_framing_errors++; 799 goto error_common; 800 801 case C_CM_OVR_ERROR: 802 sc->sc_overflows++; 803 error_common: 804 if (sc->sc_errors++ == 0) 805 callout_reset(&sc->sc_diag_ch, 60 * hz, 806 cztty_diag, sc); 807 break; 808 809 case C_CM_RXBRK: 810 if (!ISSET(tp->t_state, TS_ISOPEN)) 811 break; 812 813 /* 814 * A break is a \000 character with TTY_FE error 815 * flags set. So TTY_FE by itself works. 816 */ 817 (*tp->t_linesw->l_rint)(TTY_FE, tp); 818 ttwakeup(tp); 819 wakeup(tp); 820 break; 821 822 default: 823 #ifdef CZ_DEBUG 824 printf("%s: channel %d: Unknown interrupt 0x%x\n", 825 cz->cz_dev.dv_xname, sc->sc_channel, command); 826 #endif 827 break; 828 } 829 } 830 831 return (rval); 832 } 833 834 /* 835 * cz_wait_pci_doorbell: 836 * 837 * Wait for the pci doorbell to be clear - wait for pending 838 * activity to drain. 839 */ 840 int 841 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 842 { 843 int error; 844 845 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 846 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 847 if ((error != 0) && (error != EWOULDBLOCK)) 848 return (error); 849 } 850 return (0); 851 } 852 853 /***************************************************************************** 854 * Cyclades-Z TTY code starts here... 855 *****************************************************************************/ 856 857 #define CZTTYCHAN_MASK 0x0003f 858 #define CZTTYBOARD_MASK (0x7ffff & ~CZTTYCHAN_MASK) 859 #define CZTTYBOARD_SHIFT 6 860 #define CZTTYDIALOUT_MASK 0x80000 861 862 #define CZTTY_CHAN(dev) (minor((dev)) & CZTTYCHAN_MASK) 863 #define CZTTY_BOARD(dev) ((minor((dev)) & CZTTYBOARD_MASK) >> \ 864 CZTTYBOARD_SHIFT) 865 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 866 #define CZTTY_CZ(sc) ((sc)->sc_parent) 867 868 #define CZ_SOFTC(dev) \ 869 ((struct cz_softc *)(CZTTY_BOARD(dev) < cz_cd.cd_ndevs ? \ 870 cz_cd.cd_devs[CZTTY_BOARD(dev)] : NULL)) 871 872 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 873 874 struct cztty_softc * 875 cztty_getttysoftc(dev_t dev) 876 { 877 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 878 struct cz_softc *cz; 879 880 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 881 k = j; 882 cz = cz_cd.cd_devs[i]; 883 if (cz->cz_ports == NULL) 884 continue; 885 j += cz->cz_nchannels; 886 if (j > u) 887 break; 888 } 889 890 if (i >= cz_cd.cd_ndevs) { 891 return (NULL); 892 } else 893 return (&cz->cz_ports[u - k]); 894 } 895 896 int 897 cztty_findmajor(void) 898 { 899 int maj; 900 901 for (maj = 0; maj < nchrdev; maj++) { 902 if (cdevsw[maj].d_open == czttyopen) 903 break; 904 } 905 906 return (maj == nchrdev) ? 0 : maj; 907 } 908 909 /* 910 * czttytty: 911 * 912 * Return a pointer to our tty. 913 */ 914 struct tty * 915 czttytty(dev_t dev) 916 { 917 struct cztty_softc *sc = CZTTY_SOFTC(dev); 918 919 #ifdef DIAGNOSTIC 920 if (sc == NULL) 921 panic("czttytty"); 922 #endif 923 924 return (sc->sc_tty); 925 } 926 927 /* 928 * cztty_shutdown: 929 * 930 * Shut down a port. 931 */ 932 void 933 cztty_shutdown(struct cztty_softc *sc) 934 { 935 struct cz_softc *cz = CZTTY_CZ(sc); 936 struct tty *tp = sc->sc_tty; 937 int s; 938 939 s = spltty(); 940 941 /* Clear any break condition set with TIOCSBRK. */ 942 cztty_break(sc, 0); 943 944 /* 945 * Hang up if necessary. Wait a bit, so the other side has time to 946 * notice even if we immediately open the port again. 947 */ 948 if (ISSET(tp->t_cflag, HUPCL)) { 949 cztty_modem(sc, 0); 950 (void) tsleep(tp, TTIPRI, ttclos, hz); 951 } 952 953 /* Disable the channel. */ 954 cz_wait_pci_doorbell(cz, "czdis"); 955 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 956 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 957 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 958 959 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 960 #ifdef CZ_DEBUG 961 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 962 #endif 963 callout_stop(&cz->cz_callout); 964 } 965 966 splx(s); 967 } 968 969 /* 970 * czttyopen: 971 * 972 * Open a Cyclades-Z serial port. 973 */ 974 int 975 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 976 { 977 struct cztty_softc *sc = CZTTY_SOFTC(dev); 978 struct cz_softc *cz; 979 struct tty *tp; 980 int s, error; 981 982 if (sc == NULL) 983 return (ENXIO); 984 985 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 986 return (ENXIO); 987 988 cz = CZTTY_CZ(sc); 989 tp = sc->sc_tty; 990 991 if (ISSET(tp->t_state, TS_ISOPEN) && 992 ISSET(tp->t_state, TS_XCLUDE) && 993 p->p_ucred->cr_uid != 0) 994 return (EBUSY); 995 996 s = spltty(); 997 998 /* 999 * Do the following iff this is a first open. 1000 */ 1001 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 1002 struct termios t; 1003 1004 tp->t_dev = dev; 1005 1006 /* If we're turning things on, enable interrupts */ 1007 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 1008 #ifdef CZ_DEBUG 1009 printf("%s: Enabling polling.\n", 1010 cz->cz_dev.dv_xname); 1011 #endif 1012 callout_reset(&cz->cz_callout, cz_timeout_ticks, 1013 cz_poll, cz); 1014 } 1015 1016 /* 1017 * Enable the channel. Don't actually ring the 1018 * doorbell here; czttyparam() will do it for us. 1019 */ 1020 cz_wait_pci_doorbell(cz, "czopen"); 1021 1022 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1023 1024 /* 1025 * Initialize the termios status to the defaults. Add in the 1026 * sticky bits from TIOCSFLAGS. 1027 */ 1028 t.c_ispeed = 0; 1029 t.c_ospeed = TTYDEF_SPEED; 1030 t.c_cflag = TTYDEF_CFLAG; 1031 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1032 SET(t.c_cflag, CLOCAL); 1033 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1034 SET(t.c_cflag, CRTSCTS); 1035 1036 /* 1037 * Reset the input and output rings. Do this before 1038 * we call czttyparam(), as that function enables 1039 * the channel. 1040 */ 1041 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1042 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1043 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1044 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1045 1046 /* Make sure czttyparam() will see changes. */ 1047 tp->t_ospeed = 0; 1048 (void) czttyparam(tp, &t); 1049 tp->t_iflag = TTYDEF_IFLAG; 1050 tp->t_oflag = TTYDEF_OFLAG; 1051 tp->t_lflag = TTYDEF_LFLAG; 1052 ttychars(tp); 1053 ttsetwater(tp); 1054 1055 /* 1056 * Turn on DTR. We must always do this, even if carrier is not 1057 * present, because otherwise we'd have to use TIOCSDTR 1058 * immediately after setting CLOCAL, which applications do not 1059 * expect. We always assert DTR while the device is open 1060 * unless explicitly requested to deassert it. 1061 */ 1062 cztty_modem(sc, 1); 1063 } 1064 1065 splx(s); 1066 1067 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1068 if (error) 1069 goto bad; 1070 1071 error = (*tp->t_linesw->l_open)(dev, tp); 1072 if (error) 1073 goto bad; 1074 1075 return (0); 1076 1077 bad: 1078 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1079 /* 1080 * We failed to open the device, and nobody else had it opened. 1081 * Clean up the state as appropriate. 1082 */ 1083 cztty_shutdown(sc); 1084 } 1085 1086 return (error); 1087 } 1088 1089 /* 1090 * czttyclose: 1091 * 1092 * Close a Cyclades-Z serial port. 1093 */ 1094 int 1095 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1096 { 1097 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1098 struct tty *tp = sc->sc_tty; 1099 1100 /* XXX This is for cons.c. */ 1101 if (!ISSET(tp->t_state, TS_ISOPEN)) 1102 return (0); 1103 1104 (*tp->t_linesw->l_close)(tp, flags); 1105 ttyclose(tp); 1106 1107 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1108 /* 1109 * Although we got a last close, the device may still be in 1110 * use; e.g. if this was the dialout node, and there are still 1111 * processes waiting for carrier on the non-dialout node. 1112 */ 1113 cztty_shutdown(sc); 1114 } 1115 1116 return (0); 1117 } 1118 1119 /* 1120 * czttyread: 1121 * 1122 * Read from a Cyclades-Z serial port. 1123 */ 1124 int 1125 czttyread(dev_t dev, struct uio *uio, int flags) 1126 { 1127 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1128 struct tty *tp = sc->sc_tty; 1129 1130 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1131 } 1132 1133 /* 1134 * czttywrite: 1135 * 1136 * Write to a Cyclades-Z serial port. 1137 */ 1138 int 1139 czttywrite(dev_t dev, struct uio *uio, int flags) 1140 { 1141 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1142 struct tty *tp = sc->sc_tty; 1143 1144 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1145 } 1146 1147 /* 1148 * czttyioctl: 1149 * 1150 * Perform a control operation on a Cyclades-Z serial port. 1151 */ 1152 int 1153 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1154 { 1155 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1156 struct tty *tp = sc->sc_tty; 1157 int s, error; 1158 1159 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 1160 if (error >= 0) 1161 return (error); 1162 1163 error = ttioctl(tp, cmd, data, flag, p); 1164 if (error >= 0) 1165 return (error); 1166 1167 error = 0; 1168 1169 s = spltty(); 1170 1171 switch (cmd) { 1172 case TIOCSBRK: 1173 cztty_break(sc, 1); 1174 break; 1175 1176 case TIOCCBRK: 1177 cztty_break(sc, 0); 1178 break; 1179 1180 case TIOCGFLAGS: 1181 *(int *)data = sc->sc_swflags; 1182 break; 1183 1184 case TIOCSFLAGS: 1185 error = suser(p->p_ucred, &p->p_acflag); 1186 if (error) 1187 break; 1188 sc->sc_swflags = *(int *)data; 1189 break; 1190 1191 case TIOCSDTR: 1192 cztty_modem(sc, 1); 1193 break; 1194 1195 case TIOCCDTR: 1196 cztty_modem(sc, 0); 1197 break; 1198 1199 case TIOCMSET: 1200 case TIOCMBIS: 1201 case TIOCMBIC: 1202 tiocm_to_cztty(sc, cmd, *(int *)data); 1203 break; 1204 1205 case TIOCMGET: 1206 *(int *)data = cztty_to_tiocm(sc); 1207 break; 1208 1209 default: 1210 error = ENOTTY; 1211 break; 1212 } 1213 1214 splx(s); 1215 1216 return (error); 1217 } 1218 1219 /* 1220 * cztty_break: 1221 * 1222 * Set or clear BREAK on a port. 1223 */ 1224 void 1225 cztty_break(struct cztty_softc *sc, int onoff) 1226 { 1227 struct cz_softc *cz = CZTTY_CZ(sc); 1228 1229 cz_wait_pci_doorbell(cz, "czbreak"); 1230 1231 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1232 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1233 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1234 } 1235 1236 /* 1237 * cztty_modem: 1238 * 1239 * Set or clear DTR on a port. 1240 */ 1241 void 1242 cztty_modem(struct cztty_softc *sc, int onoff) 1243 { 1244 struct cz_softc *cz = CZTTY_CZ(sc); 1245 1246 if (sc->sc_rs_control_dtr == 0) 1247 return; 1248 1249 cz_wait_pci_doorbell(cz, "czmod"); 1250 1251 if (onoff) 1252 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1253 else 1254 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1255 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1256 1257 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1258 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1259 } 1260 1261 /* 1262 * tiocm_to_cztty: 1263 * 1264 * Process TIOCM* ioctls. 1265 */ 1266 void 1267 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1268 { 1269 struct cz_softc *cz = CZTTY_CZ(sc); 1270 u_int32_t czttybits; 1271 1272 czttybits = 0; 1273 if (ISSET(ttybits, TIOCM_DTR)) 1274 SET(czttybits, C_RS_DTR); 1275 if (ISSET(ttybits, TIOCM_RTS)) 1276 SET(czttybits, C_RS_RTS); 1277 1278 cz_wait_pci_doorbell(cz, "cztiocm"); 1279 1280 switch (how) { 1281 case TIOCMBIC: 1282 CLR(sc->sc_chanctl_rs_control, czttybits); 1283 break; 1284 1285 case TIOCMBIS: 1286 SET(sc->sc_chanctl_rs_control, czttybits); 1287 break; 1288 1289 case TIOCMSET: 1290 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1291 SET(sc->sc_chanctl_rs_control, czttybits); 1292 break; 1293 } 1294 1295 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1296 1297 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1298 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1299 } 1300 1301 /* 1302 * cztty_to_tiocm: 1303 * 1304 * Process the TIOCMGET ioctl. 1305 */ 1306 int 1307 cztty_to_tiocm(struct cztty_softc *sc) 1308 { 1309 struct cz_softc *cz = CZTTY_CZ(sc); 1310 u_int32_t rs_status, op_mode; 1311 int ttybits = 0; 1312 1313 cz_wait_pci_doorbell(cz, "cztty"); 1314 1315 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1316 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1317 1318 if (ISSET(rs_status, C_RS_RTS)) 1319 SET(ttybits, TIOCM_RTS); 1320 if (ISSET(rs_status, C_RS_CTS)) 1321 SET(ttybits, TIOCM_CTS); 1322 if (ISSET(rs_status, C_RS_DCD)) 1323 SET(ttybits, TIOCM_CAR); 1324 if (ISSET(rs_status, C_RS_DTR)) 1325 SET(ttybits, TIOCM_DTR); 1326 if (ISSET(rs_status, C_RS_RI)) 1327 SET(ttybits, TIOCM_RNG); 1328 if (ISSET(rs_status, C_RS_DSR)) 1329 SET(ttybits, TIOCM_DSR); 1330 1331 if (ISSET(op_mode, C_CH_ENABLE)) 1332 SET(ttybits, TIOCM_LE); 1333 1334 return (ttybits); 1335 } 1336 1337 /* 1338 * czttyparam: 1339 * 1340 * Set Cyclades-Z serial port parameters from termios. 1341 * 1342 * XXX Should just copy the whole termios after making 1343 * XXX sure all the changes could be done. 1344 */ 1345 int 1346 czttyparam(struct tty *tp, struct termios *t) 1347 { 1348 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1349 struct cz_softc *cz = CZTTY_CZ(sc); 1350 u_int32_t rs_status; 1351 int ospeed, cflag; 1352 1353 ospeed = t->c_ospeed; 1354 cflag = t->c_cflag; 1355 1356 /* Check requested parameters. */ 1357 if (ospeed < 0) 1358 return (EINVAL); 1359 if (t->c_ispeed && t->c_ispeed != ospeed) 1360 return (EINVAL); 1361 1362 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1363 SET(cflag, CLOCAL); 1364 CLR(cflag, HUPCL); 1365 } 1366 1367 /* 1368 * If there were no changes, don't do anything. This avoids dropping 1369 * input and improves performance when all we did was frob things like 1370 * VMIN and VTIME. 1371 */ 1372 if (tp->t_ospeed == ospeed && 1373 tp->t_cflag == cflag) 1374 return (0); 1375 1376 /* Data bits. */ 1377 sc->sc_chanctl_comm_data_l = 0; 1378 switch (t->c_cflag & CSIZE) { 1379 case CS5: 1380 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1381 break; 1382 1383 case CS6: 1384 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1385 break; 1386 1387 case CS7: 1388 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1389 break; 1390 1391 case CS8: 1392 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1393 break; 1394 } 1395 1396 /* Stop bits. */ 1397 if (t->c_cflag & CSTOPB) { 1398 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1399 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1400 else 1401 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1402 } else 1403 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1404 1405 /* Parity. */ 1406 if (t->c_cflag & PARENB) { 1407 if (t->c_cflag & PARODD) 1408 sc->sc_chanctl_comm_parity = C_PR_ODD; 1409 else 1410 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1411 } else 1412 sc->sc_chanctl_comm_parity = C_PR_NONE; 1413 1414 /* 1415 * Initialize flow control pins depending on the current flow control 1416 * mode. 1417 */ 1418 if (ISSET(t->c_cflag, CRTSCTS)) { 1419 sc->sc_rs_control_dtr = C_RS_DTR; 1420 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1421 } else if (ISSET(t->c_cflag, MDMBUF)) { 1422 sc->sc_rs_control_dtr = 0; 1423 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1424 } else { 1425 /* 1426 * If no flow control, then always set RTS. This will make 1427 * the other side happy if it mistakenly thinks we're doing 1428 * RTS/CTS flow control. 1429 */ 1430 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1431 sc->sc_chanctl_hw_flow = 0; 1432 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1433 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1434 else 1435 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1436 } 1437 1438 /* Baud rate. */ 1439 sc->sc_chanctl_comm_baud = ospeed; 1440 1441 /* Copy to tty. */ 1442 tp->t_ispeed = 0; 1443 tp->t_ospeed = t->c_ospeed; 1444 tp->t_cflag = t->c_cflag; 1445 1446 /* 1447 * Now load the channel control structure. 1448 */ 1449 1450 cz_wait_pci_doorbell(cz, "czparam"); 1451 1452 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1453 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1454 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1455 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1456 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1457 1458 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1459 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1460 1461 cz_wait_pci_doorbell(cz, "czparam"); 1462 1463 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1464 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1465 1466 cz_wait_pci_doorbell(cz, "czparam"); 1467 1468 /* 1469 * Update the tty layer's idea of the carrier bit, in case we changed 1470 * CLOCAL. We don't hang up here; we only do that by explicit 1471 * request. 1472 */ 1473 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1474 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1475 1476 return (0); 1477 } 1478 1479 /* 1480 * czttystart: 1481 * 1482 * Start or restart transmission. 1483 */ 1484 void 1485 czttystart(struct tty *tp) 1486 { 1487 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1488 int s; 1489 1490 s = spltty(); 1491 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1492 goto out; 1493 1494 if (tp->t_outq.c_cc <= tp->t_lowat) { 1495 if (ISSET(tp->t_state, TS_ASLEEP)) { 1496 CLR(tp->t_state, TS_ASLEEP); 1497 wakeup(&tp->t_outq); 1498 } 1499 selwakeup(&tp->t_wsel); 1500 if (tp->t_outq.c_cc == 0) 1501 goto out; 1502 } 1503 1504 cztty_transmit(sc, tp); 1505 out: 1506 splx(s); 1507 } 1508 1509 /* 1510 * czttystop: 1511 * 1512 * Stop output, e.g., for ^S or output flush. 1513 */ 1514 void 1515 czttystop(struct tty *tp, int flag) 1516 { 1517 1518 /* 1519 * XXX We don't do anything here, yet. Mostly, I don't know 1520 * XXX exactly how this should be implemented on this device. 1521 * XXX We've given a big chunk of data to the MIPS already, 1522 * XXX and I don't know how we request the MIPS to stop sending 1523 * XXX the data. So, punt for now. --thorpej 1524 */ 1525 } 1526 1527 /* 1528 * cztty_diag: 1529 * 1530 * Issue a scheduled diagnostic message. 1531 */ 1532 void 1533 cztty_diag(void *arg) 1534 { 1535 struct cztty_softc *sc = arg; 1536 struct cz_softc *cz = CZTTY_CZ(sc); 1537 u_int overflows, parity_errors, framing_errors; 1538 int s; 1539 1540 s = spltty(); 1541 1542 overflows = sc->sc_overflows; 1543 sc->sc_overflows = 0; 1544 1545 parity_errors = sc->sc_parity_errors; 1546 sc->sc_parity_errors = 0; 1547 1548 framing_errors = sc->sc_framing_errors; 1549 sc->sc_framing_errors = 0; 1550 1551 sc->sc_errors = 0; 1552 1553 splx(s); 1554 1555 log(LOG_WARNING, 1556 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1557 cz->cz_dev.dv_xname, sc->sc_channel, 1558 overflows, overflows == 1 ? "" : "s", 1559 parity_errors, 1560 framing_errors, framing_errors == 1 ? "" : "s"); 1561 } 1562 1563 /* 1564 * tx and rx ring buffer size macros: 1565 * 1566 * The transmitter and receiver both use ring buffers. For each one, there 1567 * is a get (consumer) and a put (producer) offset. The get value is the 1568 * next byte to be read from the ring, and the put is the next one to be 1569 * put into the ring. get == put means the ring is empty. 1570 * 1571 * For each ring, the firmware controls one of (get, put) and this driver 1572 * controls the other. For transmission, this driver updates put to point 1573 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1574 * for receive, the driver controls put, and this driver controls get. 1575 */ 1576 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1577 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1578 1579 /* 1580 * cztty_transmit() 1581 * 1582 * Look at the tty for this port and start sending. 1583 */ 1584 int 1585 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1586 { 1587 struct cz_softc *cz = CZTTY_CZ(sc); 1588 u_int move, get, put, size, address; 1589 #ifdef HOSTRAMCODE 1590 int error, done = 0; 1591 #else 1592 int done = 0; 1593 #endif 1594 1595 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1596 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1597 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1598 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1599 1600 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1601 #ifdef HOSTRAMCODE 1602 if (0) { 1603 move = min(tp->t_outq.c_cc, move); 1604 error = q_to_b(&tp->t_outq, 0, move); 1605 if (error != move) { 1606 printf("%s: channel %d: error moving to " 1607 "transmit buf\n", cz->cz_dev.dv_xname, 1608 sc->sc_channel); 1609 move = error; 1610 } 1611 } else { 1612 #endif 1613 move = min(ndqb(&tp->t_outq, 0), move); 1614 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1615 address + put, tp->t_outq.c_cf, move); 1616 ndflush(&tp->t_outq, move); 1617 #ifdef HOSTRAMCODE 1618 } 1619 #endif 1620 1621 put = ((put + move) % size); 1622 done = 1; 1623 } 1624 if (done) { 1625 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1626 } 1627 return (done); 1628 } 1629 1630 int 1631 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1632 { 1633 struct cz_softc *cz = CZTTY_CZ(sc); 1634 u_int get, put, size, address; 1635 int done = 0, ch; 1636 1637 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1638 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1639 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1640 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1641 1642 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1643 #ifdef HOSTRAMCODE 1644 if (hostram) 1645 ch = ((char *)fifoaddr)[get]; 1646 } else { 1647 #endif 1648 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1649 address + get); 1650 #ifdef HOSTRAMCODE 1651 } 1652 #endif 1653 (*tp->t_linesw->l_rint)(ch, tp); 1654 get = (get + 1) % size; 1655 done = 1; 1656 } 1657 if (done) { 1658 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1659 } 1660 return (done); 1661 } 1662