1 /* $NetBSD: cz.c,v 1.9 2000/06/14 17:54:33 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only utilize RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/proc.h> 78 #include <sys/device.h> 79 #include <sys/malloc.h> 80 #include <sys/tty.h> 81 #include <sys/conf.h> 82 #include <sys/time.h> 83 #include <sys/kernel.h> 84 #include <sys/fcntl.h> 85 #include <sys/syslog.h> 86 87 #include <sys/callout.h> 88 89 #include <dev/pci/pcireg.h> 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/czreg.h> 93 94 #include <dev/pci/plx9060reg.h> 95 #include <dev/pci/plx9060var.h> 96 97 #include <dev/microcode/cyclades-z/cyzfirm.h> 98 99 #define CZ_DRIVER_VERSION 0x20000411 100 101 #define CZ_POLL_MS 20 102 103 /* These are the interrupts we always use. */ 104 #define CZ_INTERRUPTS \ 105 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 106 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 107 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 108 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 109 110 /* 111 * cztty_softc: 112 * 113 * Per-channel (TTY) state. 114 */ 115 struct cztty_softc { 116 struct cz_softc *sc_parent; 117 struct tty *sc_tty; 118 119 struct callout sc_diag_ch; 120 121 int sc_channel; /* Also used to flag unattached chan */ 122 #define CZTTY_CHANNEL_DEAD -1 123 124 bus_space_tag_t sc_chan_st; /* channel space tag */ 125 bus_space_handle_t sc_chan_sh; /* channel space handle */ 126 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 127 128 u_int sc_overflows, 129 sc_parity_errors, 130 sc_framing_errors, 131 sc_errors; 132 133 int sc_swflags; 134 135 u_int32_t sc_rs_control_dtr, 136 sc_chanctl_hw_flow, 137 sc_chanctl_comm_baud, 138 sc_chanctl_rs_control, 139 sc_chanctl_comm_data_l, 140 sc_chanctl_comm_parity; 141 }; 142 143 /* 144 * cz_softc: 145 * 146 * Per-board state. 147 */ 148 struct cz_softc { 149 struct device cz_dev; /* generic device info */ 150 struct plx9060_config cz_plx; /* PLX 9060 config info */ 151 bus_space_tag_t cz_win_st; /* window space tag */ 152 bus_space_handle_t cz_win_sh; /* window space handle */ 153 struct callout cz_callout; /* callout for polling-mode */ 154 155 void *cz_ih; /* interrupt handle */ 156 157 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 158 int cz_nchannels; /* number of channels */ 159 int cz_nopenchan; /* number of open channels */ 160 struct cztty_softc *cz_ports; /* our array of ports */ 161 162 bus_addr_t cz_fwctl; /* offset of firmware control */ 163 }; 164 165 int cz_match(struct device *, struct cfdata *, void *); 166 void cz_attach(struct device *, struct device *, void *); 167 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 168 169 struct cfattach cz_ca = { 170 sizeof(struct cz_softc), cz_match, cz_attach 171 }; 172 173 void cz_reset_board(struct cz_softc *); 174 int cz_load_firmware(struct cz_softc *); 175 176 int cz_intr(void *); 177 void cz_poll(void *); 178 int cztty_transmit(struct cztty_softc *, struct tty *); 179 int cztty_receive(struct cztty_softc *, struct tty *); 180 181 struct cztty_softc * cztty_getttysoftc(dev_t dev); 182 int cztty_findmajor(void); 183 int cztty_major; 184 int cztty_attached_ttys; 185 int cz_timeout_ticks; 186 187 cdev_decl(cztty); 188 189 void czttystart(struct tty *tp); 190 int czttyparam(struct tty *tp, struct termios *t); 191 void cztty_shutdown(struct cztty_softc *sc); 192 void cztty_modem(struct cztty_softc *sc, int onoff); 193 void cztty_break(struct cztty_softc *sc, int onoff); 194 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 195 int cztty_to_tiocm(struct cztty_softc *sc); 196 void cztty_diag(void *arg); 197 198 extern struct cfdriver cz_cd; 199 200 /* Macros to clear/set/test flags. */ 201 #define SET(t, f) (t) |= (f) 202 #define CLR(t, f) (t) &= ~(f) 203 #define ISSET(t, f) ((t) & (f)) 204 205 /* 206 * Macros to read and write the PLX. 207 */ 208 #define CZ_PLX_READ(cz, reg) \ 209 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 210 #define CZ_PLX_WRITE(cz, reg, val) \ 211 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 212 (reg), (val)) 213 214 /* 215 * Macros to read and write the FPGA. We must already be in the FPGA 216 * window for this. 217 */ 218 #define CZ_FPGA_READ(cz, reg) \ 219 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 220 #define CZ_FPGA_WRITE(cz, reg, val) \ 221 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 222 223 /* 224 * Macros to read and write the firmware control structures in board RAM. 225 */ 226 #define CZ_FWCTL_READ(cz, off) \ 227 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 228 (cz)->cz_fwctl + (off)) 229 230 #define CZ_FWCTL_WRITE(cz, off, val) \ 231 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 232 (cz)->cz_fwctl + (off), (val)) 233 234 /* 235 * Convenience macros for cztty routines. PLX window MUST be to RAM. 236 */ 237 #define CZTTY_CHAN_READ(sc, off) \ 238 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 239 240 #define CZTTY_CHAN_WRITE(sc, off, val) \ 241 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 242 (off), (val)) 243 244 #define CZTTY_BUF_READ(sc, off) \ 245 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 246 247 #define CZTTY_BUF_WRITE(sc, off, val) \ 248 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 249 (off), (val)) 250 251 /* 252 * Convenience macros. 253 */ 254 #define CZ_WIN_RAM(cz) \ 255 do { \ 256 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 257 delay(100); \ 258 } while (0) 259 260 #define CZ_WIN_FPGA(cz) \ 261 do { \ 262 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 263 delay(100); \ 264 } while (0) 265 266 /***************************************************************************** 267 * Cyclades-Z controller code starts here... 268 *****************************************************************************/ 269 270 /* 271 * cz_match: 272 * 273 * Determine if the given PCI device is a Cyclades-Z board. 274 */ 275 int 276 cz_match(struct device *parent, 277 struct cfdata *match, 278 void *aux) 279 { 280 struct pci_attach_args *pa = aux; 281 282 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 283 switch (PCI_PRODUCT(pa->pa_id)) { 284 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 285 return (1); 286 } 287 } 288 289 return (0); 290 } 291 292 /* 293 * cz_attach: 294 * 295 * A Cyclades-Z board was found; attach it. 296 */ 297 void 298 cz_attach(struct device *parent, 299 struct device *self, 300 void *aux) 301 { 302 struct cz_softc *cz = (void *) self; 303 struct pci_attach_args *pa = aux; 304 pci_intr_handle_t ih; 305 const char *intrstr = NULL; 306 struct cztty_softc *sc; 307 struct tty *tp; 308 int i; 309 310 printf(": Cyclades-Z multiport serial\n"); 311 312 cz->cz_plx.plx_pc = pa->pa_pc; 313 cz->cz_plx.plx_tag = pa->pa_tag; 314 315 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 316 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 317 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 318 printf("%s: unable to map PLX registers\n", 319 cz->cz_dev.dv_xname); 320 return; 321 } 322 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 323 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 324 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 325 printf("%s: unable to map device window\n", 326 cz->cz_dev.dv_xname); 327 return; 328 } 329 330 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 331 cz->cz_nopenchan = 0; 332 333 /* 334 * Make sure that the board is completely stopped. 335 */ 336 CZ_WIN_FPGA(cz); 337 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 338 339 /* 340 * Load the board's firmware. 341 */ 342 if (cz_load_firmware(cz) != 0) 343 return; 344 345 /* 346 * Now that we're ready to roll, map and establish the interrupt 347 * handler. 348 */ 349 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 350 pa->pa_intrline, &ih) != 0) { 351 /* 352 * The common case is for Cyclades-Z boards to run 353 * in polling mode, and thus not have an interrupt 354 * mapped for them. Don't bother reporting that 355 * the interrupt is not mappable, since this isn't 356 * really an error. 357 */ 358 cz->cz_ih = NULL; 359 goto polling_mode; 360 } else { 361 intrstr = pci_intr_string(pa->pa_pc, ih); 362 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 363 cz_intr, cz); 364 } 365 if (cz->cz_ih == NULL) { 366 printf("%s: unable to establish interrupt", 367 cz->cz_dev.dv_xname); 368 if (intrstr != NULL) 369 printf(" at %s", intrstr); 370 printf("\n"); 371 /* We will fall-back on polling mode. */ 372 } else 373 printf("%s: interrupting at %s\n", 374 cz->cz_dev.dv_xname, intrstr); 375 376 polling_mode: 377 if (cz->cz_ih == NULL) { 378 callout_init(&cz->cz_callout); 379 if (cz_timeout_ticks == 0) 380 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 381 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 382 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 383 cz_timeout_ticks == 1 ? "" : "s"); 384 } 385 386 if (cztty_major == 0) 387 cztty_major = cztty_findmajor(); 388 /* 389 * Allocate sufficient pointers for the children and 390 * attach them. Set all ports to a reasonable initial 391 * configuration while we're at it: 392 * 393 * disabled 394 * 8N1 395 * default baud rate 396 * hardware flow control. 397 */ 398 CZ_WIN_RAM(cz); 399 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 400 M_DEVBUF, M_WAITOK); 401 cztty_attached_ttys += cz->cz_nchannels; 402 memset(cz->cz_ports, 0, 403 sizeof(struct cztty_softc) * cz->cz_nchannels); 404 405 for (i = 0; i < cz->cz_nchannels; i++) { 406 sc = &cz->cz_ports[i]; 407 408 sc->sc_channel = i; 409 sc->sc_chan_st = cz->cz_win_st; 410 sc->sc_parent = cz; 411 412 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 413 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 414 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 415 printf("%s: unable to subregion channel %d control\n", 416 cz->cz_dev.dv_xname, i); 417 sc->sc_channel = CZTTY_CHANNEL_DEAD; 418 continue; 419 } 420 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 421 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 422 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 423 printf("%s: unable to subregion channel %d buffer\n", 424 cz->cz_dev.dv_xname, i); 425 sc->sc_channel = CZTTY_CHANNEL_DEAD; 426 continue; 427 } 428 429 callout_init(&sc->sc_diag_ch); 430 431 tp = ttymalloc(); 432 tp->t_dev = makedev(cztty_major, 433 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 434 tp->t_oproc = czttystart; 435 tp->t_param = czttyparam; 436 tty_attach(tp); 437 438 sc->sc_tty = tp; 439 440 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 441 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 442 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 443 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 444 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 445 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 446 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 447 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 448 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 449 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 450 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 451 } 452 } 453 454 /* 455 * cz_reset_board: 456 * 457 * Reset the board via the PLX. 458 */ 459 void 460 cz_reset_board(struct cz_softc *cz) 461 { 462 u_int32_t reg; 463 464 reg = CZ_PLX_READ(cz, PLX_CONTROL); 465 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 466 delay(1000); 467 468 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 469 delay(1000); 470 471 /* Now reload the PLX from its EEPROM. */ 472 reg = CZ_PLX_READ(cz, PLX_CONTROL); 473 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 474 delay(1000); 475 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 476 } 477 478 /* 479 * cz_load_firmware: 480 * 481 * Load the ZFIRM firmware into the board's RAM and start it 482 * running. 483 */ 484 int 485 cz_load_firmware(struct cz_softc *cz) 486 { 487 struct zfirm_header *zfh; 488 struct zfirm_config *zfc; 489 struct zfirm_block *zfb, *zblocks; 490 const u_int8_t *cp; 491 const char *board; 492 u_int32_t fid; 493 int i, j, nconfigs, nblocks, nbytes; 494 495 zfh = (struct zfirm_header *) cycladesz_firmware; 496 497 /* Find the config header. */ 498 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 499 printf("%s: bad ZFIRM config offset: 0x%x\n", 500 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 501 return (EIO); 502 } 503 zfc = (struct zfirm_config *)(cycladesz_firmware + 504 le32toh(zfh->zfh_configoff)); 505 nconfigs = le32toh(zfh->zfh_nconfig); 506 507 /* Locate the correct configuration for our board. */ 508 for (i = 0; i < nconfigs; i++, zfc++) { 509 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 510 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 511 break; 512 } 513 if (i == nconfigs) { 514 printf("%s: unable to locate config header\n", 515 cz->cz_dev.dv_xname); 516 return (EIO); 517 } 518 519 nblocks = le32toh(zfc->zfc_nblocks); 520 zblocks = (struct zfirm_block *)(cycladesz_firmware + 521 le32toh(zfh->zfh_blockoff)); 522 523 /* 524 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 525 * necessary. 526 */ 527 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 528 #if 0 529 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 530 #endif 531 ) { 532 #ifdef CZ_DEBUG 533 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 534 #endif 535 CZ_WIN_FPGA(cz); 536 for (i = 0; i < nblocks; i++) { 537 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 538 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 539 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 540 nbytes = le32toh(zfb->zfb_size); 541 cp = &cycladesz_firmware[ 542 le32toh(zfb->zfb_fileoff)]; 543 for (j = 0; j < nbytes; j++, cp++) { 544 bus_space_write_1(cz->cz_win_st, 545 cz->cz_win_sh, 0, *cp); 546 /* FPGA needs 30-100us to settle. */ 547 delay(10); 548 } 549 } 550 } 551 #ifdef CZ_DEBUG 552 printf("done\n"); 553 #endif 554 } 555 556 /* Now load the firmware. */ 557 CZ_WIN_RAM(cz); 558 559 for (i = 0; i < nblocks; i++) { 560 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 561 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 562 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 563 const u_int32_t *lp; 564 u_int32_t ro = le32toh(zfb->zfb_ramoff); 565 nbytes = le32toh(zfb->zfb_size); 566 lp = (const u_int32_t *) 567 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 568 for (j = 0; j < nbytes; j += 4, lp++) { 569 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 570 ro + j, le32toh(*lp)); 571 delay(10); 572 } 573 } 574 } 575 576 /* Now restart the MIPS. */ 577 CZ_WIN_FPGA(cz); 578 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 579 580 /* Wait for the MIPS to start, then report the results. */ 581 CZ_WIN_RAM(cz); 582 583 #ifdef CZ_DEBUG 584 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 585 #endif 586 for (i = 0; i < 100; i++) { 587 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 588 ZFIRM_SIG_OFF); 589 if (fid == ZFIRM_SIG) { 590 /* MIPS has booted. */ 591 break; 592 } else if (fid == ZFIRM_HLT) { 593 /* 594 * The MIPS has halted, usually due to a power 595 * shortage on the expansion module. 596 */ 597 printf("%s: MIPS halted; possible power supply " 598 "problem\n", cz->cz_dev.dv_xname); 599 return (EIO); 600 } else { 601 #ifdef CZ_DEBUG 602 if ((i % 8) == 0) 603 printf("."); 604 #endif 605 delay(250000); 606 } 607 } 608 #ifdef CZ_DEBUG 609 printf("\n"); 610 #endif 611 if (i == 100) { 612 CZ_WIN_FPGA(cz); 613 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 614 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 615 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 616 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 617 CZ_FPGA_READ(cz, FPGA_VERSION)); 618 return (EIO); 619 } 620 621 /* 622 * Locate the firmware control structures. 623 */ 624 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 625 ZFIRM_CTRLADDR_OFF); 626 #ifdef CZ_DEBUG 627 printf("%s: FWCTL structure at offset 0x%08lx\n", 628 cz->cz_dev.dv_xname, cz->cz_fwctl); 629 #endif 630 631 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 632 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 633 634 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 635 636 switch (cz->cz_mailbox0) { 637 case MAILBOX0_8Zo_V1: 638 board = "Cyclades-8Zo ver. 1"; 639 break; 640 641 case MAILBOX0_8Zo_V2: 642 board = "Cyclades-8Zo ver. 2"; 643 break; 644 645 case MAILBOX0_Ze_V1: 646 board = "Cyclades-Ze"; 647 break; 648 649 default: 650 board = "unknown Cyclades Z-series"; 651 break; 652 } 653 654 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 655 printf("%s: %s, %d channels (ttyCZ%04d..ttyCZ%04d), " 656 "firmware %x.%x.%x\n", 657 cz->cz_dev.dv_xname, board, cz->cz_nchannels, 658 cztty_attached_ttys, cztty_attached_ttys + (cz->cz_nchannels - 1), 659 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 660 661 return (0); 662 } 663 664 /* 665 * cz_poll: 666 * 667 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 668 * ms. 669 */ 670 void 671 cz_poll(void *arg) 672 { 673 int s = spltty(); 674 struct cz_softc *cz = arg; 675 676 cz_intr(cz); 677 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 678 679 splx(s); 680 } 681 682 /* 683 * cz_intr: 684 * 685 * Interrupt service routine. 686 * 687 * We either are receiving an interrupt directly from the board, or we are 688 * in polling mode and it's time to poll. 689 */ 690 int 691 cz_intr(void *arg) 692 { 693 int rval = 0; 694 u_int command, channel, param; 695 struct cz_softc *cz = arg; 696 struct cztty_softc *sc; 697 struct tty *tp; 698 699 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 700 rval = 1; 701 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 702 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 703 704 /* now clear this interrupt, posslibly enabling another */ 705 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 706 707 sc = &cz->cz_ports[channel]; 708 709 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 710 break; 711 712 tp = sc->sc_tty; 713 714 switch (command) { 715 case C_CM_TXFEMPTY: /* transmit cases */ 716 case C_CM_TXBEMPTY: 717 case C_CM_TXLOWWM: 718 case C_CM_INTBACK: 719 if (!ISSET(tp->t_state, TS_ISOPEN)) { 720 #ifdef CZ_DEBUG 721 printf("%s: tx intr on closed channel %d\n", 722 cz->cz_dev.dv_xname, channel); 723 #endif 724 break; 725 } 726 727 if (cztty_transmit(sc, tp)) { 728 /* 729 * Do wakeup stuff here. 730 */ 731 ttwakeup(tp); 732 wakeup(tp); 733 } 734 break; 735 736 case C_CM_RXNNDT: /* receive cases */ 737 case C_CM_RXHIWM: 738 case C_CM_INTBACK2: /* from restart ?? */ 739 #if 0 740 case C_CM_ICHAR: 741 #endif 742 if (!ISSET(tp->t_state, TS_ISOPEN)) { 743 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 744 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 745 break; 746 } 747 748 if (cztty_receive(sc, tp)) { 749 /* 750 * Do wakeup stuff here. 751 */ 752 ttwakeup(tp); 753 wakeup(tp); 754 } 755 break; 756 757 case C_CM_MDCD: 758 if (!ISSET(tp->t_state, TS_ISOPEN)) 759 break; 760 761 (void) (*linesw[tp->t_line].l_modem)(tp, 762 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 763 CHNCTL_RS_STATUS))); 764 break; 765 766 case C_CM_MDSR: 767 case C_CM_MRI: 768 case C_CM_MCTS: 769 case C_CM_MRTS: 770 break; 771 772 case C_CM_IOCTLW: 773 break; 774 775 case C_CM_PR_ERROR: 776 sc->sc_parity_errors++; 777 goto error_common; 778 779 case C_CM_FR_ERROR: 780 sc->sc_framing_errors++; 781 goto error_common; 782 783 case C_CM_OVR_ERROR: 784 sc->sc_overflows++; 785 error_common: 786 if (sc->sc_errors++ == 0) 787 callout_reset(&sc->sc_diag_ch, 60 * hz, 788 cztty_diag, sc); 789 break; 790 791 case C_CM_RXBRK: 792 if (!ISSET(tp->t_state, TS_ISOPEN)) 793 break; 794 795 /* 796 * A break is a \000 character with TTY_FE error 797 * flags set. So TTY_FE by itself works. 798 */ 799 (*linesw[tp->t_line].l_rint)(TTY_FE, tp); 800 ttwakeup(tp); 801 wakeup(tp); 802 break; 803 804 default: 805 #ifdef CZ_DEBUG 806 printf("%s: channel %d: Unknown interrupt 0x%x\n", 807 cz->cz_dev.dv_xname, sc->sc_channel, command); 808 #endif 809 break; 810 } 811 } 812 813 return (rval); 814 } 815 816 /* 817 * cz_wait_pci_doorbell: 818 * 819 * Wait for the pci doorbell to be clear - wait for pending 820 * activity to drain. 821 */ 822 int 823 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 824 { 825 int error; 826 827 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 828 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 829 if ((error != 0) && (error != EWOULDBLOCK)) 830 return (error); 831 } 832 return (0); 833 } 834 835 /***************************************************************************** 836 * Cyclades-Z TTY code starts here... 837 *****************************************************************************/ 838 839 #define CZTTYCHAN_MASK 0x0003f 840 #define CZTTYBOARD_MASK (0x7ffff & ~CZTTYCHAN_MASK) 841 #define CZTTYBOARD_SHIFT 6 842 #define CZTTYDIALOUT_MASK 0x80000 843 844 #define CZTTY_CHAN(dev) (minor((dev)) & CZTTYCHAN_MASK) 845 #define CZTTY_BOARD(dev) ((minor((dev)) & CZTTYBOARD_MASK) >> \ 846 CZTTYBOARD_SHIFT) 847 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 848 #define CZTTY_CZ(sc) ((sc)->sc_parent) 849 850 #define CZ_SOFTC(dev) \ 851 ((struct cz_softc *)(CZTTY_BOARD(dev) < cz_cd.cd_ndevs ? \ 852 cz_cd.cd_devs[CZTTY_BOARD(dev)] : NULL)) 853 854 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 855 856 struct cztty_softc * 857 cztty_getttysoftc(dev_t dev) 858 { 859 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 860 struct cz_softc *cz; 861 862 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 863 k = j; 864 cz = cz_cd.cd_devs[i]; 865 j += cz->cz_nchannels; 866 if (j > u) 867 break; 868 } 869 870 if (i >= cz_cd.cd_ndevs) { 871 return (NULL); 872 } else 873 return (&cz->cz_ports[u - k]); 874 } 875 876 int 877 cztty_findmajor(void) 878 { 879 int maj; 880 881 for (maj = 0; maj < nchrdev; maj++) { 882 if (cdevsw[maj].d_open == czttyopen) 883 break; 884 } 885 886 return (maj == nchrdev) ? 0 : maj; 887 } 888 889 /* 890 * czttytty: 891 * 892 * Return a pointer to our tty. 893 */ 894 struct tty * 895 czttytty(dev_t dev) 896 { 897 struct cztty_softc *sc = CZTTY_SOFTC(dev); 898 899 #ifdef DIAGNOSTIC 900 if (sc == NULL) 901 panic("czttytty"); 902 #endif 903 904 return (sc->sc_tty); 905 } 906 907 /* 908 * cztty_shutdown: 909 * 910 * Shut down a port. 911 */ 912 void 913 cztty_shutdown(struct cztty_softc *sc) 914 { 915 struct cz_softc *cz = CZTTY_CZ(sc); 916 struct tty *tp = sc->sc_tty; 917 int s; 918 919 s = spltty(); 920 921 /* Clear any break condition set with TIOCSBRK. */ 922 cztty_break(sc, 0); 923 924 /* 925 * Hang up if necessary. Wait a bit, so the other side has time to 926 * notice even if we immediately open the port again. 927 */ 928 if (ISSET(tp->t_cflag, HUPCL)) { 929 cztty_modem(sc, 0); 930 (void) tsleep(tp, TTIPRI, ttclos, hz); 931 } 932 933 /* Disable the channel. */ 934 cz_wait_pci_doorbell(cz, "czdis"); 935 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 936 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 937 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 938 939 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 940 #ifdef CZ_DEBUG 941 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 942 #endif 943 callout_stop(&cz->cz_callout); 944 } 945 946 splx(s); 947 } 948 949 /* 950 * czttyopen: 951 * 952 * Open a Cyclades-Z serial port. 953 */ 954 int 955 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 956 { 957 struct cztty_softc *sc = CZTTY_SOFTC(dev); 958 struct cz_softc *cz; 959 struct tty *tp; 960 int s, error; 961 962 if (sc == NULL) 963 return (ENXIO); 964 965 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 966 return (ENXIO); 967 968 cz = CZTTY_CZ(sc); 969 tp = sc->sc_tty; 970 971 if (ISSET(tp->t_state, TS_ISOPEN) && 972 ISSET(tp->t_state, TS_XCLUDE) && 973 p->p_ucred->cr_uid != 0) 974 return (EBUSY); 975 976 s = spltty(); 977 978 /* 979 * Do the following iff this is a first open. 980 */ 981 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 982 struct termios t; 983 984 tp->t_dev = dev; 985 986 /* If we're turning things on, enable interrupts */ 987 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 988 #ifdef CZ_DEBUG 989 printf("%s: Enabling polling.\n", 990 cz->cz_dev.dv_xname); 991 #endif 992 callout_reset(&cz->cz_callout, cz_timeout_ticks, 993 cz_poll, cz); 994 } 995 996 /* 997 * Enable the channel. Don't actually ring the 998 * doorbell here; czttyparam() will do it for us. 999 */ 1000 cz_wait_pci_doorbell(cz, "czopen"); 1001 1002 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1003 1004 /* 1005 * Initialize the termios status to the defaults. Add in the 1006 * sticky bits from TIOCSFLAGS. 1007 */ 1008 t.c_ispeed = 0; 1009 t.c_ospeed = TTYDEF_SPEED; 1010 t.c_cflag = TTYDEF_CFLAG; 1011 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1012 SET(t.c_cflag, CLOCAL); 1013 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1014 SET(t.c_cflag, CRTSCTS); 1015 1016 /* 1017 * Reset the input and output rings. Do this before 1018 * we call czttyparam(), as that function enables 1019 * the channel. 1020 */ 1021 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1022 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1023 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1024 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1025 1026 /* Make sure czttyparam() will see changes. */ 1027 tp->t_ospeed = 0; 1028 (void) czttyparam(tp, &t); 1029 tp->t_iflag = TTYDEF_IFLAG; 1030 tp->t_oflag = TTYDEF_OFLAG; 1031 tp->t_lflag = TTYDEF_LFLAG; 1032 ttychars(tp); 1033 ttsetwater(tp); 1034 1035 /* 1036 * Turn on DTR. We must always do this, even if carrier is not 1037 * present, because otherwise we'd have to use TIOCSDTR 1038 * immediately after setting CLOCAL, which applications do not 1039 * expect. We always assert DTR while the device is open 1040 * unless explicitly requested to deassert it. 1041 */ 1042 cztty_modem(sc, 1); 1043 } 1044 1045 splx(s); 1046 1047 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1048 if (error) 1049 goto bad; 1050 1051 error = (*linesw[tp->t_line].l_open)(dev, tp); 1052 if (error) 1053 goto bad; 1054 1055 return (0); 1056 1057 bad: 1058 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1059 /* 1060 * We failed to open the device, and nobody else had it opened. 1061 * Clean up the state as appropriate. 1062 */ 1063 cztty_shutdown(sc); 1064 } 1065 1066 return (error); 1067 } 1068 1069 /* 1070 * czttyclose: 1071 * 1072 * Close a Cyclades-Z serial port. 1073 */ 1074 int 1075 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1076 { 1077 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1078 struct tty *tp = sc->sc_tty; 1079 1080 /* XXX This is for cons.c. */ 1081 if (!ISSET(tp->t_state, TS_ISOPEN)) 1082 return (0); 1083 1084 (*linesw[tp->t_line].l_close)(tp, flags); 1085 ttyclose(tp); 1086 1087 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1088 /* 1089 * Although we got a last close, the device may still be in 1090 * use; e.g. if this was the dialout node, and there are still 1091 * processes waiting for carrier on the non-dialout node. 1092 */ 1093 cztty_shutdown(sc); 1094 } 1095 1096 return (0); 1097 } 1098 1099 /* 1100 * czttyread: 1101 * 1102 * Read from a Cyclades-Z serial port. 1103 */ 1104 int 1105 czttyread(dev_t dev, struct uio *uio, int flags) 1106 { 1107 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1108 struct tty *tp = sc->sc_tty; 1109 1110 return ((*linesw[tp->t_line].l_read)(tp, uio, flags)); 1111 } 1112 1113 /* 1114 * czttywrite: 1115 * 1116 * Write to a Cyclades-Z serial port. 1117 */ 1118 int 1119 czttywrite(dev_t dev, struct uio *uio, int flags) 1120 { 1121 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1122 struct tty *tp = sc->sc_tty; 1123 1124 return ((*linesw[tp->t_line].l_write)(tp, uio, flags)); 1125 } 1126 1127 /* 1128 * czttyioctl: 1129 * 1130 * Perform a control operation on a Cyclades-Z serial port. 1131 */ 1132 int 1133 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1134 { 1135 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1136 struct tty *tp = sc->sc_tty; 1137 int s, error; 1138 1139 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1140 if (error >= 0) 1141 return (error); 1142 1143 error = ttioctl(tp, cmd, data, flag, p); 1144 if (error >= 0) 1145 return (error); 1146 1147 error = 0; 1148 1149 s = spltty(); 1150 1151 switch (cmd) { 1152 case TIOCSBRK: 1153 cztty_break(sc, 1); 1154 break; 1155 1156 case TIOCCBRK: 1157 cztty_break(sc, 0); 1158 break; 1159 1160 case TIOCGFLAGS: 1161 *(int *)data = sc->sc_swflags; 1162 break; 1163 1164 case TIOCSFLAGS: 1165 error = suser(p->p_ucred, &p->p_acflag); 1166 if (error) 1167 break; 1168 sc->sc_swflags = *(int *)data; 1169 break; 1170 1171 case TIOCSDTR: 1172 cztty_modem(sc, 1); 1173 break; 1174 1175 case TIOCCDTR: 1176 cztty_modem(sc, 0); 1177 break; 1178 1179 case TIOCMSET: 1180 case TIOCMBIS: 1181 case TIOCMBIC: 1182 tiocm_to_cztty(sc, cmd, *(int *)data); 1183 break; 1184 1185 case TIOCMGET: 1186 *(int *)data = cztty_to_tiocm(sc); 1187 break; 1188 1189 default: 1190 error = ENOTTY; 1191 break; 1192 } 1193 1194 splx(s); 1195 1196 return (error); 1197 } 1198 1199 /* 1200 * cztty_break: 1201 * 1202 * Set or clear BREAK on a port. 1203 */ 1204 void 1205 cztty_break(struct cztty_softc *sc, int onoff) 1206 { 1207 struct cz_softc *cz = CZTTY_CZ(sc); 1208 1209 cz_wait_pci_doorbell(cz, "czbreak"); 1210 1211 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1212 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1213 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1214 } 1215 1216 /* 1217 * cztty_modem: 1218 * 1219 * Set or clear DTR on a port. 1220 */ 1221 void 1222 cztty_modem(struct cztty_softc *sc, int onoff) 1223 { 1224 struct cz_softc *cz = CZTTY_CZ(sc); 1225 1226 if (sc->sc_rs_control_dtr == 0) 1227 return; 1228 1229 cz_wait_pci_doorbell(cz, "czmod"); 1230 1231 if (onoff) 1232 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1233 else 1234 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1235 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1236 1237 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1238 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1239 } 1240 1241 /* 1242 * tiocm_to_cztty: 1243 * 1244 * Process TIOCM* ioctls. 1245 */ 1246 void 1247 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1248 { 1249 struct cz_softc *cz = CZTTY_CZ(sc); 1250 u_int32_t czttybits; 1251 1252 czttybits = 0; 1253 if (ISSET(ttybits, TIOCM_DTR)) 1254 SET(czttybits, C_RS_DTR); 1255 if (ISSET(ttybits, TIOCM_RTS)) 1256 SET(czttybits, C_RS_RTS); 1257 1258 cz_wait_pci_doorbell(cz, "cztiocm"); 1259 1260 switch (how) { 1261 case TIOCMBIC: 1262 CLR(sc->sc_chanctl_rs_control, czttybits); 1263 break; 1264 1265 case TIOCMBIS: 1266 SET(sc->sc_chanctl_rs_control, czttybits); 1267 break; 1268 1269 case TIOCMSET: 1270 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1271 SET(sc->sc_chanctl_rs_control, czttybits); 1272 break; 1273 } 1274 1275 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1276 1277 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1278 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1279 } 1280 1281 /* 1282 * cztty_to_tiocm: 1283 * 1284 * Process the TIOCMGET ioctl. 1285 */ 1286 int 1287 cztty_to_tiocm(struct cztty_softc *sc) 1288 { 1289 struct cz_softc *cz = CZTTY_CZ(sc); 1290 u_int32_t rs_status, op_mode; 1291 int ttybits = 0; 1292 1293 cz_wait_pci_doorbell(cz, "cztty"); 1294 1295 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1296 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1297 1298 if (ISSET(rs_status, C_RS_RTS)) 1299 SET(ttybits, TIOCM_RTS); 1300 if (ISSET(rs_status, C_RS_CTS)) 1301 SET(ttybits, TIOCM_CTS); 1302 if (ISSET(rs_status, C_RS_DCD)) 1303 SET(ttybits, TIOCM_CAR); 1304 if (ISSET(rs_status, C_RS_DTR)) 1305 SET(ttybits, TIOCM_DTR); 1306 if (ISSET(rs_status, C_RS_RI)) 1307 SET(ttybits, TIOCM_RNG); 1308 if (ISSET(rs_status, C_RS_DSR)) 1309 SET(ttybits, TIOCM_DSR); 1310 1311 if (ISSET(op_mode, C_CH_ENABLE)) 1312 SET(ttybits, TIOCM_LE); 1313 1314 return (ttybits); 1315 } 1316 1317 /* 1318 * czttyparam: 1319 * 1320 * Set Cyclades-Z serial port parameters from termios. 1321 * 1322 * XXX Should just copy the whole termios after making 1323 * XXX sure all the changes could be done. 1324 */ 1325 int 1326 czttyparam(struct tty *tp, struct termios *t) 1327 { 1328 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1329 struct cz_softc *cz = CZTTY_CZ(sc); 1330 u_int32_t rs_status; 1331 int ospeed, cflag; 1332 1333 ospeed = t->c_ospeed; 1334 cflag = t->c_cflag; 1335 1336 /* Check requested parameters. */ 1337 if (ospeed < 0) 1338 return (EINVAL); 1339 if (t->c_ispeed && t->c_ispeed != ospeed) 1340 return (EINVAL); 1341 1342 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1343 SET(cflag, CLOCAL); 1344 CLR(cflag, HUPCL); 1345 } 1346 1347 /* 1348 * If there were no changes, don't do anything. This avoids dropping 1349 * input and improves performance when all we did was frob things like 1350 * VMIN and VTIME. 1351 */ 1352 if (tp->t_ospeed == ospeed && 1353 tp->t_cflag == cflag) 1354 return (0); 1355 1356 /* Data bits. */ 1357 sc->sc_chanctl_comm_data_l = 0; 1358 switch (t->c_cflag & CSIZE) { 1359 case CS5: 1360 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1361 break; 1362 1363 case CS6: 1364 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1365 break; 1366 1367 case CS7: 1368 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1369 break; 1370 1371 case CS8: 1372 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1373 break; 1374 } 1375 1376 /* Stop bits. */ 1377 if (t->c_cflag & CSTOPB) { 1378 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1379 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1380 else 1381 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1382 } else 1383 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1384 1385 /* Parity. */ 1386 if (t->c_cflag & PARENB) { 1387 if (t->c_cflag & PARODD) 1388 sc->sc_chanctl_comm_parity = C_PR_ODD; 1389 else 1390 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1391 } else 1392 sc->sc_chanctl_comm_parity = C_PR_NONE; 1393 1394 /* 1395 * Initialize flow control pins depending on the current flow control 1396 * mode. 1397 */ 1398 if (ISSET(t->c_cflag, CRTSCTS)) { 1399 sc->sc_rs_control_dtr = C_RS_DTR; 1400 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1401 } else if (ISSET(t->c_cflag, MDMBUF)) { 1402 sc->sc_rs_control_dtr = 0; 1403 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1404 } else { 1405 /* 1406 * If no flow control, then always set RTS. This will make 1407 * the other side happy if it mistakenly thinks we're doing 1408 * RTS/CTS flow control. 1409 */ 1410 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1411 sc->sc_chanctl_hw_flow = 0; 1412 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1413 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1414 else 1415 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1416 } 1417 1418 /* Baud rate. */ 1419 sc->sc_chanctl_comm_baud = ospeed; 1420 1421 /* Copy to tty. */ 1422 tp->t_ispeed = 0; 1423 tp->t_ospeed = t->c_ospeed; 1424 tp->t_cflag = t->c_cflag; 1425 1426 /* 1427 * Now load the channel control structure. 1428 */ 1429 1430 cz_wait_pci_doorbell(cz, "czparam"); 1431 1432 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1433 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1434 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1435 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1436 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1437 1438 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1439 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1440 1441 cz_wait_pci_doorbell(cz, "czparam"); 1442 1443 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1444 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1445 1446 cz_wait_pci_doorbell(cz, "czparam"); 1447 1448 /* 1449 * Update the tty layer's idea of the carrier bit, in case we changed 1450 * CLOCAL. We don't hang up here; we only do that by explicit 1451 * request. 1452 */ 1453 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1454 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1455 1456 return (0); 1457 } 1458 1459 /* 1460 * czttystart: 1461 * 1462 * Start or restart transmission. 1463 */ 1464 void 1465 czttystart(struct tty *tp) 1466 { 1467 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1468 int s; 1469 1470 s = spltty(); 1471 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1472 goto out; 1473 1474 if (tp->t_outq.c_cc <= tp->t_lowat) { 1475 if (ISSET(tp->t_state, TS_ASLEEP)) { 1476 CLR(tp->t_state, TS_ASLEEP); 1477 wakeup(&tp->t_outq); 1478 } 1479 selwakeup(&tp->t_wsel); 1480 if (tp->t_outq.c_cc == 0) 1481 goto out; 1482 } 1483 1484 cztty_transmit(sc, tp); 1485 out: 1486 splx(s); 1487 } 1488 1489 /* 1490 * czttystop: 1491 * 1492 * Stop output, e.g., for ^S or output flush. 1493 */ 1494 void 1495 czttystop(struct tty *tp, int flag) 1496 { 1497 1498 /* 1499 * XXX We don't do anything here, yet. Mostly, I don't know 1500 * XXX exactly how this should be implemented on this device. 1501 * XXX We've given a big chunk of data to the MIPS already, 1502 * XXX and I don't know how we request the MIPS to stop sending 1503 * XXX the data. So, punt for now. --thorpej 1504 */ 1505 } 1506 1507 /* 1508 * cztty_diag: 1509 * 1510 * Issue a scheduled diagnostic message. 1511 */ 1512 void 1513 cztty_diag(void *arg) 1514 { 1515 struct cztty_softc *sc = arg; 1516 struct cz_softc *cz = CZTTY_CZ(sc); 1517 u_int overflows, parity_errors, framing_errors; 1518 int s; 1519 1520 s = spltty(); 1521 1522 overflows = sc->sc_overflows; 1523 sc->sc_overflows = 0; 1524 1525 parity_errors = sc->sc_parity_errors; 1526 sc->sc_parity_errors = 0; 1527 1528 framing_errors = sc->sc_framing_errors; 1529 sc->sc_framing_errors = 0; 1530 1531 sc->sc_errors = 0; 1532 1533 splx(s); 1534 1535 log(LOG_WARNING, 1536 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1537 cz->cz_dev.dv_xname, sc->sc_channel, 1538 overflows, overflows == 1 ? "" : "s", 1539 parity_errors, 1540 framing_errors, framing_errors == 1 ? "" : "s"); 1541 } 1542 1543 /* 1544 * tx and rx ring buffer size macros: 1545 * 1546 * The transmitter and receiver both use ring buffers. For each one, there 1547 * is a get (consumer) and a put (producer) offset. The get value is the 1548 * next byte to be read from the ring, and the put is the next one to be 1549 * put into the ring. get == put means the ring is empty. 1550 * 1551 * For each ring, the firmware controls one of (get, put) and this driver 1552 * controls the other. For transmission, this driver updates put to point 1553 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1554 * for receive, the driver controls put, and this driver controls get. 1555 */ 1556 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1557 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1558 1559 /* 1560 * cztty_transmit() 1561 * 1562 * Look at the tty for this port and start sending. 1563 */ 1564 int 1565 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1566 { 1567 struct cz_softc *cz = CZTTY_CZ(sc); 1568 u_int move, get, put, size, address; 1569 #ifdef HOSTRAMCODE 1570 int error, done = 0; 1571 #else 1572 int done = 0; 1573 #endif 1574 1575 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1576 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1577 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1578 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1579 1580 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1581 #ifdef HOSTRAMCODE 1582 if (0) { 1583 move = min(tp->t_outq.c_cc, move); 1584 error = q_to_b(&tp->t_outq, 0, move); 1585 if (error != move) { 1586 printf("%s: channel %d: error moving to " 1587 "transmit buf\n", cz->cz_dev.dv_xname, 1588 sc->sc_channel); 1589 move = error; 1590 } 1591 } else { 1592 #endif 1593 move = min(ndqb(&tp->t_outq, 0), move); 1594 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1595 address + put, tp->t_outq.c_cf, move); 1596 ndflush(&tp->t_outq, move); 1597 #ifdef HOSTRAMCODE 1598 } 1599 #endif 1600 1601 put = ((put + move) % size); 1602 done = 1; 1603 } 1604 if (done) { 1605 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1606 } 1607 return (done); 1608 } 1609 1610 int 1611 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1612 { 1613 struct cz_softc *cz = CZTTY_CZ(sc); 1614 u_int get, put, size, address; 1615 int done = 0, ch; 1616 1617 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1618 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1619 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1620 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1621 1622 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1623 #ifdef HOSTRAMCODE 1624 if (hostram) 1625 ch = ((char *)fifoaddr)[get]; 1626 } else { 1627 #endif 1628 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1629 address + get); 1630 #ifdef HOSTRAMCODE 1631 } 1632 #endif 1633 (*linesw[tp->t_line].l_rint)(ch, tp); 1634 get = (get + 1) % size; 1635 done = 1; 1636 } 1637 if (done) { 1638 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1639 } 1640 return (done); 1641 } 1642