1 /* $NetBSD: cz.c,v 1.6 2000/05/24 22:26:35 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only utilize RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/proc.h> 78 #include <sys/device.h> 79 #include <sys/malloc.h> 80 #include <sys/tty.h> 81 #include <sys/conf.h> 82 #include <sys/time.h> 83 #include <sys/kernel.h> 84 #include <sys/fcntl.h> 85 #include <sys/syslog.h> 86 87 #include <sys/callout.h> 88 89 #include <dev/pci/pcireg.h> 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/czreg.h> 93 94 #include <dev/pci/plx9060reg.h> 95 #include <dev/pci/plx9060var.h> 96 97 #include <dev/microcode/cyclades-z/cyzfirm.h> 98 99 #define CZ_DRIVER_VERSION 0x20000411 100 101 #define CZ_POLL_MS 20 102 103 /* These are the interrupts we always use. */ 104 #define CZ_INTERRUPTS \ 105 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 106 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 107 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 108 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 109 110 /* 111 * cztty_softc: 112 * 113 * Per-channel (TTY) state. 114 */ 115 struct cztty_softc { 116 struct cz_softc *sc_parent; 117 struct tty *sc_tty; 118 119 struct callout sc_diag_ch; 120 121 int sc_channel; /* Also used to flag unattached chan */ 122 #define CZTTY_CHANNEL_DEAD -1 123 124 bus_space_tag_t sc_chan_st; /* channel space tag */ 125 bus_space_handle_t sc_chan_sh; /* channel space handle */ 126 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 127 128 u_int sc_overflows, 129 sc_parity_errors, 130 sc_framing_errors, 131 sc_errors; 132 133 int sc_swflags; 134 135 u_int32_t sc_rs_control_dtr, 136 sc_chanctl_hw_flow, 137 sc_chanctl_comm_baud, 138 sc_chanctl_rs_control, 139 sc_chanctl_comm_data_l, 140 sc_chanctl_comm_parity; 141 }; 142 143 /* 144 * cz_softc: 145 * 146 * Per-board state. 147 */ 148 struct cz_softc { 149 struct device cz_dev; /* generic device info */ 150 struct plx9060_config cz_plx; /* PLX 9060 config info */ 151 bus_space_tag_t cz_win_st; /* window space tag */ 152 bus_space_handle_t cz_win_sh; /* window space handle */ 153 struct callout cz_callout; /* callout for polling-mode */ 154 155 void *cz_ih; /* interrupt handle */ 156 157 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 158 int cz_nchannels; /* number of channels */ 159 int cz_nopenchan; /* number of open channels */ 160 struct cztty_softc *cz_ports; /* our array of ports */ 161 162 bus_addr_t cz_fwctl; /* offset of firmware control */ 163 }; 164 165 int cz_match(struct device *, struct cfdata *, void *); 166 void cz_attach(struct device *, struct device *, void *); 167 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 168 169 struct cfattach cz_ca = { 170 sizeof(struct cz_softc), cz_match, cz_attach 171 }; 172 173 void cz_reset_board(struct cz_softc *); 174 int cz_load_firmware(struct cz_softc *); 175 176 int cz_intr(void *); 177 void cz_poll(void *); 178 int cztty_transmit(struct cztty_softc *, struct tty *); 179 int cztty_receive(struct cztty_softc *, struct tty *); 180 181 int cztty_findmajor(void); 182 int cztty_major; 183 int cz_timeout_ticks; 184 185 cdev_decl(cztty); 186 187 void czttystart(struct tty *tp); 188 int czttyparam(struct tty *tp, struct termios *t); 189 void cztty_shutdown(struct cztty_softc *sc); 190 void cztty_modem(struct cztty_softc *sc, int onoff); 191 void cztty_break(struct cztty_softc *sc, int onoff); 192 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 193 int cztty_to_tiocm(struct cztty_softc *sc); 194 void cztty_diag(void *arg); 195 196 extern struct cfdriver cz_cd; 197 198 /* Macros to clear/set/test flags. */ 199 #define SET(t, f) (t) |= (f) 200 #define CLR(t, f) (t) &= ~(f) 201 #define ISSET(t, f) ((t) & (f)) 202 203 /* 204 * Macros to read and write the PLX. 205 */ 206 #define CZ_PLX_READ(cz, reg) \ 207 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 208 #define CZ_PLX_WRITE(cz, reg, val) \ 209 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 210 (reg), (val)) 211 212 /* 213 * Macros to read and write the FPGA. We must already be in the FPGA 214 * window for this. 215 */ 216 #define CZ_FPGA_READ(cz, reg) \ 217 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 218 #define CZ_FPGA_WRITE(cz, reg, val) \ 219 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 220 221 /* 222 * Macros to read and write the firmware control structures in board RAM. 223 */ 224 #define CZ_FWCTL_READ(cz, off) \ 225 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 226 (cz)->cz_fwctl + (off)) 227 228 #define CZ_FWCTL_WRITE(cz, off, val) \ 229 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 230 (cz)->cz_fwctl + (off), (val)) 231 232 /* 233 * Convenience macros for cztty routines. PLX window MUST be to RAM. 234 */ 235 #define CZTTY_CHAN_READ(sc, off) \ 236 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 237 238 #define CZTTY_CHAN_WRITE(sc, off, val) \ 239 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 240 (off), (val)) 241 242 #define CZTTY_BUF_READ(sc, off) \ 243 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 244 245 #define CZTTY_BUF_WRITE(sc, off, val) \ 246 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 247 (off), (val)) 248 249 /* 250 * Convenience macros. 251 */ 252 #define CZ_WIN_RAM(cz) \ 253 do { \ 254 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 255 delay(100); \ 256 } while (0) 257 258 #define CZ_WIN_FPGA(cz) \ 259 do { \ 260 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 261 delay(100); \ 262 } while (0) 263 264 /***************************************************************************** 265 * Cyclades-Z controller code starts here... 266 *****************************************************************************/ 267 268 /* 269 * cz_match: 270 * 271 * Determine if the given PCI device is a Cyclades-Z board. 272 */ 273 int 274 cz_match(struct device *parent, 275 struct cfdata *match, 276 void *aux) 277 { 278 struct pci_attach_args *pa = aux; 279 280 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 281 switch (PCI_PRODUCT(pa->pa_id)) { 282 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 283 return (1); 284 } 285 } 286 287 return (0); 288 } 289 290 /* 291 * cz_attach: 292 * 293 * A Cyclades-Z board was found; attach it. 294 */ 295 void 296 cz_attach(struct device *parent, 297 struct device *self, 298 void *aux) 299 { 300 struct cz_softc *cz = (void *) self; 301 struct pci_attach_args *pa = aux; 302 pci_intr_handle_t ih; 303 const char *intrstr = NULL; 304 struct cztty_softc *sc; 305 struct tty *tp; 306 int i; 307 308 printf(": Cyclades-Z multiport serial\n"); 309 310 cz->cz_plx.plx_pc = pa->pa_pc; 311 cz->cz_plx.plx_tag = pa->pa_tag; 312 313 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 314 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 315 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 316 printf("%s: unable to map PLX registers\n", 317 cz->cz_dev.dv_xname); 318 return; 319 } 320 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 321 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 322 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 323 printf("%s: unable to map device window\n", 324 cz->cz_dev.dv_xname); 325 return; 326 } 327 328 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 329 cz->cz_nopenchan = 0; 330 331 /* 332 * Make sure that the board is completely stopped. 333 */ 334 CZ_WIN_FPGA(cz); 335 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 336 337 /* 338 * Load the board's firmware. 339 */ 340 if (cz_load_firmware(cz) != 0) 341 return; 342 343 /* 344 * Now that we're ready to roll, map and establish the interrupt 345 * handler. 346 */ 347 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 348 pa->pa_intrline, &ih) != 0) { 349 /* 350 * The common case is for Cyclades-Z boards to run 351 * in polling mode, and thus not have an interrupt 352 * mapped for them. Don't bother reporting that 353 * the interrupt is not mappable, since this isn't 354 * really an error. 355 */ 356 cz->cz_ih = NULL; 357 goto polling_mode; 358 } else { 359 intrstr = pci_intr_string(pa->pa_pc, ih); 360 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 361 cz_intr, cz); 362 } 363 if (cz->cz_ih == NULL) { 364 printf("%s: unable to establish interrupt", 365 cz->cz_dev.dv_xname); 366 if (intrstr != NULL) 367 printf(" at %s", intrstr); 368 printf("\n"); 369 /* We will fall-back on polling mode. */ 370 } else 371 printf("%s: interrupting at %s\n", 372 cz->cz_dev.dv_xname, intrstr); 373 374 polling_mode: 375 if (cz->cz_ih == NULL) { 376 callout_init(&cz->cz_callout); 377 if (cz_timeout_ticks == 0) 378 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 379 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 380 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 381 cz_timeout_ticks == 1 ? "" : "s"); 382 } 383 384 if (cztty_major == 0) 385 cztty_major = cztty_findmajor(); 386 /* 387 * Allocate sufficient pointers for the children and 388 * attach them. Set all ports to a reasonable initial 389 * configuration while we're at it: 390 * 391 * disabled 392 * 8N1 393 * default baud rate 394 * hardware flow control. 395 */ 396 CZ_WIN_RAM(cz); 397 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 398 M_DEVBUF, M_WAITOK); 399 memset(cz->cz_ports, 0, 400 sizeof(struct cztty_softc) * cz->cz_nchannels); 401 402 for (i = 0; i < cz->cz_nchannels; i++) { 403 sc = &cz->cz_ports[i]; 404 405 sc->sc_channel = i; 406 sc->sc_chan_st = cz->cz_win_st; 407 sc->sc_parent = cz; 408 409 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 410 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 411 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 412 printf("%s: unable to subregion channel %d control\n", 413 cz->cz_dev.dv_xname, i); 414 sc->sc_channel = CZTTY_CHANNEL_DEAD; 415 continue; 416 } 417 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 418 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 419 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 420 printf("%s: unable to subregion channel %d buffer\n", 421 cz->cz_dev.dv_xname, i); 422 sc->sc_channel = CZTTY_CHANNEL_DEAD; 423 continue; 424 } 425 426 callout_init(&sc->sc_diag_ch); 427 428 tp = ttymalloc(); 429 tp->t_dev = makedev(cztty_major, 430 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 431 tp->t_oproc = czttystart; 432 tp->t_param = czttyparam; 433 tty_attach(tp); 434 435 sc->sc_tty = tp; 436 437 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 438 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 439 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 440 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 441 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 442 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 443 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 444 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 445 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 446 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 447 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 448 } 449 } 450 451 /* 452 * cz_reset_board: 453 * 454 * Reset the board via the PLX. 455 */ 456 void 457 cz_reset_board(struct cz_softc *cz) 458 { 459 u_int32_t reg; 460 461 reg = CZ_PLX_READ(cz, PLX_CONTROL); 462 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 463 delay(1000); 464 465 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 466 delay(1000); 467 468 /* Now reload the PLX from its EEPROM. */ 469 reg = CZ_PLX_READ(cz, PLX_CONTROL); 470 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 471 delay(1000); 472 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 473 } 474 475 /* 476 * cz_load_firmware: 477 * 478 * Load the ZFIRM firmware into the board's RAM and start it 479 * running. 480 */ 481 int 482 cz_load_firmware(struct cz_softc *cz) 483 { 484 struct zfirm_header *zfh; 485 struct zfirm_config *zfc; 486 struct zfirm_block *zfb, *zblocks; 487 const u_int8_t *cp; 488 const char *board; 489 u_int32_t fid; 490 int i, j, nconfigs, nblocks, nbytes; 491 492 zfh = (struct zfirm_header *) cycladesz_firmware; 493 494 /* Find the config header. */ 495 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 496 printf("%s: bad ZFIRM config offset: 0x%x\n", 497 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 498 return (EIO); 499 } 500 zfc = (struct zfirm_config *)(cycladesz_firmware + 501 le32toh(zfh->zfh_configoff)); 502 nconfigs = le32toh(zfh->zfh_nconfig); 503 504 /* Locate the correct configuration for our board. */ 505 for (i = 0; i < nconfigs; i++, zfc++) { 506 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 507 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 508 break; 509 } 510 if (i == nconfigs) { 511 printf("%s: unable to locate config header\n", 512 cz->cz_dev.dv_xname); 513 return (EIO); 514 } 515 516 nblocks = le32toh(zfc->zfc_nblocks); 517 zblocks = (struct zfirm_block *)(cycladesz_firmware + 518 le32toh(zfh->zfh_blockoff)); 519 520 /* 521 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 522 * necessary. 523 */ 524 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 525 #if 0 526 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 527 #endif 528 ) { 529 #ifdef CZ_DEBUG 530 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 531 #endif 532 CZ_WIN_FPGA(cz); 533 for (i = 0; i < nblocks; i++) { 534 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 535 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 536 if (zfb->zfb_type == ZFB_TYPE_FPGA) { 537 nbytes = le32toh(zfb->zfb_size); 538 cp = &cycladesz_firmware[ 539 le32toh(zfb->zfb_fileoff)]; 540 for (j = 0; j < nbytes; j++, cp++) { 541 bus_space_write_1(cz->cz_win_st, 542 cz->cz_win_sh, 0, *cp); 543 /* FPGA needs 30-100us to settle. */ 544 delay(10); 545 } 546 } 547 } 548 #ifdef CZ_DEBUG 549 printf("done\n"); 550 #endif 551 } 552 553 /* Now load the firmware. */ 554 CZ_WIN_RAM(cz); 555 556 for (i = 0; i < nblocks; i++) { 557 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 558 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 559 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 560 const u_int32_t *lp; 561 u_int32_t ro = le32toh(zfb->zfb_ramoff); 562 nbytes = le32toh(zfb->zfb_size); 563 lp = (const u_int32_t *) 564 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 565 for (j = 0; j < nbytes; j += 4, lp++) { 566 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 567 ro + j, *lp); 568 delay(10); 569 } 570 } 571 } 572 573 /* Now restart the MIPS. */ 574 CZ_WIN_FPGA(cz); 575 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 576 577 /* Wait for the MIPS to start, then report the results. */ 578 CZ_WIN_RAM(cz); 579 580 #ifdef CZ_DEBUG 581 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 582 #endif 583 for (i = 0; i < 100; i++) { 584 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 585 ZFIRM_SIG_OFF); 586 if (fid == ZFIRM_SIG) { 587 /* MIPS has booted. */ 588 break; 589 } else if (fid == ZFIRM_HLT) { 590 /* 591 * The MIPS has halted, usually due to a power 592 * shortage on the expansion module. 593 */ 594 printf("%s: MIPS halted; possible power supply " 595 "problem\n", cz->cz_dev.dv_xname); 596 return (EIO); 597 } else { 598 #ifdef CZ_DEBUG 599 if ((i % 8) == 0) 600 printf("."); 601 #endif 602 delay(250000); 603 } 604 } 605 #ifdef CZ_DEBUG 606 printf("\n"); 607 #endif 608 if (i == 100) { 609 CZ_WIN_FPGA(cz); 610 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 611 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 612 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 613 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 614 CZ_FPGA_READ(cz, FPGA_VERSION)); 615 return (EIO); 616 } 617 618 /* 619 * Locate the firmware control structures. 620 */ 621 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 622 ZFIRM_CTRLADDR_OFF); 623 #ifdef CZ_DEBUG 624 printf("%s: FWCTL structure at offset 0x%08lx\n", 625 cz->cz_dev.dv_xname, cz->cz_fwctl); 626 #endif 627 628 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 629 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 630 631 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 632 633 switch (cz->cz_mailbox0) { 634 case MAILBOX0_8Zo_V1: 635 board = "Cyclades-8Zo ver. 1"; 636 break; 637 638 case MAILBOX0_8Zo_V2: 639 board = "Cyclades-8Zo ver. 2"; 640 break; 641 642 case MAILBOX0_Ze_V1: 643 board = "Cyclades-Ze"; 644 break; 645 646 default: 647 board = "unknown Cyclades Z-series"; 648 break; 649 } 650 651 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 652 printf("%s: %s, %d channels (ttyCZ%04d..ttyCZ%04d), " 653 "firmware %x.%x.%x\n", 654 cz->cz_dev.dv_xname, board, cz->cz_nchannels, 655 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS), 656 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + (cz->cz_nchannels - 1), 657 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 658 659 return (0); 660 } 661 662 /* 663 * cz_poll: 664 * 665 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 666 * ms. 667 */ 668 void 669 cz_poll(void *arg) 670 { 671 int s = spltty(); 672 struct cz_softc *cz = arg; 673 674 cz_intr(cz); 675 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 676 677 splx(s); 678 } 679 680 /* 681 * cz_intr: 682 * 683 * Interrupt service routine. 684 * 685 * We either are receiving an interrupt directly from the board, or we are 686 * in polling mode and it's time to poll. 687 */ 688 int 689 cz_intr(void *arg) 690 { 691 int rval = 0; 692 u_int command, channel, param; 693 struct cz_softc *cz = arg; 694 struct cztty_softc *sc; 695 struct tty *tp; 696 697 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 698 rval = 1; 699 channel = CZ_FWCTL_READ(cz, BRDCTL_HCMD_CHANNEL); 700 param = CZ_FWCTL_READ(cz, BRDCTL_HCMD_PARAM); 701 702 /* now clear this interrupt, posslibly enabling another */ 703 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 704 705 sc = &cz->cz_ports[channel]; 706 707 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 708 break; 709 710 tp = sc->sc_tty; 711 712 switch (command) { 713 case C_CM_TXFEMPTY: /* transmit cases */ 714 case C_CM_TXBEMPTY: 715 case C_CM_TXLOWWM: 716 case C_CM_INTBACK: 717 if (!ISSET(tp->t_state, TS_ISOPEN)) { 718 #ifdef CZ_DEBUG 719 printf("%s: tx intr on closed channel %d\n", 720 cz->cz_dev.dv_xname, channel); 721 #endif 722 break; 723 } 724 725 if (cztty_transmit(sc, tp)) { 726 /* 727 * Do wakeup stuff here. 728 */ 729 ttwakeup(tp); 730 wakeup(tp); 731 } 732 break; 733 734 case C_CM_RXNNDT: /* receive cases */ 735 case C_CM_RXHIWM: 736 case C_CM_INTBACK2: /* from restart ?? */ 737 #if 0 738 case C_CM_ICHAR: 739 #endif 740 if (!ISSET(tp->t_state, TS_ISOPEN)) { 741 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 742 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 743 break; 744 } 745 746 if (cztty_receive(sc, tp)) { 747 /* 748 * Do wakeup stuff here. 749 */ 750 ttwakeup(tp); 751 wakeup(tp); 752 } 753 break; 754 755 case C_CM_MDCD: 756 if (!ISSET(tp->t_state, TS_ISOPEN)) 757 break; 758 759 (void) (*linesw[tp->t_line].l_modem)(tp, 760 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 761 CHNCTL_RS_STATUS))); 762 break; 763 764 case C_CM_MDSR: 765 case C_CM_MRI: 766 case C_CM_MCTS: 767 case C_CM_MRTS: 768 break; 769 770 case C_CM_IOCTLW: 771 break; 772 773 case C_CM_PR_ERROR: 774 sc->sc_parity_errors++; 775 goto error_common; 776 777 case C_CM_FR_ERROR: 778 sc->sc_framing_errors++; 779 goto error_common; 780 781 case C_CM_OVR_ERROR: 782 sc->sc_overflows++; 783 error_common: 784 if (sc->sc_errors++ == 0) 785 callout_reset(&sc->sc_diag_ch, 60 * hz, 786 cztty_diag, sc); 787 break; 788 789 case C_CM_RXBRK: 790 if (!ISSET(tp->t_state, TS_ISOPEN)) 791 break; 792 793 /* 794 * A break is a \000 character with TTY_FE error 795 * flags set. So TTY_FE by itself works. 796 */ 797 (*linesw[tp->t_line].l_rint)(TTY_FE, tp); 798 ttwakeup(tp); 799 wakeup(tp); 800 break; 801 802 default: 803 #ifdef CZ_DEBUG 804 printf("%s: channel %d: Unknown interrupt 0x%x\n", 805 cz->cz_dev.dv_xname, sc->sc_channel, command); 806 #endif 807 break; 808 } 809 } 810 811 return (rval); 812 } 813 814 /* 815 * cz_wait_pci_doorbell: 816 * 817 * Wait for the pci doorbell to be clear - wait for pending 818 * activity to drain. 819 */ 820 int 821 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 822 { 823 int error; 824 825 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 826 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 827 if ((error != 0) && (error != EWOULDBLOCK)) 828 return (error); 829 } 830 return (0); 831 } 832 833 /***************************************************************************** 834 * Cyclades-Z TTY code starts here... 835 *****************************************************************************/ 836 837 #define CZTTYCHAN_MASK 0x0003f 838 #define CZTTYBOARD_MASK (0x7ffff & ~CZTTYCHAN_MASK) 839 #define CZTTYBOARD_SHIFT 6 840 #define CZTTYDIALOUT_MASK 0x80000 841 842 #define CZTTY_CHAN(dev) (minor((dev)) & CZTTYCHAN_MASK) 843 #define CZTTY_BOARD(dev) ((minor((dev)) & CZTTYBOARD_MASK) >> \ 844 CZTTYBOARD_SHIFT) 845 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 846 #define CZTTY_CZ(sc) ((sc)->sc_parent) 847 848 #define CZ_SOFTC(dev) \ 849 ((struct cz_softc *)(CZTTY_BOARD(dev) < cz_cd.cd_ndevs ? \ 850 cz_cd.cd_devs[CZTTY_BOARD(dev)] : NULL)) 851 852 #define CZTTY_SOFTC(dev) \ 853 ((CZ_SOFTC(dev) != NULL && \ 854 CZTTY_CHAN(dev) < CZ_SOFTC(dev)->cz_nchannels) ? \ 855 &CZ_SOFTC(dev)->cz_ports[CZTTY_CHAN(dev)] : NULL) 856 857 int 858 cztty_findmajor(void) 859 { 860 int maj; 861 862 for (maj = 0; maj < nchrdev; maj++) { 863 if (cdevsw[maj].d_open == czttyopen) 864 break; 865 } 866 867 return (maj == nchrdev) ? 0 : maj; 868 } 869 870 /* 871 * czttytty: 872 * 873 * Return a pointer to our tty. 874 */ 875 struct tty * 876 czttytty(dev_t dev) 877 { 878 struct cztty_softc *sc = CZTTY_SOFTC(dev); 879 880 #ifdef DIAGNOSTIC 881 if (sc == NULL) 882 panic("czttytty"); 883 #endif 884 885 return (sc->sc_tty); 886 } 887 888 /* 889 * cztty_shutdown: 890 * 891 * Shut down a port. 892 */ 893 void 894 cztty_shutdown(struct cztty_softc *sc) 895 { 896 struct cz_softc *cz = CZTTY_CZ(sc); 897 struct tty *tp = sc->sc_tty; 898 int s; 899 900 s = spltty(); 901 902 /* Clear any break condition set with TIOCSBRK. */ 903 cztty_break(sc, 0); 904 905 /* 906 * Hang up if necessary. Wait a bit, so the other side has time to 907 * notice even if we immediately open the port again. 908 */ 909 if (ISSET(tp->t_cflag, HUPCL)) { 910 cztty_modem(sc, 0); 911 (void) tsleep(tp, TTIPRI, ttclos, hz); 912 } 913 914 /* Disable the channel. */ 915 cz_wait_pci_doorbell(cz, "czdis"); 916 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 917 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 918 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 919 920 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 921 #ifdef CZ_DEBUG 922 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 923 #endif 924 callout_stop(&cz->cz_callout); 925 } 926 927 splx(s); 928 } 929 930 /* 931 * czttyopen: 932 * 933 * Open a Cyclades-Z serial port. 934 */ 935 int 936 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 937 { 938 struct cztty_softc *sc = CZTTY_SOFTC(dev); 939 struct cz_softc *cz; 940 struct tty *tp; 941 int s, error; 942 943 if (sc == NULL) 944 return (ENXIO); 945 946 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 947 return (ENXIO); 948 949 cz = CZTTY_CZ(sc); 950 tp = sc->sc_tty; 951 952 if (ISSET(tp->t_state, TS_ISOPEN) && 953 ISSET(tp->t_state, TS_XCLUDE) && 954 p->p_ucred->cr_uid != 0) 955 return (EBUSY); 956 957 s = spltty(); 958 959 /* 960 * Do the following iff this is a first open. 961 */ 962 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 963 struct termios t; 964 965 tp->t_dev = dev; 966 967 /* If we're turning things on, enable interrupts */ 968 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 969 #ifdef CZ_DEBUG 970 printf("%s: Enabling polling.\n", 971 cz->cz_dev.dv_xname); 972 #endif 973 callout_reset(&cz->cz_callout, cz_timeout_ticks, 974 cz_poll, cz); 975 } 976 977 /* 978 * Enable the channel. Don't actually ring the 979 * doorbell here; czttyparam() will do it for us. 980 */ 981 cz_wait_pci_doorbell(cz, "czopen"); 982 983 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 984 985 /* 986 * Initialize the termios status to the defaults. Add in the 987 * sticky bits from TIOCSFLAGS. 988 */ 989 t.c_ispeed = 0; 990 t.c_ospeed = TTYDEF_SPEED; 991 t.c_cflag = TTYDEF_CFLAG; 992 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 993 SET(t.c_cflag, CLOCAL); 994 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 995 SET(t.c_cflag, CRTSCTS); 996 997 /* 998 * Reset the input and output rings. Do this before 999 * we call czttyparam(), as that function enables 1000 * the channel. 1001 */ 1002 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1003 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1004 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1005 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1006 1007 /* Make sure czttyparam() will see changes. */ 1008 tp->t_ospeed = 0; 1009 (void) czttyparam(tp, &t); 1010 tp->t_iflag = TTYDEF_IFLAG; 1011 tp->t_oflag = TTYDEF_OFLAG; 1012 tp->t_lflag = TTYDEF_LFLAG; 1013 ttychars(tp); 1014 ttsetwater(tp); 1015 1016 /* 1017 * Turn on DTR. We must always do this, even if carrier is not 1018 * present, because otherwise we'd have to use TIOCSDTR 1019 * immediately after setting CLOCAL, which applications do not 1020 * expect. We always assert DTR while the device is open 1021 * unless explicitly requested to deassert it. 1022 */ 1023 cztty_modem(sc, 1); 1024 } 1025 1026 splx(s); 1027 1028 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1029 if (error) 1030 goto bad; 1031 1032 error = (*linesw[tp->t_line].l_open)(dev, tp); 1033 if (error) 1034 goto bad; 1035 1036 return (0); 1037 1038 bad: 1039 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1040 /* 1041 * We failed to open the device, and nobody else had it opened. 1042 * Clean up the state as appropriate. 1043 */ 1044 cztty_shutdown(sc); 1045 } 1046 1047 return (error); 1048 } 1049 1050 /* 1051 * czttyclose: 1052 * 1053 * Close a Cyclades-Z serial port. 1054 */ 1055 int 1056 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1057 { 1058 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1059 struct tty *tp = sc->sc_tty; 1060 1061 /* XXX This is for cons.c. */ 1062 if (!ISSET(tp->t_state, TS_ISOPEN)) 1063 return (0); 1064 1065 (*linesw[tp->t_line].l_close)(tp, flags); 1066 ttyclose(tp); 1067 1068 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1069 /* 1070 * Although we got a last close, the device may still be in 1071 * use; e.g. if this was the dialout node, and there are still 1072 * processes waiting for carrier on the non-dialout node. 1073 */ 1074 cztty_shutdown(sc); 1075 } 1076 1077 return (0); 1078 } 1079 1080 /* 1081 * czttyread: 1082 * 1083 * Read from a Cyclades-Z serial port. 1084 */ 1085 int 1086 czttyread(dev_t dev, struct uio *uio, int flags) 1087 { 1088 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1089 struct tty *tp = sc->sc_tty; 1090 1091 return ((*linesw[tp->t_line].l_read)(tp, uio, flags)); 1092 } 1093 1094 /* 1095 * czttywrite: 1096 * 1097 * Write to a Cyclades-Z serial port. 1098 */ 1099 int 1100 czttywrite(dev_t dev, struct uio *uio, int flags) 1101 { 1102 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1103 struct tty *tp = sc->sc_tty; 1104 1105 return ((*linesw[tp->t_line].l_write)(tp, uio, flags)); 1106 } 1107 1108 /* 1109 * czttyioctl: 1110 * 1111 * Perform a control operation on a Cyclades-Z serial port. 1112 */ 1113 int 1114 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1115 { 1116 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1117 struct tty *tp = sc->sc_tty; 1118 int s, error; 1119 1120 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1121 if (error >= 0) 1122 return (error); 1123 1124 error = ttioctl(tp, cmd, data, flag, p); 1125 if (error >= 0) 1126 return (error); 1127 1128 error = 0; 1129 1130 s = spltty(); 1131 1132 switch (cmd) { 1133 case TIOCSBRK: 1134 cztty_break(sc, 1); 1135 break; 1136 1137 case TIOCCBRK: 1138 cztty_break(sc, 0); 1139 break; 1140 1141 case TIOCGFLAGS: 1142 *(int *)data = sc->sc_swflags; 1143 break; 1144 1145 case TIOCSFLAGS: 1146 error = suser(p->p_ucred, &p->p_acflag); 1147 if (error) 1148 break; 1149 sc->sc_swflags = *(int *)data; 1150 break; 1151 1152 case TIOCSDTR: 1153 cztty_modem(sc, 1); 1154 break; 1155 1156 case TIOCCDTR: 1157 cztty_modem(sc, 0); 1158 break; 1159 1160 case TIOCMSET: 1161 case TIOCMBIS: 1162 case TIOCMBIC: 1163 tiocm_to_cztty(sc, cmd, *(int *)data); 1164 break; 1165 1166 case TIOCMGET: 1167 *(int *)data = cztty_to_tiocm(sc); 1168 break; 1169 1170 default: 1171 error = ENOTTY; 1172 break; 1173 } 1174 1175 splx(s); 1176 1177 return (error); 1178 } 1179 1180 /* 1181 * cztty_break: 1182 * 1183 * Set or clear BREAK on a port. 1184 */ 1185 void 1186 cztty_break(struct cztty_softc *sc, int onoff) 1187 { 1188 struct cz_softc *cz = CZTTY_CZ(sc); 1189 1190 cz_wait_pci_doorbell(cz, "czbreak"); 1191 1192 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1193 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1194 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1195 } 1196 1197 /* 1198 * cztty_modem: 1199 * 1200 * Set or clear DTR on a port. 1201 */ 1202 void 1203 cztty_modem(struct cztty_softc *sc, int onoff) 1204 { 1205 struct cz_softc *cz = CZTTY_CZ(sc); 1206 1207 if (sc->sc_rs_control_dtr == 0) 1208 return; 1209 1210 cz_wait_pci_doorbell(cz, "czmod"); 1211 1212 if (onoff) 1213 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1214 else 1215 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1216 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1217 1218 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1219 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1220 } 1221 1222 /* 1223 * tiocm_to_cztty: 1224 * 1225 * Process TIOCM* ioctls. 1226 */ 1227 void 1228 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1229 { 1230 struct cz_softc *cz = CZTTY_CZ(sc); 1231 u_int32_t czttybits; 1232 1233 czttybits = 0; 1234 if (ISSET(ttybits, TIOCM_DTR)) 1235 SET(czttybits, C_RS_DTR); 1236 if (ISSET(ttybits, TIOCM_RTS)) 1237 SET(czttybits, C_RS_RTS); 1238 1239 cz_wait_pci_doorbell(cz, "cztiocm"); 1240 1241 switch (how) { 1242 case TIOCMBIC: 1243 CLR(sc->sc_chanctl_rs_control, czttybits); 1244 break; 1245 1246 case TIOCMBIS: 1247 SET(sc->sc_chanctl_rs_control, czttybits); 1248 break; 1249 1250 case TIOCMSET: 1251 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1252 SET(sc->sc_chanctl_rs_control, czttybits); 1253 break; 1254 } 1255 1256 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1257 1258 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1259 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1260 } 1261 1262 /* 1263 * cztty_to_tiocm: 1264 * 1265 * Process the TIOCMGET ioctl. 1266 */ 1267 int 1268 cztty_to_tiocm(struct cztty_softc *sc) 1269 { 1270 struct cz_softc *cz = CZTTY_CZ(sc); 1271 u_int32_t rs_status, op_mode; 1272 int ttybits = 0; 1273 1274 cz_wait_pci_doorbell(cz, "cztty"); 1275 1276 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1277 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1278 1279 if (ISSET(rs_status, C_RS_RTS)) 1280 SET(ttybits, TIOCM_RTS); 1281 if (ISSET(rs_status, C_RS_CTS)) 1282 SET(ttybits, TIOCM_CTS); 1283 if (ISSET(rs_status, C_RS_DCD)) 1284 SET(ttybits, TIOCM_CAR); 1285 if (ISSET(rs_status, C_RS_DTR)) 1286 SET(ttybits, TIOCM_DTR); 1287 if (ISSET(rs_status, C_RS_RI)) 1288 SET(ttybits, TIOCM_RNG); 1289 if (ISSET(rs_status, C_RS_DSR)) 1290 SET(ttybits, TIOCM_DSR); 1291 1292 if (ISSET(op_mode, C_CH_ENABLE)) 1293 SET(ttybits, TIOCM_LE); 1294 1295 return (ttybits); 1296 } 1297 1298 /* 1299 * czttyparam: 1300 * 1301 * Set Cyclades-Z serial port parameters from termios. 1302 * 1303 * XXX Should just copy the whole termios after making 1304 * XXX sure all the changes could be done. 1305 */ 1306 int 1307 czttyparam(struct tty *tp, struct termios *t) 1308 { 1309 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1310 struct cz_softc *cz = CZTTY_CZ(sc); 1311 u_int32_t rs_status; 1312 int ospeed, cflag; 1313 1314 ospeed = t->c_ospeed; 1315 cflag = t->c_cflag; 1316 1317 /* Check requested parameters. */ 1318 if (ospeed < 0) 1319 return (EINVAL); 1320 if (t->c_ispeed && t->c_ispeed != ospeed) 1321 return (EINVAL); 1322 1323 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1324 SET(cflag, CLOCAL); 1325 CLR(cflag, HUPCL); 1326 } 1327 1328 /* 1329 * If there were no changes, don't do anything. This avoids dropping 1330 * input and improves performance when all we did was frob things like 1331 * VMIN and VTIME. 1332 */ 1333 if (tp->t_ospeed == ospeed && 1334 tp->t_cflag == cflag) 1335 return (0); 1336 1337 /* Data bits. */ 1338 sc->sc_chanctl_comm_data_l = 0; 1339 switch (t->c_cflag & CSIZE) { 1340 case CS5: 1341 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1342 break; 1343 1344 case CS6: 1345 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1346 break; 1347 1348 case CS7: 1349 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1350 break; 1351 1352 case CS8: 1353 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1354 break; 1355 } 1356 1357 /* Stop bits. */ 1358 if (t->c_cflag & CSTOPB) { 1359 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1360 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1361 else 1362 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1363 } else 1364 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1365 1366 /* Parity. */ 1367 if (t->c_cflag & PARENB) { 1368 if (t->c_cflag & PARODD) 1369 sc->sc_chanctl_comm_parity = C_PR_ODD; 1370 else 1371 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1372 } else 1373 sc->sc_chanctl_comm_parity = C_PR_NONE; 1374 1375 /* 1376 * Initialize flow control pins depending on the current flow control 1377 * mode. 1378 */ 1379 if (ISSET(t->c_cflag, CRTSCTS)) { 1380 sc->sc_rs_control_dtr = C_RS_DTR; 1381 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1382 } else if (ISSET(t->c_cflag, MDMBUF)) { 1383 sc->sc_rs_control_dtr = 0; 1384 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1385 } else { 1386 /* 1387 * If no flow control, then always set RTS. This will make 1388 * the other side happy if it mistakenly thinks we're doing 1389 * RTS/CTS flow control. 1390 */ 1391 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1392 sc->sc_chanctl_hw_flow = 0; 1393 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1394 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1395 else 1396 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1397 } 1398 1399 /* Baud rate. */ 1400 sc->sc_chanctl_comm_baud = ospeed; 1401 1402 /* Copy to tty. */ 1403 tp->t_ispeed = 0; 1404 tp->t_ospeed = t->c_ospeed; 1405 tp->t_cflag = t->c_cflag; 1406 1407 /* 1408 * Now load the channel control structure. 1409 */ 1410 1411 cz_wait_pci_doorbell(cz, "czparam"); 1412 1413 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1414 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1415 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1416 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1417 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1418 1419 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1420 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1421 1422 cz_wait_pci_doorbell(cz, "czparam"); 1423 1424 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1425 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1426 1427 cz_wait_pci_doorbell(cz, "czparam"); 1428 1429 /* 1430 * Update the tty layer's idea of the carrier bit, in case we changed 1431 * CLOCAL. We don't hang up here; we only do that by explicit 1432 * request. 1433 */ 1434 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1435 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1436 1437 return (0); 1438 } 1439 1440 /* 1441 * czttystart: 1442 * 1443 * Start or restart transmission. 1444 */ 1445 void 1446 czttystart(struct tty *tp) 1447 { 1448 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1449 int s; 1450 1451 s = spltty(); 1452 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1453 goto out; 1454 1455 if (tp->t_outq.c_cc <= tp->t_lowat) { 1456 if (ISSET(tp->t_state, TS_ASLEEP)) { 1457 CLR(tp->t_state, TS_ASLEEP); 1458 wakeup(&tp->t_outq); 1459 } 1460 selwakeup(&tp->t_wsel); 1461 if (tp->t_outq.c_cc == 0) 1462 goto out; 1463 } 1464 1465 cztty_transmit(sc, tp); 1466 out: 1467 splx(s); 1468 } 1469 1470 /* 1471 * czttystop: 1472 * 1473 * Stop output, e.g., for ^S or output flush. 1474 */ 1475 void 1476 czttystop(struct tty *tp, int flag) 1477 { 1478 1479 /* 1480 * XXX We don't do anything here, yet. Mostly, I don't know 1481 * XXX exactly how this should be implemented on this device. 1482 * XXX We've given a big chunk of data to the MIPS already, 1483 * XXX and I don't know how we request the MIPS to stop sending 1484 * XXX the data. So, punt for now. --thorpej 1485 */ 1486 } 1487 1488 /* 1489 * cztty_diag: 1490 * 1491 * Issue a scheduled diagnostic message. 1492 */ 1493 void 1494 cztty_diag(void *arg) 1495 { 1496 struct cztty_softc *sc = arg; 1497 struct cz_softc *cz = CZTTY_CZ(sc); 1498 u_int overflows, parity_errors, framing_errors; 1499 int s; 1500 1501 s = spltty(); 1502 1503 overflows = sc->sc_overflows; 1504 sc->sc_overflows = 0; 1505 1506 parity_errors = sc->sc_parity_errors; 1507 sc->sc_parity_errors = 0; 1508 1509 framing_errors = sc->sc_framing_errors; 1510 sc->sc_framing_errors = 0; 1511 1512 sc->sc_errors = 0; 1513 1514 splx(s); 1515 1516 log(LOG_WARNING, 1517 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1518 cz->cz_dev.dv_xname, sc->sc_channel, 1519 overflows, overflows == 1 ? "" : "s", 1520 parity_errors, 1521 framing_errors, framing_errors == 1 ? "" : "s"); 1522 } 1523 1524 /* 1525 * tx and rx ring buffer size macros: 1526 * 1527 * The transmitter and receiver both use ring buffers. For each one, there 1528 * is a get (consumer) and a put (producer) offset. The get value is the 1529 * next byte to be read from the ring, and the put is the next one to be 1530 * put into the ring. get == put means the ring is empty. 1531 * 1532 * For each ring, the firmware controls one of (get, put) and this driver 1533 * controls the other. For transmission, this driver updates put to point 1534 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1535 * for receive, the driver controls put, and this driver controls get. 1536 */ 1537 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1538 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1539 1540 /* 1541 * cztty_transmit() 1542 * 1543 * Look at the tty for this port and start sending. 1544 */ 1545 int 1546 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1547 { 1548 struct cz_softc *cz = CZTTY_CZ(sc); 1549 u_int move, get, put, size, address; 1550 #ifdef HOSTRAMCODE 1551 int error, done = 0; 1552 #else 1553 int done = 0; 1554 #endif 1555 1556 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1557 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1558 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1559 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1560 1561 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1562 #ifdef HOSTRAMCODE 1563 if (0) { 1564 move = min(tp->t_outq.c_cc, move); 1565 error = q_to_b(&tp->t_outq, 0, move); 1566 if (error != move) { 1567 printf("%s: channel %d: error moving to " 1568 "transmit buf\n", cz->cz_dev.dv_xname, 1569 sc->sc_channel); 1570 move = error; 1571 } 1572 } else { 1573 #endif 1574 move = min(ndqb(&tp->t_outq, 0), move); 1575 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1576 address + put, tp->t_outq.c_cf, move); 1577 ndflush(&tp->t_outq, move); 1578 #ifdef HOSTRAMCODE 1579 } 1580 #endif 1581 1582 put = ((put + move) % size); 1583 done = 1; 1584 } 1585 if (done) { 1586 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1587 } 1588 return (done); 1589 } 1590 1591 int 1592 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1593 { 1594 struct cz_softc *cz = CZTTY_CZ(sc); 1595 u_int get, put, size, address; 1596 int done = 0, ch; 1597 1598 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1599 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1600 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1601 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1602 1603 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1604 #ifdef HOSTRAMCODE 1605 if (hostram) 1606 ch = ((char *)fifoaddr)[get]; 1607 } else { 1608 #endif 1609 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1610 address + get); 1611 #ifdef HOSTRAMCODE 1612 } 1613 #endif 1614 (*linesw[tp->t_line].l_rint)(ch, tp); 1615 get = (get + 1) % size; 1616 done = 1; 1617 } 1618 if (done) { 1619 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1620 } 1621 return (done); 1622 } 1623