1 /* $NetBSD: cz.c,v 1.15 2001/01/20 19:10:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only utilize RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/proc.h> 78 #include <sys/device.h> 79 #include <sys/malloc.h> 80 #include <sys/tty.h> 81 #include <sys/conf.h> 82 #include <sys/time.h> 83 #include <sys/kernel.h> 84 #include <sys/fcntl.h> 85 #include <sys/syslog.h> 86 87 #include <sys/callout.h> 88 89 #include <dev/pci/pcireg.h> 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/czreg.h> 93 94 #include <dev/pci/plx9060reg.h> 95 #include <dev/pci/plx9060var.h> 96 97 #include <dev/microcode/cyclades-z/cyzfirm.h> 98 99 #define CZ_DRIVER_VERSION 0x20000411 100 101 #define CZ_POLL_MS 20 102 103 /* These are the interrupts we always use. */ 104 #define CZ_INTERRUPTS \ 105 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 106 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 107 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 108 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 109 110 /* 111 * cztty_softc: 112 * 113 * Per-channel (TTY) state. 114 */ 115 struct cztty_softc { 116 struct cz_softc *sc_parent; 117 struct tty *sc_tty; 118 119 struct callout sc_diag_ch; 120 121 int sc_channel; /* Also used to flag unattached chan */ 122 #define CZTTY_CHANNEL_DEAD -1 123 124 bus_space_tag_t sc_chan_st; /* channel space tag */ 125 bus_space_handle_t sc_chan_sh; /* channel space handle */ 126 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 127 128 u_int sc_overflows, 129 sc_parity_errors, 130 sc_framing_errors, 131 sc_errors; 132 133 int sc_swflags; 134 135 u_int32_t sc_rs_control_dtr, 136 sc_chanctl_hw_flow, 137 sc_chanctl_comm_baud, 138 sc_chanctl_rs_control, 139 sc_chanctl_comm_data_l, 140 sc_chanctl_comm_parity; 141 }; 142 143 /* 144 * cz_softc: 145 * 146 * Per-board state. 147 */ 148 struct cz_softc { 149 struct device cz_dev; /* generic device info */ 150 struct plx9060_config cz_plx; /* PLX 9060 config info */ 151 bus_space_tag_t cz_win_st; /* window space tag */ 152 bus_space_handle_t cz_win_sh; /* window space handle */ 153 struct callout cz_callout; /* callout for polling-mode */ 154 155 void *cz_ih; /* interrupt handle */ 156 157 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 158 int cz_nchannels; /* number of channels */ 159 int cz_nopenchan; /* number of open channels */ 160 struct cztty_softc *cz_ports; /* our array of ports */ 161 162 bus_addr_t cz_fwctl; /* offset of firmware control */ 163 }; 164 165 int cz_match(struct device *, struct cfdata *, void *); 166 void cz_attach(struct device *, struct device *, void *); 167 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 168 169 struct cfattach cz_ca = { 170 sizeof(struct cz_softc), cz_match, cz_attach 171 }; 172 173 void cz_reset_board(struct cz_softc *); 174 int cz_load_firmware(struct cz_softc *); 175 176 int cz_intr(void *); 177 void cz_poll(void *); 178 int cztty_transmit(struct cztty_softc *, struct tty *); 179 int cztty_receive(struct cztty_softc *, struct tty *); 180 181 struct cztty_softc * cztty_getttysoftc(dev_t dev); 182 int cztty_findmajor(void); 183 int cztty_major; 184 int cztty_attached_ttys; 185 int cz_timeout_ticks; 186 187 cdev_decl(cztty); 188 189 void czttystart(struct tty *tp); 190 int czttyparam(struct tty *tp, struct termios *t); 191 void cztty_shutdown(struct cztty_softc *sc); 192 void cztty_modem(struct cztty_softc *sc, int onoff); 193 void cztty_break(struct cztty_softc *sc, int onoff); 194 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 195 int cztty_to_tiocm(struct cztty_softc *sc); 196 void cztty_diag(void *arg); 197 198 extern struct cfdriver cz_cd; 199 200 /* Macros to clear/set/test flags. */ 201 #define SET(t, f) (t) |= (f) 202 #define CLR(t, f) (t) &= ~(f) 203 #define ISSET(t, f) ((t) & (f)) 204 205 /* 206 * Macros to read and write the PLX. 207 */ 208 #define CZ_PLX_READ(cz, reg) \ 209 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 210 #define CZ_PLX_WRITE(cz, reg, val) \ 211 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 212 (reg), (val)) 213 214 /* 215 * Macros to read and write the FPGA. We must already be in the FPGA 216 * window for this. 217 */ 218 #define CZ_FPGA_READ(cz, reg) \ 219 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 220 #define CZ_FPGA_WRITE(cz, reg, val) \ 221 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 222 223 /* 224 * Macros to read and write the firmware control structures in board RAM. 225 */ 226 #define CZ_FWCTL_READ(cz, off) \ 227 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 228 (cz)->cz_fwctl + (off)) 229 230 #define CZ_FWCTL_WRITE(cz, off, val) \ 231 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 232 (cz)->cz_fwctl + (off), (val)) 233 234 /* 235 * Convenience macros for cztty routines. PLX window MUST be to RAM. 236 */ 237 #define CZTTY_CHAN_READ(sc, off) \ 238 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 239 240 #define CZTTY_CHAN_WRITE(sc, off, val) \ 241 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 242 (off), (val)) 243 244 #define CZTTY_BUF_READ(sc, off) \ 245 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 246 247 #define CZTTY_BUF_WRITE(sc, off, val) \ 248 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 249 (off), (val)) 250 251 /* 252 * Convenience macros. 253 */ 254 #define CZ_WIN_RAM(cz) \ 255 do { \ 256 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 257 delay(100); \ 258 } while (0) 259 260 #define CZ_WIN_FPGA(cz) \ 261 do { \ 262 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 263 delay(100); \ 264 } while (0) 265 266 /***************************************************************************** 267 * Cyclades-Z controller code starts here... 268 *****************************************************************************/ 269 270 /* 271 * cz_match: 272 * 273 * Determine if the given PCI device is a Cyclades-Z board. 274 */ 275 int 276 cz_match(struct device *parent, 277 struct cfdata *match, 278 void *aux) 279 { 280 struct pci_attach_args *pa = aux; 281 282 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 283 switch (PCI_PRODUCT(pa->pa_id)) { 284 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 285 return (1); 286 } 287 } 288 289 return (0); 290 } 291 292 /* 293 * cz_attach: 294 * 295 * A Cyclades-Z board was found; attach it. 296 */ 297 void 298 cz_attach(struct device *parent, 299 struct device *self, 300 void *aux) 301 { 302 struct cz_softc *cz = (void *) self; 303 struct pci_attach_args *pa = aux; 304 pci_intr_handle_t ih; 305 const char *intrstr = NULL; 306 struct cztty_softc *sc; 307 struct tty *tp; 308 int i; 309 310 printf(": Cyclades-Z multiport serial\n"); 311 312 cz->cz_plx.plx_pc = pa->pa_pc; 313 cz->cz_plx.plx_tag = pa->pa_tag; 314 315 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 316 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 317 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 318 printf("%s: unable to map PLX registers\n", 319 cz->cz_dev.dv_xname); 320 return; 321 } 322 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 323 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 324 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 325 printf("%s: unable to map device window\n", 326 cz->cz_dev.dv_xname); 327 return; 328 } 329 330 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 331 cz->cz_nopenchan = 0; 332 333 /* 334 * Make sure that the board is completely stopped. 335 */ 336 CZ_WIN_FPGA(cz); 337 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 338 339 /* 340 * Load the board's firmware. 341 */ 342 if (cz_load_firmware(cz) != 0) 343 return; 344 345 /* 346 * Now that we're ready to roll, map and establish the interrupt 347 * handler. 348 */ 349 if (pci_intr_map(pa, &ih) != 0) { 350 /* 351 * The common case is for Cyclades-Z boards to run 352 * in polling mode, and thus not have an interrupt 353 * mapped for them. Don't bother reporting that 354 * the interrupt is not mappable, since this isn't 355 * really an error. 356 */ 357 cz->cz_ih = NULL; 358 goto polling_mode; 359 } else { 360 intrstr = pci_intr_string(pa->pa_pc, ih); 361 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 362 cz_intr, cz); 363 } 364 if (cz->cz_ih == NULL) { 365 printf("%s: unable to establish interrupt", 366 cz->cz_dev.dv_xname); 367 if (intrstr != NULL) 368 printf(" at %s", intrstr); 369 printf("\n"); 370 /* We will fall-back on polling mode. */ 371 } else 372 printf("%s: interrupting at %s\n", 373 cz->cz_dev.dv_xname, intrstr); 374 375 polling_mode: 376 if (cz->cz_ih == NULL) { 377 callout_init(&cz->cz_callout); 378 if (cz_timeout_ticks == 0) 379 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 380 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 381 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 382 cz_timeout_ticks == 1 ? "" : "s"); 383 } 384 385 if (cztty_major == 0) 386 cztty_major = cztty_findmajor(); 387 /* 388 * Allocate sufficient pointers for the children and 389 * attach them. Set all ports to a reasonable initial 390 * configuration while we're at it: 391 * 392 * disabled 393 * 8N1 394 * default baud rate 395 * hardware flow control. 396 */ 397 CZ_WIN_RAM(cz); 398 399 if (cz->cz_nchannels == 0) { 400 /* No channels? No more work to do! */ 401 return; 402 } 403 404 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 405 M_DEVBUF, M_WAITOK); 406 cztty_attached_ttys += cz->cz_nchannels; 407 memset(cz->cz_ports, 0, 408 sizeof(struct cztty_softc) * cz->cz_nchannels); 409 410 for (i = 0; i < cz->cz_nchannels; i++) { 411 sc = &cz->cz_ports[i]; 412 413 sc->sc_channel = i; 414 sc->sc_chan_st = cz->cz_win_st; 415 sc->sc_parent = cz; 416 417 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 418 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 419 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 420 printf("%s: unable to subregion channel %d control\n", 421 cz->cz_dev.dv_xname, i); 422 sc->sc_channel = CZTTY_CHANNEL_DEAD; 423 continue; 424 } 425 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 426 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 427 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 428 printf("%s: unable to subregion channel %d buffer\n", 429 cz->cz_dev.dv_xname, i); 430 sc->sc_channel = CZTTY_CHANNEL_DEAD; 431 continue; 432 } 433 434 callout_init(&sc->sc_diag_ch); 435 436 tp = ttymalloc(); 437 tp->t_dev = makedev(cztty_major, 438 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 439 tp->t_oproc = czttystart; 440 tp->t_param = czttyparam; 441 tty_attach(tp); 442 443 sc->sc_tty = tp; 444 445 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 446 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 447 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 448 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 449 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 450 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 451 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 452 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 453 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 454 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 455 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 456 } 457 } 458 459 /* 460 * cz_reset_board: 461 * 462 * Reset the board via the PLX. 463 */ 464 void 465 cz_reset_board(struct cz_softc *cz) 466 { 467 u_int32_t reg; 468 469 reg = CZ_PLX_READ(cz, PLX_CONTROL); 470 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 471 delay(1000); 472 473 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 474 delay(1000); 475 476 /* Now reload the PLX from its EEPROM. */ 477 reg = CZ_PLX_READ(cz, PLX_CONTROL); 478 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 479 delay(1000); 480 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 481 } 482 483 /* 484 * cz_load_firmware: 485 * 486 * Load the ZFIRM firmware into the board's RAM and start it 487 * running. 488 */ 489 int 490 cz_load_firmware(struct cz_softc *cz) 491 { 492 struct zfirm_header *zfh; 493 struct zfirm_config *zfc; 494 struct zfirm_block *zfb, *zblocks; 495 const u_int8_t *cp; 496 const char *board; 497 u_int32_t fid; 498 int i, j, nconfigs, nblocks, nbytes; 499 500 zfh = (struct zfirm_header *) cycladesz_firmware; 501 502 /* Find the config header. */ 503 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 504 printf("%s: bad ZFIRM config offset: 0x%x\n", 505 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 506 return (EIO); 507 } 508 zfc = (struct zfirm_config *)(cycladesz_firmware + 509 le32toh(zfh->zfh_configoff)); 510 nconfigs = le32toh(zfh->zfh_nconfig); 511 512 /* Locate the correct configuration for our board. */ 513 for (i = 0; i < nconfigs; i++, zfc++) { 514 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 515 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 516 break; 517 } 518 if (i == nconfigs) { 519 printf("%s: unable to locate config header\n", 520 cz->cz_dev.dv_xname); 521 return (EIO); 522 } 523 524 nblocks = le32toh(zfc->zfc_nblocks); 525 zblocks = (struct zfirm_block *)(cycladesz_firmware + 526 le32toh(zfh->zfh_blockoff)); 527 528 /* 529 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 530 * necessary. 531 */ 532 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 533 #if 0 534 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 535 #endif 536 ) { 537 #ifdef CZ_DEBUG 538 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 539 #endif 540 CZ_WIN_FPGA(cz); 541 for (i = 0; i < nblocks; i++) { 542 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 543 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 544 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 545 nbytes = le32toh(zfb->zfb_size); 546 cp = &cycladesz_firmware[ 547 le32toh(zfb->zfb_fileoff)]; 548 for (j = 0; j < nbytes; j++, cp++) { 549 bus_space_write_1(cz->cz_win_st, 550 cz->cz_win_sh, 0, *cp); 551 /* FPGA needs 30-100us to settle. */ 552 delay(10); 553 } 554 } 555 } 556 #ifdef CZ_DEBUG 557 printf("done\n"); 558 #endif 559 } 560 561 /* Now load the firmware. */ 562 CZ_WIN_RAM(cz); 563 564 for (i = 0; i < nblocks; i++) { 565 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 566 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 567 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 568 const u_int32_t *lp; 569 u_int32_t ro = le32toh(zfb->zfb_ramoff); 570 nbytes = le32toh(zfb->zfb_size); 571 lp = (const u_int32_t *) 572 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 573 for (j = 0; j < nbytes; j += 4, lp++) { 574 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 575 ro + j, le32toh(*lp)); 576 delay(10); 577 } 578 } 579 } 580 581 /* Now restart the MIPS. */ 582 CZ_WIN_FPGA(cz); 583 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 584 585 /* Wait for the MIPS to start, then report the results. */ 586 CZ_WIN_RAM(cz); 587 588 #ifdef CZ_DEBUG 589 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 590 #endif 591 for (i = 0; i < 100; i++) { 592 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 593 ZFIRM_SIG_OFF); 594 if (fid == ZFIRM_SIG) { 595 /* MIPS has booted. */ 596 break; 597 } else if (fid == ZFIRM_HLT) { 598 /* 599 * The MIPS has halted, usually due to a power 600 * shortage on the expansion module. 601 */ 602 printf("%s: MIPS halted; possible power supply " 603 "problem\n", cz->cz_dev.dv_xname); 604 return (EIO); 605 } else { 606 #ifdef CZ_DEBUG 607 if ((i % 8) == 0) 608 printf("."); 609 #endif 610 delay(250000); 611 } 612 } 613 #ifdef CZ_DEBUG 614 printf("\n"); 615 #endif 616 if (i == 100) { 617 CZ_WIN_FPGA(cz); 618 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 619 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 620 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 621 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 622 CZ_FPGA_READ(cz, FPGA_VERSION)); 623 return (EIO); 624 } 625 626 /* 627 * Locate the firmware control structures. 628 */ 629 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 630 ZFIRM_CTRLADDR_OFF); 631 #ifdef CZ_DEBUG 632 printf("%s: FWCTL structure at offset 0x%08lx\n", 633 cz->cz_dev.dv_xname, cz->cz_fwctl); 634 #endif 635 636 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 637 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 638 639 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 640 641 switch (cz->cz_mailbox0) { 642 case MAILBOX0_8Zo_V1: 643 board = "Cyclades-8Zo ver. 1"; 644 break; 645 646 case MAILBOX0_8Zo_V2: 647 board = "Cyclades-8Zo ver. 2"; 648 break; 649 650 case MAILBOX0_Ze_V1: 651 board = "Cyclades-Ze"; 652 break; 653 654 default: 655 board = "unknown Cyclades Z-series"; 656 break; 657 } 658 659 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 660 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 661 if (cz->cz_nchannels == 0) 662 printf("no channels attached, "); 663 else 664 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 665 cz->cz_nchannels, cztty_attached_ttys, 666 cztty_attached_ttys + (cz->cz_nchannels - 1)); 667 printf("firmware %x.%x.%x\n", 668 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 669 670 return (0); 671 } 672 673 /* 674 * cz_poll: 675 * 676 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 677 * ms. 678 */ 679 void 680 cz_poll(void *arg) 681 { 682 int s = spltty(); 683 struct cz_softc *cz = arg; 684 685 cz_intr(cz); 686 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 687 688 splx(s); 689 } 690 691 /* 692 * cz_intr: 693 * 694 * Interrupt service routine. 695 * 696 * We either are receiving an interrupt directly from the board, or we are 697 * in polling mode and it's time to poll. 698 */ 699 int 700 cz_intr(void *arg) 701 { 702 int rval = 0; 703 u_int command, channel, param; 704 struct cz_softc *cz = arg; 705 struct cztty_softc *sc; 706 struct tty *tp; 707 708 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 709 rval = 1; 710 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 711 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 712 713 /* now clear this interrupt, posslibly enabling another */ 714 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 715 716 if (cz->cz_ports == NULL) { 717 #ifdef CZ_DEBUG 718 printf("%s: interrupt on channel %d, but no channels\n", 719 cz->cz_dev.dv_xname, channel); 720 #endif 721 continue; 722 } 723 724 sc = &cz->cz_ports[channel]; 725 726 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 727 break; 728 729 tp = sc->sc_tty; 730 731 switch (command) { 732 case C_CM_TXFEMPTY: /* transmit cases */ 733 case C_CM_TXBEMPTY: 734 case C_CM_TXLOWWM: 735 case C_CM_INTBACK: 736 if (!ISSET(tp->t_state, TS_ISOPEN)) { 737 #ifdef CZ_DEBUG 738 printf("%s: tx intr on closed channel %d\n", 739 cz->cz_dev.dv_xname, channel); 740 #endif 741 break; 742 } 743 744 if (cztty_transmit(sc, tp)) { 745 /* 746 * Do wakeup stuff here. 747 */ 748 ttwakeup(tp); 749 wakeup(tp); 750 } 751 break; 752 753 case C_CM_RXNNDT: /* receive cases */ 754 case C_CM_RXHIWM: 755 case C_CM_INTBACK2: /* from restart ?? */ 756 #if 0 757 case C_CM_ICHAR: 758 #endif 759 if (!ISSET(tp->t_state, TS_ISOPEN)) { 760 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 761 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 762 break; 763 } 764 765 if (cztty_receive(sc, tp)) { 766 /* 767 * Do wakeup stuff here. 768 */ 769 ttwakeup(tp); 770 wakeup(tp); 771 } 772 break; 773 774 case C_CM_MDCD: 775 if (!ISSET(tp->t_state, TS_ISOPEN)) 776 break; 777 778 (void) (*tp->t_linesw->l_modem)(tp, 779 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 780 CHNCTL_RS_STATUS))); 781 break; 782 783 case C_CM_MDSR: 784 case C_CM_MRI: 785 case C_CM_MCTS: 786 case C_CM_MRTS: 787 break; 788 789 case C_CM_IOCTLW: 790 break; 791 792 case C_CM_PR_ERROR: 793 sc->sc_parity_errors++; 794 goto error_common; 795 796 case C_CM_FR_ERROR: 797 sc->sc_framing_errors++; 798 goto error_common; 799 800 case C_CM_OVR_ERROR: 801 sc->sc_overflows++; 802 error_common: 803 if (sc->sc_errors++ == 0) 804 callout_reset(&sc->sc_diag_ch, 60 * hz, 805 cztty_diag, sc); 806 break; 807 808 case C_CM_RXBRK: 809 if (!ISSET(tp->t_state, TS_ISOPEN)) 810 break; 811 812 /* 813 * A break is a \000 character with TTY_FE error 814 * flags set. So TTY_FE by itself works. 815 */ 816 (*tp->t_linesw->l_rint)(TTY_FE, tp); 817 ttwakeup(tp); 818 wakeup(tp); 819 break; 820 821 default: 822 #ifdef CZ_DEBUG 823 printf("%s: channel %d: Unknown interrupt 0x%x\n", 824 cz->cz_dev.dv_xname, sc->sc_channel, command); 825 #endif 826 break; 827 } 828 } 829 830 return (rval); 831 } 832 833 /* 834 * cz_wait_pci_doorbell: 835 * 836 * Wait for the pci doorbell to be clear - wait for pending 837 * activity to drain. 838 */ 839 int 840 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 841 { 842 int error; 843 844 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 845 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 846 if ((error != 0) && (error != EWOULDBLOCK)) 847 return (error); 848 } 849 return (0); 850 } 851 852 /***************************************************************************** 853 * Cyclades-Z TTY code starts here... 854 *****************************************************************************/ 855 856 #define CZTTYDIALOUT_MASK 0x80000 857 858 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 859 #define CZTTY_CZ(sc) ((sc)->sc_parent) 860 861 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 862 863 struct cztty_softc * 864 cztty_getttysoftc(dev_t dev) 865 { 866 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 867 struct cz_softc *cz; 868 869 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 870 k = j; 871 cz = device_lookup(&cz_cd, i); 872 if (cz == NULL) 873 continue; 874 if (cz->cz_ports == NULL) 875 continue; 876 j += cz->cz_nchannels; 877 if (j > u) 878 break; 879 } 880 881 if (i >= cz_cd.cd_ndevs) 882 return (NULL); 883 else 884 return (&cz->cz_ports[u - k]); 885 } 886 887 int 888 cztty_findmajor(void) 889 { 890 int maj; 891 892 for (maj = 0; maj < nchrdev; maj++) { 893 if (cdevsw[maj].d_open == czttyopen) 894 break; 895 } 896 897 return (maj == nchrdev) ? 0 : maj; 898 } 899 900 /* 901 * czttytty: 902 * 903 * Return a pointer to our tty. 904 */ 905 struct tty * 906 czttytty(dev_t dev) 907 { 908 struct cztty_softc *sc = CZTTY_SOFTC(dev); 909 910 #ifdef DIAGNOSTIC 911 if (sc == NULL) 912 panic("czttytty"); 913 #endif 914 915 return (sc->sc_tty); 916 } 917 918 /* 919 * cztty_shutdown: 920 * 921 * Shut down a port. 922 */ 923 void 924 cztty_shutdown(struct cztty_softc *sc) 925 { 926 struct cz_softc *cz = CZTTY_CZ(sc); 927 struct tty *tp = sc->sc_tty; 928 int s; 929 930 s = spltty(); 931 932 /* Clear any break condition set with TIOCSBRK. */ 933 cztty_break(sc, 0); 934 935 /* 936 * Hang up if necessary. Wait a bit, so the other side has time to 937 * notice even if we immediately open the port again. 938 */ 939 if (ISSET(tp->t_cflag, HUPCL)) { 940 cztty_modem(sc, 0); 941 (void) tsleep(tp, TTIPRI, ttclos, hz); 942 } 943 944 /* Disable the channel. */ 945 cz_wait_pci_doorbell(cz, "czdis"); 946 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 947 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 948 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 949 950 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 951 #ifdef CZ_DEBUG 952 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 953 #endif 954 callout_stop(&cz->cz_callout); 955 } 956 957 splx(s); 958 } 959 960 /* 961 * czttyopen: 962 * 963 * Open a Cyclades-Z serial port. 964 */ 965 int 966 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 967 { 968 struct cztty_softc *sc = CZTTY_SOFTC(dev); 969 struct cz_softc *cz; 970 struct tty *tp; 971 int s, error; 972 973 if (sc == NULL) 974 return (ENXIO); 975 976 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 977 return (ENXIO); 978 979 cz = CZTTY_CZ(sc); 980 tp = sc->sc_tty; 981 982 if (ISSET(tp->t_state, TS_ISOPEN) && 983 ISSET(tp->t_state, TS_XCLUDE) && 984 p->p_ucred->cr_uid != 0) 985 return (EBUSY); 986 987 s = spltty(); 988 989 /* 990 * Do the following iff this is a first open. 991 */ 992 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 993 struct termios t; 994 995 tp->t_dev = dev; 996 997 /* If we're turning things on, enable interrupts */ 998 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 999 #ifdef CZ_DEBUG 1000 printf("%s: Enabling polling.\n", 1001 cz->cz_dev.dv_xname); 1002 #endif 1003 callout_reset(&cz->cz_callout, cz_timeout_ticks, 1004 cz_poll, cz); 1005 } 1006 1007 /* 1008 * Enable the channel. Don't actually ring the 1009 * doorbell here; czttyparam() will do it for us. 1010 */ 1011 cz_wait_pci_doorbell(cz, "czopen"); 1012 1013 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1014 1015 /* 1016 * Initialize the termios status to the defaults. Add in the 1017 * sticky bits from TIOCSFLAGS. 1018 */ 1019 t.c_ispeed = 0; 1020 t.c_ospeed = TTYDEF_SPEED; 1021 t.c_cflag = TTYDEF_CFLAG; 1022 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1023 SET(t.c_cflag, CLOCAL); 1024 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1025 SET(t.c_cflag, CRTSCTS); 1026 1027 /* 1028 * Reset the input and output rings. Do this before 1029 * we call czttyparam(), as that function enables 1030 * the channel. 1031 */ 1032 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1033 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1034 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1035 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1036 1037 /* Make sure czttyparam() will see changes. */ 1038 tp->t_ospeed = 0; 1039 (void) czttyparam(tp, &t); 1040 tp->t_iflag = TTYDEF_IFLAG; 1041 tp->t_oflag = TTYDEF_OFLAG; 1042 tp->t_lflag = TTYDEF_LFLAG; 1043 ttychars(tp); 1044 ttsetwater(tp); 1045 1046 /* 1047 * Turn on DTR. We must always do this, even if carrier is not 1048 * present, because otherwise we'd have to use TIOCSDTR 1049 * immediately after setting CLOCAL, which applications do not 1050 * expect. We always assert DTR while the device is open 1051 * unless explicitly requested to deassert it. 1052 */ 1053 cztty_modem(sc, 1); 1054 } 1055 1056 splx(s); 1057 1058 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1059 if (error) 1060 goto bad; 1061 1062 error = (*tp->t_linesw->l_open)(dev, tp); 1063 if (error) 1064 goto bad; 1065 1066 return (0); 1067 1068 bad: 1069 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1070 /* 1071 * We failed to open the device, and nobody else had it opened. 1072 * Clean up the state as appropriate. 1073 */ 1074 cztty_shutdown(sc); 1075 } 1076 1077 return (error); 1078 } 1079 1080 /* 1081 * czttyclose: 1082 * 1083 * Close a Cyclades-Z serial port. 1084 */ 1085 int 1086 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1087 { 1088 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1089 struct tty *tp = sc->sc_tty; 1090 1091 /* XXX This is for cons.c. */ 1092 if (!ISSET(tp->t_state, TS_ISOPEN)) 1093 return (0); 1094 1095 (*tp->t_linesw->l_close)(tp, flags); 1096 ttyclose(tp); 1097 1098 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1099 /* 1100 * Although we got a last close, the device may still be in 1101 * use; e.g. if this was the dialout node, and there are still 1102 * processes waiting for carrier on the non-dialout node. 1103 */ 1104 cztty_shutdown(sc); 1105 } 1106 1107 return (0); 1108 } 1109 1110 /* 1111 * czttyread: 1112 * 1113 * Read from a Cyclades-Z serial port. 1114 */ 1115 int 1116 czttyread(dev_t dev, struct uio *uio, int flags) 1117 { 1118 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1119 struct tty *tp = sc->sc_tty; 1120 1121 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1122 } 1123 1124 /* 1125 * czttywrite: 1126 * 1127 * Write to a Cyclades-Z serial port. 1128 */ 1129 int 1130 czttywrite(dev_t dev, struct uio *uio, int flags) 1131 { 1132 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1133 struct tty *tp = sc->sc_tty; 1134 1135 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1136 } 1137 1138 /* 1139 * czttyioctl: 1140 * 1141 * Perform a control operation on a Cyclades-Z serial port. 1142 */ 1143 int 1144 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1145 { 1146 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1147 struct tty *tp = sc->sc_tty; 1148 int s, error; 1149 1150 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 1151 if (error >= 0) 1152 return (error); 1153 1154 error = ttioctl(tp, cmd, data, flag, p); 1155 if (error >= 0) 1156 return (error); 1157 1158 error = 0; 1159 1160 s = spltty(); 1161 1162 switch (cmd) { 1163 case TIOCSBRK: 1164 cztty_break(sc, 1); 1165 break; 1166 1167 case TIOCCBRK: 1168 cztty_break(sc, 0); 1169 break; 1170 1171 case TIOCGFLAGS: 1172 *(int *)data = sc->sc_swflags; 1173 break; 1174 1175 case TIOCSFLAGS: 1176 error = suser(p->p_ucred, &p->p_acflag); 1177 if (error) 1178 break; 1179 sc->sc_swflags = *(int *)data; 1180 break; 1181 1182 case TIOCSDTR: 1183 cztty_modem(sc, 1); 1184 break; 1185 1186 case TIOCCDTR: 1187 cztty_modem(sc, 0); 1188 break; 1189 1190 case TIOCMSET: 1191 case TIOCMBIS: 1192 case TIOCMBIC: 1193 tiocm_to_cztty(sc, cmd, *(int *)data); 1194 break; 1195 1196 case TIOCMGET: 1197 *(int *)data = cztty_to_tiocm(sc); 1198 break; 1199 1200 default: 1201 error = ENOTTY; 1202 break; 1203 } 1204 1205 splx(s); 1206 1207 return (error); 1208 } 1209 1210 /* 1211 * cztty_break: 1212 * 1213 * Set or clear BREAK on a port. 1214 */ 1215 void 1216 cztty_break(struct cztty_softc *sc, int onoff) 1217 { 1218 struct cz_softc *cz = CZTTY_CZ(sc); 1219 1220 cz_wait_pci_doorbell(cz, "czbreak"); 1221 1222 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1223 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1224 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1225 } 1226 1227 /* 1228 * cztty_modem: 1229 * 1230 * Set or clear DTR on a port. 1231 */ 1232 void 1233 cztty_modem(struct cztty_softc *sc, int onoff) 1234 { 1235 struct cz_softc *cz = CZTTY_CZ(sc); 1236 1237 if (sc->sc_rs_control_dtr == 0) 1238 return; 1239 1240 cz_wait_pci_doorbell(cz, "czmod"); 1241 1242 if (onoff) 1243 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1244 else 1245 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1246 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1247 1248 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1249 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1250 } 1251 1252 /* 1253 * tiocm_to_cztty: 1254 * 1255 * Process TIOCM* ioctls. 1256 */ 1257 void 1258 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1259 { 1260 struct cz_softc *cz = CZTTY_CZ(sc); 1261 u_int32_t czttybits; 1262 1263 czttybits = 0; 1264 if (ISSET(ttybits, TIOCM_DTR)) 1265 SET(czttybits, C_RS_DTR); 1266 if (ISSET(ttybits, TIOCM_RTS)) 1267 SET(czttybits, C_RS_RTS); 1268 1269 cz_wait_pci_doorbell(cz, "cztiocm"); 1270 1271 switch (how) { 1272 case TIOCMBIC: 1273 CLR(sc->sc_chanctl_rs_control, czttybits); 1274 break; 1275 1276 case TIOCMBIS: 1277 SET(sc->sc_chanctl_rs_control, czttybits); 1278 break; 1279 1280 case TIOCMSET: 1281 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1282 SET(sc->sc_chanctl_rs_control, czttybits); 1283 break; 1284 } 1285 1286 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1287 1288 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1289 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1290 } 1291 1292 /* 1293 * cztty_to_tiocm: 1294 * 1295 * Process the TIOCMGET ioctl. 1296 */ 1297 int 1298 cztty_to_tiocm(struct cztty_softc *sc) 1299 { 1300 struct cz_softc *cz = CZTTY_CZ(sc); 1301 u_int32_t rs_status, op_mode; 1302 int ttybits = 0; 1303 1304 cz_wait_pci_doorbell(cz, "cztty"); 1305 1306 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1307 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1308 1309 if (ISSET(rs_status, C_RS_RTS)) 1310 SET(ttybits, TIOCM_RTS); 1311 if (ISSET(rs_status, C_RS_CTS)) 1312 SET(ttybits, TIOCM_CTS); 1313 if (ISSET(rs_status, C_RS_DCD)) 1314 SET(ttybits, TIOCM_CAR); 1315 if (ISSET(rs_status, C_RS_DTR)) 1316 SET(ttybits, TIOCM_DTR); 1317 if (ISSET(rs_status, C_RS_RI)) 1318 SET(ttybits, TIOCM_RNG); 1319 if (ISSET(rs_status, C_RS_DSR)) 1320 SET(ttybits, TIOCM_DSR); 1321 1322 if (ISSET(op_mode, C_CH_ENABLE)) 1323 SET(ttybits, TIOCM_LE); 1324 1325 return (ttybits); 1326 } 1327 1328 /* 1329 * czttyparam: 1330 * 1331 * Set Cyclades-Z serial port parameters from termios. 1332 * 1333 * XXX Should just copy the whole termios after making 1334 * XXX sure all the changes could be done. 1335 */ 1336 int 1337 czttyparam(struct tty *tp, struct termios *t) 1338 { 1339 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1340 struct cz_softc *cz = CZTTY_CZ(sc); 1341 u_int32_t rs_status; 1342 int ospeed, cflag; 1343 1344 ospeed = t->c_ospeed; 1345 cflag = t->c_cflag; 1346 1347 /* Check requested parameters. */ 1348 if (ospeed < 0) 1349 return (EINVAL); 1350 if (t->c_ispeed && t->c_ispeed != ospeed) 1351 return (EINVAL); 1352 1353 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1354 SET(cflag, CLOCAL); 1355 CLR(cflag, HUPCL); 1356 } 1357 1358 /* 1359 * If there were no changes, don't do anything. This avoids dropping 1360 * input and improves performance when all we did was frob things like 1361 * VMIN and VTIME. 1362 */ 1363 if (tp->t_ospeed == ospeed && 1364 tp->t_cflag == cflag) 1365 return (0); 1366 1367 /* Data bits. */ 1368 sc->sc_chanctl_comm_data_l = 0; 1369 switch (t->c_cflag & CSIZE) { 1370 case CS5: 1371 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1372 break; 1373 1374 case CS6: 1375 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1376 break; 1377 1378 case CS7: 1379 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1380 break; 1381 1382 case CS8: 1383 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1384 break; 1385 } 1386 1387 /* Stop bits. */ 1388 if (t->c_cflag & CSTOPB) { 1389 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1390 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1391 else 1392 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1393 } else 1394 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1395 1396 /* Parity. */ 1397 if (t->c_cflag & PARENB) { 1398 if (t->c_cflag & PARODD) 1399 sc->sc_chanctl_comm_parity = C_PR_ODD; 1400 else 1401 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1402 } else 1403 sc->sc_chanctl_comm_parity = C_PR_NONE; 1404 1405 /* 1406 * Initialize flow control pins depending on the current flow control 1407 * mode. 1408 */ 1409 if (ISSET(t->c_cflag, CRTSCTS)) { 1410 sc->sc_rs_control_dtr = C_RS_DTR; 1411 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1412 } else if (ISSET(t->c_cflag, MDMBUF)) { 1413 sc->sc_rs_control_dtr = 0; 1414 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1415 } else { 1416 /* 1417 * If no flow control, then always set RTS. This will make 1418 * the other side happy if it mistakenly thinks we're doing 1419 * RTS/CTS flow control. 1420 */ 1421 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1422 sc->sc_chanctl_hw_flow = 0; 1423 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1424 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1425 else 1426 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1427 } 1428 1429 /* Baud rate. */ 1430 sc->sc_chanctl_comm_baud = ospeed; 1431 1432 /* Copy to tty. */ 1433 tp->t_ispeed = 0; 1434 tp->t_ospeed = t->c_ospeed; 1435 tp->t_cflag = t->c_cflag; 1436 1437 /* 1438 * Now load the channel control structure. 1439 */ 1440 1441 cz_wait_pci_doorbell(cz, "czparam"); 1442 1443 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1444 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1445 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1446 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1447 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1448 1449 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1450 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1451 1452 cz_wait_pci_doorbell(cz, "czparam"); 1453 1454 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1455 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1456 1457 cz_wait_pci_doorbell(cz, "czparam"); 1458 1459 /* 1460 * Update the tty layer's idea of the carrier bit, in case we changed 1461 * CLOCAL. We don't hang up here; we only do that by explicit 1462 * request. 1463 */ 1464 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1465 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1466 1467 return (0); 1468 } 1469 1470 /* 1471 * czttystart: 1472 * 1473 * Start or restart transmission. 1474 */ 1475 void 1476 czttystart(struct tty *tp) 1477 { 1478 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1479 int s; 1480 1481 s = spltty(); 1482 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1483 goto out; 1484 1485 if (tp->t_outq.c_cc <= tp->t_lowat) { 1486 if (ISSET(tp->t_state, TS_ASLEEP)) { 1487 CLR(tp->t_state, TS_ASLEEP); 1488 wakeup(&tp->t_outq); 1489 } 1490 selwakeup(&tp->t_wsel); 1491 if (tp->t_outq.c_cc == 0) 1492 goto out; 1493 } 1494 1495 cztty_transmit(sc, tp); 1496 out: 1497 splx(s); 1498 } 1499 1500 /* 1501 * czttystop: 1502 * 1503 * Stop output, e.g., for ^S or output flush. 1504 */ 1505 void 1506 czttystop(struct tty *tp, int flag) 1507 { 1508 1509 /* 1510 * XXX We don't do anything here, yet. Mostly, I don't know 1511 * XXX exactly how this should be implemented on this device. 1512 * XXX We've given a big chunk of data to the MIPS already, 1513 * XXX and I don't know how we request the MIPS to stop sending 1514 * XXX the data. So, punt for now. --thorpej 1515 */ 1516 } 1517 1518 /* 1519 * cztty_diag: 1520 * 1521 * Issue a scheduled diagnostic message. 1522 */ 1523 void 1524 cztty_diag(void *arg) 1525 { 1526 struct cztty_softc *sc = arg; 1527 struct cz_softc *cz = CZTTY_CZ(sc); 1528 u_int overflows, parity_errors, framing_errors; 1529 int s; 1530 1531 s = spltty(); 1532 1533 overflows = sc->sc_overflows; 1534 sc->sc_overflows = 0; 1535 1536 parity_errors = sc->sc_parity_errors; 1537 sc->sc_parity_errors = 0; 1538 1539 framing_errors = sc->sc_framing_errors; 1540 sc->sc_framing_errors = 0; 1541 1542 sc->sc_errors = 0; 1543 1544 splx(s); 1545 1546 log(LOG_WARNING, 1547 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1548 cz->cz_dev.dv_xname, sc->sc_channel, 1549 overflows, overflows == 1 ? "" : "s", 1550 parity_errors, 1551 framing_errors, framing_errors == 1 ? "" : "s"); 1552 } 1553 1554 /* 1555 * tx and rx ring buffer size macros: 1556 * 1557 * The transmitter and receiver both use ring buffers. For each one, there 1558 * is a get (consumer) and a put (producer) offset. The get value is the 1559 * next byte to be read from the ring, and the put is the next one to be 1560 * put into the ring. get == put means the ring is empty. 1561 * 1562 * For each ring, the firmware controls one of (get, put) and this driver 1563 * controls the other. For transmission, this driver updates put to point 1564 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1565 * for receive, the driver controls put, and this driver controls get. 1566 */ 1567 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1568 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1569 1570 /* 1571 * cztty_transmit() 1572 * 1573 * Look at the tty for this port and start sending. 1574 */ 1575 int 1576 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1577 { 1578 struct cz_softc *cz = CZTTY_CZ(sc); 1579 u_int move, get, put, size, address; 1580 #ifdef HOSTRAMCODE 1581 int error, done = 0; 1582 #else 1583 int done = 0; 1584 #endif 1585 1586 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1587 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1588 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1589 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1590 1591 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1592 #ifdef HOSTRAMCODE 1593 if (0) { 1594 move = min(tp->t_outq.c_cc, move); 1595 error = q_to_b(&tp->t_outq, 0, move); 1596 if (error != move) { 1597 printf("%s: channel %d: error moving to " 1598 "transmit buf\n", cz->cz_dev.dv_xname, 1599 sc->sc_channel); 1600 move = error; 1601 } 1602 } else { 1603 #endif 1604 move = min(ndqb(&tp->t_outq, 0), move); 1605 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1606 address + put, tp->t_outq.c_cf, move); 1607 ndflush(&tp->t_outq, move); 1608 #ifdef HOSTRAMCODE 1609 } 1610 #endif 1611 1612 put = ((put + move) % size); 1613 done = 1; 1614 } 1615 if (done) { 1616 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1617 } 1618 return (done); 1619 } 1620 1621 int 1622 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1623 { 1624 struct cz_softc *cz = CZTTY_CZ(sc); 1625 u_int get, put, size, address; 1626 int done = 0, ch; 1627 1628 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1629 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1630 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1631 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1632 1633 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1634 #ifdef HOSTRAMCODE 1635 if (hostram) 1636 ch = ((char *)fifoaddr)[get]; 1637 } else { 1638 #endif 1639 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1640 address + get); 1641 #ifdef HOSTRAMCODE 1642 } 1643 #endif 1644 (*tp->t_linesw->l_rint)(ch, tp); 1645 get = (get + 1) % size; 1646 done = 1; 1647 } 1648 if (done) { 1649 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1650 } 1651 return (done); 1652 } 1653