1 /* $NetBSD: cz.c,v 1.20 2002/09/06 13:18:43 gehenna Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Zembu Labs, Inc. 5 * All rights reserved. 6 * 7 * Authors: Jason R. Thorpe <thorpej@zembu.com> 8 * Bill Studenmund <wrstuden@zembu.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Zembu Labs, Inc. 21 * 4. Neither the name of Zembu Labs nor the names of its employees may 22 * be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 27 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 28 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 39 * 40 * Some notes: 41 * 42 * - The Cyclades-Z has fully automatic hardware (and software!) 43 * flow control. We only utilize RTS/CTS flow control here, 44 * and it is implemented in a very simplistic manner. This 45 * may be an area of future work. 46 * 47 * - The PLX can map the either the board's RAM or host RAM 48 * into the MIPS's memory window. This would enable us to 49 * use less expensive (for us) memory reads/writes to host 50 * RAM, rather than time-consuming reads/writes to PCI 51 * memory space. However, the PLX can only map a 0-128M 52 * window, so we would have to ensure that the DMA address 53 * of the host RAM fits there. This is kind of a pain, 54 * so we just don't bother right now. 55 * 56 * - In a perfect world, we would use the autoconfiguration 57 * mechanism to attach the TTYs that we find. However, 58 * that leads to somewhat icky looking autoconfiguration 59 * messages (one for every TTY, up to 64 per board!). So 60 * we don't do it that way, but assign minors as if there 61 * were the max of 64 ports per board. 62 * 63 * - We don't bother with PPS support here. There are so many 64 * ports, each with a large amount of buffer space, that the 65 * normal mode of operation is to poll the boards regularly 66 * (generally, every 20ms or so). This makes this driver 67 * unsuitable for PPS, as the latency will be generally too 68 * high. 69 */ 70 /* 71 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 72 * for FreeBSD 3.2. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: cz.c,v 1.20 2002/09/06 13:18:43 gehenna Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/proc.h> 81 #include <sys/device.h> 82 #include <sys/malloc.h> 83 #include <sys/tty.h> 84 #include <sys/conf.h> 85 #include <sys/time.h> 86 #include <sys/kernel.h> 87 #include <sys/fcntl.h> 88 #include <sys/syslog.h> 89 90 #include <sys/callout.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/czreg.h> 96 97 #include <dev/pci/plx9060reg.h> 98 #include <dev/pci/plx9060var.h> 99 100 #include <dev/microcode/cyclades-z/cyzfirm.h> 101 102 #define CZ_DRIVER_VERSION 0x20000411 103 104 #define CZ_POLL_MS 20 105 106 /* These are the interrupts we always use. */ 107 #define CZ_INTERRUPTS \ 108 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 109 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 110 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 111 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 112 113 /* 114 * cztty_softc: 115 * 116 * Per-channel (TTY) state. 117 */ 118 struct cztty_softc { 119 struct cz_softc *sc_parent; 120 struct tty *sc_tty; 121 122 struct callout sc_diag_ch; 123 124 int sc_channel; /* Also used to flag unattached chan */ 125 #define CZTTY_CHANNEL_DEAD -1 126 127 bus_space_tag_t sc_chan_st; /* channel space tag */ 128 bus_space_handle_t sc_chan_sh; /* channel space handle */ 129 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 130 131 u_int sc_overflows, 132 sc_parity_errors, 133 sc_framing_errors, 134 sc_errors; 135 136 int sc_swflags; 137 138 u_int32_t sc_rs_control_dtr, 139 sc_chanctl_hw_flow, 140 sc_chanctl_comm_baud, 141 sc_chanctl_rs_control, 142 sc_chanctl_comm_data_l, 143 sc_chanctl_comm_parity; 144 }; 145 146 /* 147 * cz_softc: 148 * 149 * Per-board state. 150 */ 151 struct cz_softc { 152 struct device cz_dev; /* generic device info */ 153 struct plx9060_config cz_plx; /* PLX 9060 config info */ 154 bus_space_tag_t cz_win_st; /* window space tag */ 155 bus_space_handle_t cz_win_sh; /* window space handle */ 156 struct callout cz_callout; /* callout for polling-mode */ 157 158 void *cz_ih; /* interrupt handle */ 159 160 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 161 int cz_nchannels; /* number of channels */ 162 int cz_nopenchan; /* number of open channels */ 163 struct cztty_softc *cz_ports; /* our array of ports */ 164 165 bus_addr_t cz_fwctl; /* offset of firmware control */ 166 }; 167 168 int cz_match(struct device *, struct cfdata *, void *); 169 void cz_attach(struct device *, struct device *, void *); 170 int cz_wait_pci_doorbell(struct cz_softc *, const char *); 171 172 struct cfattach cz_ca = { 173 sizeof(struct cz_softc), cz_match, cz_attach 174 }; 175 176 void cz_reset_board(struct cz_softc *); 177 int cz_load_firmware(struct cz_softc *); 178 179 int cz_intr(void *); 180 void cz_poll(void *); 181 int cztty_transmit(struct cztty_softc *, struct tty *); 182 int cztty_receive(struct cztty_softc *, struct tty *); 183 184 struct cztty_softc * cztty_getttysoftc(dev_t dev); 185 int cztty_attached_ttys; 186 int cz_timeout_ticks; 187 188 void czttystart(struct tty *tp); 189 int czttyparam(struct tty *tp, struct termios *t); 190 void cztty_shutdown(struct cztty_softc *sc); 191 void cztty_modem(struct cztty_softc *sc, int onoff); 192 void cztty_break(struct cztty_softc *sc, int onoff); 193 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 194 int cztty_to_tiocm(struct cztty_softc *sc); 195 void cztty_diag(void *arg); 196 197 extern struct cfdriver cz_cd; 198 199 dev_type_open(czttyopen); 200 dev_type_close(czttyclose); 201 dev_type_read(czttyread); 202 dev_type_write(czttywrite); 203 dev_type_ioctl(czttyioctl); 204 dev_type_stop(czttystop); 205 dev_type_tty(czttytty); 206 dev_type_poll(czttypoll); 207 208 const struct cdevsw cz_cdevsw = { 209 czttyopen, czttyclose, czttyread, czttywrite, czttyioctl, 210 czttystop, czttytty, czttypoll, nommap, D_TTY 211 }; 212 213 /* Macros to clear/set/test flags. */ 214 #define SET(t, f) (t) |= (f) 215 #define CLR(t, f) (t) &= ~(f) 216 #define ISSET(t, f) ((t) & (f)) 217 218 /* 219 * Macros to read and write the PLX. 220 */ 221 #define CZ_PLX_READ(cz, reg) \ 222 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 223 #define CZ_PLX_WRITE(cz, reg, val) \ 224 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 225 (reg), (val)) 226 227 /* 228 * Macros to read and write the FPGA. We must already be in the FPGA 229 * window for this. 230 */ 231 #define CZ_FPGA_READ(cz, reg) \ 232 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 233 #define CZ_FPGA_WRITE(cz, reg, val) \ 234 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 235 236 /* 237 * Macros to read and write the firmware control structures in board RAM. 238 */ 239 #define CZ_FWCTL_READ(cz, off) \ 240 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 241 (cz)->cz_fwctl + (off)) 242 243 #define CZ_FWCTL_WRITE(cz, off, val) \ 244 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 245 (cz)->cz_fwctl + (off), (val)) 246 247 /* 248 * Convenience macros for cztty routines. PLX window MUST be to RAM. 249 */ 250 #define CZTTY_CHAN_READ(sc, off) \ 251 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 252 253 #define CZTTY_CHAN_WRITE(sc, off, val) \ 254 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 255 (off), (val)) 256 257 #define CZTTY_BUF_READ(sc, off) \ 258 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 259 260 #define CZTTY_BUF_WRITE(sc, off, val) \ 261 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 262 (off), (val)) 263 264 /* 265 * Convenience macros. 266 */ 267 #define CZ_WIN_RAM(cz) \ 268 do { \ 269 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 270 delay(100); \ 271 } while (0) 272 273 #define CZ_WIN_FPGA(cz) \ 274 do { \ 275 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 276 delay(100); \ 277 } while (0) 278 279 /***************************************************************************** 280 * Cyclades-Z controller code starts here... 281 *****************************************************************************/ 282 283 /* 284 * cz_match: 285 * 286 * Determine if the given PCI device is a Cyclades-Z board. 287 */ 288 int 289 cz_match(struct device *parent, 290 struct cfdata *match, 291 void *aux) 292 { 293 struct pci_attach_args *pa = aux; 294 295 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 296 switch (PCI_PRODUCT(pa->pa_id)) { 297 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 298 return (1); 299 } 300 } 301 302 return (0); 303 } 304 305 /* 306 * cz_attach: 307 * 308 * A Cyclades-Z board was found; attach it. 309 */ 310 void 311 cz_attach(struct device *parent, 312 struct device *self, 313 void *aux) 314 { 315 struct cz_softc *cz = (void *) self; 316 struct pci_attach_args *pa = aux; 317 pci_intr_handle_t ih; 318 const char *intrstr = NULL; 319 struct cztty_softc *sc; 320 struct tty *tp; 321 int i; 322 323 printf(": Cyclades-Z multiport serial\n"); 324 325 cz->cz_plx.plx_pc = pa->pa_pc; 326 cz->cz_plx.plx_tag = pa->pa_tag; 327 328 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 329 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 330 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL) != 0) { 331 printf("%s: unable to map PLX registers\n", 332 cz->cz_dev.dv_xname); 333 return; 334 } 335 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 336 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 337 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL) != 0) { 338 printf("%s: unable to map device window\n", 339 cz->cz_dev.dv_xname); 340 return; 341 } 342 343 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 344 cz->cz_nopenchan = 0; 345 346 /* 347 * Make sure that the board is completely stopped. 348 */ 349 CZ_WIN_FPGA(cz); 350 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 351 352 /* 353 * Load the board's firmware. 354 */ 355 if (cz_load_firmware(cz) != 0) 356 return; 357 358 /* 359 * Now that we're ready to roll, map and establish the interrupt 360 * handler. 361 */ 362 if (pci_intr_map(pa, &ih) != 0) { 363 /* 364 * The common case is for Cyclades-Z boards to run 365 * in polling mode, and thus not have an interrupt 366 * mapped for them. Don't bother reporting that 367 * the interrupt is not mappable, since this isn't 368 * really an error. 369 */ 370 cz->cz_ih = NULL; 371 goto polling_mode; 372 } else { 373 intrstr = pci_intr_string(pa->pa_pc, ih); 374 cz->cz_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, 375 cz_intr, cz); 376 } 377 if (cz->cz_ih == NULL) { 378 printf("%s: unable to establish interrupt", 379 cz->cz_dev.dv_xname); 380 if (intrstr != NULL) 381 printf(" at %s", intrstr); 382 printf("\n"); 383 /* We will fall-back on polling mode. */ 384 } else 385 printf("%s: interrupting at %s\n", 386 cz->cz_dev.dv_xname, intrstr); 387 388 polling_mode: 389 if (cz->cz_ih == NULL) { 390 callout_init(&cz->cz_callout); 391 if (cz_timeout_ticks == 0) 392 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 393 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 394 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 395 cz_timeout_ticks == 1 ? "" : "s"); 396 } 397 398 /* 399 * Allocate sufficient pointers for the children and 400 * attach them. Set all ports to a reasonable initial 401 * configuration while we're at it: 402 * 403 * disabled 404 * 8N1 405 * default baud rate 406 * hardware flow control. 407 */ 408 CZ_WIN_RAM(cz); 409 410 if (cz->cz_nchannels == 0) { 411 /* No channels? No more work to do! */ 412 return; 413 } 414 415 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 416 M_DEVBUF, M_WAITOK|M_ZERO); 417 cztty_attached_ttys += cz->cz_nchannels; 418 419 for (i = 0; i < cz->cz_nchannels; i++) { 420 sc = &cz->cz_ports[i]; 421 422 sc->sc_channel = i; 423 sc->sc_chan_st = cz->cz_win_st; 424 sc->sc_parent = cz; 425 426 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 427 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 428 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 429 printf("%s: unable to subregion channel %d control\n", 430 cz->cz_dev.dv_xname, i); 431 sc->sc_channel = CZTTY_CHANNEL_DEAD; 432 continue; 433 } 434 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 435 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 436 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 437 printf("%s: unable to subregion channel %d buffer\n", 438 cz->cz_dev.dv_xname, i); 439 sc->sc_channel = CZTTY_CHANNEL_DEAD; 440 continue; 441 } 442 443 callout_init(&sc->sc_diag_ch); 444 445 tp = ttymalloc(); 446 tp->t_dev = makedev(cdevsw_lookup_major(&cz_cdevsw), 447 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 448 tp->t_oproc = czttystart; 449 tp->t_param = czttyparam; 450 tty_attach(tp); 451 452 sc->sc_tty = tp; 453 454 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 455 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 456 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 457 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 458 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 459 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 460 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 461 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 462 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 463 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 464 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 465 } 466 } 467 468 /* 469 * cz_reset_board: 470 * 471 * Reset the board via the PLX. 472 */ 473 void 474 cz_reset_board(struct cz_softc *cz) 475 { 476 u_int32_t reg; 477 478 reg = CZ_PLX_READ(cz, PLX_CONTROL); 479 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 480 delay(1000); 481 482 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 483 delay(1000); 484 485 /* Now reload the PLX from its EEPROM. */ 486 reg = CZ_PLX_READ(cz, PLX_CONTROL); 487 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 488 delay(1000); 489 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 490 } 491 492 /* 493 * cz_load_firmware: 494 * 495 * Load the ZFIRM firmware into the board's RAM and start it 496 * running. 497 */ 498 int 499 cz_load_firmware(struct cz_softc *cz) 500 { 501 struct zfirm_header *zfh; 502 struct zfirm_config *zfc; 503 struct zfirm_block *zfb, *zblocks; 504 const u_int8_t *cp; 505 const char *board; 506 u_int32_t fid; 507 int i, j, nconfigs, nblocks, nbytes; 508 509 zfh = (struct zfirm_header *) cycladesz_firmware; 510 511 /* Find the config header. */ 512 if (le32toh(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 513 printf("%s: bad ZFIRM config offset: 0x%x\n", 514 cz->cz_dev.dv_xname, le32toh(zfh->zfh_configoff)); 515 return (EIO); 516 } 517 zfc = (struct zfirm_config *)(cycladesz_firmware + 518 le32toh(zfh->zfh_configoff)); 519 nconfigs = le32toh(zfh->zfh_nconfig); 520 521 /* Locate the correct configuration for our board. */ 522 for (i = 0; i < nconfigs; i++, zfc++) { 523 if (le32toh(zfc->zfc_mailbox) == cz->cz_mailbox0 && 524 le32toh(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 525 break; 526 } 527 if (i == nconfigs) { 528 printf("%s: unable to locate config header\n", 529 cz->cz_dev.dv_xname); 530 return (EIO); 531 } 532 533 nblocks = le32toh(zfc->zfc_nblocks); 534 zblocks = (struct zfirm_block *)(cycladesz_firmware + 535 le32toh(zfh->zfh_blockoff)); 536 537 /* 538 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 539 * necessary. 540 */ 541 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 542 #if 0 543 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 544 #endif 545 ) { 546 #ifdef CZ_DEBUG 547 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 548 #endif 549 CZ_WIN_FPGA(cz); 550 for (i = 0; i < nblocks; i++) { 551 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 552 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 553 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FPGA) { 554 nbytes = le32toh(zfb->zfb_size); 555 cp = &cycladesz_firmware[ 556 le32toh(zfb->zfb_fileoff)]; 557 for (j = 0; j < nbytes; j++, cp++) { 558 bus_space_write_1(cz->cz_win_st, 559 cz->cz_win_sh, 0, *cp); 560 /* FPGA needs 30-100us to settle. */ 561 delay(10); 562 } 563 } 564 } 565 #ifdef CZ_DEBUG 566 printf("done\n"); 567 #endif 568 } 569 570 /* Now load the firmware. */ 571 CZ_WIN_RAM(cz); 572 573 for (i = 0; i < nblocks; i++) { 574 /* zfb = zblocks + le32toh(zfc->zfc_blocklist[i]) ?? */ 575 zfb = &zblocks[le32toh(zfc->zfc_blocklist[i])]; 576 if (le32toh(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 577 const u_int32_t *lp; 578 u_int32_t ro = le32toh(zfb->zfb_ramoff); 579 nbytes = le32toh(zfb->zfb_size); 580 lp = (const u_int32_t *) 581 &cycladesz_firmware[le32toh(zfb->zfb_fileoff)]; 582 for (j = 0; j < nbytes; j += 4, lp++) { 583 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 584 ro + j, le32toh(*lp)); 585 delay(10); 586 } 587 } 588 } 589 590 /* Now restart the MIPS. */ 591 CZ_WIN_FPGA(cz); 592 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 593 594 /* Wait for the MIPS to start, then report the results. */ 595 CZ_WIN_RAM(cz); 596 597 #ifdef CZ_DEBUG 598 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 599 #endif 600 for (i = 0; i < 100; i++) { 601 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 602 ZFIRM_SIG_OFF); 603 if (fid == ZFIRM_SIG) { 604 /* MIPS has booted. */ 605 break; 606 } else if (fid == ZFIRM_HLT) { 607 /* 608 * The MIPS has halted, usually due to a power 609 * shortage on the expansion module. 610 */ 611 printf("%s: MIPS halted; possible power supply " 612 "problem\n", cz->cz_dev.dv_xname); 613 return (EIO); 614 } else { 615 #ifdef CZ_DEBUG 616 if ((i % 8) == 0) 617 printf("."); 618 #endif 619 delay(250000); 620 } 621 } 622 #ifdef CZ_DEBUG 623 printf("\n"); 624 #endif 625 if (i == 100) { 626 CZ_WIN_FPGA(cz); 627 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 628 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 629 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 630 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 631 CZ_FPGA_READ(cz, FPGA_VERSION)); 632 return (EIO); 633 } 634 635 /* 636 * Locate the firmware control structures. 637 */ 638 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 639 ZFIRM_CTRLADDR_OFF); 640 #ifdef CZ_DEBUG 641 printf("%s: FWCTL structure at offset 0x%08lx\n", 642 cz->cz_dev.dv_xname, cz->cz_fwctl); 643 #endif 644 645 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 646 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 647 648 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 649 650 switch (cz->cz_mailbox0) { 651 case MAILBOX0_8Zo_V1: 652 board = "Cyclades-8Zo ver. 1"; 653 break; 654 655 case MAILBOX0_8Zo_V2: 656 board = "Cyclades-8Zo ver. 2"; 657 break; 658 659 case MAILBOX0_Ze_V1: 660 board = "Cyclades-Ze"; 661 break; 662 663 default: 664 board = "unknown Cyclades Z-series"; 665 break; 666 } 667 668 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 669 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 670 if (cz->cz_nchannels == 0) 671 printf("no channels attached, "); 672 else 673 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 674 cz->cz_nchannels, cztty_attached_ttys, 675 cztty_attached_ttys + (cz->cz_nchannels - 1)); 676 printf("firmware %x.%x.%x\n", 677 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 678 679 return (0); 680 } 681 682 /* 683 * cz_poll: 684 * 685 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 686 * ms. 687 */ 688 void 689 cz_poll(void *arg) 690 { 691 int s = spltty(); 692 struct cz_softc *cz = arg; 693 694 cz_intr(cz); 695 callout_reset(&cz->cz_callout, cz_timeout_ticks, cz_poll, cz); 696 697 splx(s); 698 } 699 700 /* 701 * cz_intr: 702 * 703 * Interrupt service routine. 704 * 705 * We either are receiving an interrupt directly from the board, or we are 706 * in polling mode and it's time to poll. 707 */ 708 int 709 cz_intr(void *arg) 710 { 711 int rval = 0; 712 u_int command, channel, param; 713 struct cz_softc *cz = arg; 714 struct cztty_softc *sc; 715 struct tty *tp; 716 717 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 718 rval = 1; 719 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 720 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 721 722 /* now clear this interrupt, posslibly enabling another */ 723 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 724 725 if (cz->cz_ports == NULL) { 726 #ifdef CZ_DEBUG 727 printf("%s: interrupt on channel %d, but no channels\n", 728 cz->cz_dev.dv_xname, channel); 729 #endif 730 continue; 731 } 732 733 sc = &cz->cz_ports[channel]; 734 735 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 736 break; 737 738 tp = sc->sc_tty; 739 740 switch (command) { 741 case C_CM_TXFEMPTY: /* transmit cases */ 742 case C_CM_TXBEMPTY: 743 case C_CM_TXLOWWM: 744 case C_CM_INTBACK: 745 if (!ISSET(tp->t_state, TS_ISOPEN)) { 746 #ifdef CZ_DEBUG 747 printf("%s: tx intr on closed channel %d\n", 748 cz->cz_dev.dv_xname, channel); 749 #endif 750 break; 751 } 752 753 if (cztty_transmit(sc, tp)) { 754 /* 755 * Do wakeup stuff here. 756 */ 757 ttwakeup(tp); 758 wakeup(tp); 759 } 760 break; 761 762 case C_CM_RXNNDT: /* receive cases */ 763 case C_CM_RXHIWM: 764 case C_CM_INTBACK2: /* from restart ?? */ 765 #if 0 766 case C_CM_ICHAR: 767 #endif 768 if (!ISSET(tp->t_state, TS_ISOPEN)) { 769 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 770 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 771 break; 772 } 773 774 if (cztty_receive(sc, tp)) { 775 /* 776 * Do wakeup stuff here. 777 */ 778 ttwakeup(tp); 779 wakeup(tp); 780 } 781 break; 782 783 case C_CM_MDCD: 784 if (!ISSET(tp->t_state, TS_ISOPEN)) 785 break; 786 787 (void) (*tp->t_linesw->l_modem)(tp, 788 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 789 CHNCTL_RS_STATUS))); 790 break; 791 792 case C_CM_MDSR: 793 case C_CM_MRI: 794 case C_CM_MCTS: 795 case C_CM_MRTS: 796 break; 797 798 case C_CM_IOCTLW: 799 break; 800 801 case C_CM_PR_ERROR: 802 sc->sc_parity_errors++; 803 goto error_common; 804 805 case C_CM_FR_ERROR: 806 sc->sc_framing_errors++; 807 goto error_common; 808 809 case C_CM_OVR_ERROR: 810 sc->sc_overflows++; 811 error_common: 812 if (sc->sc_errors++ == 0) 813 callout_reset(&sc->sc_diag_ch, 60 * hz, 814 cztty_diag, sc); 815 break; 816 817 case C_CM_RXBRK: 818 if (!ISSET(tp->t_state, TS_ISOPEN)) 819 break; 820 821 /* 822 * A break is a \000 character with TTY_FE error 823 * flags set. So TTY_FE by itself works. 824 */ 825 (*tp->t_linesw->l_rint)(TTY_FE, tp); 826 ttwakeup(tp); 827 wakeup(tp); 828 break; 829 830 default: 831 #ifdef CZ_DEBUG 832 printf("%s: channel %d: Unknown interrupt 0x%x\n", 833 cz->cz_dev.dv_xname, sc->sc_channel, command); 834 #endif 835 break; 836 } 837 } 838 839 return (rval); 840 } 841 842 /* 843 * cz_wait_pci_doorbell: 844 * 845 * Wait for the pci doorbell to be clear - wait for pending 846 * activity to drain. 847 */ 848 int 849 cz_wait_pci_doorbell(struct cz_softc *cz, const char *wstring) 850 { 851 int error; 852 853 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 854 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 855 if ((error != 0) && (error != EWOULDBLOCK)) 856 return (error); 857 } 858 return (0); 859 } 860 861 /***************************************************************************** 862 * Cyclades-Z TTY code starts here... 863 *****************************************************************************/ 864 865 #define CZTTYDIALOUT_MASK 0x80000 866 867 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 868 #define CZTTY_CZ(sc) ((sc)->sc_parent) 869 870 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 871 872 struct cztty_softc * 873 cztty_getttysoftc(dev_t dev) 874 { 875 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 876 struct cz_softc *cz; 877 878 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 879 k = j; 880 cz = device_lookup(&cz_cd, i); 881 if (cz == NULL) 882 continue; 883 if (cz->cz_ports == NULL) 884 continue; 885 j += cz->cz_nchannels; 886 if (j > u) 887 break; 888 } 889 890 if (i >= cz_cd.cd_ndevs) 891 return (NULL); 892 else 893 return (&cz->cz_ports[u - k]); 894 } 895 896 /* 897 * czttytty: 898 * 899 * Return a pointer to our tty. 900 */ 901 struct tty * 902 czttytty(dev_t dev) 903 { 904 struct cztty_softc *sc = CZTTY_SOFTC(dev); 905 906 #ifdef DIAGNOSTIC 907 if (sc == NULL) 908 panic("czttytty"); 909 #endif 910 911 return (sc->sc_tty); 912 } 913 914 /* 915 * cztty_shutdown: 916 * 917 * Shut down a port. 918 */ 919 void 920 cztty_shutdown(struct cztty_softc *sc) 921 { 922 struct cz_softc *cz = CZTTY_CZ(sc); 923 struct tty *tp = sc->sc_tty; 924 int s; 925 926 s = spltty(); 927 928 /* Clear any break condition set with TIOCSBRK. */ 929 cztty_break(sc, 0); 930 931 /* 932 * Hang up if necessary. Wait a bit, so the other side has time to 933 * notice even if we immediately open the port again. 934 */ 935 if (ISSET(tp->t_cflag, HUPCL)) { 936 cztty_modem(sc, 0); 937 (void) tsleep(tp, TTIPRI, ttclos, hz); 938 } 939 940 /* Disable the channel. */ 941 cz_wait_pci_doorbell(cz, "czdis"); 942 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 943 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 944 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 945 946 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 947 #ifdef CZ_DEBUG 948 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 949 #endif 950 callout_stop(&cz->cz_callout); 951 } 952 953 splx(s); 954 } 955 956 /* 957 * czttyopen: 958 * 959 * Open a Cyclades-Z serial port. 960 */ 961 int 962 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 963 { 964 struct cztty_softc *sc = CZTTY_SOFTC(dev); 965 struct cz_softc *cz; 966 struct tty *tp; 967 int s, error; 968 969 if (sc == NULL) 970 return (ENXIO); 971 972 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 973 return (ENXIO); 974 975 cz = CZTTY_CZ(sc); 976 tp = sc->sc_tty; 977 978 if (ISSET(tp->t_state, TS_ISOPEN) && 979 ISSET(tp->t_state, TS_XCLUDE) && 980 p->p_ucred->cr_uid != 0) 981 return (EBUSY); 982 983 s = spltty(); 984 985 /* 986 * Do the following iff this is a first open. 987 */ 988 if (!ISSET(tp->t_state, TS_ISOPEN) && (tp->t_wopen == 0)) { 989 struct termios t; 990 991 tp->t_dev = dev; 992 993 /* If we're turning things on, enable interrupts */ 994 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 995 #ifdef CZ_DEBUG 996 printf("%s: Enabling polling.\n", 997 cz->cz_dev.dv_xname); 998 #endif 999 callout_reset(&cz->cz_callout, cz_timeout_ticks, 1000 cz_poll, cz); 1001 } 1002 1003 /* 1004 * Enable the channel. Don't actually ring the 1005 * doorbell here; czttyparam() will do it for us. 1006 */ 1007 cz_wait_pci_doorbell(cz, "czopen"); 1008 1009 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1010 1011 /* 1012 * Initialize the termios status to the defaults. Add in the 1013 * sticky bits from TIOCSFLAGS. 1014 */ 1015 t.c_ispeed = 0; 1016 t.c_ospeed = TTYDEF_SPEED; 1017 t.c_cflag = TTYDEF_CFLAG; 1018 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1019 SET(t.c_cflag, CLOCAL); 1020 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1021 SET(t.c_cflag, CRTSCTS); 1022 1023 /* 1024 * Reset the input and output rings. Do this before 1025 * we call czttyparam(), as that function enables 1026 * the channel. 1027 */ 1028 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1029 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1030 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1031 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1032 1033 /* Make sure czttyparam() will see changes. */ 1034 tp->t_ospeed = 0; 1035 (void) czttyparam(tp, &t); 1036 tp->t_iflag = TTYDEF_IFLAG; 1037 tp->t_oflag = TTYDEF_OFLAG; 1038 tp->t_lflag = TTYDEF_LFLAG; 1039 ttychars(tp); 1040 ttsetwater(tp); 1041 1042 /* 1043 * Turn on DTR. We must always do this, even if carrier is not 1044 * present, because otherwise we'd have to use TIOCSDTR 1045 * immediately after setting CLOCAL, which applications do not 1046 * expect. We always assert DTR while the device is open 1047 * unless explicitly requested to deassert it. 1048 */ 1049 cztty_modem(sc, 1); 1050 } 1051 1052 splx(s); 1053 1054 error = ttyopen(tp, CZTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK)); 1055 if (error) 1056 goto bad; 1057 1058 error = (*tp->t_linesw->l_open)(dev, tp); 1059 if (error) 1060 goto bad; 1061 1062 return (0); 1063 1064 bad: 1065 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1066 /* 1067 * We failed to open the device, and nobody else had it opened. 1068 * Clean up the state as appropriate. 1069 */ 1070 cztty_shutdown(sc); 1071 } 1072 1073 return (error); 1074 } 1075 1076 /* 1077 * czttyclose: 1078 * 1079 * Close a Cyclades-Z serial port. 1080 */ 1081 int 1082 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1083 { 1084 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1085 struct tty *tp = sc->sc_tty; 1086 1087 /* XXX This is for cons.c. */ 1088 if (!ISSET(tp->t_state, TS_ISOPEN)) 1089 return (0); 1090 1091 (*tp->t_linesw->l_close)(tp, flags); 1092 ttyclose(tp); 1093 1094 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1095 /* 1096 * Although we got a last close, the device may still be in 1097 * use; e.g. if this was the dialout node, and there are still 1098 * processes waiting for carrier on the non-dialout node. 1099 */ 1100 cztty_shutdown(sc); 1101 } 1102 1103 return (0); 1104 } 1105 1106 /* 1107 * czttyread: 1108 * 1109 * Read from a Cyclades-Z serial port. 1110 */ 1111 int 1112 czttyread(dev_t dev, struct uio *uio, int flags) 1113 { 1114 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1115 struct tty *tp = sc->sc_tty; 1116 1117 return ((*tp->t_linesw->l_read)(tp, uio, flags)); 1118 } 1119 1120 /* 1121 * czttywrite: 1122 * 1123 * Write to a Cyclades-Z serial port. 1124 */ 1125 int 1126 czttywrite(dev_t dev, struct uio *uio, int flags) 1127 { 1128 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1129 struct tty *tp = sc->sc_tty; 1130 1131 return ((*tp->t_linesw->l_write)(tp, uio, flags)); 1132 } 1133 1134 /* 1135 * czttypoll: 1136 * 1137 * Poll a Cyclades-Z serial port. 1138 */ 1139 int 1140 czttypoll(dev, events, p) 1141 dev_t dev; 1142 int events; 1143 struct proc *p; 1144 { 1145 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1146 struct tty *tp = sc->sc_tty; 1147 1148 return ((*tp->t_linesw->l_poll)(tp, events, p)); 1149 } 1150 1151 /* 1152 * czttyioctl: 1153 * 1154 * Perform a control operation on a Cyclades-Z serial port. 1155 */ 1156 int 1157 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1158 { 1159 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1160 struct tty *tp = sc->sc_tty; 1161 int s, error; 1162 1163 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 1164 if (error != EPASSTHROUGH) 1165 return (error); 1166 1167 error = ttioctl(tp, cmd, data, flag, p); 1168 if (error != EPASSTHROUGH) 1169 return (error); 1170 1171 error = 0; 1172 1173 s = spltty(); 1174 1175 switch (cmd) { 1176 case TIOCSBRK: 1177 cztty_break(sc, 1); 1178 break; 1179 1180 case TIOCCBRK: 1181 cztty_break(sc, 0); 1182 break; 1183 1184 case TIOCGFLAGS: 1185 *(int *)data = sc->sc_swflags; 1186 break; 1187 1188 case TIOCSFLAGS: 1189 error = suser(p->p_ucred, &p->p_acflag); 1190 if (error) 1191 break; 1192 sc->sc_swflags = *(int *)data; 1193 break; 1194 1195 case TIOCSDTR: 1196 cztty_modem(sc, 1); 1197 break; 1198 1199 case TIOCCDTR: 1200 cztty_modem(sc, 0); 1201 break; 1202 1203 case TIOCMSET: 1204 case TIOCMBIS: 1205 case TIOCMBIC: 1206 tiocm_to_cztty(sc, cmd, *(int *)data); 1207 break; 1208 1209 case TIOCMGET: 1210 *(int *)data = cztty_to_tiocm(sc); 1211 break; 1212 1213 default: 1214 error = EPASSTHROUGH; 1215 break; 1216 } 1217 1218 splx(s); 1219 1220 return (error); 1221 } 1222 1223 /* 1224 * cztty_break: 1225 * 1226 * Set or clear BREAK on a port. 1227 */ 1228 void 1229 cztty_break(struct cztty_softc *sc, int onoff) 1230 { 1231 struct cz_softc *cz = CZTTY_CZ(sc); 1232 1233 cz_wait_pci_doorbell(cz, "czbreak"); 1234 1235 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1236 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1237 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1238 } 1239 1240 /* 1241 * cztty_modem: 1242 * 1243 * Set or clear DTR on a port. 1244 */ 1245 void 1246 cztty_modem(struct cztty_softc *sc, int onoff) 1247 { 1248 struct cz_softc *cz = CZTTY_CZ(sc); 1249 1250 if (sc->sc_rs_control_dtr == 0) 1251 return; 1252 1253 cz_wait_pci_doorbell(cz, "czmod"); 1254 1255 if (onoff) 1256 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1257 else 1258 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1259 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1260 1261 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1262 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1263 } 1264 1265 /* 1266 * tiocm_to_cztty: 1267 * 1268 * Process TIOCM* ioctls. 1269 */ 1270 void 1271 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1272 { 1273 struct cz_softc *cz = CZTTY_CZ(sc); 1274 u_int32_t czttybits; 1275 1276 czttybits = 0; 1277 if (ISSET(ttybits, TIOCM_DTR)) 1278 SET(czttybits, C_RS_DTR); 1279 if (ISSET(ttybits, TIOCM_RTS)) 1280 SET(czttybits, C_RS_RTS); 1281 1282 cz_wait_pci_doorbell(cz, "cztiocm"); 1283 1284 switch (how) { 1285 case TIOCMBIC: 1286 CLR(sc->sc_chanctl_rs_control, czttybits); 1287 break; 1288 1289 case TIOCMBIS: 1290 SET(sc->sc_chanctl_rs_control, czttybits); 1291 break; 1292 1293 case TIOCMSET: 1294 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1295 SET(sc->sc_chanctl_rs_control, czttybits); 1296 break; 1297 } 1298 1299 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1300 1301 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1302 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1303 } 1304 1305 /* 1306 * cztty_to_tiocm: 1307 * 1308 * Process the TIOCMGET ioctl. 1309 */ 1310 int 1311 cztty_to_tiocm(struct cztty_softc *sc) 1312 { 1313 struct cz_softc *cz = CZTTY_CZ(sc); 1314 u_int32_t rs_status, op_mode; 1315 int ttybits = 0; 1316 1317 cz_wait_pci_doorbell(cz, "cztty"); 1318 1319 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1320 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1321 1322 if (ISSET(rs_status, C_RS_RTS)) 1323 SET(ttybits, TIOCM_RTS); 1324 if (ISSET(rs_status, C_RS_CTS)) 1325 SET(ttybits, TIOCM_CTS); 1326 if (ISSET(rs_status, C_RS_DCD)) 1327 SET(ttybits, TIOCM_CAR); 1328 if (ISSET(rs_status, C_RS_DTR)) 1329 SET(ttybits, TIOCM_DTR); 1330 if (ISSET(rs_status, C_RS_RI)) 1331 SET(ttybits, TIOCM_RNG); 1332 if (ISSET(rs_status, C_RS_DSR)) 1333 SET(ttybits, TIOCM_DSR); 1334 1335 if (ISSET(op_mode, C_CH_ENABLE)) 1336 SET(ttybits, TIOCM_LE); 1337 1338 return (ttybits); 1339 } 1340 1341 /* 1342 * czttyparam: 1343 * 1344 * Set Cyclades-Z serial port parameters from termios. 1345 * 1346 * XXX Should just copy the whole termios after making 1347 * XXX sure all the changes could be done. 1348 */ 1349 int 1350 czttyparam(struct tty *tp, struct termios *t) 1351 { 1352 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1353 struct cz_softc *cz = CZTTY_CZ(sc); 1354 u_int32_t rs_status; 1355 int ospeed, cflag; 1356 1357 ospeed = t->c_ospeed; 1358 cflag = t->c_cflag; 1359 1360 /* Check requested parameters. */ 1361 if (ospeed < 0) 1362 return (EINVAL); 1363 if (t->c_ispeed && t->c_ispeed != ospeed) 1364 return (EINVAL); 1365 1366 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1367 SET(cflag, CLOCAL); 1368 CLR(cflag, HUPCL); 1369 } 1370 1371 /* 1372 * If there were no changes, don't do anything. This avoids dropping 1373 * input and improves performance when all we did was frob things like 1374 * VMIN and VTIME. 1375 */ 1376 if (tp->t_ospeed == ospeed && 1377 tp->t_cflag == cflag) 1378 return (0); 1379 1380 /* Data bits. */ 1381 sc->sc_chanctl_comm_data_l = 0; 1382 switch (t->c_cflag & CSIZE) { 1383 case CS5: 1384 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1385 break; 1386 1387 case CS6: 1388 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1389 break; 1390 1391 case CS7: 1392 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1393 break; 1394 1395 case CS8: 1396 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1397 break; 1398 } 1399 1400 /* Stop bits. */ 1401 if (t->c_cflag & CSTOPB) { 1402 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1403 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1404 else 1405 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1406 } else 1407 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1408 1409 /* Parity. */ 1410 if (t->c_cflag & PARENB) { 1411 if (t->c_cflag & PARODD) 1412 sc->sc_chanctl_comm_parity = C_PR_ODD; 1413 else 1414 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1415 } else 1416 sc->sc_chanctl_comm_parity = C_PR_NONE; 1417 1418 /* 1419 * Initialize flow control pins depending on the current flow control 1420 * mode. 1421 */ 1422 if (ISSET(t->c_cflag, CRTSCTS)) { 1423 sc->sc_rs_control_dtr = C_RS_DTR; 1424 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1425 } else if (ISSET(t->c_cflag, MDMBUF)) { 1426 sc->sc_rs_control_dtr = 0; 1427 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1428 } else { 1429 /* 1430 * If no flow control, then always set RTS. This will make 1431 * the other side happy if it mistakenly thinks we're doing 1432 * RTS/CTS flow control. 1433 */ 1434 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1435 sc->sc_chanctl_hw_flow = 0; 1436 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1437 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1438 else 1439 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1440 } 1441 1442 /* Baud rate. */ 1443 sc->sc_chanctl_comm_baud = ospeed; 1444 1445 /* Copy to tty. */ 1446 tp->t_ispeed = 0; 1447 tp->t_ospeed = t->c_ospeed; 1448 tp->t_cflag = t->c_cflag; 1449 1450 /* 1451 * Now load the channel control structure. 1452 */ 1453 1454 cz_wait_pci_doorbell(cz, "czparam"); 1455 1456 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1457 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1458 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1459 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1460 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1461 1462 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1463 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1464 1465 cz_wait_pci_doorbell(cz, "czparam"); 1466 1467 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1468 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1469 1470 cz_wait_pci_doorbell(cz, "czparam"); 1471 1472 /* 1473 * Update the tty layer's idea of the carrier bit, in case we changed 1474 * CLOCAL. We don't hang up here; we only do that by explicit 1475 * request. 1476 */ 1477 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1478 (void) (*tp->t_linesw->l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1479 1480 return (0); 1481 } 1482 1483 /* 1484 * czttystart: 1485 * 1486 * Start or restart transmission. 1487 */ 1488 void 1489 czttystart(struct tty *tp) 1490 { 1491 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1492 int s; 1493 1494 s = spltty(); 1495 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1496 goto out; 1497 1498 if (tp->t_outq.c_cc <= tp->t_lowat) { 1499 if (ISSET(tp->t_state, TS_ASLEEP)) { 1500 CLR(tp->t_state, TS_ASLEEP); 1501 wakeup(&tp->t_outq); 1502 } 1503 selwakeup(&tp->t_wsel); 1504 if (tp->t_outq.c_cc == 0) 1505 goto out; 1506 } 1507 1508 cztty_transmit(sc, tp); 1509 out: 1510 splx(s); 1511 } 1512 1513 /* 1514 * czttystop: 1515 * 1516 * Stop output, e.g., for ^S or output flush. 1517 */ 1518 void 1519 czttystop(struct tty *tp, int flag) 1520 { 1521 1522 /* 1523 * XXX We don't do anything here, yet. Mostly, I don't know 1524 * XXX exactly how this should be implemented on this device. 1525 * XXX We've given a big chunk of data to the MIPS already, 1526 * XXX and I don't know how we request the MIPS to stop sending 1527 * XXX the data. So, punt for now. --thorpej 1528 */ 1529 } 1530 1531 /* 1532 * cztty_diag: 1533 * 1534 * Issue a scheduled diagnostic message. 1535 */ 1536 void 1537 cztty_diag(void *arg) 1538 { 1539 struct cztty_softc *sc = arg; 1540 struct cz_softc *cz = CZTTY_CZ(sc); 1541 u_int overflows, parity_errors, framing_errors; 1542 int s; 1543 1544 s = spltty(); 1545 1546 overflows = sc->sc_overflows; 1547 sc->sc_overflows = 0; 1548 1549 parity_errors = sc->sc_parity_errors; 1550 sc->sc_parity_errors = 0; 1551 1552 framing_errors = sc->sc_framing_errors; 1553 sc->sc_framing_errors = 0; 1554 1555 sc->sc_errors = 0; 1556 1557 splx(s); 1558 1559 log(LOG_WARNING, 1560 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1561 cz->cz_dev.dv_xname, sc->sc_channel, 1562 overflows, overflows == 1 ? "" : "s", 1563 parity_errors, 1564 framing_errors, framing_errors == 1 ? "" : "s"); 1565 } 1566 1567 /* 1568 * tx and rx ring buffer size macros: 1569 * 1570 * The transmitter and receiver both use ring buffers. For each one, there 1571 * is a get (consumer) and a put (producer) offset. The get value is the 1572 * next byte to be read from the ring, and the put is the next one to be 1573 * put into the ring. get == put means the ring is empty. 1574 * 1575 * For each ring, the firmware controls one of (get, put) and this driver 1576 * controls the other. For transmission, this driver updates put to point 1577 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1578 * for receive, the driver controls put, and this driver controls get. 1579 */ 1580 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1581 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1582 1583 /* 1584 * cztty_transmit() 1585 * 1586 * Look at the tty for this port and start sending. 1587 */ 1588 int 1589 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1590 { 1591 struct cz_softc *cz = CZTTY_CZ(sc); 1592 u_int move, get, put, size, address; 1593 #ifdef HOSTRAMCODE 1594 int error, done = 0; 1595 #else 1596 int done = 0; 1597 #endif 1598 1599 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1600 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1601 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1602 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1603 1604 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1605 #ifdef HOSTRAMCODE 1606 if (0) { 1607 move = min(tp->t_outq.c_cc, move); 1608 error = q_to_b(&tp->t_outq, 0, move); 1609 if (error != move) { 1610 printf("%s: channel %d: error moving to " 1611 "transmit buf\n", cz->cz_dev.dv_xname, 1612 sc->sc_channel); 1613 move = error; 1614 } 1615 } else { 1616 #endif 1617 move = min(ndqb(&tp->t_outq, 0), move); 1618 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1619 address + put, tp->t_outq.c_cf, move); 1620 ndflush(&tp->t_outq, move); 1621 #ifdef HOSTRAMCODE 1622 } 1623 #endif 1624 1625 put = ((put + move) % size); 1626 done = 1; 1627 } 1628 if (done) { 1629 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1630 } 1631 return (done); 1632 } 1633 1634 int 1635 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1636 { 1637 struct cz_softc *cz = CZTTY_CZ(sc); 1638 u_int get, put, size, address; 1639 int done = 0, ch; 1640 1641 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1642 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1643 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1644 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1645 1646 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1647 #ifdef HOSTRAMCODE 1648 if (hostram) 1649 ch = ((char *)fifoaddr)[get]; 1650 } else { 1651 #endif 1652 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1653 address + get); 1654 #ifdef HOSTRAMCODE 1655 } 1656 #endif 1657 (*tp->t_linesw->l_rint)(ch, tp); 1658 get = (get + 1) % size; 1659 done = 1; 1660 } 1661 if (done) { 1662 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1663 } 1664 return (done); 1665 } 1666