1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 29 ***************************************************************************/ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/endian.h> 34 35 #include <dev/mii/mii.h> 36 37 #ifndef _CXGB_OSDEP_H_ 38 #define _CXGB_OSDEP_H_ 39 40 typedef char *caddr_t; 41 #include <dev/pci/cxgb/cxgb_version.h> 42 #include <dev/pci/cxgb/cxgb_config.h> 43 #include <sys/mbuf.h> 44 #include <machine/bus.h> 45 46 #include <netinet/in_systm.h> 47 #include <netinet/in.h> 48 #include <netinet/ip.h> 49 50 #include <sys/simplelock.h> 51 52 #include <sys/kthread.h> 53 #include <sys/workqueue.h> 54 55 #include <sys/atomic.h> 56 57 void pci_enable_busmaster(device_t dev); 58 59 struct cxgb_task 60 { 61 const char *name; 62 void (*func)(struct work *, void *); 63 struct workqueue *wq; 64 struct work w; 65 void *context; 66 }; 67 68 void cxgb_make_task(void *); 69 70 void m_cljset(struct mbuf *m, void *cl, int type); 71 72 #define mtx simplelock 73 #define mtx_init(a, b, c, d) { (a)->lock_data = __SIMPLELOCK_UNLOCKED; } 74 #define mtx_destroy(a) 75 #define mtx_lock(a) simple_lock(a) 76 #define mtx_unlock(a) simple_unlock(a) 77 #define mtx_trylock(a) simple_lock_try(a) 78 #define MA_OWNED 1 79 #define MA_NOTOWNED 0 80 #define mtx_assert(a, w) 81 82 #if 0 83 #define RT_LOCK_INIT(_rt) \ 84 mtx_init(&(_rt)->rt_mtx, "rtentry", NULL, MTX_DEF | MTX_DUPOK) 85 #define RT_LOCK(_rt) mtx_lock(&(_rt)->rt_mtx) 86 #define RT_UNLOCK(_rt) mtx_unlock(&(_rt)->rt_mtx) 87 #define RT_LOCK_DESTROY(_rt) mtx_destroy(&(_rt)->rt_mtx) 88 #define RT_LOCK_ASSERT(_rt) mtx_assert(&(_rt)->rt_mtx, MA_OWNED) 89 #else 90 #define RT_LOCK_INIT(_rt) 91 #define RT_LOCK(_rt) 92 #define RT_UNLOCK(_rt) 93 #define RT_LOCK_DESTROY(_rt) 94 #define RT_LOCK_ASSERT(_rt) 95 #endif 96 97 #define RT_ADDREF(_rt) do { \ 98 RT_LOCK_ASSERT(_rt); \ 99 KASSERT((_rt)->rt_refcnt >= 0); \ 100 (_rt)->rt_refcnt++; \ 101 } while (0) 102 #define RT_REMREF(_rt) do { \ 103 RT_LOCK_ASSERT(_rt); \ 104 KASSERT((_rt)->rt_refcnt > 0); \ 105 (_rt)->rt_refcnt--; \ 106 } while (0) 107 108 109 #define EVL_VLID_MASK 0x0FFF 110 111 static inline void critical_enter(void) 112 { 113 } 114 115 static inline void critical_exit(void) 116 { 117 } 118 119 static inline void device_printf(device_t d, ...) 120 { 121 } 122 123 int atomic_fetchadd_int(volatile int *p, int v); 124 #if 0 125 int atomic_add_int(volatile int *p, int v); 126 #endif 127 int atomic_load_acq_int(volatile int *p); 128 void atomic_store_rel_int(volatile int *p, int v); 129 130 u_short in_cksum_hdr(struct ip *ih); 131 132 #define if_drv_flags if_flags 133 #define IFF_DRV_RUNNING IFF_RUNNING 134 #define IFF_DRV_OACTIVE IFF_OACTIVE 135 136 #define MJUM16BYTES (16*1024) 137 #define MJUMPAGESIZE PAGE_SIZE 138 139 #if 0 140 #define rw_rlock(x) rw_enter(x, RW_READER) 141 #define rw_runlock(x) rw_exit(x) 142 #define rw_wlock(x) rw_enter(x, RW_WRITER) 143 #define rw_wunlock(x) rw_exit(x) 144 #endif 145 146 #define callout_drain(x) callout_stop(x) 147 148 static inline int atomic_cmpset_ptr(volatile long *dst, long exp, long src) 149 { 150 if (*dst == exp) 151 { 152 *dst = src; 153 return (1); 154 } 155 return (0); 156 } 157 #define atomic_cmpset_int(a, b, c) atomic_cmpset_ptr((volatile long *)a, (long)b, (long)c) 158 159 static inline int atomic_set_int(volatile int *dst, int val) 160 { 161 *dst = val; 162 163 return (val); 164 } 165 166 static inline void log(int x, ...) 167 { 168 } 169 170 struct cxgb_attach_args 171 { 172 int port; 173 }; 174 175 #define INT3 __asm("int $3") 176 177 static inline struct mbuf * 178 m_defrag(struct mbuf *m0, int flags) 179 { 180 struct mbuf *m; 181 MGETHDR(m, flags, MT_DATA); 182 if (m == NULL) 183 return NULL; 184 185 M_COPY_PKTHDR(m, m0); 186 MCLGET(m, flags); 187 if ((m->m_flags & M_EXT) == 0) { 188 m_free(m); 189 return NULL; 190 } 191 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 192 m->m_len = m->m_pkthdr.len; 193 return m; 194 } 195 196 197 typedef struct adapter adapter_t; 198 struct sge_rspq; 199 200 struct t3_mbuf_hdr { 201 struct mbuf *mh_head; 202 struct mbuf *mh_tail; 203 }; 204 205 206 #define PANIC_IF(exp) do { \ 207 if (exp) \ 208 panic("BUG: %s", exp); \ 209 } while (0) 210 211 212 #define m_get_priority(m) ((uintptr_t)(m)->m_pkthdr.rcvif) 213 #define m_set_priority(m, pri) ((m)->m_pkthdr.rcvif = (struct ifnet *)((uintptr_t)pri)) 214 215 #define if_name(ifp) (ifp)->if_xname 216 #define M_SANITY(m, n) 217 218 #define __read_mostly __section(".data.read_mostly") 219 220 /* 221 * Workaround for weird Chelsio issue 222 */ 223 #define CXGB_TX_CLEANUP_THRESHOLD 32 224 225 #define LOG_WARNING 1 226 #define LOG_ERR 2 227 228 #define DPRINTF printf 229 230 #define TX_MAX_SIZE (1 << 16) /* 64KB */ 231 #define TX_MAX_SEGS 36 /* maximum supported by card */ 232 #define TX_MAX_DESC 4 /* max descriptors per packet */ 233 234 #define TX_START_MIN_DESC (TX_MAX_DESC << 2) 235 236 #if 0 237 #define TX_START_MAX_DESC (TX_ETH_Q_SIZE >> 2) /* maximum number of descriptors */ 238 #endif 239 240 #define TX_START_MAX_DESC (TX_MAX_DESC << 3) /* maximum number of descriptors 241 * call to start used per */ 242 243 #define TX_CLEAN_MAX_DESC (TX_MAX_DESC << 4) /* maximum tx descriptors 244 * to clean per iteration */ 245 246 247 #if defined(__i386__) || defined(__amd64__) 248 #define mb() __asm volatile("mfence":::"memory") 249 #define rmb() __asm volatile("lfence":::"memory") 250 #define wmb() __asm volatile("sfence" ::: "memory") 251 #define smp_mb() mb() 252 253 #define L1_CACHE_BYTES 64 254 static __inline 255 void prefetch(void *x) 256 { 257 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 258 } 259 260 extern void kdb_backtrace(void); 261 262 #define WARN_ON(condition) do { \ 263 if (unlikely((condition)!=0)) { \ 264 log(LOG_WARNING, "BUG: warning at %s:%d/%s()\n", __FILE__, __LINE__, __func__); \ 265 kdb_backtrace(); \ 266 } \ 267 } while (0) 268 269 270 #else /* !i386 && !amd64 */ 271 #define mb() 272 #define rmb() 273 #define wmb() 274 #define smp_mb() 275 #define prefetch(x) 276 #define L1_CACHE_BYTES 32 277 #endif 278 #define DBG_RX (1 << 0) 279 static const int debug_flags = DBG_RX; 280 281 #ifdef DEBUG_PRINT 282 #define DBG(flag, msg) do { \ 283 if ((flag & debug_flags)) \ 284 printf msg; \ 285 } while (0) 286 #else 287 #define DBG(...) 288 #endif 289 290 #define promisc_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_PROMISC) 291 #define allmulti_rx_mode(rm) ((rm)->port->ifp->if_flags & IFF_ALLMULTI) 292 293 #define CH_ERR(adap, fmt, ...) { } 294 295 #define CH_WARN(adap, fmt, ...) { } 296 #define CH_ALERT(adap, fmt, ...) { } 297 298 #define t3_os_sleep(x) DELAY((x) * 1000) 299 300 #define test_and_clear_bit(bit, p) atomic_cmpset_int((p), ((*(p)) | bit), ((*(p)) & ~bit)) 301 302 303 #define max_t(type, a, b) (type)max((a), (b)) 304 #define net_device ifnet 305 #define cpu_to_be32 htobe32 306 307 308 309 /* Standard PHY definitions */ 310 #define BMCR_LOOPBACK BMCR_LOOP 311 #define BMCR_ISOLATE BMCR_ISO 312 #define BMCR_ANENABLE BMCR_AUTOEN 313 #define BMCR_SPEED1000 BMCR_SPEED1 314 #define BMCR_SPEED100 BMCR_SPEED0 315 #define BMCR_ANRESTART BMCR_STARTNEG 316 #define BMCR_FULLDPLX BMCR_FDX 317 #define BMSR_LSTATUS BMSR_LINK 318 #define BMSR_ANEGCOMPLETE BMSR_ACOMP 319 320 #define MII_LPA MII_ANLPAR 321 #define MII_ADVERTISE MII_ANAR 322 #define MII_CTRL1000 MII_100T2CR 323 324 #define ADVERTISE_PAUSE_CAP ANAR_FC 325 #define ADVERTISE_PAUSE_ASYM 0x0800 326 #define ADVERTISE_1000HALF ANAR_X_HD 327 #define ADVERTISE_1000FULL ANAR_X_FD 328 #define ADVERTISE_10FULL ANAR_10_FD 329 #define ADVERTISE_10HALF ANAR_10 330 #define ADVERTISE_100FULL ANAR_TX_FD 331 #define ADVERTISE_100HALF ANAR_TX 332 333 /* Standard PCI Extended Capaibilities definitions */ 334 #define PCI_CAP_ID_VPD 0x03 335 #define PCI_VPD_ADDR 2 336 #define PCI_VPD_ADDR_F 0x8000 337 #define PCI_VPD_DATA 4 338 339 #define PCI_CAP_ID_EXP 0x10 340 #define PCI_EXP_DEVCTL 8 341 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 342 #define PCI_EXP_LNKCTL 16 343 #define PCI_EXP_LNKSTA 18 344 345 /* 346 * Linux compatibility macros 347 */ 348 349 /* Some simple translations */ 350 #define __devinit 351 #define udelay(x) DELAY(x) 352 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 353 #define le32_to_cpu(x) le32toh(x) 354 #define cpu_to_le32(x) htole32(x) 355 #define swab32(x) bswap32(x) 356 #define simple_strtoul strtoul 357 358 /* More types and endian definitions */ 359 typedef uint8_t u8; 360 typedef uint16_t u16; 361 typedef uint32_t u32; 362 typedef uint64_t u64; 363 364 typedef uint8_t __u8; 365 typedef uint16_t __u16; 366 typedef uint32_t __u32; 367 typedef uint8_t __be8; 368 typedef uint16_t __be16; 369 typedef uint32_t __be32; 370 typedef uint64_t __be64; 371 372 #if BYTE_ORDER == BIG_ENDIAN 373 #define __BIG_ENDIAN_BITFIELD 374 #elif BYTE_ORDER == LITTLE_ENDIAN 375 #define __LITTLE_ENDIAN_BITFIELD 376 #else 377 #error "Must set BYTE_ORDER" 378 #endif 379 380 /* Indicates what features are supported by the interface. */ 381 #define SUPPORTED_10baseT_Half (1 << 0) 382 #define SUPPORTED_10baseT_Full (1 << 1) 383 #define SUPPORTED_100baseT_Half (1 << 2) 384 #define SUPPORTED_100baseT_Full (1 << 3) 385 #define SUPPORTED_1000baseT_Half (1 << 4) 386 #define SUPPORTED_1000baseT_Full (1 << 5) 387 #define SUPPORTED_Autoneg (1 << 6) 388 #define SUPPORTED_TP (1 << 7) 389 #define SUPPORTED_AUI (1 << 8) 390 #define SUPPORTED_MII (1 << 9) 391 #define SUPPORTED_FIBRE (1 << 10) 392 #define SUPPORTED_BNC (1 << 11) 393 #define SUPPORTED_10000baseT_Full (1 << 12) 394 #define SUPPORTED_Pause (1 << 13) 395 #define SUPPORTED_Asym_Pause (1 << 14) 396 397 /* Indicates what features are advertised by the interface. */ 398 #define ADVERTISED_10baseT_Half (1 << 0) 399 #define ADVERTISED_10baseT_Full (1 << 1) 400 #define ADVERTISED_100baseT_Half (1 << 2) 401 #define ADVERTISED_100baseT_Full (1 << 3) 402 #define ADVERTISED_1000baseT_Half (1 << 4) 403 #define ADVERTISED_1000baseT_Full (1 << 5) 404 #define ADVERTISED_Autoneg (1 << 6) 405 #define ADVERTISED_TP (1 << 7) 406 #define ADVERTISED_AUI (1 << 8) 407 #define ADVERTISED_MII (1 << 9) 408 #define ADVERTISED_FIBRE (1 << 10) 409 #define ADVERTISED_BNC (1 << 11) 410 #define ADVERTISED_10000baseT_Full (1 << 12) 411 #define ADVERTISED_Pause (1 << 13) 412 #define ADVERTISED_Asym_Pause (1 << 14) 413 414 /* Enable or disable autonegotiation. If this is set to enable, 415 * the forced link modes above are completely ignored. 416 */ 417 #define AUTONEG_DISABLE 0x00 418 #define AUTONEG_ENABLE 0x01 419 420 #define SPEED_10 10 421 #define SPEED_100 100 422 #define SPEED_1000 1000 423 #define SPEED_10000 10000 424 #define DUPLEX_HALF 0 425 #define DUPLEX_FULL 1 426 427 #endif 428