1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 ***************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: cxgb_main.c,v 1.9 2021/04/24 23:36:57 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/conf.h> 37 #include <sys/bus.h> 38 #include <sys/ioccom.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/sockio.h> 42 #include <sys/sysctl.h> 43 #include <sys/queue.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #include <netinet/in_systm.h> 53 #include <netinet/in.h> 54 #include <netinet/ip.h> 55 #include <netinet/ip.h> 56 #include <netinet/tcp.h> 57 #include <netinet/udp.h> 58 #include <netinet/if_inarp.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 63 #ifdef CONFIG_DEFINED 64 #include <cxgb_include.h> 65 #else 66 #include <dev/pci/cxgb/cxgb_include.h> 67 #endif 68 69 #ifdef PRIV_SUPPORTED 70 #include <sys/priv.h> 71 #endif 72 73 #include <altq/altq_conf.h> 74 75 static int cxgb_setup_msix(adapter_t *, int); 76 static void cxgb_teardown_msix(adapter_t *); 77 static int cxgb_init(struct ifnet *); 78 static void cxgb_init_locked(struct port_info *); 79 static void cxgb_stop_locked(struct port_info *); 80 static void cxgb_set_rxmode(struct port_info *); 81 static int cxgb_ioctl(struct ifnet *, unsigned long, void *); 82 static void cxgb_start(struct ifnet *); 83 static void cxgb_stop(struct ifnet *, int); 84 static void cxgb_start_proc(struct work *, void *); 85 static int cxgb_media_change(struct ifnet *); 86 static void cxgb_media_status(struct ifnet *, struct ifmediareq *); 87 static int setup_sge_qsets(adapter_t *); 88 static int cxgb_async_intr(void *); 89 static void cxgb_ext_intr_handler(struct work *, void *); 90 static void cxgb_tick_handler(struct work *, void *); 91 static void cxgb_down_locked(struct adapter *sc); 92 static void cxgb_tick(void *); 93 static void setup_rss(adapter_t *sc); 94 95 /* Attachment glue for the PCI controller end of the device. Each port of 96 * the device is attached separately, as defined later. 97 */ 98 static int cxgb_controller_match(device_t dev, cfdata_t match, void *context); 99 static void cxgb_controller_attach(device_t parent, device_t dev, void *context); 100 static int cxgb_controller_detach(device_t dev, int flags); 101 static void cxgb_free(struct adapter *); 102 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 103 unsigned int end); 104 static void touch_bars(device_t dev); 105 106 #ifdef notyet 107 static int offload_close(struct toedev *tdev); 108 #endif 109 110 111 CFATTACH_DECL_NEW(cxgbc, sizeof(struct adapter), cxgb_controller_match, cxgb_controller_attach, cxgb_controller_detach, NULL); 112 113 /* 114 * Attachment glue for the ports. Attachment is done directly to the 115 * controller device. 116 */ 117 static int cxgb_port_match(device_t dev, cfdata_t match, void *context); 118 static void cxgb_port_attach(device_t dev, device_t self, void *context); 119 static int cxgb_port_detach(device_t dev, int flags); 120 121 CFATTACH_DECL_NEW(cxgb, sizeof(struct port_device), cxgb_port_match, cxgb_port_attach, cxgb_port_detach, NULL); 122 123 #define SGE_MSIX_COUNT (SGE_QSETS + 1) 124 125 extern int collapse_mbufs; 126 #ifdef MSI_SUPPORTED 127 /* 128 * The driver uses the best interrupt scheme available on a platform in the 129 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which 130 * of these schemes the driver may consider as follows: 131 * 132 * msi = 2: choose from among all three options 133 * msi = 1 : only consider MSI and pin interrupts 134 * msi = 0: force pin interrupts 135 */ 136 static int msi_allowed = 2; 137 #endif 138 139 /* 140 * The driver uses an auto-queue algorithm by default. 141 * To disable it and force a single queue-set per port, use singleq = 1. 142 */ 143 static int singleq = 1; 144 145 enum { 146 MAX_TXQ_ENTRIES = 16384, 147 MAX_CTRL_TXQ_ENTRIES = 1024, 148 MAX_RSPQ_ENTRIES = 16384, 149 MAX_RX_BUFFERS = 16384, 150 MAX_RX_JUMBO_BUFFERS = 16384, 151 MIN_TXQ_ENTRIES = 4, 152 MIN_CTRL_TXQ_ENTRIES = 4, 153 MIN_RSPQ_ENTRIES = 32, 154 MIN_FL_ENTRIES = 32, 155 MIN_FL_JUMBO_ENTRIES = 32 156 }; 157 158 struct filter_info { 159 u32 sip; 160 u32 sip_mask; 161 u32 dip; 162 u16 sport; 163 u16 dport; 164 u32 vlan:12; 165 u32 vlan_prio:3; 166 u32 mac_hit:1; 167 u32 mac_idx:4; 168 u32 mac_vld:1; 169 u32 pkt_type:2; 170 u32 report_filter_id:1; 171 u32 pass:1; 172 u32 rss:1; 173 u32 qset:3; 174 u32 locked:1; 175 u32 valid:1; 176 }; 177 178 enum { FILTER_NO_VLAN_PRI = 7 }; 179 180 #define PORT_MASK ((1 << MAX_NPORTS) - 1) 181 182 /* Table for probing the cards. The desc field isn't actually used */ 183 struct cxgb_ident { 184 uint16_t vendor; 185 uint16_t device; 186 int index; 187 const char *desc; 188 } cxgb_identifiers[] = { 189 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, 190 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, 191 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, 192 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, 193 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, 194 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, 195 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, 196 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, 197 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, 198 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, 199 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, 200 {0, 0, 0, NULL} 201 }; 202 203 204 static inline char 205 t3rev2char(struct adapter *adapter) 206 { 207 char rev = 'z'; 208 209 switch(adapter->params.rev) { 210 case T3_REV_A: 211 rev = 'a'; 212 break; 213 case T3_REV_B: 214 case T3_REV_B2: 215 rev = 'b'; 216 break; 217 case T3_REV_C: 218 rev = 'c'; 219 break; 220 } 221 return rev; 222 } 223 224 static struct cxgb_ident *cxgb_get_ident(struct pci_attach_args *pa) 225 { 226 struct cxgb_ident *id; 227 int vendorid, deviceid; 228 229 vendorid = PCI_VENDOR(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG)); 230 deviceid = PCI_PRODUCT(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG)); 231 232 for (id = cxgb_identifiers; id->desc != NULL; id++) { 233 if ((id->vendor == vendorid) && 234 (id->device == deviceid)) { 235 return (id); 236 } 237 } 238 return (NULL); 239 } 240 241 static const struct adapter_info *cxgb_get_adapter_info(struct pci_attach_args *pa) 242 { 243 struct cxgb_ident *id; 244 const struct adapter_info *ai; 245 246 id = cxgb_get_ident(pa); 247 if (id == NULL) 248 return (NULL); 249 250 ai = t3_get_adapter_info(id->index); 251 return (ai); 252 } 253 254 static int cxgb_controller_match(device_t dev, cfdata_t match, void *context) 255 { 256 struct pci_attach_args *pa = context; 257 const struct adapter_info *ai; 258 259 ai = cxgb_get_adapter_info(pa); 260 if (ai == NULL) 261 return (0); 262 263 return (100); // we ARE the best driver for this card!! 264 } 265 266 #define FW_FNAME "t3fw%d%d%d" 267 #define TPEEPROM_NAME "t3%ctpe%d%d%d" 268 #define TPSRAM_NAME "t3%cps%d%d%d" 269 270 int cxgb_cfprint(void *aux, const char *info); 271 int cxgb_cfprint(void *aux, const char *info) 272 { 273 if (info) 274 { 275 printf("cxgb_cfprint(%p, \"%s\")\n", aux, info); 276 INT3; 277 } 278 279 return (QUIET); 280 } 281 282 void cxgb_make_task(void *context) 283 { 284 struct cxgb_task *w = (struct cxgb_task *)context; 285 286 // we can only use workqueue_create() once the system is up and running 287 workqueue_create(&w->wq, w->name, w->func, w->context, PRIBIO, IPL_NET, 0); 288 // printf("======>> create workqueue for %s %p\n", w->name, w->wq); 289 } 290 291 static void 292 cxgb_controller_attach(device_t parent, device_t dev, void *context) 293 { 294 device_t child; 295 const struct adapter_info *ai; 296 struct adapter *sc; 297 struct pci_attach_args *pa = context; 298 struct cxgb_attach_args cxgb_args; 299 int locs[2]; 300 int i, error = 0; 301 uint32_t vers; 302 int port_qsets = 1; 303 int reg; 304 #ifdef MSI_SUPPORTED 305 int msi_needed; 306 #endif 307 308 sc = device_private(dev); 309 sc->dev = dev; 310 memcpy(&sc->pa, pa, sizeof(struct pci_attach_args)); 311 sc->msi_count = 0; 312 ai = cxgb_get_adapter_info(pa); 313 314 /* 315 * XXX not really related but a recent addition 316 */ 317 #ifdef MSI_SUPPORTED 318 /* find the PCIe link width and set max read request to 4KB*/ 319 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 320 uint16_t lnk, pectl; 321 lnk = pci_read_config(dev, reg + 0x12, 2); 322 sc->link_width = (lnk >> 4) & 0x3f; 323 324 pectl = pci_read_config(dev, reg + 0x8, 2); 325 pectl = (pectl & ~0x7000) | (5 << 12); 326 pci_write_config(dev, reg + 0x8, pectl, 2); 327 } 328 329 if (sc->link_width != 0 && sc->link_width <= 4 && 330 (ai->nports0 + ai->nports1) <= 2) { 331 device_printf(sc->dev, 332 "PCIe x%d Link, expect reduced performance\n", 333 sc->link_width); 334 } 335 #endif 336 337 touch_bars(dev); 338 339 pci_enable_busmaster(dev); 340 341 /* 342 * Allocate the registers and make them available to the driver. 343 * The registers that we care about for NIC mode are in BAR 0 344 */ 345 sc->regs_rid = PCI_MAPREG_START; 346 t3_os_pci_read_config_4(sc, PCI_MAPREG_START, ®); 347 348 // call bus_space_map 349 sc->bar0 = reg&0xFFFFF000; 350 bus_space_map(sc->pa.pa_memt, sc->bar0, 4096, 0, &sc->bar0_handle); 351 352 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_DEF); 353 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); 354 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); 355 356 sc->bt = sc->pa.pa_memt; 357 sc->bh = sc->bar0_handle; 358 sc->mmio_len = 4096; 359 360 if (t3_prep_adapter(sc, ai, 1) < 0) { 361 printf("prep adapter failed\n"); 362 error = ENODEV; 363 goto out; 364 } 365 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate 366 * enough messages for the queue sets. If that fails, try falling 367 * back to MSI. If that fails, then try falling back to the legacy 368 * interrupt pin model. 369 */ 370 #ifdef MSI_SUPPORTED 371 372 sc->msix_regs_rid = 0x20; 373 if ((msi_allowed >= 2) && 374 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 375 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { 376 377 msi_needed = sc->msi_count = SGE_MSIX_COUNT; 378 379 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) || 380 (sc->msi_count != msi_needed)) { 381 device_printf(dev, "msix allocation failed - msi_count = %d" 382 " msi_needed=%d will try msi err=%d\n", sc->msi_count, 383 msi_needed, error); 384 sc->msi_count = 0; 385 pci_release_msi(dev); 386 bus_release_resource(dev, SYS_RES_MEMORY, 387 sc->msix_regs_rid, sc->msix_regs_res); 388 sc->msix_regs_res = NULL; 389 } else { 390 sc->flags |= USING_MSIX; 391 sc->cxgb_intr = t3_intr_msix; 392 } 393 } 394 395 if ((msi_allowed >= 1) && (sc->msi_count == 0)) { 396 sc->msi_count = 1; 397 if (pci_alloc_msi(dev, &sc->msi_count)) { 398 device_printf(dev, "alloc msi failed - will try INTx\n"); 399 sc->msi_count = 0; 400 pci_release_msi(dev); 401 } else { 402 sc->flags |= USING_MSI; 403 sc->irq_rid = 1; 404 sc->cxgb_intr = t3_intr_msi; 405 } 406 } 407 #endif 408 if (sc->msi_count == 0) { 409 device_printf(dev, "using line interrupts\n"); 410 sc->irq_rid = 0; 411 sc->cxgb_intr = t3b_intr; 412 } 413 414 sc->ext_intr_task.name = "cxgb_ext_intr_handler"; 415 sc->ext_intr_task.func = cxgb_ext_intr_handler; 416 sc->ext_intr_task.context = sc; 417 kthread_create(PRI_NONE, 0, NULL, cxgb_make_task, &sc->ext_intr_task, NULL, "cxgb_make_task"); 418 419 sc->tick_task.name = "cxgb_tick_handler"; 420 sc->tick_task.func = cxgb_tick_handler; 421 sc->tick_task.context = sc; 422 kthread_create(PRI_NONE, 0, NULL, cxgb_make_task, &sc->tick_task, NULL, "cxgb_make_task"); 423 424 /* Create a periodic callout for checking adapter status */ 425 callout_init(&sc->cxgb_tick_ch, 0); 426 427 if (t3_check_fw_version(sc) != 0) { 428 /* 429 * Warn user that a firmware update will be attempted in init. 430 */ 431 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", 432 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); 433 sc->flags &= ~FW_UPTODATE; 434 } else { 435 sc->flags |= FW_UPTODATE; 436 } 437 438 if (t3_check_tpsram_version(sc) != 0) { 439 /* 440 * Warn user that a firmware update will be attempted in init. 441 */ 442 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", 443 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); 444 sc->flags &= ~TPS_UPTODATE; 445 } else { 446 sc->flags |= TPS_UPTODATE; 447 } 448 449 if ((sc->flags & USING_MSIX) && !singleq) 450 port_qsets = (SGE_QSETS/(sc)->params.nports); 451 452 /* 453 * Create a child device for each MAC. The ethernet attachment 454 * will be done in these children. 455 */ 456 for (i = 0; i < (sc)->params.nports; i++) { 457 struct port_info *pi; 458 459 pi = &sc->port[i]; 460 pi->adapter = sc; 461 pi->nqsets = port_qsets; 462 pi->first_qset = i*port_qsets; 463 pi->port_id = i; 464 pi->tx_chan = i >= ai->nports0; 465 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; 466 sc->rxpkt_map[pi->txpkt_intf] = i; 467 cxgb_args.port = i; 468 locs[0] = 1; 469 locs[1] = i; 470 printf("\n"); // for cleaner formatting in dmesg 471 child = config_found(dev, &cxgb_args, cxgb_cfprint, 472 CFARG_SUBMATCH, config_stdsubmatch, 473 CFARG_LOCATORS, locs, 474 CFARG_EOL); 475 printf("\n"); // for cleaner formatting in dmesg 476 sc->portdev[i] = child; 477 } 478 479 /* 480 * XXX need to poll for link status 481 */ 482 sc->params.stats_update_period = 1; 483 484 /* initialize sge private state */ 485 t3_sge_init_adapter(sc); 486 487 t3_led_ready(sc); 488 489 error = t3_get_fw_version(sc, &vers); 490 if (error) 491 goto out; 492 493 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", 494 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), 495 G_FW_VERSION_MICRO(vers)); 496 out: 497 if (error) 498 { 499 cxgb_free(sc); 500 } 501 } 502 503 static int 504 cxgb_controller_detach(device_t dev, int flags) 505 { 506 struct adapter *sc; 507 508 sc = device_private(dev); 509 510 cxgb_free(sc); 511 512 return (0); 513 } 514 515 static void 516 cxgb_free(struct adapter *sc) 517 { 518 int i; 519 520 ADAPTER_LOCK(sc); 521 /* 522 * drops the lock 523 */ 524 cxgb_down_locked(sc); 525 526 #ifdef MSI_SUPPORTED 527 if (sc->flags & (USING_MSI | USING_MSIX)) { 528 device_printf(sc->dev, "releasing msi message(s)\n"); 529 pci_release_msi(sc->dev); 530 } else { 531 device_printf(sc->dev, "no msi message to release\n"); 532 } 533 if (sc->msix_regs_res != NULL) { 534 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, 535 sc->msix_regs_res); 536 } 537 #endif 538 539 t3_sge_deinit_sw(sc); 540 /* 541 * Wait for last callout 542 */ 543 544 tsleep(&sc, 0, "cxgb unload", 3*hz); 545 546 for (i = 0; i < (sc)->params.nports; ++i) { 547 if (sc->portdev[i] != NULL) 548 { 549 INT3; 550 } 551 } 552 553 #ifdef notyet 554 if (is_offload(sc)) { 555 cxgb_adapter_unofld(sc); 556 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT)) 557 offload_close(&sc->tdev); 558 } 559 #endif 560 561 t3_free_sge_resources(sc); 562 free(sc->filters, M_DEVBUF); 563 t3_sge_free(sc); 564 565 MTX_DESTROY(&sc->mdio_lock); 566 MTX_DESTROY(&sc->sge.reg_lock); 567 MTX_DESTROY(&sc->elmer_lock); 568 ADAPTER_LOCK_DEINIT(sc); 569 570 return; 571 } 572 573 /** 574 * setup_sge_qsets - configure SGE Tx/Rx/response queues 575 * @sc: the controller softc 576 * 577 * Determines how many sets of SGE queues to use and initializes them. 578 * We support multiple queue sets per port if we have MSI-X, otherwise 579 * just one queue set per port. 580 */ 581 static int 582 setup_sge_qsets(adapter_t *sc) 583 { 584 int i, j, err, irq_idx = 0, qset_idx = 0; 585 u_int ntxq = SGE_TXQ_PER_SET; 586 587 if ((err = t3_sge_alloc(sc)) != 0) { 588 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); 589 return (err); 590 } 591 592 if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) 593 irq_idx = -1; 594 595 for (i = 0; i < (sc)->params.nports; i++) { 596 struct port_info *pi = &sc->port[i]; 597 598 for (j = 0; j < pi->nqsets; j++, qset_idx++) { 599 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, 600 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, 601 &sc->params.sge.qset[qset_idx], ntxq, pi); 602 if (err) { 603 t3_free_sge_resources(sc); 604 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", 605 err); 606 return (err); 607 } 608 } 609 } 610 611 return (0); 612 } 613 614 static void 615 cxgb_teardown_msix(adapter_t *sc) 616 { 617 int i, nqsets; 618 619 for (nqsets = i = 0; i < (sc)->params.nports; i++) 620 nqsets += sc->port[i].nqsets; 621 622 for (i = 0; i < nqsets; i++) { 623 if (sc->msix_intr_tag[i] != NULL) { 624 sc->msix_intr_tag[i] = NULL; 625 } 626 if (sc->msix_irq_res[i] != NULL) { 627 sc->msix_irq_res[i] = NULL; 628 } 629 } 630 } 631 632 static int 633 cxgb_setup_msix(adapter_t *sc, int msix_count) 634 { 635 int i, j, k, nqsets, rid; 636 637 /* The first message indicates link changes and error conditions */ 638 sc->irq_rid = 1; 639 /* Allocate PCI interrupt resources. */ 640 if (pci_intr_map(&sc->pa, &sc->intr_handle)) 641 { 642 printf("cxgb_setup_msix(%d): pci_intr_map() failed\n", __LINE__); 643 return (EINVAL); 644 } 645 sc->intr_cookie = pci_intr_establish_xname(sc->pa.pa_pc, sc->intr_handle, 646 IPL_NET, cxgb_async_intr, sc, device_xname(sc->dev)); 647 if (sc->intr_cookie == NULL) 648 { 649 printf("cxgb_setup_msix(%d): pci_intr_establish() failed\n", __LINE__); 650 return (EINVAL); 651 } 652 for (i = k = 0; i < (sc)->params.nports; i++) { 653 nqsets = sc->port[i].nqsets; 654 for (j = 0; j < nqsets; j++, k++) { 655 rid = k + 2; 656 if (cxgb_debug) 657 printf("rid=%d ", rid); 658 INT3; 659 } 660 } 661 662 663 return (0); 664 } 665 666 static int cxgb_port_match(device_t dev, cfdata_t match, void *context) 667 { 668 return (100); 669 } 670 671 #define IFCAP_HWCSUM (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_IPv4_Tx) 672 #define IFCAP_RXCSUM IFCAP_CSUM_IPv4_Rx 673 #define IFCAP_TXCSUM IFCAP_CSUM_IPv4_Tx 674 675 #ifdef TSO_SUPPORTED 676 #define CXGB_CAP (IFCAP_HWCSUM | IFCAP_TSO) 677 /* Don't enable TSO6 yet */ 678 #define CXGB_CAP_ENABLE (IFCAP_HWCSUM | IFCAP_TSO4) 679 #else 680 #define CXGB_CAP (IFCAP_HWCSUM) 681 /* Don't enable TSO6 yet */ 682 #define CXGB_CAP_ENABLE (IFCAP_HWCSUM) 683 #define IFCAP_TSO4 0x0 684 #define IFCAP_TSO6 0x0 685 #define CSUM_TSO 0x0 686 #endif 687 688 static void 689 cxgb_port_attach(device_t parent, device_t self, void *context) 690 { 691 struct port_info *p; 692 struct port_device *pd; 693 int *port_number = (int *)context; 694 char buf[32]; 695 struct ifnet *ifp; 696 int media_flags; 697 pd = device_private(self); 698 pd->dev = self; 699 pd->parent = device_private(parent); 700 pd->port_number = *port_number; 701 p = &pd->parent->port[*port_number]; 702 p->pd = pd; 703 704 PORT_LOCK_INIT(p, p->lockbuf); 705 706 /* Allocate an ifnet object and set it up */ 707 ifp = p->ifp = (void *)malloc(sizeof (struct ifnet), M_IFADDR, M_WAITOK); 708 if (ifp == NULL) { 709 device_printf(self, "Cannot allocate ifnet\n"); 710 return; 711 } 712 memset(ifp, 0, sizeof(struct ifnet)); 713 714 /* 715 * Note that there is currently no watchdog timer. 716 */ 717 snprintf(buf, sizeof(buf), "cxgb%d", p->port); 718 strcpy(ifp->if_xname, buf); 719 ifp->if_init = cxgb_init; 720 ifp->if_softc = p; 721 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 722 ifp->if_ioctl = cxgb_ioctl; 723 ifp->if_start = cxgb_start; 724 ifp->if_stop = cxgb_stop; 725 ifp->if_timer = 0; /* Disable ifnet watchdog */ 726 ifp->if_watchdog = NULL; 727 728 ifp->if_snd.ifq_maxlen = TX_ETH_Q_SIZE; 729 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_maxlen); 730 731 IFQ_SET_READY(&ifp->if_snd); 732 733 ifp->if_capabilities = ifp->if_capenable = 0; 734 ifp->if_baudrate = 10000000000; // 10 Gbps 735 /* 736 * disable TSO on 4-port - it isn't supported by the firmware yet 737 */ 738 if (p->adapter->params.nports > 2) { 739 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6); 740 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6); 741 } 742 743 if_attach(ifp); 744 ether_ifattach(ifp, p->hw_addr); 745 /* 746 * Only default to jumbo frames on 10GigE 747 */ 748 if (p->adapter->params.nports <= 2) 749 ifp->if_mtu = 9000; 750 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, 751 cxgb_media_status); 752 753 if (!strcmp(p->port_type->desc, "10GBASE-CX4")) { 754 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX; 755 } else if (!strcmp(p->port_type->desc, "10GBASE-SR")) { 756 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX; 757 } else if (!strcmp(p->port_type->desc, "10GBASE-XR")) { 758 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX; 759 } else if (!strcmp(p->port_type->desc, "10/100/1000BASE-T")) { 760 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL); 761 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX, 762 0, NULL); 763 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX, 764 0, NULL); 765 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 766 0, NULL); 767 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 768 0, NULL); 769 media_flags = 0; 770 } else { 771 printf("unsupported media type %s\n", p->port_type->desc); 772 return; 773 } 774 if (media_flags) { 775 ifmedia_add(&p->media, media_flags, 0, NULL); 776 ifmedia_set(&p->media, media_flags); 777 } else { 778 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL); 779 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO); 780 } 781 782 snprintf(p->taskqbuf, TASKQ_NAME_LEN, "cxgb_port_taskq%d", p->port_id); 783 p->start_task.name = "cxgb_start_proc"; 784 p->start_task.func = cxgb_start_proc; 785 p->start_task.context = ifp; 786 kthread_create(PRI_NONE, 0, NULL, cxgb_make_task, &p->start_task, NULL, "cxgb_make_task"); 787 788 t3_sge_init_port(p); 789 } 790 791 static int 792 cxgb_port_detach(device_t self, int flags) 793 { 794 struct port_info *p; 795 796 p = device_private(self); 797 798 PORT_LOCK(p); 799 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING) 800 cxgb_stop_locked(p); 801 PORT_UNLOCK(p); 802 803 if (p->start_task.wq != NULL) { 804 workqueue_destroy(p->start_task.wq); 805 p->start_task.wq = NULL; 806 } 807 808 ether_ifdetach(p->ifp); 809 /* 810 * the lock may be acquired in ifdetach 811 */ 812 PORT_LOCK_DEINIT(p); 813 if_detach(p->ifp); 814 815 ifmedia_fini(&p->media); 816 817 return (0); 818 } 819 820 void 821 t3_fatal_err(struct adapter *sc) 822 { 823 u_int fw_status[4]; 824 825 if (sc->flags & FULL_INIT_DONE) { 826 t3_sge_stop(sc); 827 t3_write_reg(sc, A_XGM_TX_CTRL, 0); 828 t3_write_reg(sc, A_XGM_RX_CTRL, 0); 829 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); 830 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); 831 t3_intr_disable(sc); 832 } 833 device_printf(sc->dev,"encountered fatal error, operation suspended\n"); 834 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) 835 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", 836 fw_status[0], fw_status[1], fw_status[2], fw_status[3]); 837 } 838 839 int 840 t3_os_find_pci_capability(adapter_t *sc, int cap) 841 { 842 device_t dev; 843 uint32_t status; 844 uint32_t bhlc; 845 uint32_t temp; 846 uint8_t ptr; 847 dev = sc->dev; 848 status = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, PCI_COMMAND_STATUS_REG); 849 if (!(status&PCI_STATUS_CAPLIST_SUPPORT)) 850 return (0); 851 bhlc = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, PCI_BHLC_REG); 852 switch (PCI_HDRTYPE(bhlc)) 853 { 854 case 0: 855 case 1: 856 ptr = PCI_CAPLISTPTR_REG; 857 break; 858 case 2: 859 ptr = PCI_CARDBUS_CAPLISTPTR_REG; 860 break; 861 default: 862 return (0); 863 } 864 temp = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, ptr); 865 ptr = PCI_CAPLIST_PTR(temp); 866 while (ptr != 0) { 867 temp = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, ptr); 868 if (PCI_CAPLIST_CAP(temp) == cap) 869 return (ptr); 870 ptr = PCI_CAPLIST_NEXT(temp); 871 } 872 873 return (0); 874 } 875 876 int 877 t3_os_pci_save_state(struct adapter *sc) 878 { 879 INT3; 880 return (0); 881 } 882 883 int 884 t3_os_pci_restore_state(struct adapter *sc) 885 { 886 INT3; 887 return (0); 888 } 889 890 /** 891 * t3_os_link_changed - handle link status changes 892 * @adapter: the adapter associated with the link change 893 * @port_id: the port index whose limk status has changed 894 * @link_stat: the new status of the link 895 * @speed: the new speed setting 896 * @duplex: the new duplex setting 897 * @fc: the new flow-control setting 898 * 899 * This is the OS-dependent handler for link status changes. The OS 900 * neutral handler takes care of most of the processing for these events, 901 * then calls this handler for any OS-specific processing. 902 */ 903 void 904 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, 905 int duplex, int fc) 906 { 907 struct port_info *pi = &adapter->port[port_id]; 908 struct cmac *mac = &adapter->port[port_id].mac; 909 910 if ((pi->ifp->if_flags & IFF_UP) == 0) 911 return; 912 913 if (link_status) { 914 t3_mac_enable(mac, MAC_DIRECTION_RX); 915 if_link_state_change(pi->ifp, LINK_STATE_UP); 916 } else { 917 if_link_state_change(pi->ifp, LINK_STATE_DOWN); 918 pi->phy.ops->power_down(&pi->phy, 1); 919 t3_mac_disable(mac, MAC_DIRECTION_RX); 920 t3_link_start(&pi->phy, mac, &pi->link_config); 921 } 922 } 923 924 /* 925 * Interrupt-context handler for external (PHY) interrupts. 926 */ 927 void 928 t3_os_ext_intr_handler(adapter_t *sc) 929 { 930 if (cxgb_debug) 931 printf("t3_os_ext_intr_handler\n"); 932 /* 933 * Schedule a task to handle external interrupts as they may be slow 934 * and we use a mutex to protect MDIO registers. We disable PHY 935 * interrupts in the meantime and let the task reenable them when 936 * it's done. 937 */ 938 ADAPTER_LOCK(sc); 939 if (sc->slow_intr_mask) { 940 sc->slow_intr_mask &= ~F_T3DBG; 941 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 942 workqueue_enqueue(sc->ext_intr_task.wq, &sc->ext_intr_task.w, NULL); 943 } 944 ADAPTER_UNLOCK(sc); 945 } 946 947 void 948 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) 949 { 950 951 /* 952 * The ifnet might not be allocated before this gets called, 953 * as this is called early on in attach by t3_prep_adapter 954 * save the address off in the port structure 955 */ 956 if (cxgb_debug) 957 printf("set_hw_addr on idx %d addr %02x:%02x:%02x:%02x:%02x:%02x\n", 958 port_idx, hw_addr[0], hw_addr[1], hw_addr[2], hw_addr[3], hw_addr[4], hw_addr[5]); 959 memcpy(adapter->port[port_idx].hw_addr, hw_addr, ETHER_ADDR_LEN); 960 } 961 962 /** 963 * link_start - enable a port 964 * @p: the port to enable 965 * 966 * Performs the MAC and PHY actions needed to enable a port. 967 */ 968 static void 969 cxgb_link_start(struct port_info *p) 970 { 971 struct ifnet *ifp; 972 struct t3_rx_mode rm; 973 struct cmac *mac = &p->mac; 974 975 ifp = p->ifp; 976 977 t3_init_rx_mode(&rm, p); 978 if (!mac->multiport) 979 t3_mac_reset(mac); 980 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 981 t3_mac_set_address(mac, 0, p->hw_addr); 982 t3_mac_set_rx_mode(mac, &rm); 983 t3_link_start(&p->phy, mac, &p->link_config); 984 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 985 } 986 987 /** 988 * setup_rss - configure Receive Side Steering (per-queue connection demux) 989 * @adap: the adapter 990 * 991 * Sets up RSS to distribute packets to multiple receive queues. We 992 * configure the RSS CPU lookup table to distribute to the number of HW 993 * receive queues, and the response queue lookup table to narrow that 994 * down to the response queues actually configured for each port. 995 * We always configure the RSS mapping for two ports since the mapping 996 * table has plenty of entries. 997 */ 998 static void 999 setup_rss(adapter_t *adap) 1000 { 1001 int i; 1002 u_int nq[2]; 1003 uint8_t cpus[SGE_QSETS + 1]; 1004 uint16_t rspq_map[RSS_TABLE_SIZE]; 1005 1006 for (i = 0; i < SGE_QSETS; ++i) 1007 cpus[i] = i; 1008 cpus[SGE_QSETS] = 0xff; 1009 1010 nq[0] = nq[1] = 0; 1011 for_each_port(adap, i) { 1012 const struct port_info *pi = adap2pinfo(adap, i); 1013 1014 nq[pi->tx_chan] += pi->nqsets; 1015 } 1016 nq[0] = uimax(nq[0], 1U); 1017 nq[1] = uimax(nq[1], 1U); 1018 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { 1019 rspq_map[i] = i % nq[0]; 1020 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq[1]) + nq[0]; 1021 } 1022 /* Calculate the reverse RSS map table */ 1023 for (i = 0; i < RSS_TABLE_SIZE; ++i) 1024 if (adap->rrss_map[rspq_map[i]] == 0xff) 1025 adap->rrss_map[rspq_map[i]] = i; 1026 1027 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | 1028 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | 1029 V_RRCPLCPUSIZE(6), cpus, rspq_map); 1030 1031 } 1032 1033 /* 1034 * Sends an mbuf to an offload queue driver 1035 * after dealing with any active network taps. 1036 */ 1037 static inline int 1038 offload_tx(struct toedev *tdev, struct mbuf *m) 1039 { 1040 int ret; 1041 1042 critical_enter(); 1043 ret = t3_offload_tx(tdev, m); 1044 critical_exit(); 1045 return (ret); 1046 } 1047 1048 static void 1049 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, 1050 int hi, int port) 1051 { 1052 struct mbuf *m; 1053 struct mngt_pktsched_wr *req; 1054 1055 m = m_gethdr(M_DONTWAIT, MT_DATA); 1056 if (m) { 1057 req = mtod(m, struct mngt_pktsched_wr *); 1058 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); 1059 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; 1060 req->sched = sched; 1061 req->idx = qidx; 1062 req->min = lo; 1063 req->max = hi; 1064 req->binding = port; 1065 m->m_len = m->m_pkthdr.len = sizeof(*req); 1066 t3_mgmt_tx(adap, m); 1067 } 1068 } 1069 1070 static void 1071 bind_qsets(adapter_t *sc) 1072 { 1073 int i, j; 1074 1075 for (i = 0; i < (sc)->params.nports; ++i) { 1076 const struct port_info *pi = adap2pinfo(sc, i); 1077 1078 for (j = 0; j < pi->nqsets; ++j) { 1079 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, 1080 -1, pi->tx_chan); 1081 1082 } 1083 } 1084 } 1085 1086 /** 1087 * cxgb_up - enable the adapter 1088 * @adap: adapter being enabled 1089 * 1090 * Called when the first port is enabled, this function performs the 1091 * actions necessary to make an adapter operational, such as completing 1092 * the initialization of HW modules, and enabling interrupts. 1093 * 1094 */ 1095 static int 1096 cxgb_up(struct adapter *sc) 1097 { 1098 int err = 0; 1099 1100 if ((sc->flags & FULL_INIT_DONE) == 0) { 1101 1102 if ((sc->flags & FW_UPTODATE) == 0) 1103 printf("SHOULD UPGRADE FIRMWARE!\n"); 1104 if ((sc->flags & TPS_UPTODATE) == 0) 1105 printf("SHOULD UPDATE TPSRAM\n"); 1106 err = t3_init_hw(sc, 0); 1107 if (err) 1108 goto out; 1109 1110 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); 1111 1112 err = setup_sge_qsets(sc); 1113 if (err) 1114 goto out; 1115 1116 setup_rss(sc); 1117 sc->flags |= FULL_INIT_DONE; 1118 } 1119 1120 t3_intr_clear(sc); 1121 1122 /* If it's MSI or INTx, allocate a single interrupt for everything */ 1123 if ((sc->flags & USING_MSIX) == 0) { 1124 if (pci_intr_map(&sc->pa, &sc->intr_handle)) 1125 { 1126 device_printf(sc->dev, "Cannot allocate interrupt\n"); 1127 err = EINVAL; 1128 goto out; 1129 } 1130 device_printf(sc->dev, "allocated intr_handle=%d\n", sc->intr_handle); 1131 sc->intr_cookie = pci_intr_establish_xname(sc->pa.pa_pc, 1132 sc->intr_handle, IPL_NET, 1133 sc->cxgb_intr, sc, device_xname(sc->dev)); 1134 if (sc->intr_cookie == NULL) 1135 { 1136 device_printf(sc->dev, "Cannot establish interrupt\n"); 1137 err = EINVAL; 1138 goto irq_err; 1139 } 1140 } else { 1141 printf("Using MSIX?!?!?!\n"); 1142 INT3; 1143 cxgb_setup_msix(sc, sc->msi_count); 1144 } 1145 1146 t3_sge_start(sc); 1147 t3_intr_enable(sc); 1148 1149 if (!(sc->flags & QUEUES_BOUND)) { 1150 bind_qsets(sc); 1151 sc->flags |= QUEUES_BOUND; 1152 } 1153 out: 1154 return (err); 1155 irq_err: 1156 CH_ERR(sc, "request_irq failed, err %d\n", err); 1157 goto out; 1158 } 1159 1160 1161 /* 1162 * Release resources when all the ports and offloading have been stopped. 1163 */ 1164 static void 1165 cxgb_down_locked(struct adapter *sc) 1166 { 1167 t3_sge_stop(sc); 1168 t3_intr_disable(sc); 1169 1170 INT3; // XXXXXXXXXXXXXXXXXX 1171 1172 if (sc->flags & USING_MSIX) 1173 cxgb_teardown_msix(sc); 1174 ADAPTER_UNLOCK(sc); 1175 1176 callout_drain(&sc->cxgb_tick_ch); 1177 callout_drain(&sc->sge_timer_ch); 1178 1179 #ifdef notyet 1180 1181 if (sc->port[i].tq != NULL) 1182 #endif 1183 1184 } 1185 1186 static int 1187 cxgb_init(struct ifnet *ifp) 1188 { 1189 struct port_info *p = ifp->if_softc; 1190 1191 PORT_LOCK(p); 1192 cxgb_init_locked(p); 1193 PORT_UNLOCK(p); 1194 1195 return (0); // ???????????? 1196 } 1197 1198 static void 1199 cxgb_init_locked(struct port_info *p) 1200 { 1201 struct ifnet *ifp; 1202 adapter_t *sc = p->adapter; 1203 int err; 1204 1205 PORT_LOCK_ASSERT_OWNED(p); 1206 ifp = p->ifp; 1207 1208 ADAPTER_LOCK(p->adapter); 1209 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) { 1210 ADAPTER_UNLOCK(p->adapter); 1211 cxgb_stop_locked(p); 1212 return; 1213 } 1214 if (p->adapter->open_device_map == 0) { 1215 t3_intr_clear(sc); 1216 t3_sge_init_adapter(sc); 1217 } 1218 setbit(&p->adapter->open_device_map, p->port_id); 1219 ADAPTER_UNLOCK(p->adapter); 1220 1221 cxgb_link_start(p); 1222 t3_link_changed(sc, p->port_id); 1223 ifp->if_baudrate = p->link_config.speed * 1000000; 1224 1225 device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id); 1226 t3_port_intr_enable(sc, p->port_id); 1227 1228 callout_reset(&sc->cxgb_tick_ch, sc->params.stats_update_period * hz, 1229 cxgb_tick, sc); 1230 1231 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1232 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1233 } 1234 1235 static void 1236 cxgb_set_rxmode(struct port_info *p) 1237 { 1238 struct t3_rx_mode rm; 1239 struct cmac *mac = &p->mac; 1240 1241 PORT_LOCK_ASSERT_OWNED(p); 1242 1243 t3_init_rx_mode(&rm, p); 1244 t3_mac_set_rx_mode(mac, &rm); 1245 } 1246 1247 static void 1248 cxgb_stop_locked(struct port_info *p) 1249 { 1250 struct ifnet *ifp; 1251 1252 PORT_LOCK_ASSERT_OWNED(p); 1253 ADAPTER_LOCK_ASSERT_NOTOWNED(p->adapter); 1254 1255 ifp = p->ifp; 1256 1257 t3_port_intr_disable(p->adapter, p->port_id); 1258 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1259 p->phy.ops->power_down(&p->phy, 1); 1260 t3_mac_disable(&p->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); 1261 1262 ADAPTER_LOCK(p->adapter); 1263 clrbit(&p->adapter->open_device_map, p->port_id); 1264 1265 1266 if (p->adapter->open_device_map == 0) { 1267 cxgb_down_locked(p->adapter); 1268 } else 1269 ADAPTER_UNLOCK(p->adapter); 1270 1271 } 1272 1273 static int 1274 cxgb_set_mtu(struct port_info *p, int mtu) 1275 { 1276 struct ifnet *ifp = p->ifp; 1277 struct ifreq ifr; 1278 int error = 0; 1279 1280 ifr.ifr_mtu = mtu; 1281 1282 if ((mtu < ETHERMIN) || (mtu > ETHER_MAX_LEN_JUMBO)) 1283 error = EINVAL; 1284 else if ((error = ifioctl_common(ifp, SIOCSIFMTU, &ifr)) == ENETRESET) { 1285 error = 0; 1286 PORT_LOCK(p); 1287 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1288 callout_stop(&p->adapter->cxgb_tick_ch); 1289 cxgb_stop_locked(p); 1290 cxgb_init_locked(p); 1291 } 1292 PORT_UNLOCK(p); 1293 } 1294 return (error); 1295 } 1296 1297 static int 1298 cxgb_ioctl(struct ifnet *ifp, unsigned long command, void *data) 1299 { 1300 struct port_info *p = ifp->if_softc; 1301 struct ifaddr *ifa = (struct ifaddr *)data; 1302 struct ifreq *ifr = (struct ifreq *)data; 1303 int flags, error = 0; 1304 1305 /* 1306 * XXX need to check that we aren't in the middle of an unload 1307 */ 1308 printf("cxgb_ioctl(%d): command=%08lx\n", __LINE__, command); 1309 switch (command) { 1310 case SIOCSIFMTU: 1311 error = cxgb_set_mtu(p, ifr->ifr_mtu); 1312 printf("SIOCSIFMTU: error=%d\n", error); 1313 break; 1314 case SIOCINITIFADDR: 1315 printf("SIOCINITIFADDR:\n"); 1316 PORT_LOCK(p); 1317 if (ifa->ifa_addr->sa_family == AF_INET) { 1318 ifp->if_flags |= IFF_UP; 1319 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1320 cxgb_init_locked(p); 1321 arp_ifinit(ifp, ifa); 1322 } else 1323 error = ether_ioctl(ifp, command, data); 1324 PORT_UNLOCK(p); 1325 break; 1326 case SIOCSIFFLAGS: 1327 printf("SIOCSIFFLAGS:\n"); 1328 #if 0 1329 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1330 break; 1331 #endif 1332 callout_drain(&p->adapter->cxgb_tick_ch); 1333 PORT_LOCK(p); 1334 if (ifp->if_flags & IFF_UP) { 1335 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1336 flags = p->if_flags; 1337 if (((ifp->if_flags ^ flags) & IFF_PROMISC) || 1338 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) 1339 cxgb_set_rxmode(p); 1340 } else 1341 cxgb_init_locked(p); 1342 p->if_flags = ifp->if_flags; 1343 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1344 cxgb_stop_locked(p); 1345 1346 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1347 adapter_t *sc = p->adapter; 1348 callout_reset(&sc->cxgb_tick_ch, 1349 sc->params.stats_update_period * hz, 1350 cxgb_tick, sc); 1351 } 1352 PORT_UNLOCK(p); 1353 break; 1354 case SIOCSIFMEDIA: 1355 printf("SIOCSIFMEDIA:\n"); 1356 case SIOCGIFMEDIA: 1357 error = ifmedia_ioctl(ifp, ifr, &p->media, command); 1358 printf("SIOCGIFMEDIA: error=%d\n", error); 1359 break; 1360 default: 1361 printf("Dir = %x Len = %x Group = '%c' Num = %x\n", 1362 (unsigned int)(command&0xe0000000)>>28, (unsigned int)(command&0x1fff0000)>>16, 1363 (unsigned int)(command&0xff00)>>8, (unsigned int)command&0xff); 1364 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1365 break; 1366 error = 0; 1367 break; 1368 } 1369 return (error); 1370 } 1371 1372 static int 1373 cxgb_start_tx(struct ifnet *ifp, uint32_t txmax) 1374 { 1375 struct sge_qset *qs; 1376 struct sge_txq *txq; 1377 struct port_info *p = ifp->if_softc; 1378 struct mbuf *m = NULL; 1379 int err, in_use_init, free_it; 1380 1381 if (!p->link_config.link_ok) 1382 { 1383 return (ENXIO); 1384 } 1385 1386 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1387 { 1388 return (ENOBUFS); 1389 } 1390 1391 qs = &p->adapter->sge.qs[p->first_qset]; 1392 txq = &qs->txq[TXQ_ETH]; 1393 err = 0; 1394 1395 if (txq->flags & TXQ_TRANSMITTING) 1396 { 1397 return (EINPROGRESS); 1398 } 1399 1400 mtx_lock(&txq->lock); 1401 txq->flags |= TXQ_TRANSMITTING; 1402 in_use_init = txq->in_use; 1403 while ((txq->in_use - in_use_init < txmax) && 1404 (txq->size > txq->in_use + TX_MAX_DESC)) { 1405 free_it = 0; 1406 IFQ_DEQUEUE(&ifp->if_snd, m); 1407 if (m == NULL) 1408 break; 1409 /* 1410 * Convert chain to M_IOVEC 1411 */ 1412 KASSERT((m->m_flags & M_IOVEC) == 0); 1413 #ifdef notyet 1414 m0 = m; 1415 if (collapse_mbufs && m->m_pkthdr.len > MCLBYTES && 1416 m_collapse(m, TX_MAX_SEGS, &m0) == EFBIG) { 1417 if ((m0 = m_defrag(m, M_NOWAIT)) != NULL) { 1418 m = m0; 1419 m_collapse(m, TX_MAX_SEGS, &m0); 1420 } else 1421 break; 1422 } 1423 m = m0; 1424 #endif 1425 if ((err = t3_encap(p, &m, &free_it)) != 0) 1426 { 1427 printf("t3_encap() returned %d\n", err); 1428 break; 1429 } 1430 // bpf_mtap(ifp, m, BPF_D_OUT); 1431 if (free_it) 1432 { 1433 m_freem(m); 1434 } 1435 } 1436 txq->flags &= ~TXQ_TRANSMITTING; 1437 mtx_unlock(&txq->lock); 1438 1439 if (__predict_false(err)) { 1440 if (err == ENOMEM) { 1441 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1442 // XXXXXXXXXX lock/unlock?? 1443 IF_PREPEND(&ifp->if_snd, m); 1444 } 1445 } 1446 if (err == 0 && m == NULL) 1447 err = ENOBUFS; 1448 else if ((err == 0) && (txq->size <= txq->in_use + TX_MAX_DESC) && 1449 (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 1450 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1451 err = ENOSPC; 1452 } 1453 return (err); 1454 } 1455 1456 static void 1457 cxgb_start_proc(struct work *wk, void *arg) 1458 { 1459 struct ifnet *ifp = arg; 1460 struct port_info *pi = ifp->if_softc; 1461 struct sge_qset *qs; 1462 struct sge_txq *txq; 1463 int error; 1464 1465 qs = &pi->adapter->sge.qs[pi->first_qset]; 1466 txq = &qs->txq[TXQ_ETH]; 1467 1468 do { 1469 if (desc_reclaimable(txq) > TX_CLEAN_MAX_DESC >> 2) 1470 workqueue_enqueue(pi->timer_reclaim_task.wq, &pi->timer_reclaim_task.w, NULL); 1471 1472 error = cxgb_start_tx(ifp, TX_START_MAX_DESC); 1473 } while (error == 0); 1474 } 1475 1476 static void 1477 cxgb_start(struct ifnet *ifp) 1478 { 1479 struct port_info *pi = ifp->if_softc; 1480 struct sge_qset *qs; 1481 struct sge_txq *txq; 1482 int err; 1483 1484 qs = &pi->adapter->sge.qs[pi->first_qset]; 1485 txq = &qs->txq[TXQ_ETH]; 1486 1487 if (desc_reclaimable(txq) > TX_CLEAN_MAX_DESC >> 2) 1488 workqueue_enqueue(pi->timer_reclaim_task.wq, &pi->timer_reclaim_task.w, NULL); 1489 1490 err = cxgb_start_tx(ifp, TX_START_MAX_DESC); 1491 1492 if (err == 0) 1493 workqueue_enqueue(pi->start_task.wq, &pi->start_task.w, NULL); 1494 } 1495 1496 static void 1497 cxgb_stop(struct ifnet *ifp, int reason) 1498 { 1499 struct port_info *pi = ifp->if_softc; 1500 1501 printf("cxgb_stop(): pi=%p, reason=%d\n", pi, reason); 1502 INT3; 1503 } 1504 1505 static int 1506 cxgb_media_change(struct ifnet *ifp) 1507 { 1508 printf("media change not supported: ifp=%p\n", ifp); 1509 return (ENXIO); 1510 } 1511 1512 static void 1513 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1514 { 1515 struct port_info *p; 1516 1517 p = ifp->if_softc; 1518 1519 ifmr->ifm_status = IFM_AVALID; 1520 ifmr->ifm_active = IFM_ETHER; 1521 1522 if (!p->link_config.link_ok) 1523 return; 1524 1525 ifmr->ifm_status |= IFM_ACTIVE; 1526 1527 switch (p->link_config.speed) { 1528 case 10: 1529 ifmr->ifm_active |= IFM_10_T; 1530 break; 1531 case 100: 1532 ifmr->ifm_active |= IFM_100_TX; 1533 break; 1534 case 1000: 1535 ifmr->ifm_active |= IFM_1000_T; 1536 break; 1537 } 1538 1539 if (p->link_config.duplex) 1540 ifmr->ifm_active |= IFM_FDX; 1541 else 1542 ifmr->ifm_active |= IFM_HDX; 1543 } 1544 1545 static int 1546 cxgb_async_intr(void *data) 1547 { 1548 adapter_t *sc = data; 1549 1550 if (cxgb_debug) 1551 device_printf(sc->dev, "cxgb_async_intr\n"); 1552 /* 1553 * May need to sleep - defer to taskqueue 1554 */ 1555 workqueue_enqueue(sc->slow_intr_task.wq, &sc->slow_intr_task.w, NULL); 1556 1557 return (1); 1558 } 1559 1560 static void 1561 cxgb_ext_intr_handler(struct work *wk, void *arg) 1562 { 1563 adapter_t *sc = (adapter_t *)arg; 1564 1565 if (cxgb_debug) 1566 printf("cxgb_ext_intr_handler\n"); 1567 1568 t3_phy_intr_handler(sc); 1569 1570 /* Now reenable external interrupts */ 1571 ADAPTER_LOCK(sc); 1572 if (sc->slow_intr_mask) { 1573 sc->slow_intr_mask |= F_T3DBG; 1574 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG); 1575 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); 1576 } 1577 ADAPTER_UNLOCK(sc); 1578 } 1579 1580 static void 1581 check_link_status(adapter_t *sc) 1582 { 1583 int i; 1584 1585 for (i = 0; i < (sc)->params.nports; ++i) { 1586 struct port_info *p = &sc->port[i]; 1587 1588 if (!(p->port_type->caps & SUPPORTED_IRQ)) 1589 t3_link_changed(sc, i); 1590 p->ifp->if_baudrate = p->link_config.speed * 1000000; 1591 } 1592 } 1593 1594 static void 1595 check_t3b2_mac(struct adapter *adapter) 1596 { 1597 int i; 1598 1599 for_each_port(adapter, i) { 1600 struct port_info *p = &adapter->port[i]; 1601 struct ifnet *ifp = p->ifp; 1602 int status; 1603 1604 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1605 continue; 1606 1607 status = 0; 1608 PORT_LOCK(p); 1609 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) 1610 status = t3b2_mac_watchdog_task(&p->mac); 1611 if (status == 1) 1612 p->mac.stats.num_toggled++; 1613 else if (status == 2) { 1614 struct cmac *mac = &p->mac; 1615 1616 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN 1617 + ETHER_VLAN_ENCAP_LEN); 1618 t3_mac_set_address(mac, 0, p->hw_addr); 1619 cxgb_set_rxmode(p); 1620 t3_link_start(&p->phy, mac, &p->link_config); 1621 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); 1622 t3_port_intr_enable(adapter, p->port_id); 1623 p->mac.stats.num_resets++; 1624 } 1625 PORT_UNLOCK(p); 1626 } 1627 } 1628 1629 static void 1630 cxgb_tick(void *arg) 1631 { 1632 adapter_t *sc = (adapter_t *)arg; 1633 1634 workqueue_enqueue(sc->tick_task.wq, &sc->tick_task.w, NULL); 1635 1636 if (sc->open_device_map != 0) 1637 callout_reset(&sc->cxgb_tick_ch, sc->params.stats_update_period * hz, 1638 cxgb_tick, sc); 1639 } 1640 1641 static void 1642 cxgb_tick_handler(struct work *wk, void *arg) 1643 { 1644 adapter_t *sc = (adapter_t *)arg; 1645 const struct adapter_params *p = &sc->params; 1646 1647 ADAPTER_LOCK(sc); 1648 if (p->linkpoll_period) 1649 check_link_status(sc); 1650 1651 /* 1652 * adapter lock can currently only be acquire after the 1653 * port lock 1654 */ 1655 ADAPTER_UNLOCK(sc); 1656 1657 if (p->rev == T3_REV_B2 && p->nports < 4) 1658 check_t3b2_mac(sc); 1659 } 1660 1661 static void 1662 touch_bars(device_t dev) 1663 { 1664 /* 1665 * Don't enable yet 1666 */ 1667 #if !defined(__LP64__) && 0 1668 u32 v; 1669 1670 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); 1671 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); 1672 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); 1673 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); 1674 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); 1675 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); 1676 #endif 1677 } 1678 1679 static __inline void 1680 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, 1681 unsigned int end) 1682 { 1683 uint32_t *p = (uint32_t *)buf + start; 1684 1685 for ( ; start <= end; start += sizeof(uint32_t)) 1686 *p++ = t3_read_reg(ap, start); 1687 } 1688 1689