1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 ***************************************************************************/ 29 #ifndef __CHIOCTL_H__ 30 #define __CHIOCTL_H__ 31 32 /* 33 * Ioctl commands specific to this driver. 34 */ 35 enum { 36 CH_SETREG = 0x40, 37 CH_GETREG, 38 CH_SETTPI, 39 CH_GETTPI, 40 CH_DEVUP, 41 CH_GETMTUTAB, 42 CH_SETMTUTAB, 43 CH_GETMTU, 44 CH_SET_PM, 45 CH_GET_PM, 46 CH_GET_TCAM, 47 CH_SET_TCAM, 48 CH_GET_TCB, 49 CH_READ_TCAM_WORD, 50 CH_GET_MEM, 51 CH_GET_SGE_CONTEXT, 52 CH_GET_SGE_DESC, 53 CH_LOAD_FW, 54 CH_GET_PROTO, 55 CH_SET_PROTO, 56 CH_SET_TRACE_FILTER, 57 CH_SET_QSET_PARAMS, 58 CH_GET_QSET_PARAMS, 59 CH_SET_QSET_NUM, 60 CH_GET_QSET_NUM, 61 CH_SET_PKTSCHED, 62 CH_IFCONF_GETREGS, 63 CH_GETMIIREGS, 64 CH_SETMIIREGS, 65 CH_SET_FILTER, 66 CH_SET_HW_SCHED, 67 CH_DEL_FILTER, 68 }; 69 70 struct ch_reg { 71 uint32_t addr; 72 uint32_t val; 73 }; 74 75 struct ch_cntxt { 76 uint32_t cntxt_type; 77 uint32_t cntxt_id; 78 uint32_t data[4]; 79 }; 80 81 /* context types */ 82 enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ }; 83 84 struct ch_desc { 85 uint32_t cmd; 86 uint32_t queue_num; 87 uint32_t idx; 88 uint32_t size; 89 uint8_t data[128]; 90 }; 91 92 struct ch_mem_range { 93 uint32_t cmd; 94 uint32_t mem_id; 95 uint32_t addr; 96 uint32_t len; 97 uint32_t version; 98 uint8_t *buf; 99 }; 100 101 struct ch_qset_params { 102 uint32_t qset_idx; 103 int32_t txq_size[3]; 104 int32_t rspq_size; 105 int32_t fl_size[2]; 106 int32_t intr_lat; 107 int32_t polling; 108 int32_t cong_thres; 109 int32_t vector; 110 int32_t qnum; 111 }; 112 113 struct ch_pktsched_params { 114 uint32_t cmd; 115 uint8_t sched; 116 uint8_t idx; 117 uint8_t min; 118 uint8_t max; 119 uint8_t binding; 120 }; 121 122 struct ch_hw_sched { 123 uint32_t cmd; 124 uint8_t sched; 125 int8_t mode; 126 int8_t channel; 127 int32_t kbps; /* rate in Kbps */ 128 int32_t class_ipg; /* tenths of nanoseconds */ 129 uint32_t flow_ipg; /* usec */ 130 }; 131 132 struct ch_filter_tuple { 133 uint32_t sip; 134 uint32_t dip; 135 uint16_t sport; 136 uint16_t dport; 137 uint16_t vlan:12; 138 uint16_t vlan_prio:3; 139 }; 140 141 struct ch_filter { 142 uint32_t cmd; 143 uint32_t filter_id; 144 struct ch_filter_tuple val; 145 struct ch_filter_tuple mask; 146 uint16_t mac_addr_idx; 147 uint8_t mac_hit:1; 148 uint8_t proto:2; 149 150 uint8_t want_filter_id:1; /* report filter TID instead of RSS hash */ 151 uint8_t pass:1; /* whether to pass or drop packets */ 152 uint8_t rss:1; /* use RSS or specified qset */ 153 uint8_t qset; 154 }; 155 156 #ifndef TCB_SIZE 157 # define TCB_SIZE 128 158 #endif 159 160 /* TCB size in 32-bit words */ 161 #define TCB_WORDS (TCB_SIZE / 4) 162 163 enum { MEM_CM, MEM_PMRX, MEM_PMTX }; /* ch_mem_range.mem_id values */ 164 165 struct ch_mtus { 166 uint32_t cmd; 167 uint32_t nmtus; 168 uint16_t mtus[NMTUS]; 169 }; 170 171 struct ch_pm { 172 uint32_t cmd; 173 uint32_t tx_pg_sz; 174 uint32_t tx_num_pg; 175 uint32_t rx_pg_sz; 176 uint32_t rx_num_pg; 177 uint32_t pm_total; 178 }; 179 180 struct ch_tcam { 181 uint32_t cmd; 182 uint32_t tcam_size; 183 uint32_t nservers; 184 uint32_t nroutes; 185 uint32_t nfilters; 186 }; 187 188 struct ch_tcb { 189 uint32_t cmd; 190 uint32_t tcb_index; 191 uint32_t tcb_data[TCB_WORDS]; 192 }; 193 194 struct ch_tcam_word { 195 uint32_t cmd; 196 uint32_t addr; 197 uint32_t buf[3]; 198 }; 199 200 struct ch_trace { 201 uint32_t cmd; 202 uint32_t sip; 203 uint32_t sip_mask; 204 uint32_t dip; 205 uint32_t dip_mask; 206 uint16_t sport; 207 uint16_t sport_mask; 208 uint16_t dport; 209 uint16_t dport_mask; 210 uint32_t vlan:12, 211 vlan_mask:12, 212 intf:4, 213 intf_mask:4; 214 uint8_t proto; 215 uint8_t proto_mask; 216 uint8_t invert_match:1, 217 config_tx:1, 218 config_rx:1, 219 trace_tx:1, 220 trace_rx:1; 221 }; 222 223 #define REGDUMP_SIZE (4 * 1024) 224 225 struct ifconf_regs { 226 uint32_t version; 227 uint32_t len; /* bytes */ 228 uint8_t *data; 229 }; 230 231 struct mii_data { 232 uint32_t phy_id; 233 uint32_t reg_num; 234 uint32_t val_in; 235 uint32_t val_out; 236 }; 237 238 #define CHELSIO_SETREG _IOW('f', CH_SETREG, struct ch_reg) 239 #define CHELSIO_GETREG _IOWR('f', CH_GETREG, struct ch_reg) 240 #define CHELSIO_READ_TCAM_WORD _IOR('f', CH_READ_TCAM_WORD, struct ch_tcam) 241 #define CHELSIO_GET_MEM _IOWR('f', CH_GET_MEM, struct ch_mem_range) 242 #define CHELSIO_GET_SGE_CONTEXT _IOWR('f', CH_GET_SGE_CONTEXT, struct ch_cntxt) 243 #define CHELSIO_GET_SGE_DESC _IOWR('f', CH_GET_SGE_DESC, struct ch_desc) 244 #define CHELSIO_GET_QSET_PARAMS _IOWR('f', CH_GET_QSET_PARAMS, struct ch_qset_params) 245 #define CHELSIO_SET_QSET_PARAMS _IOW('f', CH_SET_QSET_PARAMS, struct ch_qset_params) 246 #define CHELSIO_GET_QSET_NUM _IOWR('f', CH_GET_QSET_NUM, struct ch_reg) 247 #define CHELSIO_SET_QSET_NUM _IOW('f', CH_SET_QSET_NUM, struct ch_reg) 248 #define CHELSIO_GETMTUTAB _IOR('f', CH_GET_QSET_NUM, struct ch_mtus) 249 #define CHELSIO_SETMTUTAB _IOW('f', CH_SET_QSET_NUM, struct ch_mtus) 250 251 252 #define CHELSIO_SET_TRACE_FILTER _IOW('f', CH_SET_TRACE_FILTER, struct ch_trace) 253 #define CHELSIO_SET_PKTSCHED _IOW('f', CH_SET_PKTSCHED, struct ch_pktsched_params) 254 #define CHELSIO_IFCONF_GETREGS _IOWR('f', CH_IFCONF_GETREGS, struct ifconf_regs) 255 #define SIOCGMIIREG _IOWR('f', CH_GETMIIREGS, struct mii_data) 256 #define SIOCSMIIREG _IOWR('f', CH_SETMIIREGS, struct mii_data) 257 #define CHELSIO_SET_HW_SCHED _IOWR('f', CH_SET_HW_SCHED, struct ch_hw_sched) 258 #define CHELSIO_SET_FILTER _IOW('f', CH_SET_FILTER, struct ch_filter) 259 #define CHELSIO_DEL_FILTER _IOW('f', CH_DEL_FILTER, struct ch_filter) 260 #define CHELSIO_DEVUP _IO('f', CH_DEVUP) 261 #endif 262