1 /* $NetBSD: cxdtv.c,v 1.16 2018/12/09 11:14:01 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.16 2018/12/09 11:14:01 jdolecek Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/proc.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_bitbang.h> 46 47 #include <dev/i2c/tvpllvar.h> 48 #include <dev/i2c/tvpll_tuners.h> 49 50 #include <dev/i2c/nxt2kvar.h> 51 #include <dev/i2c/lg3303var.h> 52 53 #include <dev/dtv/dtvif.h> 54 55 #include <dev/pci/cxdtvreg.h> 56 #include <dev/pci/cxdtvvar.h> 57 #include <dev/pci/cxdtv_boards.h> 58 59 #define CXDTV_MMBASE 0x10 60 61 #define CXDTV_SRAM_CH_MPEG 0 62 #define CXDTV_TS_PKTSIZE (188 * 8) 63 64 static int cxdtv_match(device_t, cfdata_t, void *); 65 static void cxdtv_attach(device_t, device_t, void *); 66 static int cxdtv_detach(device_t, int); 67 static int cxdtv_rescan(device_t, const char *, const int *); 68 static void cxdtv_childdet(device_t, device_t); 69 static int cxdtv_intr(void *); 70 71 static bool cxdtv_resume(device_t, const pmf_qual_t *); 72 73 static int cxdtv_iic_acquire_bus(void *, int); 74 static void cxdtv_iic_release_bus(void *, int); 75 static int cxdtv_iic_send_start(void *, int); 76 static int cxdtv_iic_send_stop(void *, int); 77 static int cxdtv_iic_initiate_xfer(void *, i2c_addr_t, int); 78 static int cxdtv_iic_read_byte(void *, uint8_t *, int); 79 static int cxdtv_iic_write_byte(void *, uint8_t, int); 80 81 static void cxdtv_i2cbb_set_bits(void *, uint32_t); 82 static void cxdtv_i2cbb_set_dir(void *, uint32_t); 83 static uint32_t cxdtv_i2cbb_read_bits(void *); 84 85 static int cxdtv_sram_ch_setup(struct cxdtv_softc *, 86 struct cxdtv_sram_ch *, uint32_t); 87 static int cxdtv_allocmem(struct cxdtv_softc *, size_t, size_t, 88 struct cxdtv_dma *); 89 static int cxdtv_freemem(struct cxdtv_softc *, struct cxdtv_dma *); 90 static int cxdtv_risc_buffer(struct cxdtv_softc *, uint32_t, uint32_t); 91 static int cxdtv_risc_field(struct cxdtv_softc *, uint32_t *, uint32_t); 92 93 static int cxdtv_mpeg_attach(struct cxdtv_softc *); 94 static int cxdtv_mpeg_detach(struct cxdtv_softc *, int flags); 95 static int cxdtv_mpeg_intr(struct cxdtv_softc *); 96 static int cxdtv_mpeg_reset(struct cxdtv_softc *); 97 98 static int cxdtv_mpeg_trigger(struct cxdtv_softc *, void *); 99 static int cxdtv_mpeg_halt(struct cxdtv_softc *); 100 static void * cxdtv_mpeg_malloc(struct cxdtv_softc *, size_t); 101 static void cxdtv_mpeg_free(struct cxdtv_softc *, void *); 102 103 static void cxdtv_card_init_hd5500(struct cxdtv_softc *); 104 static void cxdtv_card_init_hdtvwonder(struct cxdtv_softc *); 105 106 /* MPEG TS Port */ 107 static void cxdtv_dtv_get_devinfo(void *, struct dvb_frontend_info *); 108 static int cxdtv_dtv_open(void *, int); 109 static void cxdtv_dtv_close(void *); 110 static int cxdtv_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 111 static fe_status_t cxdtv_dtv_get_status(void *); 112 static uint16_t cxdtv_dtv_get_signal_strength(void *); 113 static uint16_t cxdtv_dtv_get_snr(void *); 114 static int cxdtv_dtv_start_transfer(void *, 115 void (*)(void *, const struct dtv_payload *), void *); 116 static int cxdtv_dtv_stop_transfer(void *); 117 118 static const struct dtv_hw_if cxdtv_dtv_if = { 119 .get_devinfo = cxdtv_dtv_get_devinfo, 120 .open = cxdtv_dtv_open, 121 .close = cxdtv_dtv_close, 122 .set_tuner = cxdtv_dtv_set_tuner, 123 .get_status = cxdtv_dtv_get_status, 124 .get_signal_strength = cxdtv_dtv_get_signal_strength, 125 .get_snr = cxdtv_dtv_get_snr, 126 .start_transfer = cxdtv_dtv_start_transfer, 127 .stop_transfer = cxdtv_dtv_stop_transfer, 128 }; 129 130 const struct i2c_bitbang_ops cxdtv_i2cbb_ops = { 131 cxdtv_i2cbb_set_bits, 132 cxdtv_i2cbb_set_dir, 133 cxdtv_i2cbb_read_bits, 134 { CXDTV_I2C_C_DATACONTROL_SDA, CXDTV_I2C_C_DATACONTROL_SCL, 0, 0 } 135 }; 136 137 /* Maybe make this dynamically allocated. */ 138 static struct cxdtv_sram_ch cxdtv_sram_chs[] = { 139 [CXDTV_SRAM_CH_MPEG] = { 140 .csc_cmds = 0x180200, /* CMDS for ch. 28 */ 141 .csc_iq = 0x180340, /* after last CMDS */ 142 .csc_iqsz = 0x40, /* 16 dwords */ 143 .csc_cdt = 0x180380, /* after iq */ 144 .csc_cdtsz = 0x40, /* cluster discriptor space */ 145 .csc_fifo = 0x180400, /* after cdt */ 146 .csc_fifosz = 0x001C00, /* let's just align this up */ 147 .csc_risc = 0x182000, /* after fifo */ 148 .csc_riscsz = 0x6000, /* room for dma programs */ 149 .csc_ptr1 = CXDTV_DMA28_PTR1, 150 .csc_ptr2 = CXDTV_DMA28_PTR2, 151 .csc_cnt1 = CXDTV_DMA28_CNT1, 152 .csc_cnt2 = CXDTV_DMA28_CNT2, 153 }, 154 }; 155 156 CFATTACH_DECL2_NEW(cxdtv, sizeof(struct cxdtv_softc), 157 cxdtv_match, cxdtv_attach, cxdtv_detach, NULL, 158 cxdtv_rescan, cxdtv_childdet); 159 160 static int 161 cxdtv_match(device_t parent, cfdata_t match, void *aux) 162 { 163 const struct pci_attach_args *pa; 164 pcireg_t reg; 165 166 pa = aux; 167 168 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 169 return 0; 170 171 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX2388XMPEG) 172 return 0; 173 174 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 175 if (cxdtv_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)) == NULL) 176 return 0; 177 178 return 1; 179 } 180 181 static void 182 cxdtv_attach(device_t parent, device_t self, void *aux) 183 { 184 struct cxdtv_softc *sc; 185 const struct pci_attach_args *pa = aux; 186 pci_intr_handle_t ih; 187 pcireg_t reg; 188 const char *intrstr; 189 struct i2cbus_attach_args iba; 190 char intrbuf[PCI_INTRSTR_LEN]; 191 192 sc = device_private(self); 193 194 sc->sc_dev = self; 195 sc->sc_pc = pa->pa_pc; 196 197 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 198 199 sc->sc_vendor = PCI_VENDOR(reg); 200 sc->sc_product = PCI_PRODUCT(reg); 201 202 sc->sc_board = cxdtv_board_lookup(sc->sc_vendor, sc->sc_product); 203 KASSERT(sc->sc_board != NULL); 204 205 pci_aprint_devinfo(pa, NULL); 206 207 if (pci_mapreg_map(pa, CXDTV_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 208 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 209 aprint_error_dev(self, "couldn't map memory space\n"); 210 return; 211 } 212 213 sc->sc_dmat = pa->pa_dmat; 214 215 if (pci_intr_map(pa, &ih)) { 216 aprint_error_dev(self, "couldn't map interrupt\n"); 217 return; 218 } 219 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 220 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_VM, cxdtv_intr, 221 sc, device_xname(self)); 222 if (sc->sc_ih == NULL) { 223 aprint_error_dev(self, "couldn't establish interrupt"); 224 if (intrstr != NULL) 225 aprint_error(" at %s", intrstr); 226 aprint_error("\n"); 227 return; 228 } 229 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 230 231 /* set master */ 232 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 233 reg |= PCI_COMMAND_MASTER_ENABLE; 234 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 235 236 mutex_init(&sc->sc_i2c_buslock, MUTEX_DRIVER, IPL_NONE); 237 sc->sc_i2c.ic_cookie = sc; 238 sc->sc_i2c.ic_exec = NULL; 239 sc->sc_i2c.ic_acquire_bus = cxdtv_iic_acquire_bus; 240 sc->sc_i2c.ic_release_bus = cxdtv_iic_release_bus; 241 sc->sc_i2c.ic_send_start = cxdtv_iic_send_start; 242 sc->sc_i2c.ic_send_stop = cxdtv_iic_send_stop; 243 sc->sc_i2c.ic_initiate_xfer = cxdtv_iic_initiate_xfer; 244 sc->sc_i2c.ic_read_byte = cxdtv_iic_read_byte; 245 sc->sc_i2c.ic_write_byte = cxdtv_iic_write_byte; 246 247 #if notyet 248 /* enable i2c compatible software mode */ 249 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, 250 CXDTV_I2C_C_DATACONTROL); 251 val = CXDTV_I2C_C_DATACONTROL_SCL | CXDTV_I2C_C_DATACONTROL_SDA; 252 bus_space_write_4(sc->sc_memt, sc->sc_memh, 253 CXDTV_I2C_C_DATACONTROL, val); 254 #endif 255 256 cxdtv_mpeg_attach(sc); 257 258 /* attach other devices to iic(4) */ 259 memset(&iba, 0, sizeof(iba)); 260 iba.iba_tag = &sc->sc_i2c; 261 config_found_ia(self, "i2cbus", &iba, iicbus_print); 262 263 if (!pmf_device_register(self, NULL, cxdtv_resume)) 264 aprint_error_dev(self, "couldn't establish power handler\n"); 265 266 return; 267 } 268 269 static int 270 cxdtv_detach(device_t self, int flags) 271 { 272 struct cxdtv_softc *sc = device_private(self); 273 int error; 274 275 error = cxdtv_mpeg_detach(sc, flags); 276 if (error) 277 return error; 278 279 if (sc->sc_ih) 280 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 281 282 if (sc->sc_mems) 283 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 284 285 mutex_destroy(&sc->sc_i2c_buslock); 286 287 return 0; 288 } 289 290 static int 291 cxdtv_rescan(device_t self, const char *ifattr, const int *locs) 292 { 293 struct cxdtv_softc *sc = device_private(self); 294 struct dtv_attach_args daa; 295 296 daa.hw = &cxdtv_dtv_if; 297 daa.priv = sc; 298 299 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 300 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", 301 &daa, dtv_print); 302 303 return 0; 304 } 305 306 static void 307 cxdtv_childdet(device_t self, device_t child) 308 { 309 struct cxdtv_softc *sc = device_private(self); 310 311 if (child == sc->sc_dtvdev) 312 sc->sc_dtvdev = NULL; 313 } 314 315 static bool 316 cxdtv_resume(device_t dv, const pmf_qual_t *qual) 317 { 318 /* XXX revisit */ 319 320 aprint_debug_dev(dv, "%s\n", __func__); 321 322 return true; 323 } 324 325 static int 326 cxdtv_intr(void *intarg) 327 { 328 struct cxdtv_softc *sc = intarg; 329 uint32_t val; 330 331 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MSTAT); 332 if (val == 0) { 333 return 0; /* not ours */ 334 } 335 336 if (val & CXT_PI_TS_INT) { 337 cxdtv_mpeg_intr(sc); 338 } 339 340 if (val & ~CXT_PI_TS_INT) { 341 device_printf(sc->sc_dev, "%s, %08x\n", __func__, val); 342 } 343 344 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, val); 345 346 return 1; 347 } 348 349 /* I2C interface */ 350 351 static void 352 cxdtv_i2cbb_set_bits(void *cookie, uint32_t bits) 353 { 354 struct cxdtv_softc *sc = cookie; 355 356 bus_space_write_4(sc->sc_memt, sc->sc_memh, 357 CXDTV_I2C_C_DATACONTROL, bits); 358 (void)bus_space_read_4(sc->sc_memt, sc->sc_memh, 359 CXDTV_I2C_C_DATACONTROL); 360 361 return; 362 } 363 364 static void 365 cxdtv_i2cbb_set_dir(void *cookie, uint32_t bits) 366 { 367 return; 368 } 369 370 static uint32_t 371 cxdtv_i2cbb_read_bits(void *cookie) 372 { 373 struct cxdtv_softc *sc = cookie; 374 uint32_t value; 375 376 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 377 CXDTV_I2C_C_DATACONTROL); 378 379 return value; 380 } 381 382 static int 383 cxdtv_iic_acquire_bus(void *cookie, int flags) 384 { 385 struct cxdtv_softc *sc = cookie; 386 387 mutex_enter(&sc->sc_i2c_buslock); 388 389 return 0; 390 } 391 392 static void 393 cxdtv_iic_release_bus(void *cookie, int flags) 394 { 395 struct cxdtv_softc *sc = cookie; 396 397 mutex_exit(&sc->sc_i2c_buslock); 398 399 return; 400 } 401 402 static int 403 cxdtv_iic_send_start(void *cookie, int flags) 404 { 405 return i2c_bitbang_send_start(cookie, flags, &cxdtv_i2cbb_ops); 406 } 407 408 static int 409 cxdtv_iic_send_stop(void *cookie, int flags) 410 { 411 return i2c_bitbang_send_stop(cookie, flags, &cxdtv_i2cbb_ops); 412 } 413 414 static int 415 cxdtv_iic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 416 { 417 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &cxdtv_i2cbb_ops); 418 } 419 420 static int 421 cxdtv_iic_read_byte(void *cookie, uint8_t *data, int flags) 422 { 423 return i2c_bitbang_read_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 424 } 425 426 static int 427 cxdtv_iic_write_byte(void *cookie, uint8_t data, int flags) 428 { 429 return i2c_bitbang_write_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 430 } 431 432 int 433 cxdtv_mpeg_attach(struct cxdtv_softc *sc) 434 { 435 struct cxdtv_sram_ch *ch; 436 437 CX_DPRINTF(("cxdtv_mpeg_attach\n")); 438 439 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 440 441 sc->sc_riscbufsz = ch->csc_riscsz; 442 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 443 444 aprint_debug_dev(sc->sc_dev, "attaching frontend...\n"); 445 446 switch(sc->sc_vendor) { 447 case PCI_VENDOR_ATI: 448 cxdtv_card_init_hdtvwonder(sc); 449 break; 450 case PCI_VENDOR_PCHDTV: 451 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 452 cxdtv_card_init_hd5500(sc); 453 } 454 break; 455 } 456 457 KASSERT(sc->sc_tuner == NULL); 458 KASSERT(sc->sc_demod == NULL); 459 460 switch(sc->sc_board->cb_demod) { 461 case CXDTV_DEMOD_NXT2004: 462 sc->sc_demod = nxt2k_open(sc->sc_dev, &sc->sc_i2c, 0x0a, 0); 463 break; 464 case CXDTV_DEMOD_LG3303: 465 sc->sc_demod = lg3303_open(sc->sc_dev, &sc->sc_i2c, 0x59, 466 LG3303_CFG_SERIAL_INPUT); 467 break; 468 default: 469 break; 470 } 471 472 switch(sc->sc_board->cb_tuner) { 473 case CXDTV_TUNER_PLL: 474 if (sc->sc_vendor == PCI_VENDOR_ATI) 475 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tuv1236d_pll); 476 if (sc->sc_vendor == PCI_VENDOR_PCHDTV) 477 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tdvs_h06xf_pll); 478 break; 479 default: 480 break; 481 } 482 483 KASSERT(sc->sc_tuner != NULL); 484 KASSERT(sc->sc_demod != NULL); 485 486 cxdtv_rescan(sc->sc_dev, NULL, NULL); 487 488 return (sc->sc_dtvdev != NULL); 489 } 490 491 int 492 cxdtv_mpeg_detach(struct cxdtv_softc *sc, int flags) 493 { 494 int error = 0; 495 496 if (sc->sc_dtvdev) { 497 error = config_detach(sc->sc_dtvdev, flags); 498 if (error) 499 return error; 500 } 501 502 if (sc->sc_demod) { 503 switch (sc->sc_board->cb_demod) { 504 case CXDTV_DEMOD_NXT2004: 505 nxt2k_close(sc->sc_demod); 506 break; 507 case CXDTV_DEMOD_LG3303: 508 lg3303_close(sc->sc_demod); 509 break; 510 default: 511 break; 512 } 513 sc->sc_demod = NULL; 514 } 515 if (sc->sc_tuner) { 516 switch (sc->sc_board->cb_tuner) { 517 case CXDTV_TUNER_PLL: 518 tvpll_close(sc->sc_tuner); 519 break; 520 default: 521 break; 522 } 523 sc->sc_tuner = NULL; 524 } 525 526 if (sc->sc_riscbuf) { 527 kmem_free(sc->sc_riscbuf, sc->sc_riscbufsz); 528 sc->sc_riscbuf = NULL; 529 sc->sc_riscbufsz = 0; 530 } 531 532 return error; 533 } 534 535 static void 536 cxdtv_dtv_get_devinfo(void *priv, struct dvb_frontend_info *info) 537 { 538 memset(info, 0, sizeof(*info)); 539 strlcpy(info->name, "CX23880", sizeof(info->name)); 540 info->type = FE_ATSC; 541 info->frequency_min = 54000000; 542 info->frequency_max = 858000000; 543 info->frequency_stepsize = 62500; 544 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 545 } 546 547 static int 548 cxdtv_dtv_open(void *priv, int flags) 549 { 550 struct cxdtv_softc *sc = priv; 551 552 KASSERT(sc->sc_tsbuf == NULL); 553 554 cxdtv_mpeg_reset(sc); 555 556 /* allocate two alternating DMA areas for MPEG TS packets */ 557 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 558 559 if (sc->sc_tsbuf == NULL) 560 return ENOMEM; 561 562 return 0; 563 } 564 565 static void 566 cxdtv_dtv_close(void *priv) 567 { 568 struct cxdtv_softc *sc = priv; 569 570 cxdtv_dtv_stop_transfer(sc); 571 572 if (sc->sc_tsbuf != NULL) { 573 cxdtv_mpeg_free(sc, sc->sc_tsbuf); 574 sc->sc_tsbuf = NULL; 575 } 576 } 577 578 static int 579 cxdtv_dtv_set_tuner(void *priv, const struct dvb_frontend_parameters *params) 580 { 581 struct cxdtv_softc *sc = priv; 582 int error = -1; 583 584 switch(sc->sc_board->cb_tuner) { 585 case CXDTV_TUNER_PLL: 586 error = tvpll_tune_dtv(sc->sc_tuner, params); 587 } 588 if (error) 589 goto bad; 590 591 switch(sc->sc_board->cb_demod) { 592 case CXDTV_DEMOD_NXT2004: 593 error = nxt2k_set_modulation(sc->sc_demod, params->u.vsb.modulation); 594 break; 595 case CXDTV_DEMOD_LG3303: 596 error = lg3303_set_modulation(sc->sc_demod, params->u.vsb.modulation); 597 break; 598 default: 599 break; 600 } 601 602 bad: 603 return error; 604 } 605 606 static fe_status_t 607 cxdtv_dtv_get_status(void *priv) 608 { 609 struct cxdtv_softc *sc = priv; 610 611 switch(sc->sc_board->cb_demod) { 612 case CXDTV_DEMOD_NXT2004: 613 return nxt2k_get_dtv_status(sc->sc_demod); 614 case CXDTV_DEMOD_LG3303: 615 return lg3303_get_dtv_status(sc->sc_demod); 616 default: 617 return 0; 618 } 619 } 620 621 static uint16_t 622 cxdtv_dtv_get_signal_strength(void *priv) 623 { 624 struct cxdtv_softc *sc = priv; 625 626 switch(sc->sc_board->cb_demod) { 627 case CXDTV_DEMOD_NXT2004: 628 return 0; /* TODO */ 629 case CXDTV_DEMOD_LG3303: 630 return lg3303_get_signal_strength(sc->sc_demod); 631 } 632 633 return 0; 634 } 635 636 static uint16_t 637 cxdtv_dtv_get_snr(void *priv) 638 { 639 struct cxdtv_softc *sc = priv; 640 641 switch(sc->sc_board->cb_demod) { 642 case CXDTV_DEMOD_NXT2004: 643 return 0; /* TODO */ 644 case CXDTV_DEMOD_LG3303: 645 return lg3303_get_snr(sc->sc_demod); 646 } 647 648 return 0; 649 } 650 651 static int 652 cxdtv_dtv_start_transfer(void *priv, 653 void (*cb)(void *, const struct dtv_payload *), void *arg) 654 { 655 struct cxdtv_softc *sc = priv; 656 657 sc->sc_dtvsubmitcb = cb; 658 sc->sc_dtvsubmitarg = arg; 659 660 /* allocate two alternating DMA areas for MPEG TS packets */ 661 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 662 663 cxdtv_mpeg_trigger(sc, sc->sc_tsbuf); 664 665 return 0; 666 } 667 668 static int 669 cxdtv_dtv_stop_transfer(void *priv) 670 { 671 struct cxdtv_softc *sc = priv; 672 673 cxdtv_mpeg_halt(sc); 674 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 675 676 sc->sc_dtvsubmitcb = NULL; 677 sc->sc_dtvsubmitarg = NULL; 678 679 return 0; 680 } 681 682 int 683 cxdtv_mpeg_reset(struct cxdtv_softc *sc) 684 { 685 uint32_t v; 686 687 CX_DPRINTF(("cxdtv_mpeg_reset\n")); 688 689 v = (uint32_t)-1; 690 691 /* shutdown */ 692 /* hold RISC in reset */ 693 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 0); 694 /* disable FIFO and RISC */ 695 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 0); 696 /* mask off all interrupts */ 697 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 698 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 0); 699 700 /* clear interrupts */ 701 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, v); 702 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, v); 703 704 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 705 706 /* XXX magic */ 707 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_STHRSH, 0x0707); 708 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_DTHRSH, 0x0707); 709 710 /* reset external components*/ 711 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 0); 712 kpause("cxdtvrst", false, MAX(1, mstohz(1)), NULL); 713 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 1); 714 715 /* let error interrupts happen */ 716 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 717 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 718 v | 0x00fc00); /* XXX magic */ 719 720 return 0; 721 } 722 723 static int 724 cxdtv_risc_buffer(struct cxdtv_softc *sc, uint32_t bpl, uint32_t lines) 725 { 726 uint32_t *rm; 727 uint32_t size; 728 729 CX_DPRINTF(("cxdtv_risc_buffer: bpl=0x%x\n", bpl)); 730 731 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 732 size += 2; 733 734 device_printf(sc->sc_dev, "%s: est. inst. %d\n", __func__, size); 735 736 size *= 8; 737 device_printf(sc->sc_dev, "%s: est. qword %d\n", __func__, size); 738 739 if (sc->sc_riscbuf == NULL) { 740 device_printf(sc->sc_dev, "not enough memory for RISC\n"); 741 return ENOMEM; 742 } 743 744 rm = (uint32_t *)sc->sc_riscbuf; 745 cxdtv_risc_field(sc, rm, bpl); 746 747 return 0; 748 } 749 750 static int 751 cxdtv_risc_field(struct cxdtv_softc *sc, uint32_t *rm, uint32_t bpl) 752 { 753 struct cxdtv_dma *p; 754 755 CX_DPRINTF(("cxdtv_risc_field: bpl=0x%x\n", bpl)); 756 757 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 758 continue; 759 if (p == NULL) { 760 device_printf(sc->sc_dev, "cxdtv_risc_field: bad addr %p\n", 761 sc->sc_tsbuf); 762 return ENOENT; 763 } 764 765 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 766 767 rm = sc->sc_riscbuf; 768 769 /* htole32 will be done when program is copied to chip SRAM */ 770 771 /* XXX */ 772 *(rm++) = (CX_RISC_SYNC|0); 773 774 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 775 *(rm++) = (DMAADDR(p) + 0 * bpl); 776 777 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 778 *(rm++) = (DMAADDR(p) + 1 * bpl); 779 780 *(rm++) = (CX_RISC_JUMP|1); 781 *(rm++) = (cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG].csc_risc + 4); 782 783 return 0; 784 } 785 786 static int 787 cxdtv_sram_ch_setup(struct cxdtv_softc *sc, struct cxdtv_sram_ch *csc, 788 uint32_t bpl) 789 { 790 unsigned int i, lines; 791 uint32_t cdt; 792 793 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 794 795 /* XXX why round? */ 796 bpl = (bpl + 7) & ~7; 797 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 798 cdt = csc->csc_cdt; 799 lines = csc->csc_fifosz / bpl; 800 device_printf(sc->sc_dev, "%s %d lines\n", __func__, lines); 801 802 /* fill in CDT */ 803 for (i = 0; i < lines; i++) { 804 CX_DPRINTF(("CDT ent %08x, %08x\n", cdt + (16 * i), 805 csc->csc_fifo + (bpl * i))); 806 bus_space_write_4(sc->sc_memt, sc->sc_memh, 807 cdt + (16 * i), 808 csc->csc_fifo + (bpl * i)); 809 } 810 811 /* copy DMA program */ 812 813 /* converts program to little endian as it goes into SRAM */ 814 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 815 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 816 817 /* fill in CMDS */ 818 bus_space_write_4(sc->sc_memt, sc->sc_memh, 819 csc->csc_cmds + CX_CMDS_O_IRPC, csc->csc_risc); 820 821 bus_space_write_4(sc->sc_memt, sc->sc_memh, 822 csc->csc_cmds + CX_CMDS_O_CDTB, csc->csc_cdt); 823 bus_space_write_4(sc->sc_memt, sc->sc_memh, 824 csc->csc_cmds + CX_CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 825 826 bus_space_write_4(sc->sc_memt, sc->sc_memh, 827 csc->csc_cmds + CX_CMDS_O_IQB, csc->csc_iq); 828 bus_space_write_4(sc->sc_memt, sc->sc_memh, 829 csc->csc_cmds + CX_CMDS_O_IQS, 830 CX_CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 831 832 /* zero rest of CMDS */ 833 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x14, 0, 0x2c/4); 834 835 bus_space_write_4(sc->sc_memt, sc->sc_memh, 836 csc->csc_cnt1, (bpl >> 3) - 1); 837 838 bus_space_write_4(sc->sc_memt, sc->sc_memh, 839 csc->csc_ptr2, cdt); 840 bus_space_write_4(sc->sc_memt, sc->sc_memh, 841 csc->csc_cnt2, (lines * 16) >> 3); 842 843 return 0; 844 } 845 846 int 847 cxdtv_mpeg_trigger(struct cxdtv_softc *sc, void *buf) 848 { 849 struct cxdtv_dma *p; 850 struct cxdtv_sram_ch *ch; 851 uint32_t v; 852 853 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 854 855 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 856 continue; 857 if (p == NULL) { 858 device_printf(sc->sc_dev, "cxdtv_mpeg_trigger: bad addr %p\n", 859 buf); 860 return ENOENT; 861 } 862 863 CX_DPRINTF(("cxdtv_mpeg_trigger: buf=%p\n", buf)); 864 865 cxdtv_risc_buffer(sc, CXDTV_TS_PKTSIZE, 1); 866 cxdtv_sram_ch_setup(sc, ch, CXDTV_TS_PKTSIZE); 867 868 /* software reset */ 869 870 switch(sc->sc_vendor) { 871 case PCI_VENDOR_ATI: 872 /* both ATI boards with DTV are the same */ 873 bus_space_write_4(sc->sc_memt, sc->sc_memh, 874 CXDTV_TS_GEN_CONTROL, IPB_SW_RST); 875 delay(100); 876 /* parallel MPEG port */ 877 bus_space_write_4(sc->sc_memt, sc->sc_memh, 878 CXDTV_PINMUX_IO, MPEG_PAR_EN); 879 break; 880 case PCI_VENDOR_PCHDTV: 881 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 882 bus_space_write_4(sc->sc_memt, sc->sc_memh, 883 CXDTV_TS_GEN_CONTROL, IPB_SW_RST|IPB_SMODE); 884 delay(100); 885 bus_space_write_4(sc->sc_memt, sc->sc_memh, 886 CXDTV_PINMUX_IO, 0x00); /* serial MPEG port */ 887 /* byte-width start-of-packet */ 888 bus_space_write_4(sc->sc_memt, sc->sc_memh, 889 CXDTV_HW_SOP_CONTROL, 890 0x47 << 16 | 188 << 4 | 1); 891 bus_space_write_4(sc->sc_memt, sc->sc_memh, 892 CXDTV_TS_SOP_STATUS, IPB_SOP_BYTEWIDE); 893 /* serial MPEG port on HD5500 */ 894 bus_space_write_4(sc->sc_memt, sc->sc_memh, 895 CXDTV_TS_GEN_CONTROL, IPB_SMODE); 896 } 897 break; 898 default: 899 break; 900 } 901 902 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_LNGTH, 903 CXDTV_TS_PKTSIZE); 904 905 /* Configure for standard MPEG TS, 1 good packet to sync */ 906 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_HW_SOP_CONTROL, 907 0x47 << 16 | 188 << 4 | 1); 908 909 /* zero counter */ 910 bus_space_write_4(sc->sc_memt, sc->sc_memh, 911 CXDTV_TS_GP_CNT_CNTRL, 0x03); 912 913 /* enable bad packet interrupt */ 914 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_BD_PKT_STATUS, 915 0x1000); 916 917 /* enable overflow counter */ 918 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_FIFO_OVFL_STAT, 919 0x1000); 920 921 /* unmask TS interrupt */ 922 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 923 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 924 v | CXT_PI_TS_INT); 925 926 /* unmask all TS interrupts */ 927 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 928 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 929 v | 0x1f1011); 930 931 /* enable RISC DMA engine */ 932 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2); 933 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 934 v | CXDTV_DEV_CNTRL2_RUN_RISC); 935 936 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 937 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 938 v | CXDTV_TS_RISC_EN | CXDTV_TS_FIFO_EN); 939 940 return 0; 941 } 942 943 int 944 cxdtv_mpeg_halt(struct cxdtv_softc *sc) 945 { 946 uint32_t v; 947 948 CX_DPRINTF(("cxdtv_mpeg_halt\n")); 949 950 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 951 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 952 v & ~(CXDTV_TS_RISC_EN|CXDTV_TS_FIFO_EN)); 953 954 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 955 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 956 v & ~CXT_PI_TS_INT); 957 958 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 959 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 960 v & ~0x1f1011); 961 962 return 0; 963 } 964 965 int 966 cxdtv_mpeg_intr(struct cxdtv_softc *sc) 967 { 968 struct dtv_payload payload; 969 uint32_t s, m; 970 971 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT); 972 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 973 if ((s & m) == 0) 974 return 0; 975 976 if ( (s & ~CXDTV_TS_RISCI) != 0 ) 977 device_printf(sc->sc_dev, "unexpected TS IS %08x\n", s); 978 979 if (sc->sc_dtvsubmitcb == NULL) 980 goto done; 981 982 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 983 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 984 0, CXDTV_TS_PKTSIZE, 985 BUS_DMASYNC_POSTREAD); 986 payload.data = KERNADDR(sc->sc_dma); 987 payload.size = CXDTV_TS_PKTSIZE; 988 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 989 } 990 991 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 992 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 993 CXDTV_TS_PKTSIZE, CXDTV_TS_PKTSIZE, 994 BUS_DMASYNC_POSTREAD); 995 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CXDTV_TS_PKTSIZE; 996 payload.size = CXDTV_TS_PKTSIZE; 997 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 998 } 999 1000 done: 1001 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, s); 1002 1003 return 1; 1004 } 1005 1006 static int 1007 cxdtv_allocmem(struct cxdtv_softc *sc, size_t size, size_t align, 1008 struct cxdtv_dma *p) 1009 { 1010 int err; 1011 1012 p->size = size; 1013 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 1014 p->segs, __arraycount(p->segs), 1015 &p->nsegs, BUS_DMA_NOWAIT); 1016 if (err) 1017 return err; 1018 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 1019 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1020 if (err) 1021 goto free; 1022 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 1023 BUS_DMA_NOWAIT, &p->map); 1024 if (err) 1025 goto unmap; 1026 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 1027 BUS_DMA_NOWAIT); 1028 if (err) 1029 goto destroy; 1030 1031 return 0; 1032 1033 destroy: 1034 bus_dmamap_destroy(sc->sc_dmat, p->map); 1035 unmap: 1036 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1037 free: 1038 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1039 1040 return err; 1041 } 1042 1043 static int 1044 cxdtv_freemem(struct cxdtv_softc *sc, struct cxdtv_dma *p) 1045 { 1046 1047 bus_dmamap_unload(sc->sc_dmat, p->map); 1048 bus_dmamap_destroy(sc->sc_dmat, p->map); 1049 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1050 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1051 1052 return 0; 1053 } 1054 1055 void * 1056 cxdtv_mpeg_malloc(struct cxdtv_softc *sc, size_t size) 1057 { 1058 struct cxdtv_dma *p; 1059 int err; 1060 1061 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1062 err = cxdtv_allocmem(sc, size, 16, p); 1063 if (err) { 1064 kmem_free(p, sizeof(*p)); 1065 device_printf(sc->sc_dev, "not enough memory\n"); 1066 return NULL; 1067 } 1068 1069 p->next = sc->sc_dma; 1070 sc->sc_dma = p; 1071 1072 return KERNADDR(p); 1073 } 1074 1075 static void 1076 cxdtv_mpeg_free(struct cxdtv_softc *sc, void *addr) 1077 { 1078 struct cxdtv_dma *p; 1079 struct cxdtv_dma **pp; 1080 1081 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) { 1082 if (KERNADDR(p) == addr) { 1083 cxdtv_freemem(sc, p); 1084 *pp = p->next; 1085 kmem_free(p, sizeof(*p)); 1086 return; 1087 } 1088 } 1089 1090 device_printf(sc->sc_dev, "%p is already free\n", addr); 1091 1092 return; 1093 } 1094 1095 1096 /* ATI HDTV Wonder */ 1097 static void 1098 cxdtv_card_init_hdtvwonder(struct cxdtv_softc *sc) 1099 { 1100 int i, x; 1101 i2c_addr_t na; 1102 uint8_t nb[5][2] = { 1103 {0x10, 0x12}, {0x13, 0x04}, {0x16, 0x00}, 1104 {0x14, 0x04}, {0x17, 0x00} 1105 }; 1106 1107 /* prepare TUV1236D/TU1236F NIM */ 1108 1109 na = 0x0a; /* Nxt2004 address */ 1110 x = 0; 1111 1112 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 1113 1114 for(i = 0; i < 5; i++) 1115 x |= iic_exec(&sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, na, 1116 nb[i], 2, NULL, 0, I2C_F_POLL); 1117 1118 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 1119 1120 if (x) 1121 aprint_error_dev(sc->sc_dev, "HDTV Wonder tuner init failed"); 1122 } 1123 1124 /* pcHDTV HD5500 */ 1125 #define cxdtv_write_field(_mask, _shift, _value) \ 1126 (((_value) & (_mask)) << (_shift)) 1127 1128 static void 1129 cxdtv_write_gpio(struct cxdtv_softc *sc, uint32_t mask, uint32_t value) 1130 { 1131 uint32_t v = 0; 1132 v |= cxdtv_write_field(0xff, 16, mask); 1133 v |= cxdtv_write_field(0xff, 8, mask); 1134 v |= cxdtv_write_field(0xff, 0, (mask & value)); 1135 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_GP0_IO, v); 1136 } 1137 1138 static void 1139 cxdtv_card_init_hd5500(struct cxdtv_softc *sc) 1140 { 1141 /* hardware (demod) reset */ 1142 cxdtv_write_gpio(sc, 1, 0); 1143 delay(100000); 1144 cxdtv_write_gpio(sc, 1, 1); 1145 delay(200000); 1146 } 1147 1148 MODULE(MODULE_CLASS_DRIVER, cxdtv, "tvpll,nxt2k,lg3303,pci"); 1149 1150 #ifdef _MODULE 1151 #include "ioconf.c" 1152 #endif 1153 1154 static int 1155 cxdtv_modcmd(modcmd_t cmd, void *opaque) 1156 { 1157 switch (cmd) { 1158 case MODULE_CMD_INIT: 1159 #ifdef _MODULE 1160 return config_init_component(cfdriver_ioconf_cxdtv, 1161 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1162 #else 1163 return 0; 1164 #endif 1165 case MODULE_CMD_FINI: 1166 #ifdef _MODULE 1167 return config_fini_component(cfdriver_ioconf_cxdtv, 1168 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1169 #else 1170 return 0; 1171 #endif 1172 default: 1173 return ENOTTY; 1174 } 1175 } 1176