1 /* $NetBSD: cxdtv.c,v 1.15 2017/06/01 02:45:11 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.15 2017/06/01 02:45:11 chs Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/proc.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_bitbang.h> 46 47 #include <dev/i2c/tvpllvar.h> 48 #include <dev/i2c/tvpll_tuners.h> 49 50 #include <dev/i2c/nxt2kvar.h> 51 #include <dev/i2c/lg3303var.h> 52 53 #include <dev/dtv/dtvif.h> 54 55 #include <dev/pci/cxdtvreg.h> 56 #include <dev/pci/cxdtvvar.h> 57 #include <dev/pci/cxdtv_boards.h> 58 59 #define CXDTV_MMBASE 0x10 60 61 #define CXDTV_SRAM_CH_MPEG 0 62 #define CXDTV_TS_PKTSIZE (188 * 8) 63 64 static int cxdtv_match(device_t, cfdata_t, void *); 65 static void cxdtv_attach(device_t, device_t, void *); 66 static int cxdtv_detach(device_t, int); 67 static int cxdtv_rescan(device_t, const char *, const int *); 68 static void cxdtv_childdet(device_t, device_t); 69 static int cxdtv_intr(void *); 70 71 static bool cxdtv_resume(device_t, const pmf_qual_t *); 72 73 static int cxdtv_iic_acquire_bus(void *, int); 74 static void cxdtv_iic_release_bus(void *, int); 75 static int cxdtv_iic_send_start(void *, int); 76 static int cxdtv_iic_send_stop(void *, int); 77 static int cxdtv_iic_initiate_xfer(void *, i2c_addr_t, int); 78 static int cxdtv_iic_read_byte(void *, uint8_t *, int); 79 static int cxdtv_iic_write_byte(void *, uint8_t, int); 80 81 static void cxdtv_i2cbb_set_bits(void *, uint32_t); 82 static void cxdtv_i2cbb_set_dir(void *, uint32_t); 83 static uint32_t cxdtv_i2cbb_read_bits(void *); 84 85 static int cxdtv_sram_ch_setup(struct cxdtv_softc *, 86 struct cxdtv_sram_ch *, uint32_t); 87 static int cxdtv_allocmem(struct cxdtv_softc *, size_t, size_t, 88 struct cxdtv_dma *); 89 static int cxdtv_freemem(struct cxdtv_softc *, struct cxdtv_dma *); 90 static int cxdtv_risc_buffer(struct cxdtv_softc *, uint32_t, uint32_t); 91 static int cxdtv_risc_field(struct cxdtv_softc *, uint32_t *, uint32_t); 92 93 static int cxdtv_mpeg_attach(struct cxdtv_softc *); 94 static int cxdtv_mpeg_detach(struct cxdtv_softc *, int flags); 95 static int cxdtv_mpeg_intr(struct cxdtv_softc *); 96 static int cxdtv_mpeg_reset(struct cxdtv_softc *); 97 98 static int cxdtv_mpeg_trigger(struct cxdtv_softc *, void *); 99 static int cxdtv_mpeg_halt(struct cxdtv_softc *); 100 static void * cxdtv_mpeg_malloc(struct cxdtv_softc *, size_t); 101 static void cxdtv_mpeg_free(struct cxdtv_softc *, void *); 102 103 static void cxdtv_card_init_hd5500(struct cxdtv_softc *); 104 static void cxdtv_card_init_hdtvwonder(struct cxdtv_softc *); 105 106 /* MPEG TS Port */ 107 static void cxdtv_dtv_get_devinfo(void *, struct dvb_frontend_info *); 108 static int cxdtv_dtv_open(void *, int); 109 static void cxdtv_dtv_close(void *); 110 static int cxdtv_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 111 static fe_status_t cxdtv_dtv_get_status(void *); 112 static uint16_t cxdtv_dtv_get_signal_strength(void *); 113 static uint16_t cxdtv_dtv_get_snr(void *); 114 static int cxdtv_dtv_start_transfer(void *, 115 void (*)(void *, const struct dtv_payload *), void *); 116 static int cxdtv_dtv_stop_transfer(void *); 117 118 static const struct dtv_hw_if cxdtv_dtv_if = { 119 .get_devinfo = cxdtv_dtv_get_devinfo, 120 .open = cxdtv_dtv_open, 121 .close = cxdtv_dtv_close, 122 .set_tuner = cxdtv_dtv_set_tuner, 123 .get_status = cxdtv_dtv_get_status, 124 .get_signal_strength = cxdtv_dtv_get_signal_strength, 125 .get_snr = cxdtv_dtv_get_snr, 126 .start_transfer = cxdtv_dtv_start_transfer, 127 .stop_transfer = cxdtv_dtv_stop_transfer, 128 }; 129 130 const struct i2c_bitbang_ops cxdtv_i2cbb_ops = { 131 cxdtv_i2cbb_set_bits, 132 cxdtv_i2cbb_set_dir, 133 cxdtv_i2cbb_read_bits, 134 { CXDTV_I2C_C_DATACONTROL_SDA, CXDTV_I2C_C_DATACONTROL_SCL, 0, 0 } 135 }; 136 137 /* Maybe make this dynamically allocated. */ 138 static struct cxdtv_sram_ch cxdtv_sram_chs[] = { 139 [CXDTV_SRAM_CH_MPEG] = { 140 .csc_cmds = 0x180200, /* CMDS for ch. 28 */ 141 .csc_iq = 0x180340, /* after last CMDS */ 142 .csc_iqsz = 0x40, /* 16 dwords */ 143 .csc_cdt = 0x180380, /* after iq */ 144 .csc_cdtsz = 0x40, /* cluster discriptor space */ 145 .csc_fifo = 0x180400, /* after cdt */ 146 .csc_fifosz = 0x001C00, /* let's just align this up */ 147 .csc_risc = 0x182000, /* after fifo */ 148 .csc_riscsz = 0x6000, /* room for dma programs */ 149 .csc_ptr1 = CXDTV_DMA28_PTR1, 150 .csc_ptr2 = CXDTV_DMA28_PTR2, 151 .csc_cnt1 = CXDTV_DMA28_CNT1, 152 .csc_cnt2 = CXDTV_DMA28_CNT2, 153 }, 154 }; 155 156 CFATTACH_DECL2_NEW(cxdtv, sizeof(struct cxdtv_softc), 157 cxdtv_match, cxdtv_attach, cxdtv_detach, NULL, 158 cxdtv_rescan, cxdtv_childdet); 159 160 static int 161 cxdtv_match(device_t parent, cfdata_t match, void *aux) 162 { 163 const struct pci_attach_args *pa; 164 pcireg_t reg; 165 166 pa = aux; 167 168 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 169 return 0; 170 171 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX2388XMPEG) 172 return 0; 173 174 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 175 if (cxdtv_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)) == NULL) 176 return 0; 177 178 return 1; 179 } 180 181 static void 182 cxdtv_attach(device_t parent, device_t self, void *aux) 183 { 184 struct cxdtv_softc *sc; 185 const struct pci_attach_args *pa = aux; 186 pci_intr_handle_t ih; 187 pcireg_t reg; 188 const char *intrstr; 189 struct i2cbus_attach_args iba; 190 char intrbuf[PCI_INTRSTR_LEN]; 191 192 sc = device_private(self); 193 194 sc->sc_dev = self; 195 sc->sc_pc = pa->pa_pc; 196 197 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 198 199 sc->sc_vendor = PCI_VENDOR(reg); 200 sc->sc_product = PCI_PRODUCT(reg); 201 202 sc->sc_board = cxdtv_board_lookup(sc->sc_vendor, sc->sc_product); 203 KASSERT(sc->sc_board != NULL); 204 205 pci_aprint_devinfo(pa, NULL); 206 207 if (pci_mapreg_map(pa, CXDTV_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 208 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 209 aprint_error_dev(self, "couldn't map memory space\n"); 210 return; 211 } 212 213 sc->sc_dmat = pa->pa_dmat; 214 215 if (pci_intr_map(pa, &ih)) { 216 aprint_error_dev(self, "couldn't map interrupt\n"); 217 return; 218 } 219 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 220 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM, cxdtv_intr, sc); 221 if (sc->sc_ih == NULL) { 222 aprint_error_dev(self, "couldn't establish interrupt"); 223 if (intrstr != NULL) 224 aprint_error(" at %s", intrstr); 225 aprint_error("\n"); 226 return; 227 } 228 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 229 230 /* set master */ 231 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 232 reg |= PCI_COMMAND_MASTER_ENABLE; 233 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 234 235 mutex_init(&sc->sc_i2c_buslock, MUTEX_DRIVER, IPL_NONE); 236 sc->sc_i2c.ic_cookie = sc; 237 sc->sc_i2c.ic_exec = NULL; 238 sc->sc_i2c.ic_acquire_bus = cxdtv_iic_acquire_bus; 239 sc->sc_i2c.ic_release_bus = cxdtv_iic_release_bus; 240 sc->sc_i2c.ic_send_start = cxdtv_iic_send_start; 241 sc->sc_i2c.ic_send_stop = cxdtv_iic_send_stop; 242 sc->sc_i2c.ic_initiate_xfer = cxdtv_iic_initiate_xfer; 243 sc->sc_i2c.ic_read_byte = cxdtv_iic_read_byte; 244 sc->sc_i2c.ic_write_byte = cxdtv_iic_write_byte; 245 246 #if notyet 247 /* enable i2c compatible software mode */ 248 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, 249 CXDTV_I2C_C_DATACONTROL); 250 val = CXDTV_I2C_C_DATACONTROL_SCL | CXDTV_I2C_C_DATACONTROL_SDA; 251 bus_space_write_4(sc->sc_memt, sc->sc_memh, 252 CXDTV_I2C_C_DATACONTROL, val); 253 #endif 254 255 cxdtv_mpeg_attach(sc); 256 257 /* attach other devices to iic(4) */ 258 memset(&iba, 0, sizeof(iba)); 259 iba.iba_tag = &sc->sc_i2c; 260 config_found_ia(self, "i2cbus", &iba, iicbus_print); 261 262 if (!pmf_device_register(self, NULL, cxdtv_resume)) 263 aprint_error_dev(self, "couldn't establish power handler\n"); 264 265 return; 266 } 267 268 static int 269 cxdtv_detach(device_t self, int flags) 270 { 271 struct cxdtv_softc *sc = device_private(self); 272 int error; 273 274 error = cxdtv_mpeg_detach(sc, flags); 275 if (error) 276 return error; 277 278 if (sc->sc_ih) 279 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 280 281 if (sc->sc_mems) 282 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 283 284 mutex_destroy(&sc->sc_i2c_buslock); 285 286 return 0; 287 } 288 289 static int 290 cxdtv_rescan(device_t self, const char *ifattr, const int *locs) 291 { 292 struct cxdtv_softc *sc = device_private(self); 293 struct dtv_attach_args daa; 294 295 daa.hw = &cxdtv_dtv_if; 296 daa.priv = sc; 297 298 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 299 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", 300 &daa, dtv_print); 301 302 return 0; 303 } 304 305 static void 306 cxdtv_childdet(device_t self, device_t child) 307 { 308 struct cxdtv_softc *sc = device_private(self); 309 310 if (child == sc->sc_dtvdev) 311 sc->sc_dtvdev = NULL; 312 } 313 314 static bool 315 cxdtv_resume(device_t dv, const pmf_qual_t *qual) 316 { 317 /* XXX revisit */ 318 319 aprint_debug_dev(dv, "%s\n", __func__); 320 321 return true; 322 } 323 324 static int 325 cxdtv_intr(void *intarg) 326 { 327 struct cxdtv_softc *sc = intarg; 328 uint32_t val; 329 330 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MSTAT); 331 if (val == 0) { 332 return 0; /* not ours */ 333 } 334 335 if (val & CXT_PI_TS_INT) { 336 cxdtv_mpeg_intr(sc); 337 } 338 339 if (val & ~CXT_PI_TS_INT) { 340 device_printf(sc->sc_dev, "%s, %08x\n", __func__, val); 341 } 342 343 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, val); 344 345 return 1; 346 } 347 348 /* I2C interface */ 349 350 static void 351 cxdtv_i2cbb_set_bits(void *cookie, uint32_t bits) 352 { 353 struct cxdtv_softc *sc = cookie; 354 355 bus_space_write_4(sc->sc_memt, sc->sc_memh, 356 CXDTV_I2C_C_DATACONTROL, bits); 357 (void)bus_space_read_4(sc->sc_memt, sc->sc_memh, 358 CXDTV_I2C_C_DATACONTROL); 359 360 return; 361 } 362 363 static void 364 cxdtv_i2cbb_set_dir(void *cookie, uint32_t bits) 365 { 366 return; 367 } 368 369 static uint32_t 370 cxdtv_i2cbb_read_bits(void *cookie) 371 { 372 struct cxdtv_softc *sc = cookie; 373 uint32_t value; 374 375 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 376 CXDTV_I2C_C_DATACONTROL); 377 378 return value; 379 } 380 381 static int 382 cxdtv_iic_acquire_bus(void *cookie, int flags) 383 { 384 struct cxdtv_softc *sc = cookie; 385 386 mutex_enter(&sc->sc_i2c_buslock); 387 388 return 0; 389 } 390 391 static void 392 cxdtv_iic_release_bus(void *cookie, int flags) 393 { 394 struct cxdtv_softc *sc = cookie; 395 396 mutex_exit(&sc->sc_i2c_buslock); 397 398 return; 399 } 400 401 static int 402 cxdtv_iic_send_start(void *cookie, int flags) 403 { 404 return i2c_bitbang_send_start(cookie, flags, &cxdtv_i2cbb_ops); 405 } 406 407 static int 408 cxdtv_iic_send_stop(void *cookie, int flags) 409 { 410 return i2c_bitbang_send_stop(cookie, flags, &cxdtv_i2cbb_ops); 411 } 412 413 static int 414 cxdtv_iic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 415 { 416 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &cxdtv_i2cbb_ops); 417 } 418 419 static int 420 cxdtv_iic_read_byte(void *cookie, uint8_t *data, int flags) 421 { 422 return i2c_bitbang_read_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 423 } 424 425 static int 426 cxdtv_iic_write_byte(void *cookie, uint8_t data, int flags) 427 { 428 return i2c_bitbang_write_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 429 } 430 431 int 432 cxdtv_mpeg_attach(struct cxdtv_softc *sc) 433 { 434 struct cxdtv_sram_ch *ch; 435 436 CX_DPRINTF(("cxdtv_mpeg_attach\n")); 437 438 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 439 440 sc->sc_riscbufsz = ch->csc_riscsz; 441 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 442 443 aprint_debug_dev(sc->sc_dev, "attaching frontend...\n"); 444 445 switch(sc->sc_vendor) { 446 case PCI_VENDOR_ATI: 447 cxdtv_card_init_hdtvwonder(sc); 448 break; 449 case PCI_VENDOR_PCHDTV: 450 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 451 cxdtv_card_init_hd5500(sc); 452 } 453 break; 454 } 455 456 KASSERT(sc->sc_tuner == NULL); 457 KASSERT(sc->sc_demod == NULL); 458 459 switch(sc->sc_board->cb_demod) { 460 case CXDTV_DEMOD_NXT2004: 461 sc->sc_demod = nxt2k_open(sc->sc_dev, &sc->sc_i2c, 0x0a, 0); 462 break; 463 case CXDTV_DEMOD_LG3303: 464 sc->sc_demod = lg3303_open(sc->sc_dev, &sc->sc_i2c, 0x59, 465 LG3303_CFG_SERIAL_INPUT); 466 break; 467 default: 468 break; 469 } 470 471 switch(sc->sc_board->cb_tuner) { 472 case CXDTV_TUNER_PLL: 473 if (sc->sc_vendor == PCI_VENDOR_ATI) 474 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tuv1236d_pll); 475 if (sc->sc_vendor == PCI_VENDOR_PCHDTV) 476 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tdvs_h06xf_pll); 477 break; 478 default: 479 break; 480 } 481 482 KASSERT(sc->sc_tuner != NULL); 483 KASSERT(sc->sc_demod != NULL); 484 485 cxdtv_rescan(sc->sc_dev, NULL, NULL); 486 487 return (sc->sc_dtvdev != NULL); 488 } 489 490 int 491 cxdtv_mpeg_detach(struct cxdtv_softc *sc, int flags) 492 { 493 int error = 0; 494 495 if (sc->sc_dtvdev) { 496 error = config_detach(sc->sc_dtvdev, flags); 497 if (error) 498 return error; 499 } 500 501 if (sc->sc_demod) { 502 switch (sc->sc_board->cb_demod) { 503 case CXDTV_DEMOD_NXT2004: 504 nxt2k_close(sc->sc_demod); 505 break; 506 case CXDTV_DEMOD_LG3303: 507 lg3303_close(sc->sc_demod); 508 break; 509 default: 510 break; 511 } 512 sc->sc_demod = NULL; 513 } 514 if (sc->sc_tuner) { 515 switch (sc->sc_board->cb_tuner) { 516 case CXDTV_TUNER_PLL: 517 tvpll_close(sc->sc_tuner); 518 break; 519 default: 520 break; 521 } 522 sc->sc_tuner = NULL; 523 } 524 525 if (sc->sc_riscbuf) { 526 kmem_free(sc->sc_riscbuf, sc->sc_riscbufsz); 527 sc->sc_riscbuf = NULL; 528 sc->sc_riscbufsz = 0; 529 } 530 531 return error; 532 } 533 534 static void 535 cxdtv_dtv_get_devinfo(void *priv, struct dvb_frontend_info *info) 536 { 537 memset(info, 0, sizeof(*info)); 538 strlcpy(info->name, "CX23880", sizeof(info->name)); 539 info->type = FE_ATSC; 540 info->frequency_min = 54000000; 541 info->frequency_max = 858000000; 542 info->frequency_stepsize = 62500; 543 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 544 } 545 546 static int 547 cxdtv_dtv_open(void *priv, int flags) 548 { 549 struct cxdtv_softc *sc = priv; 550 551 KASSERT(sc->sc_tsbuf == NULL); 552 553 cxdtv_mpeg_reset(sc); 554 555 /* allocate two alternating DMA areas for MPEG TS packets */ 556 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 557 558 if (sc->sc_tsbuf == NULL) 559 return ENOMEM; 560 561 return 0; 562 } 563 564 static void 565 cxdtv_dtv_close(void *priv) 566 { 567 struct cxdtv_softc *sc = priv; 568 569 cxdtv_dtv_stop_transfer(sc); 570 571 if (sc->sc_tsbuf != NULL) { 572 cxdtv_mpeg_free(sc, sc->sc_tsbuf); 573 sc->sc_tsbuf = NULL; 574 } 575 } 576 577 static int 578 cxdtv_dtv_set_tuner(void *priv, const struct dvb_frontend_parameters *params) 579 { 580 struct cxdtv_softc *sc = priv; 581 int error = -1; 582 583 switch(sc->sc_board->cb_tuner) { 584 case CXDTV_TUNER_PLL: 585 error = tvpll_tune_dtv(sc->sc_tuner, params); 586 } 587 if (error) 588 goto bad; 589 590 switch(sc->sc_board->cb_demod) { 591 case CXDTV_DEMOD_NXT2004: 592 error = nxt2k_set_modulation(sc->sc_demod, params->u.vsb.modulation); 593 break; 594 case CXDTV_DEMOD_LG3303: 595 error = lg3303_set_modulation(sc->sc_demod, params->u.vsb.modulation); 596 break; 597 default: 598 break; 599 } 600 601 bad: 602 return error; 603 } 604 605 static fe_status_t 606 cxdtv_dtv_get_status(void *priv) 607 { 608 struct cxdtv_softc *sc = priv; 609 610 switch(sc->sc_board->cb_demod) { 611 case CXDTV_DEMOD_NXT2004: 612 return nxt2k_get_dtv_status(sc->sc_demod); 613 case CXDTV_DEMOD_LG3303: 614 return lg3303_get_dtv_status(sc->sc_demod); 615 default: 616 return 0; 617 } 618 } 619 620 static uint16_t 621 cxdtv_dtv_get_signal_strength(void *priv) 622 { 623 struct cxdtv_softc *sc = priv; 624 625 switch(sc->sc_board->cb_demod) { 626 case CXDTV_DEMOD_NXT2004: 627 return 0; /* TODO */ 628 case CXDTV_DEMOD_LG3303: 629 return lg3303_get_signal_strength(sc->sc_demod); 630 } 631 632 return 0; 633 } 634 635 static uint16_t 636 cxdtv_dtv_get_snr(void *priv) 637 { 638 struct cxdtv_softc *sc = priv; 639 640 switch(sc->sc_board->cb_demod) { 641 case CXDTV_DEMOD_NXT2004: 642 return 0; /* TODO */ 643 case CXDTV_DEMOD_LG3303: 644 return lg3303_get_snr(sc->sc_demod); 645 } 646 647 return 0; 648 } 649 650 static int 651 cxdtv_dtv_start_transfer(void *priv, 652 void (*cb)(void *, const struct dtv_payload *), void *arg) 653 { 654 struct cxdtv_softc *sc = priv; 655 656 sc->sc_dtvsubmitcb = cb; 657 sc->sc_dtvsubmitarg = arg; 658 659 /* allocate two alternating DMA areas for MPEG TS packets */ 660 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 661 662 cxdtv_mpeg_trigger(sc, sc->sc_tsbuf); 663 664 return 0; 665 } 666 667 static int 668 cxdtv_dtv_stop_transfer(void *priv) 669 { 670 struct cxdtv_softc *sc = priv; 671 672 cxdtv_mpeg_halt(sc); 673 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 674 675 sc->sc_dtvsubmitcb = NULL; 676 sc->sc_dtvsubmitarg = NULL; 677 678 return 0; 679 } 680 681 int 682 cxdtv_mpeg_reset(struct cxdtv_softc *sc) 683 { 684 uint32_t v; 685 686 CX_DPRINTF(("cxdtv_mpeg_reset\n")); 687 688 v = (uint32_t)-1; 689 690 /* shutdown */ 691 /* hold RISC in reset */ 692 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 0); 693 /* disable FIFO and RISC */ 694 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 0); 695 /* mask off all interrupts */ 696 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 697 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 0); 698 699 /* clear interrupts */ 700 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, v); 701 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, v); 702 703 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 704 705 /* XXX magic */ 706 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_STHRSH, 0x0707); 707 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_DTHRSH, 0x0707); 708 709 /* reset external components*/ 710 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 0); 711 kpause("cxdtvrst", false, MAX(1, mstohz(1)), NULL); 712 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 1); 713 714 /* let error interrupts happen */ 715 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 716 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 717 v | 0x00fc00); /* XXX magic */ 718 719 return 0; 720 } 721 722 static int 723 cxdtv_risc_buffer(struct cxdtv_softc *sc, uint32_t bpl, uint32_t lines) 724 { 725 uint32_t *rm; 726 uint32_t size; 727 728 CX_DPRINTF(("cxdtv_risc_buffer: bpl=0x%x\n", bpl)); 729 730 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 731 size += 2; 732 733 device_printf(sc->sc_dev, "%s: est. inst. %d\n", __func__, size); 734 735 size *= 8; 736 device_printf(sc->sc_dev, "%s: est. qword %d\n", __func__, size); 737 738 if (sc->sc_riscbuf == NULL) { 739 device_printf(sc->sc_dev, "not enough memory for RISC\n"); 740 return ENOMEM; 741 } 742 743 rm = (uint32_t *)sc->sc_riscbuf; 744 cxdtv_risc_field(sc, rm, bpl); 745 746 return 0; 747 } 748 749 static int 750 cxdtv_risc_field(struct cxdtv_softc *sc, uint32_t *rm, uint32_t bpl) 751 { 752 struct cxdtv_dma *p; 753 754 CX_DPRINTF(("cxdtv_risc_field: bpl=0x%x\n", bpl)); 755 756 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 757 continue; 758 if (p == NULL) { 759 device_printf(sc->sc_dev, "cxdtv_risc_field: bad addr %p\n", 760 sc->sc_tsbuf); 761 return ENOENT; 762 } 763 764 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 765 766 rm = sc->sc_riscbuf; 767 768 /* htole32 will be done when program is copied to chip SRAM */ 769 770 /* XXX */ 771 *(rm++) = (CX_RISC_SYNC|0); 772 773 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 774 *(rm++) = (DMAADDR(p) + 0 * bpl); 775 776 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 777 *(rm++) = (DMAADDR(p) + 1 * bpl); 778 779 *(rm++) = (CX_RISC_JUMP|1); 780 *(rm++) = (cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG].csc_risc + 4); 781 782 return 0; 783 } 784 785 static int 786 cxdtv_sram_ch_setup(struct cxdtv_softc *sc, struct cxdtv_sram_ch *csc, 787 uint32_t bpl) 788 { 789 unsigned int i, lines; 790 uint32_t cdt; 791 792 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 793 794 /* XXX why round? */ 795 bpl = (bpl + 7) & ~7; 796 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 797 cdt = csc->csc_cdt; 798 lines = csc->csc_fifosz / bpl; 799 device_printf(sc->sc_dev, "%s %d lines\n", __func__, lines); 800 801 /* fill in CDT */ 802 for (i = 0; i < lines; i++) { 803 CX_DPRINTF(("CDT ent %08x, %08x\n", cdt + (16 * i), 804 csc->csc_fifo + (bpl * i))); 805 bus_space_write_4(sc->sc_memt, sc->sc_memh, 806 cdt + (16 * i), 807 csc->csc_fifo + (bpl * i)); 808 } 809 810 /* copy DMA program */ 811 812 /* converts program to little endian as it goes into SRAM */ 813 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 814 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 815 816 /* fill in CMDS */ 817 bus_space_write_4(sc->sc_memt, sc->sc_memh, 818 csc->csc_cmds + CX_CMDS_O_IRPC, csc->csc_risc); 819 820 bus_space_write_4(sc->sc_memt, sc->sc_memh, 821 csc->csc_cmds + CX_CMDS_O_CDTB, csc->csc_cdt); 822 bus_space_write_4(sc->sc_memt, sc->sc_memh, 823 csc->csc_cmds + CX_CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 824 825 bus_space_write_4(sc->sc_memt, sc->sc_memh, 826 csc->csc_cmds + CX_CMDS_O_IQB, csc->csc_iq); 827 bus_space_write_4(sc->sc_memt, sc->sc_memh, 828 csc->csc_cmds + CX_CMDS_O_IQS, 829 CX_CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 830 831 /* zero rest of CMDS */ 832 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x14, 0, 0x2c/4); 833 834 bus_space_write_4(sc->sc_memt, sc->sc_memh, 835 csc->csc_cnt1, (bpl >> 3) - 1); 836 837 bus_space_write_4(sc->sc_memt, sc->sc_memh, 838 csc->csc_ptr2, cdt); 839 bus_space_write_4(sc->sc_memt, sc->sc_memh, 840 csc->csc_cnt2, (lines * 16) >> 3); 841 842 return 0; 843 } 844 845 int 846 cxdtv_mpeg_trigger(struct cxdtv_softc *sc, void *buf) 847 { 848 struct cxdtv_dma *p; 849 struct cxdtv_sram_ch *ch; 850 uint32_t v; 851 852 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 853 854 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 855 continue; 856 if (p == NULL) { 857 device_printf(sc->sc_dev, "cxdtv_mpeg_trigger: bad addr %p\n", 858 buf); 859 return ENOENT; 860 } 861 862 CX_DPRINTF(("cxdtv_mpeg_trigger: buf=%p\n", buf)); 863 864 cxdtv_risc_buffer(sc, CXDTV_TS_PKTSIZE, 1); 865 cxdtv_sram_ch_setup(sc, ch, CXDTV_TS_PKTSIZE); 866 867 /* software reset */ 868 869 switch(sc->sc_vendor) { 870 case PCI_VENDOR_ATI: 871 /* both ATI boards with DTV are the same */ 872 bus_space_write_4(sc->sc_memt, sc->sc_memh, 873 CXDTV_TS_GEN_CONTROL, IPB_SW_RST); 874 delay(100); 875 /* parallel MPEG port */ 876 bus_space_write_4(sc->sc_memt, sc->sc_memh, 877 CXDTV_PINMUX_IO, MPEG_PAR_EN); 878 break; 879 case PCI_VENDOR_PCHDTV: 880 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 881 bus_space_write_4(sc->sc_memt, sc->sc_memh, 882 CXDTV_TS_GEN_CONTROL, IPB_SW_RST|IPB_SMODE); 883 delay(100); 884 bus_space_write_4(sc->sc_memt, sc->sc_memh, 885 CXDTV_PINMUX_IO, 0x00); /* serial MPEG port */ 886 /* byte-width start-of-packet */ 887 bus_space_write_4(sc->sc_memt, sc->sc_memh, 888 CXDTV_HW_SOP_CONTROL, 889 0x47 << 16 | 188 << 4 | 1); 890 bus_space_write_4(sc->sc_memt, sc->sc_memh, 891 CXDTV_TS_SOP_STATUS, IPB_SOP_BYTEWIDE); 892 /* serial MPEG port on HD5500 */ 893 bus_space_write_4(sc->sc_memt, sc->sc_memh, 894 CXDTV_TS_GEN_CONTROL, IPB_SMODE); 895 } 896 break; 897 default: 898 break; 899 } 900 901 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_LNGTH, 902 CXDTV_TS_PKTSIZE); 903 904 /* Configure for standard MPEG TS, 1 good packet to sync */ 905 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_HW_SOP_CONTROL, 906 0x47 << 16 | 188 << 4 | 1); 907 908 /* zero counter */ 909 bus_space_write_4(sc->sc_memt, sc->sc_memh, 910 CXDTV_TS_GP_CNT_CNTRL, 0x03); 911 912 /* enable bad packet interrupt */ 913 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_BD_PKT_STATUS, 914 0x1000); 915 916 /* enable overflow counter */ 917 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_FIFO_OVFL_STAT, 918 0x1000); 919 920 /* unmask TS interrupt */ 921 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 922 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 923 v | CXT_PI_TS_INT); 924 925 /* unmask all TS interrupts */ 926 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 927 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 928 v | 0x1f1011); 929 930 /* enable RISC DMA engine */ 931 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2); 932 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 933 v | CXDTV_DEV_CNTRL2_RUN_RISC); 934 935 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 936 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 937 v | CXDTV_TS_RISC_EN | CXDTV_TS_FIFO_EN); 938 939 return 0; 940 } 941 942 int 943 cxdtv_mpeg_halt(struct cxdtv_softc *sc) 944 { 945 uint32_t v; 946 947 CX_DPRINTF(("cxdtv_mpeg_halt\n")); 948 949 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 950 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 951 v & ~(CXDTV_TS_RISC_EN|CXDTV_TS_FIFO_EN)); 952 953 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 954 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 955 v & ~CXT_PI_TS_INT); 956 957 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 958 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 959 v & ~0x1f1011); 960 961 return 0; 962 } 963 964 int 965 cxdtv_mpeg_intr(struct cxdtv_softc *sc) 966 { 967 struct dtv_payload payload; 968 uint32_t s, m; 969 970 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT); 971 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 972 if ((s & m) == 0) 973 return 0; 974 975 if ( (s & ~CXDTV_TS_RISCI) != 0 ) 976 device_printf(sc->sc_dev, "unexpected TS IS %08x\n", s); 977 978 if (sc->sc_dtvsubmitcb == NULL) 979 goto done; 980 981 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 982 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 983 0, CXDTV_TS_PKTSIZE, 984 BUS_DMASYNC_POSTREAD); 985 payload.data = KERNADDR(sc->sc_dma); 986 payload.size = CXDTV_TS_PKTSIZE; 987 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 988 } 989 990 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 991 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 992 CXDTV_TS_PKTSIZE, CXDTV_TS_PKTSIZE, 993 BUS_DMASYNC_POSTREAD); 994 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CXDTV_TS_PKTSIZE; 995 payload.size = CXDTV_TS_PKTSIZE; 996 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 997 } 998 999 done: 1000 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, s); 1001 1002 return 1; 1003 } 1004 1005 static int 1006 cxdtv_allocmem(struct cxdtv_softc *sc, size_t size, size_t align, 1007 struct cxdtv_dma *p) 1008 { 1009 int err; 1010 1011 p->size = size; 1012 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 1013 p->segs, __arraycount(p->segs), 1014 &p->nsegs, BUS_DMA_NOWAIT); 1015 if (err) 1016 return err; 1017 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 1018 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1019 if (err) 1020 goto free; 1021 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 1022 BUS_DMA_NOWAIT, &p->map); 1023 if (err) 1024 goto unmap; 1025 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 1026 BUS_DMA_NOWAIT); 1027 if (err) 1028 goto destroy; 1029 1030 return 0; 1031 1032 destroy: 1033 bus_dmamap_destroy(sc->sc_dmat, p->map); 1034 unmap: 1035 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1036 free: 1037 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1038 1039 return err; 1040 } 1041 1042 static int 1043 cxdtv_freemem(struct cxdtv_softc *sc, struct cxdtv_dma *p) 1044 { 1045 1046 bus_dmamap_unload(sc->sc_dmat, p->map); 1047 bus_dmamap_destroy(sc->sc_dmat, p->map); 1048 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1049 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1050 1051 return 0; 1052 } 1053 1054 void * 1055 cxdtv_mpeg_malloc(struct cxdtv_softc *sc, size_t size) 1056 { 1057 struct cxdtv_dma *p; 1058 int err; 1059 1060 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1061 err = cxdtv_allocmem(sc, size, 16, p); 1062 if (err) { 1063 kmem_free(p, sizeof(*p)); 1064 device_printf(sc->sc_dev, "not enough memory\n"); 1065 return NULL; 1066 } 1067 1068 p->next = sc->sc_dma; 1069 sc->sc_dma = p; 1070 1071 return KERNADDR(p); 1072 } 1073 1074 static void 1075 cxdtv_mpeg_free(struct cxdtv_softc *sc, void *addr) 1076 { 1077 struct cxdtv_dma *p; 1078 struct cxdtv_dma **pp; 1079 1080 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) { 1081 if (KERNADDR(p) == addr) { 1082 cxdtv_freemem(sc, p); 1083 *pp = p->next; 1084 kmem_free(p, sizeof(*p)); 1085 return; 1086 } 1087 } 1088 1089 device_printf(sc->sc_dev, "%p is already free\n", addr); 1090 1091 return; 1092 } 1093 1094 1095 /* ATI HDTV Wonder */ 1096 static void 1097 cxdtv_card_init_hdtvwonder(struct cxdtv_softc *sc) 1098 { 1099 int i, x; 1100 i2c_addr_t na; 1101 uint8_t nb[5][2] = { 1102 {0x10, 0x12}, {0x13, 0x04}, {0x16, 0x00}, 1103 {0x14, 0x04}, {0x17, 0x00} 1104 }; 1105 1106 /* prepare TUV1236D/TU1236F NIM */ 1107 1108 na = 0x0a; /* Nxt2004 address */ 1109 x = 0; 1110 1111 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 1112 1113 for(i = 0; i < 5; i++) 1114 x |= iic_exec(&sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, na, 1115 nb[i], 2, NULL, 0, I2C_F_POLL); 1116 1117 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 1118 1119 if (x) 1120 aprint_error_dev(sc->sc_dev, "HDTV Wonder tuner init failed"); 1121 } 1122 1123 /* pcHDTV HD5500 */ 1124 #define cxdtv_write_field(_mask, _shift, _value) \ 1125 (((_value) & (_mask)) << (_shift)) 1126 1127 static void 1128 cxdtv_write_gpio(struct cxdtv_softc *sc, uint32_t mask, uint32_t value) 1129 { 1130 uint32_t v = 0; 1131 v |= cxdtv_write_field(0xff, 16, mask); 1132 v |= cxdtv_write_field(0xff, 8, mask); 1133 v |= cxdtv_write_field(0xff, 0, (mask & value)); 1134 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_GP0_IO, v); 1135 } 1136 1137 static void 1138 cxdtv_card_init_hd5500(struct cxdtv_softc *sc) 1139 { 1140 /* hardware (demod) reset */ 1141 cxdtv_write_gpio(sc, 1, 0); 1142 delay(100000); 1143 cxdtv_write_gpio(sc, 1, 1); 1144 delay(200000); 1145 } 1146 1147 MODULE(MODULE_CLASS_DRIVER, cxdtv, "tvpll,nxt2k,lg3303,pci"); 1148 1149 #ifdef _MODULE 1150 #include "ioconf.c" 1151 #endif 1152 1153 static int 1154 cxdtv_modcmd(modcmd_t cmd, void *opaque) 1155 { 1156 switch (cmd) { 1157 case MODULE_CMD_INIT: 1158 #ifdef _MODULE 1159 return config_init_component(cfdriver_ioconf_cxdtv, 1160 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1161 #else 1162 return 0; 1163 #endif 1164 case MODULE_CMD_FINI: 1165 #ifdef _MODULE 1166 return config_fini_component(cfdriver_ioconf_cxdtv, 1167 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1168 #else 1169 return 0; 1170 #endif 1171 default: 1172 return ENOTTY; 1173 } 1174 } 1175