1 /* $NetBSD: cxdtv.c,v 1.13 2013/10/16 18:20:16 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cxdtv.c,v 1.13 2013/10/16 18:20:16 christos Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/proc.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_bitbang.h> 46 47 #include <dev/i2c/tvpllvar.h> 48 #include <dev/i2c/tvpll_tuners.h> 49 50 #include <dev/i2c/nxt2kvar.h> 51 #include <dev/i2c/lg3303var.h> 52 53 #include <dev/dtv/dtvif.h> 54 55 #include <dev/pci/cxdtvreg.h> 56 #include <dev/pci/cxdtvvar.h> 57 #include <dev/pci/cxdtv_boards.h> 58 59 #define CXDTV_MMBASE 0x10 60 61 #define CXDTV_SRAM_CH_MPEG 0 62 #define CXDTV_TS_PKTSIZE (188 * 8) 63 64 static int cxdtv_match(device_t, cfdata_t, void *); 65 static void cxdtv_attach(device_t, device_t, void *); 66 static int cxdtv_detach(device_t, int); 67 static int cxdtv_rescan(device_t, const char *, const int *); 68 static void cxdtv_childdet(device_t, device_t); 69 static int cxdtv_intr(void *); 70 71 static bool cxdtv_resume(device_t, const pmf_qual_t *); 72 73 static int cxdtv_iic_acquire_bus(void *, int); 74 static void cxdtv_iic_release_bus(void *, int); 75 static int cxdtv_iic_send_start(void *, int); 76 static int cxdtv_iic_send_stop(void *, int); 77 static int cxdtv_iic_initiate_xfer(void *, i2c_addr_t, int); 78 static int cxdtv_iic_read_byte(void *, uint8_t *, int); 79 static int cxdtv_iic_write_byte(void *, uint8_t, int); 80 81 static void cxdtv_i2cbb_set_bits(void *, uint32_t); 82 static void cxdtv_i2cbb_set_dir(void *, uint32_t); 83 static uint32_t cxdtv_i2cbb_read_bits(void *); 84 85 static int cxdtv_sram_ch_setup(struct cxdtv_softc *, 86 struct cxdtv_sram_ch *, uint32_t); 87 static int cxdtv_allocmem(struct cxdtv_softc *, size_t, size_t, 88 struct cxdtv_dma *); 89 static int cxdtv_freemem(struct cxdtv_softc *, struct cxdtv_dma *); 90 static int cxdtv_risc_buffer(struct cxdtv_softc *, uint32_t, uint32_t); 91 static int cxdtv_risc_field(struct cxdtv_softc *, uint32_t *, uint32_t); 92 93 static int cxdtv_mpeg_attach(struct cxdtv_softc *); 94 static int cxdtv_mpeg_detach(struct cxdtv_softc *, int flags); 95 static int cxdtv_mpeg_intr(struct cxdtv_softc *); 96 static int cxdtv_mpeg_reset(struct cxdtv_softc *); 97 98 static int cxdtv_mpeg_trigger(struct cxdtv_softc *, void *); 99 static int cxdtv_mpeg_halt(struct cxdtv_softc *); 100 static void * cxdtv_mpeg_malloc(struct cxdtv_softc *, size_t); 101 static void cxdtv_mpeg_free(struct cxdtv_softc *, void *); 102 103 static void cxdtv_card_init_hd5500(struct cxdtv_softc *); 104 static void cxdtv_card_init_hdtvwonder(struct cxdtv_softc *); 105 106 /* MPEG TS Port */ 107 static void cxdtv_dtv_get_devinfo(void *, struct dvb_frontend_info *); 108 static int cxdtv_dtv_open(void *, int); 109 static void cxdtv_dtv_close(void *); 110 static int cxdtv_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 111 static fe_status_t cxdtv_dtv_get_status(void *); 112 static uint16_t cxdtv_dtv_get_signal_strength(void *); 113 static uint16_t cxdtv_dtv_get_snr(void *); 114 static int cxdtv_dtv_start_transfer(void *, 115 void (*)(void *, const struct dtv_payload *), void *); 116 static int cxdtv_dtv_stop_transfer(void *); 117 118 static const struct dtv_hw_if cxdtv_dtv_if = { 119 .get_devinfo = cxdtv_dtv_get_devinfo, 120 .open = cxdtv_dtv_open, 121 .close = cxdtv_dtv_close, 122 .set_tuner = cxdtv_dtv_set_tuner, 123 .get_status = cxdtv_dtv_get_status, 124 .get_signal_strength = cxdtv_dtv_get_signal_strength, 125 .get_snr = cxdtv_dtv_get_snr, 126 .start_transfer = cxdtv_dtv_start_transfer, 127 .stop_transfer = cxdtv_dtv_stop_transfer, 128 }; 129 130 const struct i2c_bitbang_ops cxdtv_i2cbb_ops = { 131 cxdtv_i2cbb_set_bits, 132 cxdtv_i2cbb_set_dir, 133 cxdtv_i2cbb_read_bits, 134 { CXDTV_I2C_C_DATACONTROL_SDA, CXDTV_I2C_C_DATACONTROL_SCL, 0, 0 } 135 }; 136 137 /* Maybe make this dynamically allocated. */ 138 static struct cxdtv_sram_ch cxdtv_sram_chs[] = { 139 [CXDTV_SRAM_CH_MPEG] = { 140 .csc_cmds = 0x180200, /* CMDS for ch. 28 */ 141 .csc_iq = 0x180340, /* after last CMDS */ 142 .csc_iqsz = 0x40, /* 16 dwords */ 143 .csc_cdt = 0x180380, /* after iq */ 144 .csc_cdtsz = 0x40, /* cluster discriptor space */ 145 .csc_fifo = 0x180400, /* after cdt */ 146 .csc_fifosz = 0x001C00, /* let's just align this up */ 147 .csc_risc = 0x182000, /* after fifo */ 148 .csc_riscsz = 0x6000, /* room for dma programs */ 149 .csc_ptr1 = CXDTV_DMA28_PTR1, 150 .csc_ptr2 = CXDTV_DMA28_PTR2, 151 .csc_cnt1 = CXDTV_DMA28_CNT1, 152 .csc_cnt2 = CXDTV_DMA28_CNT2, 153 }, 154 }; 155 156 CFATTACH_DECL2_NEW(cxdtv, sizeof(struct cxdtv_softc), 157 cxdtv_match, cxdtv_attach, cxdtv_detach, NULL, 158 cxdtv_rescan, cxdtv_childdet); 159 160 static int 161 cxdtv_match(device_t parent, cfdata_t match, void *aux) 162 { 163 const struct pci_attach_args *pa; 164 pcireg_t reg; 165 166 pa = aux; 167 168 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 169 return 0; 170 171 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX2388XMPEG) 172 return 0; 173 174 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 175 if (cxdtv_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)) == NULL) 176 return 0; 177 178 return 1; 179 } 180 181 static void 182 cxdtv_attach(device_t parent, device_t self, void *aux) 183 { 184 struct cxdtv_softc *sc; 185 const struct pci_attach_args *pa = aux; 186 pci_intr_handle_t ih; 187 pcireg_t reg; 188 const char *intrstr; 189 struct i2cbus_attach_args iba; 190 191 sc = device_private(self); 192 193 sc->sc_dev = self; 194 sc->sc_pc = pa->pa_pc; 195 196 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 197 198 sc->sc_vendor = PCI_VENDOR(reg); 199 sc->sc_product = PCI_PRODUCT(reg); 200 201 sc->sc_board = cxdtv_board_lookup(sc->sc_vendor, sc->sc_product); 202 KASSERT(sc->sc_board != NULL); 203 204 pci_aprint_devinfo(pa, NULL); 205 206 if (pci_mapreg_map(pa, CXDTV_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 207 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 208 aprint_error_dev(self, "couldn't map memory space\n"); 209 return; 210 } 211 212 sc->sc_dmat = pa->pa_dmat; 213 214 if (pci_intr_map(pa, &ih)) { 215 aprint_error_dev(self, "couldn't map interrupt\n"); 216 return; 217 } 218 intrstr = pci_intr_string(pa->pa_pc, ih); 219 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM, cxdtv_intr, sc); 220 if (sc->sc_ih == NULL) { 221 aprint_error_dev(self, "couldn't establish interrupt"); 222 if (intrstr != NULL) 223 aprint_error(" at %s", intrstr); 224 aprint_error("\n"); 225 return; 226 } 227 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 228 229 /* set master */ 230 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 231 reg |= PCI_COMMAND_MASTER_ENABLE; 232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 233 234 mutex_init(&sc->sc_i2c_buslock, MUTEX_DRIVER, IPL_NONE); 235 sc->sc_i2c.ic_cookie = sc; 236 sc->sc_i2c.ic_exec = NULL; 237 sc->sc_i2c.ic_acquire_bus = cxdtv_iic_acquire_bus; 238 sc->sc_i2c.ic_release_bus = cxdtv_iic_release_bus; 239 sc->sc_i2c.ic_send_start = cxdtv_iic_send_start; 240 sc->sc_i2c.ic_send_stop = cxdtv_iic_send_stop; 241 sc->sc_i2c.ic_initiate_xfer = cxdtv_iic_initiate_xfer; 242 sc->sc_i2c.ic_read_byte = cxdtv_iic_read_byte; 243 sc->sc_i2c.ic_write_byte = cxdtv_iic_write_byte; 244 245 #if notyet 246 /* enable i2c compatible software mode */ 247 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, 248 CXDTV_I2C_C_DATACONTROL); 249 val = CXDTV_I2C_C_DATACONTROL_SCL | CXDTV_I2C_C_DATACONTROL_SDA; 250 bus_space_write_4(sc->sc_memt, sc->sc_memh, 251 CXDTV_I2C_C_DATACONTROL, val); 252 #endif 253 254 cxdtv_mpeg_attach(sc); 255 256 /* attach other devices to iic(4) */ 257 memset(&iba, 0, sizeof(iba)); 258 iba.iba_tag = &sc->sc_i2c; 259 config_found_ia(self, "i2cbus", &iba, iicbus_print); 260 261 if (!pmf_device_register(self, NULL, cxdtv_resume)) 262 aprint_error_dev(self, "couldn't establish power handler\n"); 263 264 return; 265 } 266 267 static int 268 cxdtv_detach(device_t self, int flags) 269 { 270 struct cxdtv_softc *sc = device_private(self); 271 int error; 272 273 error = cxdtv_mpeg_detach(sc, flags); 274 if (error) 275 return error; 276 277 if (sc->sc_ih) 278 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 279 280 if (sc->sc_mems) 281 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 282 283 mutex_destroy(&sc->sc_i2c_buslock); 284 285 return 0; 286 } 287 288 static int 289 cxdtv_rescan(device_t self, const char *ifattr, const int *locs) 290 { 291 struct cxdtv_softc *sc = device_private(self); 292 struct dtv_attach_args daa; 293 294 daa.hw = &cxdtv_dtv_if; 295 daa.priv = sc; 296 297 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 298 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", 299 &daa, dtv_print); 300 301 return 0; 302 } 303 304 static void 305 cxdtv_childdet(device_t self, device_t child) 306 { 307 struct cxdtv_softc *sc = device_private(self); 308 309 if (child == sc->sc_dtvdev) 310 sc->sc_dtvdev = NULL; 311 } 312 313 static bool 314 cxdtv_resume(device_t dv, const pmf_qual_t *qual) 315 { 316 /* XXX revisit */ 317 318 aprint_debug_dev(dv, "%s\n", __func__); 319 320 return true; 321 } 322 323 static int 324 cxdtv_intr(void *intarg) 325 { 326 struct cxdtv_softc *sc = intarg; 327 uint32_t val; 328 329 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MSTAT); 330 if (val == 0) { 331 return 0; /* not ours */ 332 } 333 334 if (val & CXT_PI_TS_INT) { 335 cxdtv_mpeg_intr(sc); 336 } 337 338 if (val & ~CXT_PI_TS_INT) { 339 device_printf(sc->sc_dev, "%s, %08x\n", __func__, val); 340 } 341 342 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, val); 343 344 return 1; 345 } 346 347 /* I2C interface */ 348 349 static void 350 cxdtv_i2cbb_set_bits(void *cookie, uint32_t bits) 351 { 352 struct cxdtv_softc *sc = cookie; 353 354 bus_space_write_4(sc->sc_memt, sc->sc_memh, 355 CXDTV_I2C_C_DATACONTROL, bits); 356 (void)bus_space_read_4(sc->sc_memt, sc->sc_memh, 357 CXDTV_I2C_C_DATACONTROL); 358 359 return; 360 } 361 362 static void 363 cxdtv_i2cbb_set_dir(void *cookie, uint32_t bits) 364 { 365 return; 366 } 367 368 static uint32_t 369 cxdtv_i2cbb_read_bits(void *cookie) 370 { 371 struct cxdtv_softc *sc = cookie; 372 uint32_t value; 373 374 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 375 CXDTV_I2C_C_DATACONTROL); 376 377 return value; 378 } 379 380 static int 381 cxdtv_iic_acquire_bus(void *cookie, int flags) 382 { 383 struct cxdtv_softc *sc = cookie; 384 385 mutex_enter(&sc->sc_i2c_buslock); 386 387 return 0; 388 } 389 390 static void 391 cxdtv_iic_release_bus(void *cookie, int flags) 392 { 393 struct cxdtv_softc *sc = cookie; 394 395 mutex_exit(&sc->sc_i2c_buslock); 396 397 return; 398 } 399 400 static int 401 cxdtv_iic_send_start(void *cookie, int flags) 402 { 403 return i2c_bitbang_send_start(cookie, flags, &cxdtv_i2cbb_ops); 404 } 405 406 static int 407 cxdtv_iic_send_stop(void *cookie, int flags) 408 { 409 return i2c_bitbang_send_stop(cookie, flags, &cxdtv_i2cbb_ops); 410 } 411 412 static int 413 cxdtv_iic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 414 { 415 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &cxdtv_i2cbb_ops); 416 } 417 418 static int 419 cxdtv_iic_read_byte(void *cookie, uint8_t *data, int flags) 420 { 421 return i2c_bitbang_read_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 422 } 423 424 static int 425 cxdtv_iic_write_byte(void *cookie, uint8_t data, int flags) 426 { 427 return i2c_bitbang_write_byte(cookie, data, flags, &cxdtv_i2cbb_ops); 428 } 429 430 int 431 cxdtv_mpeg_attach(struct cxdtv_softc *sc) 432 { 433 struct cxdtv_sram_ch *ch; 434 435 CX_DPRINTF(("cxdtv_mpeg_attach\n")); 436 437 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 438 439 sc->sc_riscbufsz = ch->csc_riscsz; 440 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 441 442 if ( sc->sc_riscbuf == NULL ) 443 panic("riscbuf null"); 444 445 aprint_debug_dev(sc->sc_dev, "attaching frontend...\n"); 446 447 switch(sc->sc_vendor) { 448 case PCI_VENDOR_ATI: 449 cxdtv_card_init_hdtvwonder(sc); 450 break; 451 case PCI_VENDOR_PCHDTV: 452 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 453 cxdtv_card_init_hd5500(sc); 454 } 455 break; 456 } 457 458 KASSERT(sc->sc_tuner == NULL); 459 KASSERT(sc->sc_demod == NULL); 460 461 switch(sc->sc_board->cb_demod) { 462 case CXDTV_DEMOD_NXT2004: 463 sc->sc_demod = nxt2k_open(sc->sc_dev, &sc->sc_i2c, 0x0a, 0); 464 break; 465 case CXDTV_DEMOD_LG3303: 466 sc->sc_demod = lg3303_open(sc->sc_dev, &sc->sc_i2c, 0x59, 467 LG3303_CFG_SERIAL_INPUT); 468 break; 469 default: 470 break; 471 } 472 473 switch(sc->sc_board->cb_tuner) { 474 case CXDTV_TUNER_PLL: 475 if (sc->sc_vendor == PCI_VENDOR_ATI) 476 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tuv1236d_pll); 477 if (sc->sc_vendor == PCI_VENDOR_PCHDTV) 478 sc->sc_tuner = tvpll_open(sc->sc_dev, &sc->sc_i2c, 0x61, &tvpll_tdvs_h06xf_pll); 479 break; 480 default: 481 break; 482 } 483 484 KASSERT(sc->sc_tuner != NULL); 485 KASSERT(sc->sc_demod != NULL); 486 487 cxdtv_rescan(sc->sc_dev, NULL, NULL); 488 489 return (sc->sc_dtvdev != NULL); 490 } 491 492 int 493 cxdtv_mpeg_detach(struct cxdtv_softc *sc, int flags) 494 { 495 int error = 0; 496 497 if (sc->sc_dtvdev) { 498 error = config_detach(sc->sc_dtvdev, flags); 499 if (error) 500 return error; 501 } 502 503 if (sc->sc_demod) { 504 switch (sc->sc_board->cb_demod) { 505 case CXDTV_DEMOD_NXT2004: 506 nxt2k_close(sc->sc_demod); 507 break; 508 case CXDTV_DEMOD_LG3303: 509 lg3303_close(sc->sc_demod); 510 break; 511 default: 512 break; 513 } 514 sc->sc_demod = NULL; 515 } 516 if (sc->sc_tuner) { 517 switch (sc->sc_board->cb_tuner) { 518 case CXDTV_TUNER_PLL: 519 tvpll_close(sc->sc_tuner); 520 break; 521 default: 522 break; 523 } 524 sc->sc_tuner = NULL; 525 } 526 527 if (sc->sc_riscbuf) { 528 kmem_free(sc->sc_riscbuf, sc->sc_riscbufsz); 529 sc->sc_riscbuf = NULL; 530 sc->sc_riscbufsz = 0; 531 } 532 533 return error; 534 } 535 536 static void 537 cxdtv_dtv_get_devinfo(void *priv, struct dvb_frontend_info *info) 538 { 539 memset(info, 0, sizeof(*info)); 540 strlcpy(info->name, "CX23880", sizeof(info->name)); 541 info->type = FE_ATSC; 542 info->frequency_min = 54000000; 543 info->frequency_max = 858000000; 544 info->frequency_stepsize = 62500; 545 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 546 } 547 548 static int 549 cxdtv_dtv_open(void *priv, int flags) 550 { 551 struct cxdtv_softc *sc = priv; 552 553 KASSERT(sc->sc_tsbuf == NULL); 554 555 cxdtv_mpeg_reset(sc); 556 557 /* allocate two alternating DMA areas for MPEG TS packets */ 558 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 559 560 if (sc->sc_tsbuf == NULL) 561 return ENOMEM; 562 563 return 0; 564 } 565 566 static void 567 cxdtv_dtv_close(void *priv) 568 { 569 struct cxdtv_softc *sc = priv; 570 571 cxdtv_dtv_stop_transfer(sc); 572 573 if (sc->sc_tsbuf != NULL) { 574 cxdtv_mpeg_free(sc, sc->sc_tsbuf); 575 sc->sc_tsbuf = NULL; 576 } 577 } 578 579 static int 580 cxdtv_dtv_set_tuner(void *priv, const struct dvb_frontend_parameters *params) 581 { 582 struct cxdtv_softc *sc = priv; 583 int error = -1; 584 585 switch(sc->sc_board->cb_tuner) { 586 case CXDTV_TUNER_PLL: 587 error = tvpll_tune_dtv(sc->sc_tuner, params); 588 } 589 if (error) 590 goto bad; 591 592 switch(sc->sc_board->cb_demod) { 593 case CXDTV_DEMOD_NXT2004: 594 error = nxt2k_set_modulation(sc->sc_demod, params->u.vsb.modulation); 595 break; 596 case CXDTV_DEMOD_LG3303: 597 error = lg3303_set_modulation(sc->sc_demod, params->u.vsb.modulation); 598 break; 599 default: 600 break; 601 } 602 603 bad: 604 return error; 605 } 606 607 static fe_status_t 608 cxdtv_dtv_get_status(void *priv) 609 { 610 struct cxdtv_softc *sc = priv; 611 612 switch(sc->sc_board->cb_demod) { 613 case CXDTV_DEMOD_NXT2004: 614 return nxt2k_get_dtv_status(sc->sc_demod); 615 case CXDTV_DEMOD_LG3303: 616 return lg3303_get_dtv_status(sc->sc_demod); 617 default: 618 return 0; 619 } 620 } 621 622 static uint16_t 623 cxdtv_dtv_get_signal_strength(void *priv) 624 { 625 struct cxdtv_softc *sc = priv; 626 627 switch(sc->sc_board->cb_demod) { 628 case CXDTV_DEMOD_NXT2004: 629 return 0; /* TODO */ 630 case CXDTV_DEMOD_LG3303: 631 return lg3303_get_signal_strength(sc->sc_demod); 632 } 633 634 return 0; 635 } 636 637 static uint16_t 638 cxdtv_dtv_get_snr(void *priv) 639 { 640 struct cxdtv_softc *sc = priv; 641 642 switch(sc->sc_board->cb_demod) { 643 case CXDTV_DEMOD_NXT2004: 644 return 0; /* TODO */ 645 case CXDTV_DEMOD_LG3303: 646 return lg3303_get_snr(sc->sc_demod); 647 } 648 649 return 0; 650 } 651 652 static int 653 cxdtv_dtv_start_transfer(void *priv, 654 void (*cb)(void *, const struct dtv_payload *), void *arg) 655 { 656 struct cxdtv_softc *sc = priv; 657 658 sc->sc_dtvsubmitcb = cb; 659 sc->sc_dtvsubmitarg = arg; 660 661 /* allocate two alternating DMA areas for MPEG TS packets */ 662 sc->sc_tsbuf = cxdtv_mpeg_malloc(sc, CXDTV_TS_PKTSIZE * 2); 663 664 cxdtv_mpeg_trigger(sc, sc->sc_tsbuf); 665 666 return 0; 667 } 668 669 static int 670 cxdtv_dtv_stop_transfer(void *priv) 671 { 672 struct cxdtv_softc *sc = priv; 673 674 cxdtv_mpeg_halt(sc); 675 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 676 677 sc->sc_dtvsubmitcb = NULL; 678 sc->sc_dtvsubmitarg = NULL; 679 680 return 0; 681 } 682 683 int 684 cxdtv_mpeg_reset(struct cxdtv_softc *sc) 685 { 686 uint32_t v; 687 688 CX_DPRINTF(("cxdtv_mpeg_reset\n")); 689 690 v = (uint32_t)-1; 691 692 /* shutdown */ 693 /* hold RISC in reset */ 694 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 0); 695 /* disable FIFO and RISC */ 696 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 0); 697 /* mask off all interrupts */ 698 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 0); 699 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 0); 700 701 /* clear interrupts */ 702 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_STAT, v); 703 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, v); 704 705 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 706 707 /* XXX magic */ 708 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_STHRSH, 0x0707); 709 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PDMA_DTHRSH, 0x0707); 710 711 /* reset external components*/ 712 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 0); 713 kpause("cxdtvrst", false, MAX(1, mstohz(1)), NULL); 714 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_SRST_IO, 1); 715 716 /* let error interrupts happen */ 717 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 718 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 719 v | 0x00fc00); /* XXX magic */ 720 721 return 0; 722 } 723 724 static int 725 cxdtv_risc_buffer(struct cxdtv_softc *sc, uint32_t bpl, uint32_t lines) 726 { 727 uint32_t *rm; 728 uint32_t size; 729 730 CX_DPRINTF(("cxdtv_risc_buffer: bpl=0x%x\n", bpl)); 731 732 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 733 size += 2; 734 735 device_printf(sc->sc_dev, "%s: est. inst. %d\n", __func__, size); 736 737 size *= 8; 738 device_printf(sc->sc_dev, "%s: est. qword %d\n", __func__, size); 739 740 if (sc->sc_riscbuf == NULL) { 741 device_printf(sc->sc_dev, "not enough memory for RISC\n"); 742 return ENOMEM; 743 } 744 745 rm = (uint32_t *)sc->sc_riscbuf; 746 cxdtv_risc_field(sc, rm, bpl); 747 748 return 0; 749 } 750 751 static int 752 cxdtv_risc_field(struct cxdtv_softc *sc, uint32_t *rm, uint32_t bpl) 753 { 754 struct cxdtv_dma *p; 755 756 CX_DPRINTF(("cxdtv_risc_field: bpl=0x%x\n", bpl)); 757 758 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 759 continue; 760 if (p == NULL) { 761 device_printf(sc->sc_dev, "cxdtv_risc_field: bad addr %p\n", 762 sc->sc_tsbuf); 763 return ENOENT; 764 } 765 766 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 767 768 rm = sc->sc_riscbuf; 769 770 /* htole32 will be done when program is copied to chip SRAM */ 771 772 /* XXX */ 773 *(rm++) = (CX_RISC_SYNC|0); 774 775 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 776 *(rm++) = (DMAADDR(p) + 0 * bpl); 777 778 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 779 *(rm++) = (DMAADDR(p) + 1 * bpl); 780 781 *(rm++) = (CX_RISC_JUMP|1); 782 *(rm++) = (cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG].csc_risc + 4); 783 784 return 0; 785 } 786 787 static int 788 cxdtv_sram_ch_setup(struct cxdtv_softc *sc, struct cxdtv_sram_ch *csc, 789 uint32_t bpl) 790 { 791 unsigned int i, lines; 792 uint32_t cdt; 793 794 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 795 796 /* XXX why round? */ 797 bpl = (bpl + 7) & ~7; 798 CX_DPRINTF(("cxdtv_sram_ch_setup: bpl=0x%x\n", bpl)); 799 cdt = csc->csc_cdt; 800 lines = csc->csc_fifosz / bpl; 801 device_printf(sc->sc_dev, "%s %d lines\n", __func__, lines); 802 803 /* fill in CDT */ 804 for (i = 0; i < lines; i++) { 805 CX_DPRINTF(("CDT ent %08x, %08x\n", cdt + (16 * i), 806 csc->csc_fifo + (bpl * i))); 807 bus_space_write_4(sc->sc_memt, sc->sc_memh, 808 cdt + (16 * i), 809 csc->csc_fifo + (bpl * i)); 810 } 811 812 /* copy DMA program */ 813 814 /* converts program to little endian as it goes into SRAM */ 815 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 816 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 817 818 /* fill in CMDS */ 819 bus_space_write_4(sc->sc_memt, sc->sc_memh, 820 csc->csc_cmds + CX_CMDS_O_IRPC, csc->csc_risc); 821 822 bus_space_write_4(sc->sc_memt, sc->sc_memh, 823 csc->csc_cmds + CX_CMDS_O_CDTB, csc->csc_cdt); 824 bus_space_write_4(sc->sc_memt, sc->sc_memh, 825 csc->csc_cmds + CX_CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 826 827 bus_space_write_4(sc->sc_memt, sc->sc_memh, 828 csc->csc_cmds + CX_CMDS_O_IQB, csc->csc_iq); 829 bus_space_write_4(sc->sc_memt, sc->sc_memh, 830 csc->csc_cmds + CX_CMDS_O_IQS, 831 CX_CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 832 833 /* zero rest of CMDS */ 834 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x14, 0, 0x2c/4); 835 836 bus_space_write_4(sc->sc_memt, sc->sc_memh, 837 csc->csc_cnt1, (bpl >> 3) - 1); 838 839 bus_space_write_4(sc->sc_memt, sc->sc_memh, 840 csc->csc_ptr2, cdt); 841 bus_space_write_4(sc->sc_memt, sc->sc_memh, 842 csc->csc_cnt2, (lines * 16) >> 3); 843 844 return 0; 845 } 846 847 int 848 cxdtv_mpeg_trigger(struct cxdtv_softc *sc, void *buf) 849 { 850 struct cxdtv_dma *p; 851 struct cxdtv_sram_ch *ch; 852 uint32_t v; 853 854 ch = &cxdtv_sram_chs[CXDTV_SRAM_CH_MPEG]; 855 856 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 857 continue; 858 if (p == NULL) { 859 device_printf(sc->sc_dev, "cxdtv_mpeg_trigger: bad addr %p\n", 860 buf); 861 return ENOENT; 862 } 863 864 CX_DPRINTF(("cxdtv_mpeg_trigger: buf=%p\n", buf)); 865 866 cxdtv_risc_buffer(sc, CXDTV_TS_PKTSIZE, 1); 867 cxdtv_sram_ch_setup(sc, ch, CXDTV_TS_PKTSIZE); 868 869 /* software reset */ 870 871 switch(sc->sc_vendor) { 872 case PCI_VENDOR_ATI: 873 /* both ATI boards with DTV are the same */ 874 bus_space_write_4(sc->sc_memt, sc->sc_memh, 875 CXDTV_TS_GEN_CONTROL, IPB_SW_RST); 876 delay(100); 877 /* parallel MPEG port */ 878 bus_space_write_4(sc->sc_memt, sc->sc_memh, 879 CXDTV_PINMUX_IO, MPEG_PAR_EN); 880 break; 881 case PCI_VENDOR_PCHDTV: 882 if (sc->sc_product == PCI_PRODUCT_PCHDTV_HD5500) { 883 bus_space_write_4(sc->sc_memt, sc->sc_memh, 884 CXDTV_TS_GEN_CONTROL, IPB_SW_RST|IPB_SMODE); 885 delay(100); 886 bus_space_write_4(sc->sc_memt, sc->sc_memh, 887 CXDTV_PINMUX_IO, 0x00); /* serial MPEG port */ 888 /* byte-width start-of-packet */ 889 bus_space_write_4(sc->sc_memt, sc->sc_memh, 890 CXDTV_HW_SOP_CONTROL, 891 0x47 << 16 | 188 << 4 | 1); 892 bus_space_write_4(sc->sc_memt, sc->sc_memh, 893 CXDTV_TS_SOP_STATUS, IPB_SOP_BYTEWIDE); 894 /* serial MPEG port on HD5500 */ 895 bus_space_write_4(sc->sc_memt, sc->sc_memh, 896 CXDTV_TS_GEN_CONTROL, IPB_SMODE); 897 } 898 break; 899 default: 900 break; 901 } 902 903 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_LNGTH, 904 CXDTV_TS_PKTSIZE); 905 906 /* Configure for standard MPEG TS, 1 good packet to sync */ 907 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_HW_SOP_CONTROL, 908 0x47 << 16 | 188 << 4 | 1); 909 910 /* zero counter */ 911 bus_space_write_4(sc->sc_memt, sc->sc_memh, 912 CXDTV_TS_GP_CNT_CNTRL, 0x03); 913 914 /* enable bad packet interrupt */ 915 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_BD_PKT_STATUS, 916 0x1000); 917 918 /* enable overflow counter */ 919 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_FIFO_OVFL_STAT, 920 0x1000); 921 922 /* unmask TS interrupt */ 923 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 924 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 925 v | CXT_PI_TS_INT); 926 927 /* unmask all TS interrupts */ 928 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 929 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 930 v | 0x1f1011); 931 932 /* enable RISC DMA engine */ 933 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2); 934 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_DEV_CNTRL2, 935 v | CXDTV_DEV_CNTRL2_RUN_RISC); 936 937 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 938 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 939 v | CXDTV_TS_RISC_EN | CXDTV_TS_FIFO_EN); 940 941 return 0; 942 } 943 944 int 945 cxdtv_mpeg_halt(struct cxdtv_softc *sc) 946 { 947 uint32_t v; 948 949 CX_DPRINTF(("cxdtv_mpeg_halt\n")); 950 951 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL); 952 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_DMA_CNTRL, 953 v & ~(CXDTV_TS_RISC_EN|CXDTV_TS_FIFO_EN)); 954 955 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK); 956 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_PCI_INT_MASK, 957 v & ~CXT_PI_TS_INT); 958 959 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 960 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK, 961 v & ~0x1f1011); 962 963 return 0; 964 } 965 966 int 967 cxdtv_mpeg_intr(struct cxdtv_softc *sc) 968 { 969 struct dtv_payload payload; 970 uint32_t s, m; 971 972 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT); 973 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_MASK); 974 if ((s & m) == 0) 975 return 0; 976 977 if ( (s & ~CXDTV_TS_RISCI) != 0 ) 978 device_printf(sc->sc_dev, "unexpected TS IS %08x\n", s); 979 980 if (sc->sc_dtvsubmitcb == NULL) 981 goto done; 982 983 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 984 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 985 0, CXDTV_TS_PKTSIZE, 986 BUS_DMASYNC_POSTREAD); 987 payload.data = KERNADDR(sc->sc_dma); 988 payload.size = CXDTV_TS_PKTSIZE; 989 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 990 } 991 992 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 993 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 994 CXDTV_TS_PKTSIZE, CXDTV_TS_PKTSIZE, 995 BUS_DMASYNC_POSTREAD); 996 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CXDTV_TS_PKTSIZE; 997 payload.size = CXDTV_TS_PKTSIZE; 998 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 999 } 1000 1001 done: 1002 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_TS_INT_STAT, s); 1003 1004 return 1; 1005 } 1006 1007 static int 1008 cxdtv_allocmem(struct cxdtv_softc *sc, size_t size, size_t align, 1009 struct cxdtv_dma *p) 1010 { 1011 int err; 1012 1013 p->size = size; 1014 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 1015 p->segs, __arraycount(p->segs), 1016 &p->nsegs, BUS_DMA_NOWAIT); 1017 if (err) 1018 return err; 1019 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 1020 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1021 if (err) 1022 goto free; 1023 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 1024 BUS_DMA_NOWAIT, &p->map); 1025 if (err) 1026 goto unmap; 1027 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 1028 BUS_DMA_NOWAIT); 1029 if (err) 1030 goto destroy; 1031 1032 return 0; 1033 1034 destroy: 1035 bus_dmamap_destroy(sc->sc_dmat, p->map); 1036 unmap: 1037 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1038 free: 1039 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1040 1041 return err; 1042 } 1043 1044 static int 1045 cxdtv_freemem(struct cxdtv_softc *sc, struct cxdtv_dma *p) 1046 { 1047 1048 bus_dmamap_unload(sc->sc_dmat, p->map); 1049 bus_dmamap_destroy(sc->sc_dmat, p->map); 1050 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 1051 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 1052 1053 return 0; 1054 } 1055 1056 void * 1057 cxdtv_mpeg_malloc(struct cxdtv_softc *sc, size_t size) 1058 { 1059 struct cxdtv_dma *p; 1060 int err; 1061 1062 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1063 if (p == NULL) { 1064 return NULL; 1065 } 1066 1067 err = cxdtv_allocmem(sc, size, 16, p); 1068 if (err) { 1069 kmem_free(p, sizeof(*p)); 1070 device_printf(sc->sc_dev, "not enough memory\n"); 1071 return NULL; 1072 } 1073 1074 p->next = sc->sc_dma; 1075 sc->sc_dma = p; 1076 1077 return KERNADDR(p); 1078 } 1079 1080 static void 1081 cxdtv_mpeg_free(struct cxdtv_softc *sc, void *addr) 1082 { 1083 struct cxdtv_dma *p; 1084 struct cxdtv_dma **pp; 1085 1086 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) { 1087 if (KERNADDR(p) == addr) { 1088 cxdtv_freemem(sc, p); 1089 *pp = p->next; 1090 kmem_free(p, sizeof(*p)); 1091 return; 1092 } 1093 } 1094 1095 device_printf(sc->sc_dev, "%p is already free\n", addr); 1096 1097 return; 1098 } 1099 1100 1101 /* ATI HDTV Wonder */ 1102 static void 1103 cxdtv_card_init_hdtvwonder(struct cxdtv_softc *sc) 1104 { 1105 int i, x; 1106 i2c_addr_t na; 1107 uint8_t nb[5][2] = { 1108 {0x10, 0x12}, {0x13, 0x04}, {0x16, 0x00}, 1109 {0x14, 0x04}, {0x17, 0x00} 1110 }; 1111 1112 /* prepare TUV1236D/TU1236F NIM */ 1113 1114 na = 0x0a; /* Nxt2004 address */ 1115 x = 0; 1116 1117 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 1118 1119 for(i = 0; i < 5; i++) 1120 x |= iic_exec(&sc->sc_i2c, I2C_OP_WRITE_WITH_STOP, na, 1121 nb[i], 2, NULL, 0, I2C_F_POLL); 1122 1123 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 1124 1125 if (x) 1126 aprint_error_dev(sc->sc_dev, "HDTV Wonder tuner init failed"); 1127 } 1128 1129 /* pcHDTV HD5500 */ 1130 #define cxdtv_write_field(_mask, _shift, _value) \ 1131 (((_value) & (_mask)) << (_shift)) 1132 1133 static void 1134 cxdtv_write_gpio(struct cxdtv_softc *sc, uint32_t mask, uint32_t value) 1135 { 1136 uint32_t v = 0; 1137 v |= cxdtv_write_field(0xff, 16, mask); 1138 v |= cxdtv_write_field(0xff, 8, mask); 1139 v |= cxdtv_write_field(0xff, 0, (mask & value)); 1140 bus_space_write_4(sc->sc_memt, sc->sc_memh, CXDTV_GP0_IO, v); 1141 } 1142 1143 static void 1144 cxdtv_card_init_hd5500(struct cxdtv_softc *sc) 1145 { 1146 /* hardware (demod) reset */ 1147 cxdtv_write_gpio(sc, 1, 0); 1148 delay(100000); 1149 cxdtv_write_gpio(sc, 1, 1); 1150 delay(200000); 1151 } 1152 1153 MODULE(MODULE_CLASS_DRIVER, cxdtv, "tvpll,nxt2k,lg3303,pci"); 1154 1155 #ifdef _MODULE 1156 #include "ioconf.c" 1157 #endif 1158 1159 static int 1160 cxdtv_modcmd(modcmd_t cmd, void *opaque) 1161 { 1162 switch (cmd) { 1163 case MODULE_CMD_INIT: 1164 #ifdef _MODULE 1165 return config_init_component(cfdriver_ioconf_cxdtv, 1166 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1167 #else 1168 return 0; 1169 #endif 1170 case MODULE_CMD_FINI: 1171 #ifdef _MODULE 1172 return config_fini_component(cfdriver_ioconf_cxdtv, 1173 cfattach_ioconf_cxdtv, cfdata_ioconf_cxdtv); 1174 #else 1175 return 0; 1176 #endif 1177 default: 1178 return ENOTTY; 1179 } 1180 } 1181