1 /* $NetBSD: cs4281.c,v 1.46 2011/11/24 03:35:58 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.46 2011/11/24 03:35:58 mrg Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <sys/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(device_t, cfdata_t, void *); 84 static void cs4281_attach(device_t, device_t, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static bool cs4281_suspend(device_t, const pmf_qual_t *); 110 static bool cs4281_resume(device_t, const pmf_qual_t *); 111 112 static const struct audio_hw_if cs4281_hw_if = { 113 NULL, /* open */ 114 NULL, /* close */ 115 NULL, 116 cs4281_query_encoding, 117 cs4281_set_params, 118 cs428x_round_blocksize, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 NULL, 124 cs4281_halt_output, 125 cs4281_halt_input, 126 NULL, 127 cs4281_getdev, 128 NULL, 129 cs428x_mixer_set_port, 130 cs428x_mixer_get_port, 131 cs428x_query_devinfo, 132 cs428x_malloc, 133 cs428x_free, 134 cs428x_round_buffersize, 135 cs428x_mappage, 136 cs428x_get_props, 137 cs4281_trigger_output, 138 cs4281_trigger_input, 139 NULL, 140 cs428x_get_locks, 141 }; 142 143 #if NMIDI > 0 && 0 144 /* Midi Interface */ 145 static void cs4281_midi_close(void*); 146 static void cs4281_midi_getinfo(void *, struct midi_info *); 147 static int cs4281_midi_open(void *, int, void (*)(void *, int), 148 void (*)(void *), void *); 149 static int cs4281_midi_output(void *, int); 150 151 static const struct midi_hw_if cs4281_midi_hw_if = { 152 cs4281_midi_open, 153 cs4281_midi_close, 154 cs4281_midi_output, 155 cs4281_midi_getinfo, 156 0, 157 cs428x_get_locks, 158 }; 159 #endif 160 161 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 162 cs4281_match, cs4281_attach, NULL, NULL); 163 164 static struct audio_device cs4281_device = { 165 "CS4281", 166 "", 167 "cs4281" 168 }; 169 170 171 static int 172 cs4281_match(device_t parent, cfdata_t match, void *aux) 173 { 174 struct pci_attach_args *pa; 175 176 pa = (struct pci_attach_args *)aux; 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 178 return 0; 179 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 180 return 1; 181 return 0; 182 } 183 184 static void 185 cs4281_attach(device_t parent, device_t self, void *aux) 186 { 187 struct cs428x_softc *sc; 188 struct pci_attach_args *pa; 189 pci_chipset_tag_t pc; 190 char const *intrstr; 191 pcireg_t reg; 192 char devinfo[256]; 193 int error; 194 195 sc = device_private(self); 196 pa = (struct pci_attach_args *)aux; 197 pc = pa->pa_pc; 198 aprint_naive(": Audio controller\n"); 199 200 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 201 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 202 PCI_REVISION(pa->pa_class)); 203 204 sc->sc_pc = pa->pa_pc; 205 sc->sc_pt = pa->pa_tag; 206 207 /* Map I/O register */ 208 if (pci_mapreg_map(pa, PCI_BA0, 209 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 210 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 211 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n"); 212 return; 213 } 214 if (pci_mapreg_map(pa, PCI_BA1, 215 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 216 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 217 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n"); 218 return; 219 } 220 221 sc->sc_dmatag = pa->pa_dmat; 222 223 /* power up chip */ 224 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 225 pci_activate_null)) && error != EOPNOTSUPP) { 226 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 227 return; 228 } 229 230 /* Enable the device (set bus master flag) */ 231 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 233 reg | PCI_COMMAND_MASTER_ENABLE); 234 235 #if 0 236 /* LATENCY_TIMER setting */ 237 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 238 if (PCI_LATTIMER(temp1) < 32) { 239 temp1 &= 0xffff00ff; 240 temp1 |= 0x00002000; 241 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 242 } 243 #endif 244 245 /* Map and establish the interrupt. */ 246 if (pci_intr_map(pa, &sc->intrh)) { 247 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 248 return; 249 } 250 intrstr = pci_intr_string(pc, sc->intrh); 251 252 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 253 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 254 255 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 256 cs4281_intr, sc); 257 if (sc->sc_ih == NULL) { 258 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 259 if (intrstr != NULL) 260 aprint_error(" at %s", intrstr); 261 aprint_error("\n"); 262 mutex_destroy(&sc->sc_lock); 263 mutex_destroy(&sc->sc_intr_lock); 264 return; 265 } 266 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 267 268 /* 269 * Sound System start-up 270 */ 271 if (cs4281_init(sc, 1) != 0) { 272 mutex_destroy(&sc->sc_lock); 273 mutex_destroy(&sc->sc_intr_lock); 274 return; 275 } 276 277 sc->type = TYPE_CS4281; 278 sc->halt_input = cs4281_halt_input; 279 sc->halt_output = cs4281_halt_output; 280 281 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 282 sc->dma_align = 0x10; 283 sc->hw_blocksize = sc->dma_size / 2; 284 285 /* AC 97 attachment */ 286 sc->host_if.arg = sc; 287 sc->host_if.attach = cs428x_attach_codec; 288 sc->host_if.read = cs428x_read_codec; 289 sc->host_if.write = cs428x_write_codec; 290 sc->host_if.reset = cs4281_reset_codec; 291 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 292 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n"); 293 mutex_destroy(&sc->sc_lock); 294 mutex_destroy(&sc->sc_intr_lock); 295 return; 296 } 297 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 298 299 #if NMIDI > 0 && 0 300 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 301 #endif 302 303 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 304 aprint_error_dev(self, "couldn't establish power handler\n"); 305 } 306 307 static int 308 cs4281_intr(void *p) 309 { 310 struct cs428x_softc *sc; 311 uint32_t intr, hdsr0, hdsr1; 312 char *empty_dma; 313 int handled; 314 315 sc = p; 316 handled = 0; 317 hdsr0 = 0; 318 hdsr1 = 0; 319 320 mutex_spin_enter(&sc->sc_intr_lock); 321 322 /* grab interrupt register */ 323 intr = BA0READ4(sc, CS4281_HISR); 324 325 DPRINTF(("cs4281_intr:")); 326 /* not for me */ 327 if ((intr & HISR_INTENA) == 0) { 328 /* clear the interrupt register */ 329 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 330 mutex_spin_exit(&sc->sc_intr_lock); 331 return 0; 332 } 333 334 if (intr & HISR_DMA0) 335 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 336 if (intr & HISR_DMA1) 337 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 338 /* clear the interrupt register */ 339 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 340 341 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 342 intr, hdsr0, hdsr1)); 343 344 /* Playback Interrupt */ 345 if (intr & HISR_DMA0) { 346 handled = 1; 347 if (sc->sc_prun) { 348 DPRINTF((" PB DMA 0x%x(%d)", 349 (int)BA0READ4(sc, CS4281_DCA0), 350 (int)BA0READ4(sc, CS4281_DCC0))); 351 if ((sc->sc_pi%sc->sc_pcount) == 0) 352 sc->sc_pintr(sc->sc_parg); 353 /* copy buffer */ 354 ++sc->sc_pi; 355 empty_dma = sc->sc_pdma->addr; 356 if (sc->sc_pi&1) 357 empty_dma += sc->hw_blocksize; 358 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 359 sc->sc_pn += sc->hw_blocksize; 360 if (sc->sc_pn >= sc->sc_pe) 361 sc->sc_pn = sc->sc_ps; 362 } else { 363 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n"); 364 } 365 } 366 if (intr & HISR_DMA1) { 367 handled = 1; 368 if (sc->sc_rrun) { 369 /* copy from DMA */ 370 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 371 (int)BA0READ4(sc, CS4281_DCC1))); 372 ++sc->sc_ri; 373 empty_dma = sc->sc_rdma->addr; 374 if ((sc->sc_ri & 1) == 0) 375 empty_dma += sc->hw_blocksize; 376 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 377 sc->sc_rn += sc->hw_blocksize; 378 if (sc->sc_rn >= sc->sc_re) 379 sc->sc_rn = sc->sc_rs; 380 if ((sc->sc_ri % sc->sc_rcount) == 0) 381 sc->sc_rintr(sc->sc_rarg); 382 } else { 383 aprint_error_dev(&sc->sc_dev, 384 "unexpected record intr\n"); 385 } 386 } 387 DPRINTF(("\n")); 388 389 mutex_spin_exit(&sc->sc_intr_lock); 390 391 return handled; 392 } 393 394 static int 395 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 396 { 397 398 switch (fp->index) { 399 case 0: 400 strcpy(fp->name, AudioEulinear); 401 fp->encoding = AUDIO_ENCODING_ULINEAR; 402 fp->precision = 8; 403 fp->flags = 0; 404 break; 405 case 1: 406 strcpy(fp->name, AudioEmulaw); 407 fp->encoding = AUDIO_ENCODING_ULAW; 408 fp->precision = 8; 409 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 410 break; 411 case 2: 412 strcpy(fp->name, AudioEalaw); 413 fp->encoding = AUDIO_ENCODING_ALAW; 414 fp->precision = 8; 415 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 416 break; 417 case 3: 418 strcpy(fp->name, AudioEslinear); 419 fp->encoding = AUDIO_ENCODING_SLINEAR; 420 fp->precision = 8; 421 fp->flags = 0; 422 break; 423 case 4: 424 strcpy(fp->name, AudioEslinear_le); 425 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 426 fp->precision = 16; 427 fp->flags = 0; 428 break; 429 case 5: 430 strcpy(fp->name, AudioEulinear_le); 431 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 432 fp->precision = 16; 433 fp->flags = 0; 434 break; 435 case 6: 436 strcpy(fp->name, AudioEslinear_be); 437 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 438 fp->precision = 16; 439 fp->flags = 0; 440 break; 441 case 7: 442 strcpy(fp->name, AudioEulinear_be); 443 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 444 fp->precision = 16; 445 fp->flags = 0; 446 break; 447 default: 448 return EINVAL; 449 } 450 return 0; 451 } 452 453 static int 454 cs4281_set_params(void *addr, int setmode, int usemode, 455 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 456 stream_filter_list_t *rfil) 457 { 458 audio_params_t hw; 459 struct cs428x_softc *sc; 460 audio_params_t *p; 461 stream_filter_list_t *fil; 462 int mode; 463 464 sc = addr; 465 for (mode = AUMODE_RECORD; mode != -1; 466 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 467 if ((setmode & mode) == 0) 468 continue; 469 470 p = mode == AUMODE_PLAY ? play : rec; 471 472 if (p == play) { 473 DPRINTFN(5, 474 ("play: sample=%u precision=%u channels=%u\n", 475 p->sample_rate, p->precision, p->channels)); 476 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 477 (p->precision != 8 && p->precision != 16) || 478 (p->channels != 1 && p->channels != 2)) { 479 return EINVAL; 480 } 481 } else { 482 DPRINTFN(5, 483 ("rec: sample=%u precision=%u channels=%u\n", 484 p->sample_rate, p->precision, p->channels)); 485 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 486 (p->precision != 8 && p->precision != 16) || 487 (p->channels != 1 && p->channels != 2)) { 488 return EINVAL; 489 } 490 } 491 hw = *p; 492 fil = mode == AUMODE_PLAY ? pfil : rfil; 493 494 switch (p->encoding) { 495 case AUDIO_ENCODING_SLINEAR_BE: 496 break; 497 case AUDIO_ENCODING_SLINEAR_LE: 498 break; 499 case AUDIO_ENCODING_ULINEAR_BE: 500 break; 501 case AUDIO_ENCODING_ULINEAR_LE: 502 break; 503 case AUDIO_ENCODING_ULAW: 504 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 505 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 506 : linear8_to_mulaw, &hw); 507 break; 508 case AUDIO_ENCODING_ALAW: 509 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 510 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 511 : linear8_to_alaw, &hw); 512 break; 513 default: 514 return EINVAL; 515 } 516 } 517 518 /* set sample rate */ 519 cs4281_set_dac_rate(sc, play->sample_rate); 520 cs4281_set_adc_rate(sc, rec->sample_rate); 521 return 0; 522 } 523 524 static int 525 cs4281_halt_output(void *addr) 526 { 527 struct cs428x_softc *sc; 528 529 sc = addr; 530 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 531 sc->sc_prun = 0; 532 return 0; 533 } 534 535 static int 536 cs4281_halt_input(void *addr) 537 { 538 struct cs428x_softc *sc; 539 540 sc = addr; 541 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 542 sc->sc_rrun = 0; 543 return 0; 544 } 545 546 static int 547 cs4281_getdev(void *addr, struct audio_device *retp) 548 { 549 550 *retp = cs4281_device; 551 return 0; 552 } 553 554 static int 555 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 556 void (*intr)(void *), void *arg, 557 const audio_params_t *param) 558 { 559 struct cs428x_softc *sc; 560 uint32_t fmt; 561 struct cs428x_dma *p; 562 int dma_count; 563 564 sc = addr; 565 fmt = 0; 566 #ifdef DIAGNOSTIC 567 if (sc->sc_prun) 568 printf("cs4281_trigger_output: already running\n"); 569 #endif 570 sc->sc_prun = 1; 571 572 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 573 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 574 sc->sc_pintr = intr; 575 sc->sc_parg = arg; 576 577 /* stop playback DMA */ 578 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 579 580 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 581 param->precision, param->channels, param->encoding)); 582 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 583 continue; 584 if (p == NULL) { 585 printf("cs4281_trigger_output: bad addr %p\n", start); 586 return EINVAL; 587 } 588 589 sc->sc_pcount = blksize / sc->hw_blocksize; 590 sc->sc_ps = (char *)start; 591 sc->sc_pe = (char *)end; 592 sc->sc_pdma = p; 593 sc->sc_pbuf = KERNADDR(p); 594 sc->sc_pi = 0; 595 sc->sc_pn = sc->sc_ps; 596 if (blksize >= sc->dma_size) { 597 sc->sc_pn = sc->sc_ps + sc->dma_size; 598 memcpy(sc->sc_pbuf, start, sc->dma_size); 599 ++sc->sc_pi; 600 } else { 601 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 602 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 603 } 604 605 dma_count = sc->dma_size; 606 if (param->precision != 8) 607 dma_count /= 2; /* 16 bit */ 608 if (param->channels > 1) 609 dma_count /= 2; /* Stereo */ 610 611 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 612 (int)DMAADDR(p), dma_count)); 613 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 614 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 615 616 /* set playback format */ 617 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 618 if (param->precision == 8) 619 fmt |= DMRn_SIZE8; 620 if (param->channels == 1) 621 fmt |= DMRn_MONO; 622 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 623 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 624 fmt |= DMRn_BEND; 625 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 626 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 627 fmt |= DMRn_USIGN; 628 BA0WRITE4(sc, CS4281_DMR0, fmt); 629 630 /* set sample rate */ 631 sc->sc_prate = param->sample_rate; 632 cs4281_set_dac_rate(sc, param->sample_rate); 633 634 /* start DMA */ 635 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 636 /* Enable interrupts */ 637 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 638 639 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 640 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 641 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 642 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 643 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 644 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 645 BA0READ4(sc, CS4281_DACSR))); 646 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 647 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 648 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 649 650 return 0; 651 } 652 653 static int 654 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 655 void (*intr)(void *), void *arg, 656 const audio_params_t *param) 657 { 658 struct cs428x_softc *sc; 659 struct cs428x_dma *p; 660 uint32_t fmt; 661 int dma_count; 662 663 sc = addr; 664 fmt = 0; 665 #ifdef DIAGNOSTIC 666 if (sc->sc_rrun) 667 printf("cs4281_trigger_input: already running\n"); 668 #endif 669 sc->sc_rrun = 1; 670 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 671 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 672 sc->sc_rintr = intr; 673 sc->sc_rarg = arg; 674 675 /* stop recording DMA */ 676 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 677 678 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 679 continue; 680 if (!p) { 681 printf("cs4281_trigger_input: bad addr %p\n", start); 682 return EINVAL; 683 } 684 685 sc->sc_rcount = blksize / sc->hw_blocksize; 686 sc->sc_rs = (char *)start; 687 sc->sc_re = (char *)end; 688 sc->sc_rdma = p; 689 sc->sc_rbuf = KERNADDR(p); 690 sc->sc_ri = 0; 691 sc->sc_rn = sc->sc_rs; 692 693 dma_count = sc->dma_size; 694 if (param->precision != 8) 695 dma_count /= 2; 696 if (param->channels > 1) 697 dma_count /= 2; 698 699 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 700 (int)DMAADDR(p), dma_count)); 701 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 702 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 703 704 /* set recording format */ 705 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 706 if (param->precision == 8) 707 fmt |= DMRn_SIZE8; 708 if (param->channels == 1) 709 fmt |= DMRn_MONO; 710 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 711 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 712 fmt |= DMRn_BEND; 713 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 714 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 715 fmt |= DMRn_USIGN; 716 BA0WRITE4(sc, CS4281_DMR1, fmt); 717 718 /* set sample rate */ 719 sc->sc_rrate = param->sample_rate; 720 cs4281_set_adc_rate(sc, param->sample_rate); 721 722 /* Start DMA */ 723 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 724 /* Enable interrupts */ 725 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 726 727 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 728 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 729 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 730 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 731 732 return 0; 733 } 734 735 static bool 736 cs4281_suspend(device_t dv, const pmf_qual_t *qual) 737 { 738 struct cs428x_softc *sc = device_private(dv); 739 740 mutex_enter(&sc->sc_lock); 741 mutex_spin_exit(&sc->sc_intr_lock); 742 743 /* save current playback status */ 744 if (sc->sc_prun) { 745 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 746 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 747 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 748 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 749 } 750 751 /* save current capture status */ 752 if (sc->sc_rrun) { 753 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 754 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 755 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 756 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 757 } 758 /* Stop DMA */ 759 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 760 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 761 762 mutex_spin_exit(&sc->sc_intr_lock); 763 mutex_exit(&sc->sc_lock); 764 765 return true; 766 } 767 768 static bool 769 cs4281_resume(device_t dv, const pmf_qual_t *qual) 770 { 771 struct cs428x_softc *sc = device_private(dv); 772 773 mutex_enter(&sc->sc_lock); 774 mutex_spin_enter(&sc->sc_intr_lock); 775 776 cs4281_init(sc, 0); 777 cs4281_reset_codec(sc); 778 779 /* restore ac97 registers */ 780 mutex_spin_exit(&sc->sc_intr_lock); 781 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 782 mutex_spin_enter(&sc->sc_intr_lock); 783 784 /* restore DMA related status */ 785 if (sc->sc_prun) { 786 cs4281_set_dac_rate(sc, sc->sc_prate); 787 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 788 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 789 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 790 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 791 } 792 if (sc->sc_rrun) { 793 cs4281_set_adc_rate(sc, sc->sc_rrate); 794 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 795 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 796 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 797 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 798 } 799 /* enable intterupts */ 800 if (sc->sc_prun || sc->sc_rrun) 801 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 802 803 mutex_spin_exit(&sc->sc_intr_lock); 804 mutex_exit(&sc->sc_lock); 805 806 return true; 807 } 808 809 /* control AC97 codec */ 810 static int 811 cs4281_reset_codec(void *addr) 812 { 813 struct cs428x_softc *sc; 814 uint16_t data; 815 uint32_t dat32; 816 int n; 817 818 sc = addr; 819 820 DPRINTFN(3, ("cs4281_reset_codec\n")); 821 822 /* Reset codec */ 823 BA0WRITE4(sc, CS428X_ACCTL, 0); 824 delay(50); /* delay 50us */ 825 826 BA0WRITE4(sc, CS4281_SPMC, 0); 827 delay(100); /* delay 100us */ 828 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 829 #if defined(ENABLE_SECONDARY_CODEC) 830 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 831 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 832 #endif 833 delay(50000); /* XXX: delay 50ms */ 834 835 /* Enable ASYNC generation */ 836 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 837 838 /* Wait for codec ready. Linux driver waits 50ms here */ 839 n = 0; 840 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 841 delay(100); 842 if (++n > 1000) { 843 printf("reset_codec: AC97 codec ready timeout\n"); 844 return ETIMEDOUT; 845 } 846 } 847 #if defined(ENABLE_SECONDARY_CODEC) 848 /* secondary codec ready*/ 849 n = 0; 850 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 851 delay(100); 852 if (++n > 1000) 853 return 0; 854 } 855 #endif 856 /* Set the serial timing configuration */ 857 /* XXX: undocumented but the Linux driver do this */ 858 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 859 860 /* Wait for codec ready signal */ 861 n = 0; 862 do { 863 delay(1000); 864 if (++n > 1000) { 865 aprint_error_dev(&sc->sc_dev, 866 "timeout waiting for codec ready\n"); 867 return ETIMEDOUT; 868 } 869 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 870 } while (dat32 == 0); 871 872 /* Enable Valid Frame output on ASDOUT */ 873 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 874 875 /* Wait until codec calibration is finished. Codec register 26h */ 876 n = 0; 877 do { 878 delay(1); 879 if (++n > 1000) { 880 aprint_error_dev(&sc->sc_dev, 881 "timeout waiting for codec calibration\n"); 882 return ETIMEDOUT; 883 } 884 cs428x_read_codec(sc, AC97_REG_POWER, &data); 885 } while ((data & 0x0f) != 0x0f); 886 887 /* Set the serial timing configuration again */ 888 /* XXX: undocumented but the Linux driver do this */ 889 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 890 891 /* Wait until we've sampled input slots 3 & 4 as valid */ 892 n = 0; 893 do { 894 delay(1000); 895 if (++n > 1000) { 896 aprint_error_dev(&sc->sc_dev, "timeout waiting for " 897 "sampled input slots as valid\n"); 898 return ETIMEDOUT; 899 } 900 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 901 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 902 903 /* Start digital data transfer of audio data to the codec */ 904 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 905 return 0; 906 } 907 908 909 /* Internal functions */ 910 911 /* convert sample rate to register value */ 912 static uint8_t 913 cs4281_sr2regval(int rate) 914 { 915 uint8_t retval; 916 917 /* We don't have to change here. but anyway ... */ 918 if (rate > 48000) 919 rate = 48000; 920 if (rate < 6023) 921 rate = 6023; 922 923 switch (rate) { 924 case 8000: 925 retval = 5; 926 break; 927 case 11025: 928 retval = 4; 929 break; 930 case 16000: 931 retval = 3; 932 break; 933 case 22050: 934 retval = 2; 935 break; 936 case 44100: 937 retval = 1; 938 break; 939 case 48000: 940 retval = 0; 941 break; 942 default: 943 retval = 1536000/rate; /* == 24576000/(rate*16) */ 944 } 945 return retval; 946 } 947 948 static void 949 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 950 { 951 952 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 953 } 954 955 static void 956 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 957 { 958 959 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 960 } 961 962 static int 963 cs4281_init(struct cs428x_softc *sc, int init) 964 { 965 int n; 966 uint16_t data; 967 uint32_t dat32; 968 969 /* set "Configuration Write Protect" register to 970 * 0x4281 to allow to write */ 971 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 972 973 /* 974 * Unset "Full Power-Down bit of Extended PCI Power Management 975 * Control" register to release the reset state. 976 */ 977 dat32 = BA0READ4(sc, CS4281_EPPMC); 978 if (dat32 & EPPMC_FPDN) { 979 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 980 } 981 982 /* Start PLL out in known state */ 983 BA0WRITE4(sc, CS4281_CLKCR1, 0); 984 /* Start serial ports out in known state */ 985 BA0WRITE4(sc, CS4281_SERMC, 0); 986 987 /* Reset codec */ 988 BA0WRITE4(sc, CS428X_ACCTL, 0); 989 delay(50); /* delay 50us */ 990 991 BA0WRITE4(sc, CS4281_SPMC, 0); 992 delay(100); /* delay 100us */ 993 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 994 #if defined(ENABLE_SECONDARY_CODEC) 995 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 996 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 997 #endif 998 delay(50000); /* XXX: delay 50ms */ 999 1000 /* Turn on Sound System clocks based on ABITCLK */ 1001 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 1002 delay(50000); /* XXX: delay 50ms */ 1003 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1004 1005 /* Set enables for sections that are needed in the SSPM registers */ 1006 BA0WRITE4(sc, CS4281_SSPM, 1007 SSPM_MIXEN | /* Mixer */ 1008 SSPM_CSRCEN | /* Capture SRC */ 1009 SSPM_PSRCEN | /* Playback SRC */ 1010 SSPM_JSEN | /* Joystick */ 1011 SSPM_ACLEN | /* AC LINK */ 1012 SSPM_FMEN /* FM */ 1013 ); 1014 1015 /* Wait for clock stabilization */ 1016 n = 0; 1017 #if 1 1018 /* what document says */ 1019 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1020 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1021 delay(100); 1022 if (++n > 1000) { 1023 aprint_error_dev(&sc->sc_dev, 1024 "timeout waiting for clock stabilization\n"); 1025 return -1; 1026 } 1027 } 1028 #else 1029 /* Cirrus driver for Linux does */ 1030 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1031 delay(1000); 1032 if (++n > 1000) { 1033 aprint_error_dev(&sc->sc_dev, 1034 "timeout waiting for clock stabilization\n"); 1035 return -1; 1036 } 1037 } 1038 #endif 1039 1040 /* Enable ASYNC generation */ 1041 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1042 1043 /* Wait for codec ready. Linux driver waits 50ms here */ 1044 n = 0; 1045 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1046 delay(100); 1047 if (++n > 1000) { 1048 aprint_error_dev(&sc->sc_dev, 1049 "timeout waiting for codec ready\n"); 1050 return -1; 1051 } 1052 } 1053 1054 #if defined(ENABLE_SECONDARY_CODEC) 1055 /* secondary codec ready*/ 1056 n = 0; 1057 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1058 delay(100); 1059 if (++n > 1000) { 1060 aprint_error_dev(&sc->sc_dev, 1061 "timeout waiting for secondary codec ready\n"); 1062 return -1; 1063 } 1064 } 1065 #endif 1066 1067 /* Set the serial timing configuration */ 1068 /* XXX: undocumented but the Linux driver do this */ 1069 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1070 1071 /* Wait for codec ready signal */ 1072 n = 0; 1073 do { 1074 delay(1000); 1075 if (++n > 1000) { 1076 aprint_error_dev(&sc->sc_dev, 1077 "timeout waiting for codec ready\n"); 1078 return -1; 1079 } 1080 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1081 } while (dat32 == 0); 1082 1083 /* Enable Valid Frame output on ASDOUT */ 1084 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1085 1086 /* Wait until codec calibration is finished. codec register 26h */ 1087 n = 0; 1088 do { 1089 delay(1); 1090 if (++n > 1000) { 1091 aprint_error_dev(&sc->sc_dev, 1092 "timeout waiting for codec calibration\n"); 1093 return -1; 1094 } 1095 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1096 } while ((data & 0x0f) != 0x0f); 1097 1098 /* Set the serial timing configuration again */ 1099 /* XXX: undocumented but the Linux driver do this */ 1100 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1101 1102 /* Wait until we've sampled input slots 3 & 4 as valid */ 1103 n = 0; 1104 do { 1105 delay(1000); 1106 if (++n > 1000) { 1107 aprint_error_dev(&sc->sc_dev, "timeout waiting for " 1108 "sampled input slots as valid\n"); 1109 return -1; 1110 } 1111 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1112 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1113 1114 /* Start digital data transfer of audio data to the codec */ 1115 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1116 1117 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1118 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1119 1120 /* Power on the DAC */ 1121 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1122 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1123 1124 /* Wait until we sample a DAC ready state. 1125 * Not documented, but Linux driver does. 1126 */ 1127 for (n = 0; n < 32; ++n) { 1128 delay(1000); 1129 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1130 if (data & 0x02) 1131 break; 1132 } 1133 1134 /* Power on the ADC */ 1135 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1136 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1137 1138 /* Wait until we sample ADC ready state. 1139 * Not documented, but Linux driver does. 1140 */ 1141 for (n = 0; n < 32; ++n) { 1142 delay(1000); 1143 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1144 if (data & 0x01) 1145 break; 1146 } 1147 1148 #if 0 1149 /* Initialize AC-Link features */ 1150 /* variable sample-rate support */ 1151 mem = BA0READ4(sc, CS4281_SERMC); 1152 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1153 BA0WRITE4(sc, CS4281_SERMC, mem); 1154 /* XXX: more... */ 1155 1156 /* Initialize SSCR register features */ 1157 /* XXX: hardware volume setting */ 1158 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1159 #endif 1160 1161 /* disable Sound Blaster Pro emulation */ 1162 /* XXX: 1163 * Cannot set since the documents does not describe which bit is 1164 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1165 * we can ignore it.*/ 1166 #if 0 1167 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1168 #endif 1169 1170 /* map AC97 PCM playback to DMA Channel 0 */ 1171 /* Reset FEN bit to setup first */ 1172 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1173 /* 1174 *| RS[4:0]/| | 1175 *| LS[4:0] | AC97 | Slot Function 1176 *|---------+--------+-------------------- 1177 *| 0 | 3 | Left PCM Playback 1178 *| 1 | 4 | Right PCM Playback 1179 *| 2 | 5 | Phone Line 1 DAC 1180 *| 3 | 6 | Center PCM Playback 1181 *.... 1182 * quoted from Table 29(p109) 1183 */ 1184 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1185 0x00 << 16 | /* LS[4:0] = 0 see above */ 1186 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1187 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1188 BA0WRITE4(sc, CS4281_FCR0, dat32); 1189 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1190 1191 /* map AC97 PCM record to DMA Channel 1 */ 1192 /* Reset FEN bit to setup first */ 1193 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1194 /* 1195 *| RS[4:0]/| 1196 *| LS[4:0] | AC97 | Slot Function 1197 *|---------+------+------------------- 1198 *| 10 | 3 | Left PCM Record 1199 *| 11 | 4 | Right PCM Record 1200 *| 12 | 5 | Phone Line 1 ADC 1201 *| 13 | 6 | Mic ADC 1202 *.... 1203 * quoted from Table 30(p109) 1204 */ 1205 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1206 0x0a << 16 | /* LS[4:0] = 10 See above */ 1207 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1208 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1209 1210 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1211 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1212 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1213 1214 #if 0 1215 /* Disable DMA Channel 2, 3 */ 1216 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1217 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1218 #endif 1219 1220 /* Set the SRC Slot Assignment accordingly */ 1221 /*| PLSS[4:0]/ 1222 *| PRSS[4:0] | AC97 | Slot Function 1223 *|-----------+------+---------------- 1224 *| 0 | 3 | Left PCM Playback 1225 *| 1 | 4 | Right PCM Playback 1226 *| 2 | 5 | phone line 1 DAC 1227 *| 3 | 6 | Center PCM Playback 1228 *| 4 | 7 | Left Surround PCM Playback 1229 *| 5 | 8 | Right Surround PCM Playback 1230 *...... 1231 * 1232 *| CLSS[4:0]/ 1233 *| CRSS[4:0] | AC97 | Codec |Slot Function 1234 *|-----------+------+-------+----------------- 1235 *| 10 | 3 |Primary| Left PCM Record 1236 *| 11 | 4 |Primary| Right PCM Record 1237 *| 12 | 5 |Primary| Phone Line 1 ADC 1238 *| 13 | 6 |Primary| Mic ADC 1239 *|..... 1240 *| 20 | 3 | Sec. | Left PCM Record 1241 *| 21 | 4 | Sec. | Right PCM Record 1242 *| 22 | 5 | Sec. | Phone Line 1 ADC 1243 *| 23 | 6 | Sec. | Mic ADC 1244 */ 1245 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1246 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1247 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1248 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1249 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1250 1251 /* Set interrupt to occurred at Half and Full terminal 1252 * count interrupt enable for DMA channel 0 and 1. 1253 * To keep DMA stop, set MSK. 1254 */ 1255 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1256 BA0WRITE4(sc, CS4281_DCR0, dat32); 1257 BA0WRITE4(sc, CS4281_DCR1, dat32); 1258 1259 /* Set Auto-Initialize Contorl enable */ 1260 BA0WRITE4(sc, CS4281_DMR0, 1261 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1262 BA0WRITE4(sc, CS4281_DMR1, 1263 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1264 1265 /* Clear DMA Mask in HIMR */ 1266 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1267 BA0WRITE4(sc, CS4281_HIMR, 1268 BA0READ4(sc, CS4281_HIMR) & dat32); 1269 1270 /* set current status */ 1271 if (init != 0) { 1272 sc->sc_prun = 0; 1273 sc->sc_rrun = 0; 1274 } 1275 1276 /* setup playback volume */ 1277 BA0WRITE4(sc, CS4281_PPRVC, 7); 1278 BA0WRITE4(sc, CS4281_PPLVC, 7); 1279 1280 return 0; 1281 } 1282