1 /* $NetBSD: cs4281.c,v 1.36 2007/12/09 20:28:07 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.36 2007/12/09 20:28:07 jmcneill Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <sys/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(struct device *, struct cfdata *, void *); 84 static void cs4281_attach(struct device *, struct device *, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static bool cs4281_suspend(device_t); 110 static bool cs4281_resume(device_t); 111 112 static const struct audio_hw_if cs4281_hw_if = { 113 NULL, /* open */ 114 NULL, /* close */ 115 NULL, 116 cs4281_query_encoding, 117 cs4281_set_params, 118 cs428x_round_blocksize, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 NULL, 124 cs4281_halt_output, 125 cs4281_halt_input, 126 NULL, 127 cs4281_getdev, 128 NULL, 129 cs428x_mixer_set_port, 130 cs428x_mixer_get_port, 131 cs428x_query_devinfo, 132 cs428x_malloc, 133 cs428x_free, 134 cs428x_round_buffersize, 135 cs428x_mappage, 136 cs428x_get_props, 137 cs4281_trigger_output, 138 cs4281_trigger_input, 139 NULL, 140 NULL, 141 }; 142 143 #if NMIDI > 0 && 0 144 /* Midi Interface */ 145 static void cs4281_midi_close(void*); 146 static void cs4281_midi_getinfo(void *, struct midi_info *); 147 static int cs4281_midi_open(void *, int, void (*)(void *, int), 148 void (*)(void *), void *); 149 static int cs4281_midi_output(void *, int); 150 151 static const struct midi_hw_if cs4281_midi_hw_if = { 152 cs4281_midi_open, 153 cs4281_midi_close, 154 cs4281_midi_output, 155 cs4281_midi_getinfo, 156 0, 157 }; 158 #endif 159 160 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 161 cs4281_match, cs4281_attach, NULL, NULL); 162 163 static struct audio_device cs4281_device = { 164 "CS4281", 165 "", 166 "cs4281" 167 }; 168 169 170 static int 171 cs4281_match(struct device *parent, struct cfdata *match, 172 void *aux) 173 { 174 struct pci_attach_args *pa; 175 176 pa = (struct pci_attach_args *)aux; 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 178 return 0; 179 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 180 return 1; 181 return 0; 182 } 183 184 static void 185 cs4281_attach(struct device *parent, struct device *self, void *aux) 186 { 187 struct cs428x_softc *sc; 188 struct pci_attach_args *pa; 189 pci_chipset_tag_t pc; 190 char const *intrstr; 191 pcireg_t reg; 192 char devinfo[256]; 193 int error; 194 195 sc = (struct cs428x_softc *)self; 196 pa = (struct pci_attach_args *)aux; 197 pc = pa->pa_pc; 198 aprint_naive(": Audio controller\n"); 199 200 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 201 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 202 PCI_REVISION(pa->pa_class)); 203 204 sc->sc_pc = pa->pa_pc; 205 sc->sc_pt = pa->pa_tag; 206 207 /* Map I/O register */ 208 if (pci_mapreg_map(pa, PCI_BA0, 209 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 210 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 211 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 212 return; 213 } 214 if (pci_mapreg_map(pa, PCI_BA1, 215 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 216 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 217 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 218 return; 219 } 220 221 sc->sc_dmatag = pa->pa_dmat; 222 223 /* power up chip */ 224 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 225 pci_activate_null)) && error != EOPNOTSUPP) { 226 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 227 error); 228 return; 229 } 230 231 /* Enable the device (set bus master flag) */ 232 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 233 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 234 reg | PCI_COMMAND_MASTER_ENABLE); 235 236 #if 0 237 /* LATENCY_TIMER setting */ 238 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 239 if (PCI_LATTIMER(temp1) < 32) { 240 temp1 &= 0xffff00ff; 241 temp1 |= 0x00002000; 242 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 243 } 244 #endif 245 246 /* Map and establish the interrupt. */ 247 if (pci_intr_map(pa, &sc->intrh)) { 248 aprint_error("%s: couldn't map interrupt\n", 249 sc->sc_dev.dv_xname); 250 return; 251 } 252 intrstr = pci_intr_string(pc, sc->intrh); 253 254 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 255 cs4281_intr, sc); 256 if (sc->sc_ih == NULL) { 257 aprint_error("%s: couldn't establish interrupt", 258 sc->sc_dev.dv_xname); 259 if (intrstr != NULL) 260 aprint_normal(" at %s", intrstr); 261 aprint_normal("\n"); 262 return; 263 } 264 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 265 266 /* 267 * Sound System start-up 268 */ 269 if (cs4281_init(sc, 1) != 0) 270 return; 271 272 sc->type = TYPE_CS4281; 273 sc->halt_input = cs4281_halt_input; 274 sc->halt_output = cs4281_halt_output; 275 276 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 277 sc->dma_align = 0x10; 278 sc->hw_blocksize = sc->dma_size / 2; 279 280 /* AC 97 attachment */ 281 sc->host_if.arg = sc; 282 sc->host_if.attach = cs428x_attach_codec; 283 sc->host_if.read = cs428x_read_codec; 284 sc->host_if.write = cs428x_write_codec; 285 sc->host_if.reset = cs4281_reset_codec; 286 if (ac97_attach(&sc->host_if, self) != 0) { 287 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 288 return; 289 } 290 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 291 292 #if NMIDI > 0 && 0 293 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 294 #endif 295 296 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 297 aprint_error_dev(self, "couldn't establish power handler\n"); 298 } 299 300 static int 301 cs4281_intr(void *p) 302 { 303 struct cs428x_softc *sc; 304 uint32_t intr, hdsr0, hdsr1; 305 char *empty_dma; 306 int handled; 307 308 sc = p; 309 handled = 0; 310 hdsr0 = 0; 311 hdsr1 = 0; 312 313 /* grab interrupt register */ 314 intr = BA0READ4(sc, CS4281_HISR); 315 316 DPRINTF(("cs4281_intr:")); 317 /* not for me */ 318 if ((intr & HISR_INTENA) == 0) { 319 /* clear the interrupt register */ 320 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 321 return 0; 322 } 323 324 if (intr & HISR_DMA0) 325 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 326 if (intr & HISR_DMA1) 327 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 328 /* clear the interrupt register */ 329 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 330 331 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 332 intr, hdsr0, hdsr1)); 333 334 /* Playback Interrupt */ 335 if (intr & HISR_DMA0) { 336 handled = 1; 337 if (sc->sc_prun) { 338 DPRINTF((" PB DMA 0x%x(%d)", 339 (int)BA0READ4(sc, CS4281_DCA0), 340 (int)BA0READ4(sc, CS4281_DCC0))); 341 if ((sc->sc_pi%sc->sc_pcount) == 0) 342 sc->sc_pintr(sc->sc_parg); 343 /* copy buffer */ 344 ++sc->sc_pi; 345 empty_dma = sc->sc_pdma->addr; 346 if (sc->sc_pi&1) 347 empty_dma += sc->hw_blocksize; 348 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 349 sc->sc_pn += sc->hw_blocksize; 350 if (sc->sc_pn >= sc->sc_pe) 351 sc->sc_pn = sc->sc_ps; 352 } else { 353 printf("%s: unexpected play intr\n", 354 sc->sc_dev.dv_xname); 355 } 356 } 357 if (intr & HISR_DMA1) { 358 handled = 1; 359 if (sc->sc_rrun) { 360 /* copy from DMA */ 361 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 362 (int)BA0READ4(sc, CS4281_DCC1))); 363 ++sc->sc_ri; 364 empty_dma = sc->sc_rdma->addr; 365 if ((sc->sc_ri & 1) == 0) 366 empty_dma += sc->hw_blocksize; 367 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 368 sc->sc_rn += sc->hw_blocksize; 369 if (sc->sc_rn >= sc->sc_re) 370 sc->sc_rn = sc->sc_rs; 371 if ((sc->sc_ri % sc->sc_rcount) == 0) 372 sc->sc_rintr(sc->sc_rarg); 373 } else { 374 printf("%s: unexpected record intr\n", 375 sc->sc_dev.dv_xname); 376 } 377 } 378 DPRINTF(("\n")); 379 380 return handled; 381 } 382 383 static int 384 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 385 { 386 387 switch (fp->index) { 388 case 0: 389 strcpy(fp->name, AudioEulinear); 390 fp->encoding = AUDIO_ENCODING_ULINEAR; 391 fp->precision = 8; 392 fp->flags = 0; 393 break; 394 case 1: 395 strcpy(fp->name, AudioEmulaw); 396 fp->encoding = AUDIO_ENCODING_ULAW; 397 fp->precision = 8; 398 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 399 break; 400 case 2: 401 strcpy(fp->name, AudioEalaw); 402 fp->encoding = AUDIO_ENCODING_ALAW; 403 fp->precision = 8; 404 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 405 break; 406 case 3: 407 strcpy(fp->name, AudioEslinear); 408 fp->encoding = AUDIO_ENCODING_SLINEAR; 409 fp->precision = 8; 410 fp->flags = 0; 411 break; 412 case 4: 413 strcpy(fp->name, AudioEslinear_le); 414 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 415 fp->precision = 16; 416 fp->flags = 0; 417 break; 418 case 5: 419 strcpy(fp->name, AudioEulinear_le); 420 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 421 fp->precision = 16; 422 fp->flags = 0; 423 break; 424 case 6: 425 strcpy(fp->name, AudioEslinear_be); 426 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 427 fp->precision = 16; 428 fp->flags = 0; 429 break; 430 case 7: 431 strcpy(fp->name, AudioEulinear_be); 432 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 433 fp->precision = 16; 434 fp->flags = 0; 435 break; 436 default: 437 return EINVAL; 438 } 439 return 0; 440 } 441 442 static int 443 cs4281_set_params(void *addr, int setmode, int usemode, 444 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 445 stream_filter_list_t *rfil) 446 { 447 audio_params_t hw; 448 struct cs428x_softc *sc; 449 audio_params_t *p; 450 stream_filter_list_t *fil; 451 int mode; 452 453 sc = addr; 454 for (mode = AUMODE_RECORD; mode != -1; 455 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 456 if ((setmode & mode) == 0) 457 continue; 458 459 p = mode == AUMODE_PLAY ? play : rec; 460 461 if (p == play) { 462 DPRINTFN(5, 463 ("play: sample=%u precision=%u channels=%u\n", 464 p->sample_rate, p->precision, p->channels)); 465 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 466 (p->precision != 8 && p->precision != 16) || 467 (p->channels != 1 && p->channels != 2)) { 468 return EINVAL; 469 } 470 } else { 471 DPRINTFN(5, 472 ("rec: sample=%u precision=%u channels=%u\n", 473 p->sample_rate, p->precision, p->channels)); 474 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 475 (p->precision != 8 && p->precision != 16) || 476 (p->channels != 1 && p->channels != 2)) { 477 return EINVAL; 478 } 479 } 480 hw = *p; 481 fil = mode == AUMODE_PLAY ? pfil : rfil; 482 483 switch (p->encoding) { 484 case AUDIO_ENCODING_SLINEAR_BE: 485 break; 486 case AUDIO_ENCODING_SLINEAR_LE: 487 break; 488 case AUDIO_ENCODING_ULINEAR_BE: 489 break; 490 case AUDIO_ENCODING_ULINEAR_LE: 491 break; 492 case AUDIO_ENCODING_ULAW: 493 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 494 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 495 : linear8_to_mulaw, &hw); 496 break; 497 case AUDIO_ENCODING_ALAW: 498 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 499 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 500 : linear8_to_alaw, &hw); 501 break; 502 default: 503 return EINVAL; 504 } 505 } 506 507 /* set sample rate */ 508 cs4281_set_dac_rate(sc, play->sample_rate); 509 cs4281_set_adc_rate(sc, rec->sample_rate); 510 return 0; 511 } 512 513 static int 514 cs4281_halt_output(void *addr) 515 { 516 struct cs428x_softc *sc; 517 518 sc = addr; 519 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 520 sc->sc_prun = 0; 521 return 0; 522 } 523 524 static int 525 cs4281_halt_input(void *addr) 526 { 527 struct cs428x_softc *sc; 528 529 sc = addr; 530 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 531 sc->sc_rrun = 0; 532 return 0; 533 } 534 535 static int 536 cs4281_getdev(void *addr, struct audio_device *retp) 537 { 538 539 *retp = cs4281_device; 540 return 0; 541 } 542 543 static int 544 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 545 void (*intr)(void *), void *arg, 546 const audio_params_t *param) 547 { 548 struct cs428x_softc *sc; 549 uint32_t fmt; 550 struct cs428x_dma *p; 551 int dma_count; 552 553 sc = addr; 554 fmt = 0; 555 #ifdef DIAGNOSTIC 556 if (sc->sc_prun) 557 printf("cs4281_trigger_output: already running\n"); 558 #endif 559 sc->sc_prun = 1; 560 561 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 562 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 563 sc->sc_pintr = intr; 564 sc->sc_parg = arg; 565 566 /* stop playback DMA */ 567 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 568 569 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 570 param->precision, param->channels, param->encoding)); 571 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 572 continue; 573 if (p == NULL) { 574 printf("cs4281_trigger_output: bad addr %p\n", start); 575 return EINVAL; 576 } 577 578 sc->sc_pcount = blksize / sc->hw_blocksize; 579 sc->sc_ps = (char *)start; 580 sc->sc_pe = (char *)end; 581 sc->sc_pdma = p; 582 sc->sc_pbuf = KERNADDR(p); 583 sc->sc_pi = 0; 584 sc->sc_pn = sc->sc_ps; 585 if (blksize >= sc->dma_size) { 586 sc->sc_pn = sc->sc_ps + sc->dma_size; 587 memcpy(sc->sc_pbuf, start, sc->dma_size); 588 ++sc->sc_pi; 589 } else { 590 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 591 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 592 } 593 594 dma_count = sc->dma_size; 595 if (param->precision != 8) 596 dma_count /= 2; /* 16 bit */ 597 if (param->channels > 1) 598 dma_count /= 2; /* Stereo */ 599 600 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 601 (int)DMAADDR(p), dma_count)); 602 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 603 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 604 605 /* set playback format */ 606 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 607 if (param->precision == 8) 608 fmt |= DMRn_SIZE8; 609 if (param->channels == 1) 610 fmt |= DMRn_MONO; 611 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 612 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 613 fmt |= DMRn_BEND; 614 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 615 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 616 fmt |= DMRn_USIGN; 617 BA0WRITE4(sc, CS4281_DMR0, fmt); 618 619 /* set sample rate */ 620 sc->sc_prate = param->sample_rate; 621 cs4281_set_dac_rate(sc, param->sample_rate); 622 623 /* start DMA */ 624 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 625 /* Enable interrupts */ 626 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 627 628 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 629 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 630 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 631 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 632 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 633 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 634 BA0READ4(sc, CS4281_DACSR))); 635 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 636 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 637 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 638 639 return 0; 640 } 641 642 static int 643 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 644 void (*intr)(void *), void *arg, 645 const audio_params_t *param) 646 { 647 struct cs428x_softc *sc; 648 struct cs428x_dma *p; 649 uint32_t fmt; 650 int dma_count; 651 652 sc = addr; 653 fmt = 0; 654 #ifdef DIAGNOSTIC 655 if (sc->sc_rrun) 656 printf("cs4281_trigger_input: already running\n"); 657 #endif 658 sc->sc_rrun = 1; 659 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 660 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 661 sc->sc_rintr = intr; 662 sc->sc_rarg = arg; 663 664 /* stop recording DMA */ 665 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 666 667 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 668 continue; 669 if (!p) { 670 printf("cs4281_trigger_input: bad addr %p\n", start); 671 return EINVAL; 672 } 673 674 sc->sc_rcount = blksize / sc->hw_blocksize; 675 sc->sc_rs = (char *)start; 676 sc->sc_re = (char *)end; 677 sc->sc_rdma = p; 678 sc->sc_rbuf = KERNADDR(p); 679 sc->sc_ri = 0; 680 sc->sc_rn = sc->sc_rs; 681 682 dma_count = sc->dma_size; 683 if (param->precision != 8) 684 dma_count /= 2; 685 if (param->channels > 1) 686 dma_count /= 2; 687 688 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 689 (int)DMAADDR(p), dma_count)); 690 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 691 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 692 693 /* set recording format */ 694 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 695 if (param->precision == 8) 696 fmt |= DMRn_SIZE8; 697 if (param->channels == 1) 698 fmt |= DMRn_MONO; 699 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 700 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 701 fmt |= DMRn_BEND; 702 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 703 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 704 fmt |= DMRn_USIGN; 705 BA0WRITE4(sc, CS4281_DMR1, fmt); 706 707 /* set sample rate */ 708 sc->sc_rrate = param->sample_rate; 709 cs4281_set_adc_rate(sc, param->sample_rate); 710 711 /* Start DMA */ 712 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 713 /* Enable interrupts */ 714 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 715 716 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 717 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 718 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 719 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 720 721 return 0; 722 } 723 724 static bool 725 cs4281_suspend(device_t dv) 726 { 727 struct cs428x_softc *sc = device_private(dv); 728 729 /* save current playback status */ 730 if (sc->sc_prun) { 731 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 732 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 733 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 734 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 735 } 736 737 /* save current capture status */ 738 if (sc->sc_rrun) { 739 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 740 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 741 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 742 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 743 } 744 /* Stop DMA */ 745 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 746 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 747 748 return true; 749 } 750 751 static bool 752 cs4281_resume(device_t dv) 753 { 754 struct cs428x_softc *sc = device_private(dv); 755 756 cs4281_init(sc, 0); 757 cs4281_reset_codec(sc); 758 759 /* restore ac97 registers */ 760 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 761 762 /* restore DMA related status */ 763 if (sc->sc_prun) { 764 cs4281_set_dac_rate(sc, sc->sc_prate); 765 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 766 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 767 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 768 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 769 } 770 if (sc->sc_rrun) { 771 cs4281_set_adc_rate(sc, sc->sc_rrate); 772 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 773 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 774 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 775 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 776 } 777 /* enable intterupts */ 778 if (sc->sc_prun || sc->sc_rrun) 779 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 780 781 return true; 782 } 783 784 /* control AC97 codec */ 785 static int 786 cs4281_reset_codec(void *addr) 787 { 788 struct cs428x_softc *sc; 789 uint16_t data; 790 uint32_t dat32; 791 int n; 792 793 sc = addr; 794 795 DPRINTFN(3, ("cs4281_reset_codec\n")); 796 797 /* Reset codec */ 798 BA0WRITE4(sc, CS428X_ACCTL, 0); 799 delay(50); /* delay 50us */ 800 801 BA0WRITE4(sc, CS4281_SPMC, 0); 802 delay(100); /* delay 100us */ 803 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 804 #if defined(ENABLE_SECONDARY_CODEC) 805 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 806 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 807 #endif 808 delay(50000); /* XXX: delay 50ms */ 809 810 /* Enable ASYNC generation */ 811 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 812 813 /* Wait for codec ready. Linux driver waits 50ms here */ 814 n = 0; 815 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 816 delay(100); 817 if (++n > 1000) { 818 printf("reset_codec: AC97 codec ready timeout\n"); 819 return ETIMEDOUT; 820 } 821 } 822 #if defined(ENABLE_SECONDARY_CODEC) 823 /* secondary codec ready*/ 824 n = 0; 825 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 826 delay(100); 827 if (++n > 1000) 828 return 0; 829 } 830 #endif 831 /* Set the serial timing configuration */ 832 /* XXX: undocumented but the Linux driver do this */ 833 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 834 835 /* Wait for codec ready signal */ 836 n = 0; 837 do { 838 delay(1000); 839 if (++n > 1000) { 840 printf("%s: timeout waiting for codec ready\n", 841 sc->sc_dev.dv_xname); 842 return ETIMEDOUT; 843 } 844 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 845 } while (dat32 == 0); 846 847 /* Enable Valid Frame output on ASDOUT */ 848 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 849 850 /* Wait until codec calibration is finished. Codec register 26h */ 851 n = 0; 852 do { 853 delay(1); 854 if (++n > 1000) { 855 printf("%s: timeout waiting for codec calibration\n", 856 sc->sc_dev.dv_xname); 857 return ETIMEDOUT; 858 } 859 cs428x_read_codec(sc, AC97_REG_POWER, &data); 860 } while ((data & 0x0f) != 0x0f); 861 862 /* Set the serial timing configuration again */ 863 /* XXX: undocumented but the Linux driver do this */ 864 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 865 866 /* Wait until we've sampled input slots 3 & 4 as valid */ 867 n = 0; 868 do { 869 delay(1000); 870 if (++n > 1000) { 871 printf("%s: timeout waiting for sampled input slots as valid\n", 872 sc->sc_dev.dv_xname); 873 return ETIMEDOUT; 874 } 875 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 876 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 877 878 /* Start digital data transfer of audio data to the codec */ 879 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 880 return 0; 881 } 882 883 884 /* Internal functions */ 885 886 /* convert sample rate to register value */ 887 static uint8_t 888 cs4281_sr2regval(int rate) 889 { 890 uint8_t retval; 891 892 /* We don't have to change here. but anyway ... */ 893 if (rate > 48000) 894 rate = 48000; 895 if (rate < 6023) 896 rate = 6023; 897 898 switch (rate) { 899 case 8000: 900 retval = 5; 901 break; 902 case 11025: 903 retval = 4; 904 break; 905 case 16000: 906 retval = 3; 907 break; 908 case 22050: 909 retval = 2; 910 break; 911 case 44100: 912 retval = 1; 913 break; 914 case 48000: 915 retval = 0; 916 break; 917 default: 918 retval = 1536000/rate; /* == 24576000/(rate*16) */ 919 } 920 return retval; 921 } 922 923 static void 924 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 925 { 926 927 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 928 } 929 930 static void 931 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 932 { 933 934 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 935 } 936 937 static int 938 cs4281_init(struct cs428x_softc *sc, int init) 939 { 940 int n; 941 uint16_t data; 942 uint32_t dat32; 943 944 /* set "Configuration Write Protect" register to 945 * 0x4281 to allow to write */ 946 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 947 948 /* 949 * Unset "Full Power-Down bit of Extended PCI Power Management 950 * Control" register to release the reset state. 951 */ 952 dat32 = BA0READ4(sc, CS4281_EPPMC); 953 if (dat32 & EPPMC_FPDN) { 954 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 955 } 956 957 /* Start PLL out in known state */ 958 BA0WRITE4(sc, CS4281_CLKCR1, 0); 959 /* Start serial ports out in known state */ 960 BA0WRITE4(sc, CS4281_SERMC, 0); 961 962 /* Reset codec */ 963 BA0WRITE4(sc, CS428X_ACCTL, 0); 964 delay(50); /* delay 50us */ 965 966 BA0WRITE4(sc, CS4281_SPMC, 0); 967 delay(100); /* delay 100us */ 968 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 969 #if defined(ENABLE_SECONDARY_CODEC) 970 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 971 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 972 #endif 973 delay(50000); /* XXX: delay 50ms */ 974 975 /* Turn on Sound System clocks based on ABITCLK */ 976 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 977 delay(50000); /* XXX: delay 50ms */ 978 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 979 980 /* Set enables for sections that are needed in the SSPM registers */ 981 BA0WRITE4(sc, CS4281_SSPM, 982 SSPM_MIXEN | /* Mixer */ 983 SSPM_CSRCEN | /* Capture SRC */ 984 SSPM_PSRCEN | /* Playback SRC */ 985 SSPM_JSEN | /* Joystick */ 986 SSPM_ACLEN | /* AC LINK */ 987 SSPM_FMEN /* FM */ 988 ); 989 990 /* Wait for clock stabilization */ 991 n = 0; 992 #if 1 993 /* what document says */ 994 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 995 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 996 delay(100); 997 if (++n > 1000) { 998 printf("%s: timeout waiting for clock stabilization\n", 999 sc->sc_dev.dv_xname); 1000 return -1; 1001 } 1002 } 1003 #else 1004 /* Cirrus driver for Linux does */ 1005 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1006 delay(1000); 1007 if (++n > 1000) { 1008 printf("%s: timeout waiting for clock stabilization\n", 1009 sc->sc_dev.dv_xname); 1010 return -1; 1011 } 1012 } 1013 #endif 1014 1015 /* Enable ASYNC generation */ 1016 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1017 1018 /* Wait for codec ready. Linux driver waits 50ms here */ 1019 n = 0; 1020 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1021 delay(100); 1022 if (++n > 1000) { 1023 printf("%s: timeout waiting for codec ready\n", 1024 sc->sc_dev.dv_xname); 1025 return -1; 1026 } 1027 } 1028 1029 #if defined(ENABLE_SECONDARY_CODEC) 1030 /* secondary codec ready*/ 1031 n = 0; 1032 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1033 delay(100); 1034 if (++n > 1000) { 1035 printf("%s: timeout waiting for secondary codec ready\n", 1036 sc->sc_dev.dv_xname); 1037 return -1; 1038 } 1039 } 1040 #endif 1041 1042 /* Set the serial timing configuration */ 1043 /* XXX: undocumented but the Linux driver do this */ 1044 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1045 1046 /* Wait for codec ready signal */ 1047 n = 0; 1048 do { 1049 delay(1000); 1050 if (++n > 1000) { 1051 printf("%s: timeout waiting for codec ready\n", 1052 sc->sc_dev.dv_xname); 1053 return -1; 1054 } 1055 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1056 } while (dat32 == 0); 1057 1058 /* Enable Valid Frame output on ASDOUT */ 1059 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1060 1061 /* Wait until codec calibration is finished. codec register 26h */ 1062 n = 0; 1063 do { 1064 delay(1); 1065 if (++n > 1000) { 1066 printf("%s: timeout waiting for codec calibration\n", 1067 sc->sc_dev.dv_xname); 1068 return -1; 1069 } 1070 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1071 } while ((data & 0x0f) != 0x0f); 1072 1073 /* Set the serial timing configuration again */ 1074 /* XXX: undocumented but the Linux driver do this */ 1075 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1076 1077 /* Wait until we've sampled input slots 3 & 4 as valid */ 1078 n = 0; 1079 do { 1080 delay(1000); 1081 if (++n > 1000) { 1082 printf("%s: timeout waiting for sampled input slots as valid\n", 1083 sc->sc_dev.dv_xname); 1084 return -1; 1085 } 1086 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1087 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1088 1089 /* Start digital data transfer of audio data to the codec */ 1090 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1091 1092 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1093 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1094 1095 /* Power on the DAC */ 1096 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1097 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1098 1099 /* Wait until we sample a DAC ready state. 1100 * Not documented, but Linux driver does. 1101 */ 1102 for (n = 0; n < 32; ++n) { 1103 delay(1000); 1104 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1105 if (data & 0x02) 1106 break; 1107 } 1108 1109 /* Power on the ADC */ 1110 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1111 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1112 1113 /* Wait until we sample ADC ready state. 1114 * Not documented, but Linux driver does. 1115 */ 1116 for (n = 0; n < 32; ++n) { 1117 delay(1000); 1118 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1119 if (data & 0x01) 1120 break; 1121 } 1122 1123 #if 0 1124 /* Initialize AC-Link features */ 1125 /* variable sample-rate support */ 1126 mem = BA0READ4(sc, CS4281_SERMC); 1127 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1128 BA0WRITE4(sc, CS4281_SERMC, mem); 1129 /* XXX: more... */ 1130 1131 /* Initialize SSCR register features */ 1132 /* XXX: hardware volume setting */ 1133 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1134 #endif 1135 1136 /* disable Sound Blaster Pro emulation */ 1137 /* XXX: 1138 * Cannot set since the documents does not describe which bit is 1139 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1140 * we can ignore it.*/ 1141 #if 0 1142 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1143 #endif 1144 1145 /* map AC97 PCM playback to DMA Channel 0 */ 1146 /* Reset FEN bit to setup first */ 1147 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1148 /* 1149 *| RS[4:0]/| | 1150 *| LS[4:0] | AC97 | Slot Function 1151 *|---------+--------+-------------------- 1152 *| 0 | 3 | Left PCM Playback 1153 *| 1 | 4 | Right PCM Playback 1154 *| 2 | 5 | Phone Line 1 DAC 1155 *| 3 | 6 | Center PCM Playback 1156 *.... 1157 * quoted from Table 29(p109) 1158 */ 1159 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1160 0x00 << 16 | /* LS[4:0] = 0 see above */ 1161 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1162 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1163 BA0WRITE4(sc, CS4281_FCR0, dat32); 1164 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1165 1166 /* map AC97 PCM record to DMA Channel 1 */ 1167 /* Reset FEN bit to setup first */ 1168 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1169 /* 1170 *| RS[4:0]/| 1171 *| LS[4:0] | AC97 | Slot Function 1172 *|---------+------+------------------- 1173 *| 10 | 3 | Left PCM Record 1174 *| 11 | 4 | Right PCM Record 1175 *| 12 | 5 | Phone Line 1 ADC 1176 *| 13 | 6 | Mic ADC 1177 *.... 1178 * quoted from Table 30(p109) 1179 */ 1180 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1181 0x0a << 16 | /* LS[4:0] = 10 See above */ 1182 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1183 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1184 1185 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1186 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1187 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1188 1189 #if 0 1190 /* Disable DMA Channel 2, 3 */ 1191 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1192 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1193 #endif 1194 1195 /* Set the SRC Slot Assignment accordingly */ 1196 /*| PLSS[4:0]/ 1197 *| PRSS[4:0] | AC97 | Slot Function 1198 *|-----------+------+---------------- 1199 *| 0 | 3 | Left PCM Playback 1200 *| 1 | 4 | Right PCM Playback 1201 *| 2 | 5 | phone line 1 DAC 1202 *| 3 | 6 | Center PCM Playback 1203 *| 4 | 7 | Left Surround PCM Playback 1204 *| 5 | 8 | Right Surround PCM Playback 1205 *...... 1206 * 1207 *| CLSS[4:0]/ 1208 *| CRSS[4:0] | AC97 | Codec |Slot Function 1209 *|-----------+------+-------+----------------- 1210 *| 10 | 3 |Primary| Left PCM Record 1211 *| 11 | 4 |Primary| Right PCM Record 1212 *| 12 | 5 |Primary| Phone Line 1 ADC 1213 *| 13 | 6 |Primary| Mic ADC 1214 *|..... 1215 *| 20 | 3 | Sec. | Left PCM Record 1216 *| 21 | 4 | Sec. | Right PCM Record 1217 *| 22 | 5 | Sec. | Phone Line 1 ADC 1218 *| 23 | 6 | Sec. | Mic ADC 1219 */ 1220 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1221 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1222 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1223 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1224 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1225 1226 /* Set interrupt to occurred at Half and Full terminal 1227 * count interrupt enable for DMA channel 0 and 1. 1228 * To keep DMA stop, set MSK. 1229 */ 1230 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1231 BA0WRITE4(sc, CS4281_DCR0, dat32); 1232 BA0WRITE4(sc, CS4281_DCR1, dat32); 1233 1234 /* Set Auto-Initialize Contorl enable */ 1235 BA0WRITE4(sc, CS4281_DMR0, 1236 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1237 BA0WRITE4(sc, CS4281_DMR1, 1238 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1239 1240 /* Clear DMA Mask in HIMR */ 1241 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1242 BA0WRITE4(sc, CS4281_HIMR, 1243 BA0READ4(sc, CS4281_HIMR) & dat32); 1244 1245 /* set current status */ 1246 if (init != 0) { 1247 sc->sc_prun = 0; 1248 sc->sc_rrun = 0; 1249 } 1250 1251 /* setup playback volume */ 1252 BA0WRITE4(sc, CS4281_PPRVC, 7); 1253 BA0WRITE4(sc, CS4281_PPLVC, 7); 1254 1255 return 0; 1256 } 1257