1 /* $NetBSD: cs4281.c,v 1.35 2007/10/19 12:00:41 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.35 2007/10/19 12:00:41 ad Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/fcntl.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/cs4281reg.h> 59 #include <dev/pci/cs428xreg.h> 60 61 #include <sys/audioio.h> 62 #include <dev/audio_if.h> 63 #include <dev/midi_if.h> 64 #include <dev/mulaw.h> 65 #include <dev/auconv.h> 66 67 #include <dev/ic/ac97reg.h> 68 #include <dev/ic/ac97var.h> 69 70 #include <dev/pci/cs428x.h> 71 72 #include <sys/bus.h> 73 74 #if defined(ENABLE_SECONDARY_CODEC) 75 #define MAX_CHANNELS (4) 76 #define MAX_FIFO_SIZE 32 /* 128/4channels */ 77 #else 78 #define MAX_CHANNELS (2) 79 #define MAX_FIFO_SIZE 64 /* 128/2channels */ 80 #endif 81 82 /* IF functions for audio driver */ 83 static int cs4281_match(struct device *, struct cfdata *, void *); 84 static void cs4281_attach(struct device *, struct device *, void *); 85 static int cs4281_intr(void *); 86 static int cs4281_query_encoding(void *, struct audio_encoding *); 87 static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90 static int cs4281_halt_output(void *); 91 static int cs4281_halt_input(void *); 92 static int cs4281_getdev(void *, struct audio_device *); 93 static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96 static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100 static int cs4281_reset_codec(void *); 101 102 /* Internal functions */ 103 static uint8_t cs4281_sr2regval(int); 104 static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105 static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106 static int cs4281_init(struct cs428x_softc *, int); 107 108 /* Power Management */ 109 static void cs4281_power(int, void *); 110 111 static const struct audio_hw_if cs4281_hw_if = { 112 NULL, /* open */ 113 NULL, /* close */ 114 NULL, 115 cs4281_query_encoding, 116 cs4281_set_params, 117 cs428x_round_blocksize, 118 NULL, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 cs4281_halt_output, 124 cs4281_halt_input, 125 NULL, 126 cs4281_getdev, 127 NULL, 128 cs428x_mixer_set_port, 129 cs428x_mixer_get_port, 130 cs428x_query_devinfo, 131 cs428x_malloc, 132 cs428x_free, 133 cs428x_round_buffersize, 134 cs428x_mappage, 135 cs428x_get_props, 136 cs4281_trigger_output, 137 cs4281_trigger_input, 138 NULL, 139 NULL, 140 }; 141 142 #if NMIDI > 0 && 0 143 /* Midi Interface */ 144 static void cs4281_midi_close(void*); 145 static void cs4281_midi_getinfo(void *, struct midi_info *); 146 static int cs4281_midi_open(void *, int, void (*)(void *, int), 147 void (*)(void *), void *); 148 static int cs4281_midi_output(void *, int); 149 150 static const struct midi_hw_if cs4281_midi_hw_if = { 151 cs4281_midi_open, 152 cs4281_midi_close, 153 cs4281_midi_output, 154 cs4281_midi_getinfo, 155 0, 156 }; 157 #endif 158 159 CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 160 cs4281_match, cs4281_attach, NULL, NULL); 161 162 static struct audio_device cs4281_device = { 163 "CS4281", 164 "", 165 "cs4281" 166 }; 167 168 169 static int 170 cs4281_match(struct device *parent, struct cfdata *match, 171 void *aux) 172 { 173 struct pci_attach_args *pa; 174 175 pa = (struct pci_attach_args *)aux; 176 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 177 return 0; 178 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 179 return 1; 180 return 0; 181 } 182 183 static void 184 cs4281_attach(struct device *parent, struct device *self, void *aux) 185 { 186 struct cs428x_softc *sc; 187 struct pci_attach_args *pa; 188 pci_chipset_tag_t pc; 189 char const *intrstr; 190 pcireg_t reg; 191 char devinfo[256]; 192 int error; 193 194 sc = (struct cs428x_softc *)self; 195 pa = (struct pci_attach_args *)aux; 196 pc = pa->pa_pc; 197 aprint_naive(": Audio controller\n"); 198 199 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 200 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 201 PCI_REVISION(pa->pa_class)); 202 203 sc->sc_pc = pa->pa_pc; 204 sc->sc_pt = pa->pa_tag; 205 206 /* Map I/O register */ 207 if (pci_mapreg_map(pa, PCI_BA0, 208 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 209 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 210 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 211 return; 212 } 213 if (pci_mapreg_map(pa, PCI_BA1, 214 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 215 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 216 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 217 return; 218 } 219 220 sc->sc_dmatag = pa->pa_dmat; 221 222 /* power up chip */ 223 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 224 pci_activate_null)) && error != EOPNOTSUPP) { 225 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 226 error); 227 return; 228 } 229 230 /* Enable the device (set bus master flag) */ 231 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 232 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 233 reg | PCI_COMMAND_MASTER_ENABLE); 234 235 #if 0 236 /* LATENCY_TIMER setting */ 237 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 238 if (PCI_LATTIMER(temp1) < 32) { 239 temp1 &= 0xffff00ff; 240 temp1 |= 0x00002000; 241 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 242 } 243 #endif 244 245 /* Map and establish the interrupt. */ 246 if (pci_intr_map(pa, &sc->intrh)) { 247 aprint_error("%s: couldn't map interrupt\n", 248 sc->sc_dev.dv_xname); 249 return; 250 } 251 intrstr = pci_intr_string(pc, sc->intrh); 252 253 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 254 cs4281_intr, sc); 255 if (sc->sc_ih == NULL) { 256 aprint_error("%s: couldn't establish interrupt", 257 sc->sc_dev.dv_xname); 258 if (intrstr != NULL) 259 aprint_normal(" at %s", intrstr); 260 aprint_normal("\n"); 261 return; 262 } 263 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 264 265 /* 266 * Sound System start-up 267 */ 268 if (cs4281_init(sc, 1) != 0) 269 return; 270 271 sc->type = TYPE_CS4281; 272 sc->halt_input = cs4281_halt_input; 273 sc->halt_output = cs4281_halt_output; 274 275 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 276 sc->dma_align = 0x10; 277 sc->hw_blocksize = sc->dma_size / 2; 278 279 /* AC 97 attachment */ 280 sc->host_if.arg = sc; 281 sc->host_if.attach = cs428x_attach_codec; 282 sc->host_if.read = cs428x_read_codec; 283 sc->host_if.write = cs428x_write_codec; 284 sc->host_if.reset = cs4281_reset_codec; 285 if (ac97_attach(&sc->host_if, self) != 0) { 286 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 287 return; 288 } 289 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 290 291 #if NMIDI > 0 && 0 292 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 293 #endif 294 295 sc->sc_suspend = PWR_RESUME; 296 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 297 cs4281_power, sc); 298 } 299 300 static int 301 cs4281_intr(void *p) 302 { 303 struct cs428x_softc *sc; 304 uint32_t intr, hdsr0, hdsr1; 305 char *empty_dma; 306 int handled; 307 308 sc = p; 309 handled = 0; 310 hdsr0 = 0; 311 hdsr1 = 0; 312 313 /* grab interrupt register */ 314 intr = BA0READ4(sc, CS4281_HISR); 315 316 DPRINTF(("cs4281_intr:")); 317 /* not for me */ 318 if ((intr & HISR_INTENA) == 0) { 319 /* clear the interrupt register */ 320 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 321 return 0; 322 } 323 324 if (intr & HISR_DMA0) 325 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 326 if (intr & HISR_DMA1) 327 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 328 /* clear the interrupt register */ 329 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 330 331 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 332 intr, hdsr0, hdsr1)); 333 334 /* Playback Interrupt */ 335 if (intr & HISR_DMA0) { 336 handled = 1; 337 if (sc->sc_prun) { 338 DPRINTF((" PB DMA 0x%x(%d)", 339 (int)BA0READ4(sc, CS4281_DCA0), 340 (int)BA0READ4(sc, CS4281_DCC0))); 341 if ((sc->sc_pi%sc->sc_pcount) == 0) 342 sc->sc_pintr(sc->sc_parg); 343 /* copy buffer */ 344 ++sc->sc_pi; 345 empty_dma = sc->sc_pdma->addr; 346 if (sc->sc_pi&1) 347 empty_dma += sc->hw_blocksize; 348 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 349 sc->sc_pn += sc->hw_blocksize; 350 if (sc->sc_pn >= sc->sc_pe) 351 sc->sc_pn = sc->sc_ps; 352 } else { 353 printf("%s: unexpected play intr\n", 354 sc->sc_dev.dv_xname); 355 } 356 } 357 if (intr & HISR_DMA1) { 358 handled = 1; 359 if (sc->sc_rrun) { 360 /* copy from DMA */ 361 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 362 (int)BA0READ4(sc, CS4281_DCC1))); 363 ++sc->sc_ri; 364 empty_dma = sc->sc_rdma->addr; 365 if ((sc->sc_ri & 1) == 0) 366 empty_dma += sc->hw_blocksize; 367 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 368 sc->sc_rn += sc->hw_blocksize; 369 if (sc->sc_rn >= sc->sc_re) 370 sc->sc_rn = sc->sc_rs; 371 if ((sc->sc_ri % sc->sc_rcount) == 0) 372 sc->sc_rintr(sc->sc_rarg); 373 } else { 374 printf("%s: unexpected record intr\n", 375 sc->sc_dev.dv_xname); 376 } 377 } 378 DPRINTF(("\n")); 379 380 return handled; 381 } 382 383 static int 384 cs4281_query_encoding(void *addr, struct audio_encoding *fp) 385 { 386 387 switch (fp->index) { 388 case 0: 389 strcpy(fp->name, AudioEulinear); 390 fp->encoding = AUDIO_ENCODING_ULINEAR; 391 fp->precision = 8; 392 fp->flags = 0; 393 break; 394 case 1: 395 strcpy(fp->name, AudioEmulaw); 396 fp->encoding = AUDIO_ENCODING_ULAW; 397 fp->precision = 8; 398 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 399 break; 400 case 2: 401 strcpy(fp->name, AudioEalaw); 402 fp->encoding = AUDIO_ENCODING_ALAW; 403 fp->precision = 8; 404 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 405 break; 406 case 3: 407 strcpy(fp->name, AudioEslinear); 408 fp->encoding = AUDIO_ENCODING_SLINEAR; 409 fp->precision = 8; 410 fp->flags = 0; 411 break; 412 case 4: 413 strcpy(fp->name, AudioEslinear_le); 414 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 415 fp->precision = 16; 416 fp->flags = 0; 417 break; 418 case 5: 419 strcpy(fp->name, AudioEulinear_le); 420 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 421 fp->precision = 16; 422 fp->flags = 0; 423 break; 424 case 6: 425 strcpy(fp->name, AudioEslinear_be); 426 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 427 fp->precision = 16; 428 fp->flags = 0; 429 break; 430 case 7: 431 strcpy(fp->name, AudioEulinear_be); 432 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 433 fp->precision = 16; 434 fp->flags = 0; 435 break; 436 default: 437 return EINVAL; 438 } 439 return 0; 440 } 441 442 static int 443 cs4281_set_params(void *addr, int setmode, int usemode, 444 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 445 stream_filter_list_t *rfil) 446 { 447 audio_params_t hw; 448 struct cs428x_softc *sc; 449 audio_params_t *p; 450 stream_filter_list_t *fil; 451 int mode; 452 453 sc = addr; 454 for (mode = AUMODE_RECORD; mode != -1; 455 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 456 if ((setmode & mode) == 0) 457 continue; 458 459 p = mode == AUMODE_PLAY ? play : rec; 460 461 if (p == play) { 462 DPRINTFN(5, 463 ("play: sample=%u precision=%u channels=%u\n", 464 p->sample_rate, p->precision, p->channels)); 465 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 466 (p->precision != 8 && p->precision != 16) || 467 (p->channels != 1 && p->channels != 2)) { 468 return EINVAL; 469 } 470 } else { 471 DPRINTFN(5, 472 ("rec: sample=%u precision=%u channels=%u\n", 473 p->sample_rate, p->precision, p->channels)); 474 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 475 (p->precision != 8 && p->precision != 16) || 476 (p->channels != 1 && p->channels != 2)) { 477 return EINVAL; 478 } 479 } 480 hw = *p; 481 fil = mode == AUMODE_PLAY ? pfil : rfil; 482 483 switch (p->encoding) { 484 case AUDIO_ENCODING_SLINEAR_BE: 485 break; 486 case AUDIO_ENCODING_SLINEAR_LE: 487 break; 488 case AUDIO_ENCODING_ULINEAR_BE: 489 break; 490 case AUDIO_ENCODING_ULINEAR_LE: 491 break; 492 case AUDIO_ENCODING_ULAW: 493 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 494 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 495 : linear8_to_mulaw, &hw); 496 break; 497 case AUDIO_ENCODING_ALAW: 498 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 499 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 500 : linear8_to_alaw, &hw); 501 break; 502 default: 503 return EINVAL; 504 } 505 } 506 507 /* set sample rate */ 508 cs4281_set_dac_rate(sc, play->sample_rate); 509 cs4281_set_adc_rate(sc, rec->sample_rate); 510 return 0; 511 } 512 513 static int 514 cs4281_halt_output(void *addr) 515 { 516 struct cs428x_softc *sc; 517 518 sc = addr; 519 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 520 sc->sc_prun = 0; 521 return 0; 522 } 523 524 static int 525 cs4281_halt_input(void *addr) 526 { 527 struct cs428x_softc *sc; 528 529 sc = addr; 530 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 531 sc->sc_rrun = 0; 532 return 0; 533 } 534 535 static int 536 cs4281_getdev(void *addr, struct audio_device *retp) 537 { 538 539 *retp = cs4281_device; 540 return 0; 541 } 542 543 static int 544 cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 545 void (*intr)(void *), void *arg, 546 const audio_params_t *param) 547 { 548 struct cs428x_softc *sc; 549 uint32_t fmt; 550 struct cs428x_dma *p; 551 int dma_count; 552 553 sc = addr; 554 fmt = 0; 555 #ifdef DIAGNOSTIC 556 if (sc->sc_prun) 557 printf("cs4281_trigger_output: already running\n"); 558 #endif 559 sc->sc_prun = 1; 560 561 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 562 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 563 sc->sc_pintr = intr; 564 sc->sc_parg = arg; 565 566 /* stop playback DMA */ 567 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 568 569 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 570 param->precision, param->channels, param->encoding)); 571 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 572 continue; 573 if (p == NULL) { 574 printf("cs4281_trigger_output: bad addr %p\n", start); 575 return EINVAL; 576 } 577 578 sc->sc_pcount = blksize / sc->hw_blocksize; 579 sc->sc_ps = (char *)start; 580 sc->sc_pe = (char *)end; 581 sc->sc_pdma = p; 582 sc->sc_pbuf = KERNADDR(p); 583 sc->sc_pi = 0; 584 sc->sc_pn = sc->sc_ps; 585 if (blksize >= sc->dma_size) { 586 sc->sc_pn = sc->sc_ps + sc->dma_size; 587 memcpy(sc->sc_pbuf, start, sc->dma_size); 588 ++sc->sc_pi; 589 } else { 590 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 591 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 592 } 593 594 dma_count = sc->dma_size; 595 if (param->precision != 8) 596 dma_count /= 2; /* 16 bit */ 597 if (param->channels > 1) 598 dma_count /= 2; /* Stereo */ 599 600 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 601 (int)DMAADDR(p), dma_count)); 602 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 603 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 604 605 /* set playback format */ 606 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 607 if (param->precision == 8) 608 fmt |= DMRn_SIZE8; 609 if (param->channels == 1) 610 fmt |= DMRn_MONO; 611 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 612 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 613 fmt |= DMRn_BEND; 614 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 615 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 616 fmt |= DMRn_USIGN; 617 BA0WRITE4(sc, CS4281_DMR0, fmt); 618 619 /* set sample rate */ 620 sc->sc_prate = param->sample_rate; 621 cs4281_set_dac_rate(sc, param->sample_rate); 622 623 /* start DMA */ 624 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 625 /* Enable interrupts */ 626 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 627 628 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 629 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 630 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 631 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 632 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 633 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 634 BA0READ4(sc, CS4281_DACSR))); 635 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 636 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 637 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 638 639 return 0; 640 } 641 642 static int 643 cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 644 void (*intr)(void *), void *arg, 645 const audio_params_t *param) 646 { 647 struct cs428x_softc *sc; 648 struct cs428x_dma *p; 649 uint32_t fmt; 650 int dma_count; 651 652 sc = addr; 653 fmt = 0; 654 #ifdef DIAGNOSTIC 655 if (sc->sc_rrun) 656 printf("cs4281_trigger_input: already running\n"); 657 #endif 658 sc->sc_rrun = 1; 659 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 660 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 661 sc->sc_rintr = intr; 662 sc->sc_rarg = arg; 663 664 /* stop recording DMA */ 665 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 666 667 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 668 continue; 669 if (!p) { 670 printf("cs4281_trigger_input: bad addr %p\n", start); 671 return EINVAL; 672 } 673 674 sc->sc_rcount = blksize / sc->hw_blocksize; 675 sc->sc_rs = (char *)start; 676 sc->sc_re = (char *)end; 677 sc->sc_rdma = p; 678 sc->sc_rbuf = KERNADDR(p); 679 sc->sc_ri = 0; 680 sc->sc_rn = sc->sc_rs; 681 682 dma_count = sc->dma_size; 683 if (param->precision != 8) 684 dma_count /= 2; 685 if (param->channels > 1) 686 dma_count /= 2; 687 688 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 689 (int)DMAADDR(p), dma_count)); 690 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 691 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 692 693 /* set recording format */ 694 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 695 if (param->precision == 8) 696 fmt |= DMRn_SIZE8; 697 if (param->channels == 1) 698 fmt |= DMRn_MONO; 699 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 700 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 701 fmt |= DMRn_BEND; 702 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 703 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 704 fmt |= DMRn_USIGN; 705 BA0WRITE4(sc, CS4281_DMR1, fmt); 706 707 /* set sample rate */ 708 sc->sc_rrate = param->sample_rate; 709 cs4281_set_adc_rate(sc, param->sample_rate); 710 711 /* Start DMA */ 712 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 713 /* Enable interrupts */ 714 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 715 716 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 717 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 718 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 719 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 720 721 return 0; 722 } 723 724 /* Power Hook */ 725 static void 726 cs4281_power(int why, void *v) 727 { 728 static uint32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 729 static uint32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 730 struct cs428x_softc *sc; 731 732 sc = (struct cs428x_softc *)v; 733 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 734 switch (why) { 735 case PWR_SUSPEND: 736 case PWR_STANDBY: 737 sc->sc_suspend = why; 738 739 /* save current playback status */ 740 if (sc->sc_prun) { 741 dcr0 = BA0READ4(sc, CS4281_DCR0); 742 dmr0 = BA0READ4(sc, CS4281_DMR0); 743 dbc0 = BA0READ4(sc, CS4281_DBC0); 744 dba0 = BA0READ4(sc, CS4281_DBA0); 745 } 746 747 /* save current capture status */ 748 if (sc->sc_rrun) { 749 dcr1 = BA0READ4(sc, CS4281_DCR1); 750 dmr1 = BA0READ4(sc, CS4281_DMR1); 751 dbc1 = BA0READ4(sc, CS4281_DBC1); 752 dba1 = BA0READ4(sc, CS4281_DBA1); 753 } 754 /* Stop DMA */ 755 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 756 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 757 758 pci_conf_capture(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 759 if (sc->sc_ih != NULL) 760 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 761 762 break; 763 case PWR_RESUME: 764 if (sc->sc_suspend == PWR_RESUME) { 765 printf("cs4281_power: odd, resume without suspend.\n"); 766 sc->sc_suspend = why; 767 return; 768 } 769 770 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, 771 IPL_AUDIO, cs4281_intr, sc); 772 if (sc->sc_ih == NULL) { 773 aprint_error("%s: can't establish interrupt", 774 sc->sc_dev.dv_xname); 775 /* XXX jmcneill what should we do here? */ 776 return; 777 } 778 pci_conf_restore(sc->sc_pc, sc->sc_pt, &sc->sc_pciconf); 779 780 sc->sc_suspend = why; 781 cs4281_init(sc, 0); 782 cs4281_reset_codec(sc); 783 784 /* restore ac97 registers */ 785 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 786 787 /* restore DMA related status */ 788 if (sc->sc_prun) { 789 cs4281_set_dac_rate(sc, sc->sc_prate); 790 BA0WRITE4(sc, CS4281_DBA0, dba0); 791 BA0WRITE4(sc, CS4281_DBC0, dbc0); 792 BA0WRITE4(sc, CS4281_DMR0, dmr0); 793 BA0WRITE4(sc, CS4281_DCR0, dcr0); 794 } 795 if (sc->sc_rrun) { 796 cs4281_set_adc_rate(sc, sc->sc_rrate); 797 BA0WRITE4(sc, CS4281_DBA1, dba1); 798 BA0WRITE4(sc, CS4281_DBC1, dbc1); 799 BA0WRITE4(sc, CS4281_DMR1, dmr1); 800 BA0WRITE4(sc, CS4281_DCR1, dcr1); 801 } 802 /* enable intterupts */ 803 if (sc->sc_prun || sc->sc_rrun) 804 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 805 break; 806 case PWR_SOFTSUSPEND: 807 case PWR_SOFTSTANDBY: 808 case PWR_SOFTRESUME: 809 break; 810 } 811 } 812 813 /* control AC97 codec */ 814 static int 815 cs4281_reset_codec(void *addr) 816 { 817 struct cs428x_softc *sc; 818 uint16_t data; 819 uint32_t dat32; 820 int n; 821 822 sc = addr; 823 824 DPRINTFN(3, ("cs4281_reset_codec\n")); 825 826 /* Reset codec */ 827 BA0WRITE4(sc, CS428X_ACCTL, 0); 828 delay(50); /* delay 50us */ 829 830 BA0WRITE4(sc, CS4281_SPMC, 0); 831 delay(100); /* delay 100us */ 832 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 833 #if defined(ENABLE_SECONDARY_CODEC) 834 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 835 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 836 #endif 837 delay(50000); /* XXX: delay 50ms */ 838 839 /* Enable ASYNC generation */ 840 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 841 842 /* Wait for codec ready. Linux driver waits 50ms here */ 843 n = 0; 844 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 845 delay(100); 846 if (++n > 1000) { 847 printf("reset_codec: AC97 codec ready timeout\n"); 848 return ETIMEDOUT; 849 } 850 } 851 #if defined(ENABLE_SECONDARY_CODEC) 852 /* secondary codec ready*/ 853 n = 0; 854 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 855 delay(100); 856 if (++n > 1000) 857 return 0; 858 } 859 #endif 860 /* Set the serial timing configuration */ 861 /* XXX: undocumented but the Linux driver do this */ 862 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 863 864 /* Wait for codec ready signal */ 865 n = 0; 866 do { 867 delay(1000); 868 if (++n > 1000) { 869 printf("%s: timeout waiting for codec ready\n", 870 sc->sc_dev.dv_xname); 871 return ETIMEDOUT; 872 } 873 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 874 } while (dat32 == 0); 875 876 /* Enable Valid Frame output on ASDOUT */ 877 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 878 879 /* Wait until codec calibration is finished. Codec register 26h */ 880 n = 0; 881 do { 882 delay(1); 883 if (++n > 1000) { 884 printf("%s: timeout waiting for codec calibration\n", 885 sc->sc_dev.dv_xname); 886 return ETIMEDOUT; 887 } 888 cs428x_read_codec(sc, AC97_REG_POWER, &data); 889 } while ((data & 0x0f) != 0x0f); 890 891 /* Set the serial timing configuration again */ 892 /* XXX: undocumented but the Linux driver do this */ 893 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 894 895 /* Wait until we've sampled input slots 3 & 4 as valid */ 896 n = 0; 897 do { 898 delay(1000); 899 if (++n > 1000) { 900 printf("%s: timeout waiting for sampled input slots as valid\n", 901 sc->sc_dev.dv_xname); 902 return ETIMEDOUT; 903 } 904 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 905 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 906 907 /* Start digital data transfer of audio data to the codec */ 908 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 909 return 0; 910 } 911 912 913 /* Internal functions */ 914 915 /* convert sample rate to register value */ 916 static uint8_t 917 cs4281_sr2regval(int rate) 918 { 919 uint8_t retval; 920 921 /* We don't have to change here. but anyway ... */ 922 if (rate > 48000) 923 rate = 48000; 924 if (rate < 6023) 925 rate = 6023; 926 927 switch (rate) { 928 case 8000: 929 retval = 5; 930 break; 931 case 11025: 932 retval = 4; 933 break; 934 case 16000: 935 retval = 3; 936 break; 937 case 22050: 938 retval = 2; 939 break; 940 case 44100: 941 retval = 1; 942 break; 943 case 48000: 944 retval = 0; 945 break; 946 default: 947 retval = 1536000/rate; /* == 24576000/(rate*16) */ 948 } 949 return retval; 950 } 951 952 static void 953 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 954 { 955 956 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 957 } 958 959 static void 960 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 961 { 962 963 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 964 } 965 966 static int 967 cs4281_init(struct cs428x_softc *sc, int init) 968 { 969 int n; 970 uint16_t data; 971 uint32_t dat32; 972 973 /* set "Configuration Write Protect" register to 974 * 0x4281 to allow to write */ 975 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 976 977 /* 978 * Unset "Full Power-Down bit of Extended PCI Power Management 979 * Control" register to release the reset state. 980 */ 981 dat32 = BA0READ4(sc, CS4281_EPPMC); 982 if (dat32 & EPPMC_FPDN) { 983 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 984 } 985 986 /* Start PLL out in known state */ 987 BA0WRITE4(sc, CS4281_CLKCR1, 0); 988 /* Start serial ports out in known state */ 989 BA0WRITE4(sc, CS4281_SERMC, 0); 990 991 /* Reset codec */ 992 BA0WRITE4(sc, CS428X_ACCTL, 0); 993 delay(50); /* delay 50us */ 994 995 BA0WRITE4(sc, CS4281_SPMC, 0); 996 delay(100); /* delay 100us */ 997 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 998 #if defined(ENABLE_SECONDARY_CODEC) 999 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 1000 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 1001 #endif 1002 delay(50000); /* XXX: delay 50ms */ 1003 1004 /* Turn on Sound System clocks based on ABITCLK */ 1005 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 1006 delay(50000); /* XXX: delay 50ms */ 1007 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1008 1009 /* Set enables for sections that are needed in the SSPM registers */ 1010 BA0WRITE4(sc, CS4281_SSPM, 1011 SSPM_MIXEN | /* Mixer */ 1012 SSPM_CSRCEN | /* Capture SRC */ 1013 SSPM_PSRCEN | /* Playback SRC */ 1014 SSPM_JSEN | /* Joystick */ 1015 SSPM_ACLEN | /* AC LINK */ 1016 SSPM_FMEN /* FM */ 1017 ); 1018 1019 /* Wait for clock stabilization */ 1020 n = 0; 1021 #if 1 1022 /* what document says */ 1023 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1024 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1025 delay(100); 1026 if (++n > 1000) { 1027 printf("%s: timeout waiting for clock stabilization\n", 1028 sc->sc_dev.dv_xname); 1029 return -1; 1030 } 1031 } 1032 #else 1033 /* Cirrus driver for Linux does */ 1034 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1035 delay(1000); 1036 if (++n > 1000) { 1037 printf("%s: timeout waiting for clock stabilization\n", 1038 sc->sc_dev.dv_xname); 1039 return -1; 1040 } 1041 } 1042 #endif 1043 1044 /* Enable ASYNC generation */ 1045 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1046 1047 /* Wait for codec ready. Linux driver waits 50ms here */ 1048 n = 0; 1049 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1050 delay(100); 1051 if (++n > 1000) { 1052 printf("%s: timeout waiting for codec ready\n", 1053 sc->sc_dev.dv_xname); 1054 return -1; 1055 } 1056 } 1057 1058 #if defined(ENABLE_SECONDARY_CODEC) 1059 /* secondary codec ready*/ 1060 n = 0; 1061 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1062 delay(100); 1063 if (++n > 1000) { 1064 printf("%s: timeout waiting for secondary codec ready\n", 1065 sc->sc_dev.dv_xname); 1066 return -1; 1067 } 1068 } 1069 #endif 1070 1071 /* Set the serial timing configuration */ 1072 /* XXX: undocumented but the Linux driver do this */ 1073 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1074 1075 /* Wait for codec ready signal */ 1076 n = 0; 1077 do { 1078 delay(1000); 1079 if (++n > 1000) { 1080 printf("%s: timeout waiting for codec ready\n", 1081 sc->sc_dev.dv_xname); 1082 return -1; 1083 } 1084 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1085 } while (dat32 == 0); 1086 1087 /* Enable Valid Frame output on ASDOUT */ 1088 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1089 1090 /* Wait until codec calibration is finished. codec register 26h */ 1091 n = 0; 1092 do { 1093 delay(1); 1094 if (++n > 1000) { 1095 printf("%s: timeout waiting for codec calibration\n", 1096 sc->sc_dev.dv_xname); 1097 return -1; 1098 } 1099 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1100 } while ((data & 0x0f) != 0x0f); 1101 1102 /* Set the serial timing configuration again */ 1103 /* XXX: undocumented but the Linux driver do this */ 1104 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1105 1106 /* Wait until we've sampled input slots 3 & 4 as valid */ 1107 n = 0; 1108 do { 1109 delay(1000); 1110 if (++n > 1000) { 1111 printf("%s: timeout waiting for sampled input slots as valid\n", 1112 sc->sc_dev.dv_xname); 1113 return -1; 1114 } 1115 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1116 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1117 1118 /* Start digital data transfer of audio data to the codec */ 1119 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1120 1121 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1122 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1123 1124 /* Power on the DAC */ 1125 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1126 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1127 1128 /* Wait until we sample a DAC ready state. 1129 * Not documented, but Linux driver does. 1130 */ 1131 for (n = 0; n < 32; ++n) { 1132 delay(1000); 1133 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1134 if (data & 0x02) 1135 break; 1136 } 1137 1138 /* Power on the ADC */ 1139 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1140 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1141 1142 /* Wait until we sample ADC ready state. 1143 * Not documented, but Linux driver does. 1144 */ 1145 for (n = 0; n < 32; ++n) { 1146 delay(1000); 1147 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1148 if (data & 0x01) 1149 break; 1150 } 1151 1152 #if 0 1153 /* Initialize AC-Link features */ 1154 /* variable sample-rate support */ 1155 mem = BA0READ4(sc, CS4281_SERMC); 1156 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1157 BA0WRITE4(sc, CS4281_SERMC, mem); 1158 /* XXX: more... */ 1159 1160 /* Initialize SSCR register features */ 1161 /* XXX: hardware volume setting */ 1162 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1163 #endif 1164 1165 /* disable Sound Blaster Pro emulation */ 1166 /* XXX: 1167 * Cannot set since the documents does not describe which bit is 1168 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1169 * we can ignore it.*/ 1170 #if 0 1171 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1172 #endif 1173 1174 /* map AC97 PCM playback to DMA Channel 0 */ 1175 /* Reset FEN bit to setup first */ 1176 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1177 /* 1178 *| RS[4:0]/| | 1179 *| LS[4:0] | AC97 | Slot Function 1180 *|---------+--------+-------------------- 1181 *| 0 | 3 | Left PCM Playback 1182 *| 1 | 4 | Right PCM Playback 1183 *| 2 | 5 | Phone Line 1 DAC 1184 *| 3 | 6 | Center PCM Playback 1185 *.... 1186 * quoted from Table 29(p109) 1187 */ 1188 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1189 0x00 << 16 | /* LS[4:0] = 0 see above */ 1190 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1191 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1192 BA0WRITE4(sc, CS4281_FCR0, dat32); 1193 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1194 1195 /* map AC97 PCM record to DMA Channel 1 */ 1196 /* Reset FEN bit to setup first */ 1197 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1198 /* 1199 *| RS[4:0]/| 1200 *| LS[4:0] | AC97 | Slot Function 1201 *|---------+------+------------------- 1202 *| 10 | 3 | Left PCM Record 1203 *| 11 | 4 | Right PCM Record 1204 *| 12 | 5 | Phone Line 1 ADC 1205 *| 13 | 6 | Mic ADC 1206 *.... 1207 * quoted from Table 30(p109) 1208 */ 1209 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1210 0x0a << 16 | /* LS[4:0] = 10 See above */ 1211 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1212 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1213 1214 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1215 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1216 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1217 1218 #if 0 1219 /* Disable DMA Channel 2, 3 */ 1220 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1221 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1222 #endif 1223 1224 /* Set the SRC Slot Assignment accordingly */ 1225 /*| PLSS[4:0]/ 1226 *| PRSS[4:0] | AC97 | Slot Function 1227 *|-----------+------+---------------- 1228 *| 0 | 3 | Left PCM Playback 1229 *| 1 | 4 | Right PCM Playback 1230 *| 2 | 5 | phone line 1 DAC 1231 *| 3 | 6 | Center PCM Playback 1232 *| 4 | 7 | Left Surround PCM Playback 1233 *| 5 | 8 | Right Surround PCM Playback 1234 *...... 1235 * 1236 *| CLSS[4:0]/ 1237 *| CRSS[4:0] | AC97 | Codec |Slot Function 1238 *|-----------+------+-------+----------------- 1239 *| 10 | 3 |Primary| Left PCM Record 1240 *| 11 | 4 |Primary| Right PCM Record 1241 *| 12 | 5 |Primary| Phone Line 1 ADC 1242 *| 13 | 6 |Primary| Mic ADC 1243 *|..... 1244 *| 20 | 3 | Sec. | Left PCM Record 1245 *| 21 | 4 | Sec. | Right PCM Record 1246 *| 22 | 5 | Sec. | Phone Line 1 ADC 1247 *| 23 | 6 | Sec. | Mic ADC 1248 */ 1249 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1250 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1251 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1252 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1253 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1254 1255 /* Set interrupt to occurred at Half and Full terminal 1256 * count interrupt enable for DMA channel 0 and 1. 1257 * To keep DMA stop, set MSK. 1258 */ 1259 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1260 BA0WRITE4(sc, CS4281_DCR0, dat32); 1261 BA0WRITE4(sc, CS4281_DCR1, dat32); 1262 1263 /* Set Auto-Initialize Contorl enable */ 1264 BA0WRITE4(sc, CS4281_DMR0, 1265 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1266 BA0WRITE4(sc, CS4281_DMR1, 1267 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1268 1269 /* Clear DMA Mask in HIMR */ 1270 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1271 BA0WRITE4(sc, CS4281_HIMR, 1272 BA0READ4(sc, CS4281_HIMR) & dat32); 1273 1274 /* set current status */ 1275 if (init != 0) { 1276 sc->sc_prun = 0; 1277 sc->sc_rrun = 0; 1278 } 1279 1280 /* setup playback volume */ 1281 BA0WRITE4(sc, CS4281_PPRVC, 7); 1282 BA0WRITE4(sc, CS4281_PPLVC, 7); 1283 1284 return 0; 1285 } 1286