1 /* $NetBSD: cs4280.c,v 1.68 2014/09/21 15:07:19 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.68 2014/09/21 15:07:19 christos Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/audioio.h> 68 #include <sys/bus.h> 69 #include <sys/bswap.h> 70 71 #include <dev/audio_if.h> 72 #include <dev/midi_if.h> 73 #include <dev/mulaw.h> 74 #include <dev/auconv.h> 75 76 #include <dev/ic/ac97reg.h> 77 #include <dev/ic/ac97var.h> 78 79 #include <dev/pci/pcidevs.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/cs4280reg.h> 82 #include <dev/pci/cs4280_image.h> 83 #include <dev/pci/cs428xreg.h> 84 #include <dev/pci/cs428x.h> 85 86 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 87 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 88 89 /* IF functions for audio driver */ 90 static int cs4280_match(device_t, cfdata_t, void *); 91 static void cs4280_attach(device_t, device_t, void *); 92 static int cs4280_intr(void *); 93 static int cs4280_query_encoding(void *, struct audio_encoding *); 94 static int cs4280_set_params(void *, int, int, audio_params_t *, 95 audio_params_t *, stream_filter_list_t *, 96 stream_filter_list_t *); 97 static int cs4280_halt_output(void *); 98 static int cs4280_halt_input(void *); 99 static int cs4280_getdev(void *, struct audio_device *); 100 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 101 void *, const audio_params_t *); 102 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 105 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 106 #if 0 107 static int cs4280_reset_codec(void *); 108 #endif 109 static enum ac97_host_flags cs4280_flags_codec(void *); 110 111 static bool cs4280_resume(device_t, const pmf_qual_t *); 112 static bool cs4280_suspend(device_t, const pmf_qual_t *); 113 114 /* Internal functions */ 115 static const struct cs4280_card_t * cs4280_identify_card(const struct pci_attach_args *); 116 static int cs4280_piix4_match(const struct pci_attach_args *); 117 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 118 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 119 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 120 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 121 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 122 uint32_t); 123 static int cs4280_download_image(struct cs428x_softc *); 124 static void cs4280_reset(void *); 125 static int cs4280_init(struct cs428x_softc *, int); 126 static void cs4280_clear_fifos(struct cs428x_softc *); 127 128 #if CS4280_DEBUG > 10 129 /* Thease two function is only for checking image loading is succeeded or not. */ 130 static int cs4280_check_images(struct cs428x_softc *); 131 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 132 uint32_t); 133 #endif 134 135 /* Special cards */ 136 struct cs4280_card_t 137 { 138 pcireg_t id; 139 enum cs428x_flags flags; 140 }; 141 142 #define _card(vend, prod, flags) \ 143 {PCI_ID_CODE(vend, prod), flags} 144 145 static const struct cs4280_card_t cs4280_cards[] = { 146 #if 0 /* untested, from ALSA driver */ 147 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 148 CS428X_FLAG_INVAC97EAMP), 149 #endif 150 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 151 CS428X_FLAG_INVAC97EAMP), 152 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 153 CS428X_FLAG_CLKRUNHACK) 154 }; 155 156 #undef _card 157 158 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 159 160 static const struct audio_hw_if cs4280_hw_if = { 161 NULL, /* open */ 162 NULL, /* close */ 163 NULL, 164 cs4280_query_encoding, 165 cs4280_set_params, 166 cs428x_round_blocksize, 167 NULL, 168 NULL, 169 NULL, 170 NULL, 171 NULL, 172 cs4280_halt_output, 173 cs4280_halt_input, 174 NULL, 175 cs4280_getdev, 176 NULL, 177 cs428x_mixer_set_port, 178 cs428x_mixer_get_port, 179 cs428x_query_devinfo, 180 cs428x_malloc, 181 cs428x_free, 182 cs428x_round_buffersize, 183 cs428x_mappage, 184 cs428x_get_props, 185 cs4280_trigger_output, 186 cs4280_trigger_input, 187 NULL, 188 cs428x_get_locks, 189 }; 190 191 #if NMIDI > 0 192 /* Midi Interface */ 193 static int cs4280_midi_open(void *, int, void (*)(void *, int), 194 void (*)(void *), void *); 195 static void cs4280_midi_close(void*); 196 static int cs4280_midi_output(void *, int); 197 static void cs4280_midi_getinfo(void *, struct midi_info *); 198 199 static const struct midi_hw_if cs4280_midi_hw_if = { 200 cs4280_midi_open, 201 cs4280_midi_close, 202 cs4280_midi_output, 203 cs4280_midi_getinfo, 204 0, 205 cs428x_get_locks, 206 }; 207 #endif 208 209 CFATTACH_DECL_NEW(clcs, sizeof(struct cs428x_softc), 210 cs4280_match, cs4280_attach, NULL, NULL); 211 212 static struct audio_device cs4280_device = { 213 "CS4280", 214 "", 215 "cs4280" 216 }; 217 218 219 static int 220 cs4280_match(device_t parent, cfdata_t match, void *aux) 221 { 222 struct pci_attach_args *pa; 223 224 pa = (struct pci_attach_args *)aux; 225 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 226 return 0; 227 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 228 #if 0 /* I can't confirm */ 229 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 230 #endif 231 ) 232 return 1; 233 return 0; 234 } 235 236 static void 237 cs4280_attach(device_t parent, device_t self, void *aux) 238 { 239 struct cs428x_softc *sc; 240 struct pci_attach_args *pa; 241 pci_chipset_tag_t pc; 242 const struct cs4280_card_t *cs_card; 243 char const *intrstr; 244 pcireg_t reg; 245 uint32_t mem; 246 int error; 247 char vendor[PCI_VENDORSTR_LEN]; 248 char product[PCI_PRODUCTSTR_LEN]; 249 char intrbuf[PCI_INTRSTR_LEN]; 250 251 sc = device_private(self); 252 sc->sc_dev = self; 253 pa = (struct pci_attach_args *)aux; 254 pc = pa->pa_pc; 255 256 pci_aprint_devinfo(pa, "Audio controller"); 257 258 cs_card = cs4280_identify_card(pa); 259 if (cs_card != NULL) { 260 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(cs_card->id)); 261 pci_findproduct(product, sizeof(product), 262 PCI_VENDOR(cs_card->id), PCI_PRODUCT(cs_card->id)); 263 aprint_normal_dev(sc->sc_dev, "%s %s\n", vendor, product); 264 sc->sc_flags = cs_card->flags; 265 } else { 266 sc->sc_flags = CS428X_FLAG_NONE; 267 } 268 269 sc->sc_pc = pa->pa_pc; 270 sc->sc_pt = pa->pa_tag; 271 272 /* Map I/O register */ 273 if (pci_mapreg_map(pa, PCI_BA0, 274 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 275 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 276 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 277 return; 278 } 279 if (pci_mapreg_map(pa, PCI_BA1, 280 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 281 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 282 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 283 return; 284 } 285 286 sc->sc_dmatag = pa->pa_dmat; 287 288 /* power up chip */ 289 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 290 pci_activate_null)) && error != EOPNOTSUPP) { 291 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 292 return; 293 } 294 295 /* Enable the device (set bus master flag) */ 296 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 297 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 298 reg | PCI_COMMAND_MASTER_ENABLE); 299 300 /* LATENCY_TIMER setting */ 301 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 302 if ( PCI_LATTIMER(mem) < 32 ) { 303 mem &= 0xffff00ff; 304 mem |= 0x00002000; 305 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 306 } 307 308 /* CLKRUN hack initialization */ 309 cs4280_clkrun_hack_init(sc); 310 311 /* Map and establish the interrupt. */ 312 if (pci_intr_map(pa, &sc->intrh)) { 313 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 314 return; 315 } 316 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 317 318 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 319 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 320 321 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 322 cs4280_intr, sc); 323 if (sc->sc_ih == NULL) { 324 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 325 if (intrstr != NULL) 326 aprint_error(" at %s", intrstr); 327 aprint_error("\n"); 328 mutex_destroy(&sc->sc_lock); 329 mutex_destroy(&sc->sc_intr_lock); 330 return; 331 } 332 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 333 334 /* Initialization */ 335 if(cs4280_init(sc, 1) != 0) { 336 mutex_destroy(&sc->sc_lock); 337 mutex_destroy(&sc->sc_intr_lock); 338 return; 339 } 340 341 sc->type = TYPE_CS4280; 342 sc->halt_input = cs4280_halt_input; 343 sc->halt_output = cs4280_halt_output; 344 345 /* setup buffer related parameters */ 346 sc->dma_size = CS4280_DCHUNK; 347 sc->dma_align = CS4280_DALIGN; 348 sc->hw_blocksize = CS4280_ICHUNK; 349 350 /* AC 97 attachment */ 351 sc->host_if.arg = sc; 352 sc->host_if.attach = cs428x_attach_codec; 353 sc->host_if.read = cs4280_read_codec; 354 sc->host_if.write = cs4280_write_codec; 355 #if 0 356 sc->host_if.reset = cs4280_reset_codec; 357 #else 358 sc->host_if.reset = NULL; 359 #endif 360 sc->host_if.flags = cs4280_flags_codec; 361 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 362 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 363 return; 364 } 365 366 audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev); 367 368 #if NMIDI > 0 369 midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev); 370 #endif 371 372 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume)) 373 aprint_error_dev(self, "couldn't establish power handler\n"); 374 } 375 376 /* Interrupt handling function */ 377 static int 378 cs4280_intr(void *p) 379 { 380 /* 381 * XXX 382 * 383 * Since CS4280 has only 4kB DMA buffer and 384 * interrupt occurs every 2kB block, I create dummy buffer 385 * which returns to audio driver and actual DMA buffer 386 * using in DMA transfer. 387 * 388 * 389 * ring buffer in audio.c is pointed by BUFADDR 390 * <------ ring buffer size == 64kB ------> 391 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 392 * |= = = =|= = = =|= = = =|= = = =|= = = =| 393 * | | | | | | <- call audio_intp every 394 * sc->sc_[pr]_count time. 395 * 396 * actual DMA buffer is pointed by KERNADDR 397 * <-> DMA buffer size = 4kB 398 * |= =| 399 * 400 * 401 */ 402 struct cs428x_softc *sc; 403 uint32_t intr, mem; 404 char * empty_dma; 405 int handled; 406 407 sc = p; 408 handled = 0; 409 410 mutex_spin_enter(&sc->sc_intr_lock); 411 412 /* grab interrupt register then clear it */ 413 intr = BA0READ4(sc, CS4280_HISR); 414 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 415 416 /* not for us ? */ 417 if ((intr & HISR_INTENA) == 0) { 418 mutex_spin_exit(&sc->sc_intr_lock); 419 return 0; 420 } 421 422 /* Playback Interrupt */ 423 if (intr & HISR_PINT) { 424 handled = 1; 425 mem = BA1READ4(sc, CS4280_PFIE); 426 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 427 if (sc->sc_prun) { 428 if ((sc->sc_pi%sc->sc_pcount) == 0) 429 sc->sc_pintr(sc->sc_parg); 430 /* copy buffer */ 431 ++sc->sc_pi; 432 empty_dma = sc->sc_pdma->addr; 433 if (sc->sc_pi&1) 434 empty_dma += sc->hw_blocksize; 435 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 436 sc->sc_pn += sc->hw_blocksize; 437 if (sc->sc_pn >= sc->sc_pe) 438 sc->sc_pn = sc->sc_ps; 439 } else { 440 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 441 } 442 BA1WRITE4(sc, CS4280_PFIE, mem); 443 } 444 /* Capture Interrupt */ 445 if (intr & HISR_CINT) { 446 int i; 447 int16_t rdata; 448 449 handled = 1; 450 mem = BA1READ4(sc, CS4280_CIE); 451 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 452 453 if (sc->sc_rrun) { 454 ++sc->sc_ri; 455 empty_dma = sc->sc_rdma->addr; 456 if ((sc->sc_ri&1) == 0) 457 empty_dma += sc->hw_blocksize; 458 459 /* 460 * XXX 461 * I think this audio data conversion should be 462 * happend in upper layer, but I put this here 463 * since there is no conversion function available. 464 */ 465 switch(sc->sc_rparam) { 466 case CF_16BIT_STEREO: 467 /* just copy it */ 468 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 469 sc->sc_rn += sc->hw_blocksize; 470 break; 471 case CF_16BIT_MONO: 472 for (i = 0; i < 512; i++) { 473 rdata = *((int16_t *)empty_dma)>>1; 474 empty_dma += 2; 475 rdata += *((int16_t *)empty_dma)>>1; 476 empty_dma += 2; 477 *((int16_t *)sc->sc_rn) = rdata; 478 sc->sc_rn += 2; 479 } 480 break; 481 case CF_8BIT_STEREO: 482 for (i = 0; i < 512; i++) { 483 rdata = *((int16_t*)empty_dma); 484 empty_dma += 2; 485 *sc->sc_rn++ = rdata >> 8; 486 rdata = *((int16_t*)empty_dma); 487 empty_dma += 2; 488 *sc->sc_rn++ = rdata >> 8; 489 } 490 break; 491 case CF_8BIT_MONO: 492 for (i = 0; i < 512; i++) { 493 rdata = *((int16_t*)empty_dma) >>1; 494 empty_dma += 2; 495 rdata += *((int16_t*)empty_dma) >>1; 496 empty_dma += 2; 497 *sc->sc_rn++ = rdata >>8; 498 } 499 break; 500 default: 501 /* Should not reach here */ 502 aprint_error_dev(sc->sc_dev, 503 "unknown sc->sc_rparam: %d\n", 504 sc->sc_rparam); 505 } 506 if (sc->sc_rn >= sc->sc_re) 507 sc->sc_rn = sc->sc_rs; 508 } 509 BA1WRITE4(sc, CS4280_CIE, mem); 510 511 if (sc->sc_rrun) { 512 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 513 sc->sc_rintr(sc->sc_rarg); 514 } else { 515 aprint_error_dev(sc->sc_dev, 516 "unexpected record intr\n"); 517 } 518 } 519 520 #if NMIDI > 0 521 /* Midi port Interrupt */ 522 if (intr & HISR_MIDI) { 523 int data; 524 525 handled = 1; 526 DPRINTF(("i: %d: ", 527 BA0READ4(sc, CS4280_MIDSR))); 528 /* Read the received data */ 529 while ((sc->sc_iintr != NULL) && 530 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 531 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 532 DPRINTF(("r:%x\n",data)); 533 sc->sc_iintr(sc->sc_arg, data); 534 } 535 536 /* Write the data */ 537 #if 1 538 /* XXX: 539 * It seems "Transmit Buffer Full" never activate until EOI 540 * is deliverd. Shall I throw EOI top of this routine ? 541 */ 542 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 543 DPRINTF(("w: ")); 544 if (sc->sc_ointr != NULL) 545 sc->sc_ointr(sc->sc_arg); 546 } 547 #else 548 while ((sc->sc_ointr != NULL) && 549 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 550 DPRINTF(("w: ")); 551 sc->sc_ointr(sc->sc_arg); 552 } 553 #endif 554 DPRINTF(("\n")); 555 } 556 #endif 557 558 mutex_spin_exit(&sc->sc_intr_lock); 559 return handled; 560 } 561 562 static int 563 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 564 { 565 switch (fp->index) { 566 case 0: 567 strcpy(fp->name, AudioEulinear); 568 fp->encoding = AUDIO_ENCODING_ULINEAR; 569 fp->precision = 8; 570 fp->flags = 0; 571 break; 572 case 1: 573 strcpy(fp->name, AudioEmulaw); 574 fp->encoding = AUDIO_ENCODING_ULAW; 575 fp->precision = 8; 576 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 577 break; 578 case 2: 579 strcpy(fp->name, AudioEalaw); 580 fp->encoding = AUDIO_ENCODING_ALAW; 581 fp->precision = 8; 582 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 583 break; 584 case 3: 585 strcpy(fp->name, AudioEslinear); 586 fp->encoding = AUDIO_ENCODING_SLINEAR; 587 fp->precision = 8; 588 fp->flags = 0; 589 break; 590 case 4: 591 strcpy(fp->name, AudioEslinear_le); 592 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 593 fp->precision = 16; 594 fp->flags = 0; 595 break; 596 case 5: 597 strcpy(fp->name, AudioEulinear_le); 598 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 599 fp->precision = 16; 600 fp->flags = 0; 601 break; 602 case 6: 603 strcpy(fp->name, AudioEslinear_be); 604 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 605 fp->precision = 16; 606 fp->flags = 0; 607 break; 608 case 7: 609 strcpy(fp->name, AudioEulinear_be); 610 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 611 fp->precision = 16; 612 fp->flags = 0; 613 break; 614 default: 615 return EINVAL; 616 } 617 return 0; 618 } 619 620 static int 621 cs4280_set_params(void *addr, int setmode, int usemode, 622 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 623 stream_filter_list_t *rfil) 624 { 625 audio_params_t hw; 626 struct cs428x_softc *sc; 627 struct audio_params *p; 628 stream_filter_list_t *fil; 629 int mode; 630 631 sc = addr; 632 for (mode = AUMODE_RECORD; mode != -1; 633 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 634 if ((setmode & mode) == 0) 635 continue; 636 637 p = mode == AUMODE_PLAY ? play : rec; 638 639 if (p == play) { 640 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 641 p->sample_rate, p->precision, p->channels)); 642 /* play back data format may be 8- or 16-bit and 643 * either stereo or mono. 644 * playback rate may range from 8000Hz to 48000Hz 645 */ 646 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 647 (p->precision != 8 && p->precision != 16) || 648 (p->channels != 1 && p->channels != 2) ) { 649 return EINVAL; 650 } 651 } else { 652 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 653 p->sample_rate, p->precision, p->channels)); 654 /* capture data format must be 16bit stereo 655 * and sample rate range from 11025Hz to 48000Hz. 656 * 657 * XXX: it looks like to work with 8000Hz, 658 * although data sheets say lower limit is 659 * 11025 Hz. 660 */ 661 662 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 663 (p->precision != 8 && p->precision != 16) || 664 (p->channels != 1 && p->channels != 2) ) { 665 return EINVAL; 666 } 667 } 668 fil = mode == AUMODE_PLAY ? pfil : rfil; 669 hw = *p; 670 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 671 672 /* capturing data is slinear */ 673 switch (p->encoding) { 674 case AUDIO_ENCODING_SLINEAR_BE: 675 if (mode == AUMODE_RECORD && p->precision == 16) { 676 fil->append(fil, swap_bytes, &hw); 677 } 678 break; 679 case AUDIO_ENCODING_SLINEAR_LE: 680 break; 681 case AUDIO_ENCODING_ULINEAR_BE: 682 if (mode == AUMODE_RECORD) { 683 fil->append(fil, p->precision == 16 684 ? swap_bytes_change_sign16 685 : change_sign8, &hw); 686 } 687 break; 688 case AUDIO_ENCODING_ULINEAR_LE: 689 if (mode == AUMODE_RECORD) { 690 fil->append(fil, p->precision == 16 691 ? change_sign16 : change_sign8, 692 &hw); 693 } 694 break; 695 case AUDIO_ENCODING_ULAW: 696 if (mode == AUMODE_PLAY) { 697 hw.precision = 16; 698 hw.validbits = 16; 699 fil->append(fil, mulaw_to_linear16, &hw); 700 } else { 701 fil->append(fil, linear8_to_mulaw, &hw); 702 } 703 break; 704 case AUDIO_ENCODING_ALAW: 705 if (mode == AUMODE_PLAY) { 706 hw.precision = 16; 707 hw.validbits = 16; 708 fil->append(fil, alaw_to_linear16, &hw); 709 } else { 710 fil->append(fil, linear8_to_alaw, &hw); 711 } 712 break; 713 default: 714 return EINVAL; 715 } 716 } 717 718 /* set sample rate */ 719 cs4280_set_dac_rate(sc, play->sample_rate); 720 cs4280_set_adc_rate(sc, rec->sample_rate); 721 return 0; 722 } 723 724 static int 725 cs4280_halt_output(void *addr) 726 { 727 struct cs428x_softc *sc; 728 uint32_t mem; 729 730 sc = addr; 731 mem = BA1READ4(sc, CS4280_PCTL); 732 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 733 sc->sc_prun = 0; 734 cs4280_clkrun_hack(sc, -1); 735 736 return 0; 737 } 738 739 static int 740 cs4280_halt_input(void *addr) 741 { 742 struct cs428x_softc *sc; 743 uint32_t mem; 744 745 sc = addr; 746 mem = BA1READ4(sc, CS4280_CCTL); 747 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 748 sc->sc_rrun = 0; 749 cs4280_clkrun_hack(sc, -1); 750 751 return 0; 752 } 753 754 static int 755 cs4280_getdev(void *addr, struct audio_device *retp) 756 { 757 758 *retp = cs4280_device; 759 return 0; 760 } 761 762 static int 763 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 764 void (*intr)(void *), void *arg, 765 const audio_params_t *param) 766 { 767 struct cs428x_softc *sc; 768 uint32_t pfie, pctl, pdtc; 769 struct cs428x_dma *p; 770 771 sc = addr; 772 #ifdef DIAGNOSTIC 773 if (sc->sc_prun) 774 printf("cs4280_trigger_output: already running\n"); 775 #endif 776 sc->sc_prun = 1; 777 cs4280_clkrun_hack(sc, 1); 778 779 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 780 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 781 sc->sc_pintr = intr; 782 sc->sc_parg = arg; 783 784 /* stop playback DMA */ 785 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 786 787 /* setup PDTC */ 788 pdtc = BA1READ4(sc, CS4280_PDTC); 789 pdtc &= ~PDTC_MASK; 790 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 791 BA1WRITE4(sc, CS4280_PDTC, pdtc); 792 793 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 794 param->precision, param->channels, param->encoding)); 795 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 796 continue; 797 if (p == NULL) { 798 printf("cs4280_trigger_output: bad addr %p\n", start); 799 return EINVAL; 800 } 801 if (DMAADDR(p) % sc->dma_align != 0 ) { 802 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 803 "4kB align\n", (ulong)DMAADDR(p)); 804 return EINVAL; 805 } 806 807 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 808 sc->sc_ps = (char *)start; 809 sc->sc_pe = (char *)end; 810 sc->sc_pdma = p; 811 sc->sc_pbuf = KERNADDR(p); 812 sc->sc_pi = 0; 813 sc->sc_pn = sc->sc_ps; 814 if (blksize >= sc->dma_size) { 815 sc->sc_pn = sc->sc_ps + sc->dma_size; 816 memcpy(sc->sc_pbuf, start, sc->dma_size); 817 ++sc->sc_pi; 818 } else { 819 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 820 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 821 } 822 823 /* initiate playback DMA */ 824 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 825 826 /* set PFIE */ 827 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 828 829 if (param->precision == 8) 830 pfie |= PFIE_8BIT; 831 if (param->channels == 1) 832 pfie |= PFIE_MONO; 833 834 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 835 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 836 pfie |= PFIE_SWAPPED; 837 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 838 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 839 pfie |= PFIE_UNSIGNED; 840 841 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 842 843 sc->sc_prate = param->sample_rate; 844 cs4280_set_dac_rate(sc, param->sample_rate); 845 846 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 847 pctl |= sc->pctl; 848 BA1WRITE4(sc, CS4280_PCTL, pctl); 849 return 0; 850 } 851 852 static int 853 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 854 void (*intr)(void *), void *arg, 855 const audio_params_t *param) 856 { 857 struct cs428x_softc *sc; 858 uint32_t cctl, cie; 859 struct cs428x_dma *p; 860 861 sc = addr; 862 #ifdef DIAGNOSTIC 863 if (sc->sc_rrun) 864 printf("cs4280_trigger_input: already running\n"); 865 #endif 866 sc->sc_rrun = 1; 867 cs4280_clkrun_hack(sc, 1); 868 869 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 870 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 871 sc->sc_rintr = intr; 872 sc->sc_rarg = arg; 873 874 /* stop capture DMA */ 875 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 876 877 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 878 continue; 879 if (p == NULL) { 880 printf("cs4280_trigger_input: bad addr %p\n", start); 881 return EINVAL; 882 } 883 if (DMAADDR(p) % sc->dma_align != 0) { 884 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 885 "4kB align\n", (ulong)DMAADDR(p)); 886 return EINVAL; 887 } 888 889 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 890 sc->sc_rs = (char *)start; 891 sc->sc_re = (char *)end; 892 sc->sc_rdma = p; 893 sc->sc_rbuf = KERNADDR(p); 894 sc->sc_ri = 0; 895 sc->sc_rn = sc->sc_rs; 896 897 /* initiate capture DMA */ 898 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 899 900 /* setup format information for internal converter */ 901 sc->sc_rparam = 0; 902 if (param->precision == 8) { 903 sc->sc_rparam += CF_8BIT; 904 sc->sc_rcount <<= 1; 905 } 906 if (param->channels == 1) { 907 sc->sc_rparam += CF_MONO; 908 sc->sc_rcount <<= 1; 909 } 910 911 /* set CIE */ 912 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 913 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 914 915 sc->sc_rrate = param->sample_rate; 916 cs4280_set_adc_rate(sc, param->sample_rate); 917 918 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 919 cctl |= sc->cctl; 920 BA1WRITE4(sc, CS4280_CCTL, cctl); 921 return 0; 922 } 923 924 static bool 925 cs4280_suspend(device_t dv, const pmf_qual_t *qual) 926 { 927 struct cs428x_softc *sc = device_private(dv); 928 929 mutex_exit(&sc->sc_lock); 930 mutex_spin_enter(&sc->sc_intr_lock); 931 932 if (sc->sc_prun) { 933 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL); 934 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE); 935 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA); 936 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC); 937 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 938 sc->sc_suspend_state.cs4280.pctl, 939 sc->sc_suspend_state.cs4280.pfie, 940 sc->sc_suspend_state.cs4280.pba, 941 sc->sc_suspend_state.cs4280.pdtc)); 942 } 943 944 /* save current capture status */ 945 if (sc->sc_rrun) { 946 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL); 947 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE); 948 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA); 949 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 950 sc->sc_suspend_state.cs4280.cctl, 951 sc->sc_suspend_state.cs4280.cie, 952 sc->sc_suspend_state.cs4280.cba)); 953 } 954 955 /* Stop DMA */ 956 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK); 957 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 958 959 mutex_spin_exit(&sc->sc_intr_lock); 960 mutex_exit(&sc->sc_lock); 961 962 return true; 963 } 964 965 static bool 966 cs4280_resume(device_t dv, const pmf_qual_t *qual) 967 { 968 struct cs428x_softc *sc = device_private(dv); 969 970 mutex_exit(&sc->sc_lock); 971 mutex_spin_enter(&sc->sc_intr_lock); 972 cs4280_init(sc, 0); 973 #if 0 974 cs4280_reset_codec(sc); 975 #endif 976 977 /* restore DMA related status */ 978 if(sc->sc_prun) { 979 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 980 sc->sc_suspend_state.cs4280.pctl, 981 sc->sc_suspend_state.cs4280.pfie, 982 sc->sc_suspend_state.cs4280.pba, 983 sc->sc_suspend_state.cs4280.pdtc)); 984 cs4280_set_dac_rate(sc, sc->sc_prate); 985 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc); 986 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba); 987 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie); 988 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl); 989 } 990 991 if (sc->sc_rrun) { 992 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 993 sc->sc_suspend_state.cs4280.cctl, 994 sc->sc_suspend_state.cs4280.cie, 995 sc->sc_suspend_state.cs4280.cba)); 996 cs4280_set_adc_rate(sc, sc->sc_rrate); 997 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba); 998 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie); 999 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl); 1000 } 1001 1002 mutex_spin_exit(&sc->sc_intr_lock); 1003 1004 /* restore ac97 registers */ 1005 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1006 1007 mutex_exit(&sc->sc_lock); 1008 1009 return true; 1010 } 1011 1012 static int 1013 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 1014 { 1015 struct cs428x_softc *sc = addr; 1016 int rv; 1017 1018 cs4280_clkrun_hack(sc, 1); 1019 rv = cs428x_read_codec(addr, reg, result); 1020 cs4280_clkrun_hack(sc, -1); 1021 1022 return rv; 1023 } 1024 1025 static int 1026 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1027 { 1028 struct cs428x_softc *sc = addr; 1029 int rv; 1030 1031 cs4280_clkrun_hack(sc, 1); 1032 rv = cs428x_write_codec(addr, reg, data); 1033 cs4280_clkrun_hack(sc, -1); 1034 1035 return rv; 1036 } 1037 1038 #if 0 /* XXX buggy and not required */ 1039 /* control AC97 codec */ 1040 static int 1041 cs4280_reset_codec(void *addr) 1042 { 1043 struct cs428x_softc *sc; 1044 int n; 1045 1046 sc = addr; 1047 1048 /* Reset codec */ 1049 BA0WRITE4(sc, CS428X_ACCTL, 0); 1050 delay(100); /* delay 100us */ 1051 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1052 1053 /* 1054 * It looks like we do the following procedure, too 1055 */ 1056 1057 /* Enable AC-link sync generation */ 1058 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1059 delay(50*1000); /* XXX delay 50ms */ 1060 1061 /* Assert valid frame signal */ 1062 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1063 1064 /* Wait for valid AC97 input slot */ 1065 n = 0; 1066 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1067 (ACISV_ISV3 | ACISV_ISV4)) { 1068 delay(1000); 1069 if (++n > 1000) { 1070 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1071 return ETIMEDOUT; 1072 } 1073 } 1074 1075 return 0; 1076 } 1077 #endif 1078 1079 static enum ac97_host_flags 1080 cs4280_flags_codec(void *addr) 1081 { 1082 struct cs428x_softc *sc; 1083 1084 sc = addr; 1085 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1086 return AC97_HOST_INVERTED_EAMP; 1087 1088 return 0; 1089 } 1090 1091 /* Internal functions */ 1092 1093 static const struct cs4280_card_t * 1094 cs4280_identify_card(const struct pci_attach_args *pa) 1095 { 1096 pcireg_t idreg; 1097 u_int16_t i; 1098 1099 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1100 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1101 if (idreg == cs4280_cards[i].id) 1102 return &cs4280_cards[i]; 1103 } 1104 1105 return NULL; 1106 } 1107 1108 static int 1109 cs4280_piix4_match(const struct pci_attach_args *pa) 1110 { 1111 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1112 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1113 return 1; 1114 } 1115 1116 return 0; 1117 } 1118 1119 static void 1120 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1121 { 1122 uint16_t control, val; 1123 1124 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1125 return; 1126 1127 sc->sc_active += change; 1128 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1129 if (!sc->sc_active) 1130 val |= 0x2000; 1131 else 1132 val &= ~0x2000; 1133 if (val != control) 1134 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1135 } 1136 1137 static void 1138 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1139 { 1140 struct pci_attach_args smbuspa; 1141 uint16_t reg; 1142 pcireg_t port; 1143 1144 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1145 return; 1146 1147 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1148 sc->sc_active = 0; 1149 aprint_normal_dev(sc->sc_dev, "enabling CLKRUN hack\n"); 1150 1151 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1152 port = reg & 0xffc0; 1153 aprint_normal_dev(sc->sc_dev, "power management port 0x%x\n", 1154 port); 1155 1156 sc->sc_pm_iot = smbuspa.pa_iot; 1157 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1158 &sc->sc_pm_ioh) == 0) 1159 return; 1160 } 1161 1162 /* handle error */ 1163 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1164 aprint_normal_dev(sc->sc_dev, "disabling CLKRUN hack\n"); 1165 } 1166 1167 static void 1168 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1169 { 1170 /* calculate capture rate: 1171 * 1172 * capture_coefficient_increment = -round(rate*128*65536/48000; 1173 * capture_phase_increment = floor(48000*65536*1024/rate); 1174 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1175 * cy = floor(cx/200); 1176 * capture_sample_rate_correction = cx - 200*cy; 1177 * capture_delay = ceil(24*48000/rate); 1178 * capture_num_triplets = floor(65536*rate/24000); 1179 * capture_group_length = 24000/GCD(rate, 24000); 1180 * where GCD means "Greatest Common Divisor". 1181 * 1182 * capture_coefficient_increment, capture_phase_increment and 1183 * capture_num_triplets are 32-bit signed quantities. 1184 * capture_sample_rate_correction and capture_group_length are 1185 * 16-bit signed quantities. 1186 * capture_delay is a 14-bit unsigned quantity. 1187 */ 1188 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1189 uint16_t csrc, cgl, cdlay; 1190 1191 /* XXX 1192 * Even though, embedded_audio_spec says capture rate range 11025 to 1193 * 48000, dhwiface.cpp says, 1194 * 1195 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1196 * Return an error if an attempt is made to stray outside that limit." 1197 * 1198 * so assume range as 48000/9 to 48000 1199 */ 1200 1201 if (rate < 8000) 1202 rate = 8000; 1203 if (rate > 48000) 1204 rate = 48000; 1205 1206 cx = rate << 16; 1207 cci = cx / 48000; 1208 cx -= cci * 48000; 1209 cx <<= 7; 1210 cci <<= 7; 1211 cci += cx / 48000; 1212 cci = - cci; 1213 1214 cx = 48000 << 16; 1215 cpi = cx / rate; 1216 cx -= cpi * rate; 1217 cx <<= 10; 1218 cpi <<= 10; 1219 cy = cx / rate; 1220 cpi += cy; 1221 cx -= cy * rate; 1222 1223 cy = cx / 200; 1224 csrc = cx - 200*cy; 1225 1226 cdlay = ((48000 * 24) + rate - 1) / rate; 1227 #if 0 1228 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1229 #endif 1230 1231 cnt = rate << 16; 1232 cnt /= 24000; 1233 1234 cgl = 1; 1235 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1236 if (((rate / tmp1) * tmp1) != rate) 1237 cgl *= 2; 1238 } 1239 if (((rate / 3) * 3) != rate) 1240 cgl *= 3; 1241 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1242 if (((rate / tmp1) * tmp1) != rate) 1243 cgl *= 5; 1244 } 1245 #if 0 1246 /* XXX what manual says */ 1247 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1248 tmp1 |= csrc<<16; 1249 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1250 #else 1251 /* suggested by cs461x.c (ALSA driver) */ 1252 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1253 #endif 1254 1255 #if 0 1256 /* I am confused. The sample rate calculation section says 1257 * cci *is* 32-bit signed quantity but in the parameter description 1258 * section, CCI only assigned 16bit. 1259 * I believe size of the variable. 1260 */ 1261 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1262 tmp1 |= cci<<16; 1263 BA1WRITE4(sc, CS4280_CCI, tmp1); 1264 #else 1265 BA1WRITE4(sc, CS4280_CCI, cci); 1266 #endif 1267 1268 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1269 tmp1 |= cdlay <<18; 1270 BA1WRITE4(sc, CS4280_CD, tmp1); 1271 1272 BA1WRITE4(sc, CS4280_CPI, cpi); 1273 1274 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1275 tmp1 |= cgl; 1276 BA1WRITE4(sc, CS4280_CGL, tmp1); 1277 1278 BA1WRITE4(sc, CS4280_CNT, cnt); 1279 1280 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1281 tmp1 |= cgl; 1282 BA1WRITE4(sc, CS4280_CGC, tmp1); 1283 } 1284 1285 static void 1286 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1287 { 1288 /* 1289 * playback rate may range from 8000Hz to 48000Hz 1290 * 1291 * play_phase_increment = floor(rate*65536*1024/48000) 1292 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1293 * py=floor(px/200) 1294 * play_sample_rate_correction = px - 200*py 1295 * 1296 * play_phase_increment is a 32bit signed quantity. 1297 * play_sample_rate_correction is a 16bit signed quantity. 1298 */ 1299 int32_t ppi; 1300 int16_t psrc; 1301 uint32_t px, py; 1302 1303 if (rate < 8000) 1304 rate = 8000; 1305 if (rate > 48000) 1306 rate = 48000; 1307 px = rate << 16; 1308 ppi = px/48000; 1309 px -= ppi*48000; 1310 ppi <<= 10; 1311 px <<= 10; 1312 py = px / 48000; 1313 ppi += py; 1314 px -= py*48000; 1315 py = px/200; 1316 px -= py*200; 1317 psrc = px; 1318 #if 0 1319 /* what manual says */ 1320 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1321 BA1WRITE4(sc, CS4280_PSRC, 1322 ( ((psrc<<16) & PSRC_MASK) | px )); 1323 #else 1324 /* suggested by cs461x.c (ALSA driver) */ 1325 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1326 #endif 1327 BA1WRITE4(sc, CS4280_PPI, ppi); 1328 } 1329 1330 /* Download Processor Code and Data image */ 1331 static int 1332 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1333 uint32_t offset, uint32_t len) 1334 { 1335 uint32_t ctr; 1336 #if CS4280_DEBUG > 10 1337 uint32_t con, data; 1338 uint8_t c0, c1, c2, c3; 1339 #endif 1340 if ((offset & 3) || (len & 3)) 1341 return -1; 1342 1343 len /= sizeof(uint32_t); 1344 for (ctr = 0; ctr < len; ctr++) { 1345 /* XXX: 1346 * I cannot confirm this is the right thing or not 1347 * on BIG-ENDIAN machines. 1348 */ 1349 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1350 #if CS4280_DEBUG > 10 1351 data = htole32(*(src+ctr)); 1352 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1353 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1354 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1355 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1356 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1357 if (data != con ) { 1358 printf("0x%06x: write=0x%08x read=0x%08x\n", 1359 offset+ctr*4, data, con); 1360 return -1; 1361 } 1362 #endif 1363 } 1364 return 0; 1365 } 1366 1367 static int 1368 cs4280_download_image(struct cs428x_softc *sc) 1369 { 1370 int idx, err; 1371 uint32_t offset = 0; 1372 1373 err = 0; 1374 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1375 err = cs4280_download(sc, &BA1Struct.map[offset], 1376 BA1Struct.memory[idx].offset, 1377 BA1Struct.memory[idx].size); 1378 if (err != 0) { 1379 aprint_error_dev(sc->sc_dev, 1380 "load_image failed at %d\n", idx); 1381 return -1; 1382 } 1383 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1384 } 1385 return err; 1386 } 1387 1388 /* Processor Soft Reset */ 1389 static void 1390 cs4280_reset(void *sc_) 1391 { 1392 struct cs428x_softc *sc; 1393 1394 sc = sc_; 1395 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1396 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1397 delay(100); 1398 /* Clear RSTSP bit in SPCR */ 1399 BA1WRITE4(sc, CS4280_SPCR, 0); 1400 /* enable DMA reqest */ 1401 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1402 } 1403 1404 static int 1405 cs4280_init(struct cs428x_softc *sc, int init) 1406 { 1407 int n; 1408 uint32_t mem; 1409 int rv; 1410 1411 rv = 1; 1412 cs4280_clkrun_hack(sc, 1); 1413 1414 /* Start PLL out in known state */ 1415 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1416 /* Start serial ports out in known state */ 1417 BA0WRITE4(sc, CS4280_SERMC1, 0); 1418 1419 /* Specify type of CODEC */ 1420 /* XXX should not be here */ 1421 #define SERACC_CODEC_TYPE_1_03 1422 #ifdef SERACC_CODEC_TYPE_1_03 1423 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1424 #else 1425 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1426 #endif 1427 1428 /* Reset codec */ 1429 BA0WRITE4(sc, CS428X_ACCTL, 0); 1430 delay(100); /* delay 100us */ 1431 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1432 1433 /* Enable AC-link sync generation */ 1434 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1435 delay(50*1000); /* delay 50ms */ 1436 1437 /* Set the serial port timing configuration */ 1438 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1439 1440 /* Setup clock control */ 1441 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1442 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1443 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1444 1445 /* Power up the PLL */ 1446 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1447 delay(50*1000); /* delay 50ms */ 1448 1449 /* Turn on clock */ 1450 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1451 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1452 1453 /* Set the serial port FIFO pointer to the 1454 * first sample in FIFO. (not documented) */ 1455 cs4280_clear_fifos(sc); 1456 1457 #if 0 1458 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1459 BA0WRITE4(sc, CS4280_SERBSP, 0); 1460 #endif 1461 1462 /* Configure the serial port */ 1463 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1464 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1465 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1466 1467 /* Wait for CODEC ready */ 1468 n = 0; 1469 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1470 delay(125); 1471 if (++n > 1000) { 1472 aprint_error_dev(sc->sc_dev, "codec ready timeout\n"); 1473 goto exit; 1474 } 1475 } 1476 1477 /* Assert valid frame signal */ 1478 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1479 1480 /* Wait for valid AC97 input slot */ 1481 n = 0; 1482 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1483 (ACISV_ISV3 | ACISV_ISV4)) { 1484 delay(1000); 1485 if (++n > 1000) { 1486 printf("AC97 inputs slot ready timeout\n"); 1487 goto exit; 1488 } 1489 } 1490 1491 /* Set AC97 output slot valid signals */ 1492 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1493 1494 /* reset the processor */ 1495 cs4280_reset(sc); 1496 1497 /* Download the image to the processor */ 1498 if (cs4280_download_image(sc) != 0) { 1499 aprint_error_dev(sc->sc_dev, "image download error\n"); 1500 goto exit; 1501 } 1502 1503 /* Save playback parameter and then write zero. 1504 * this ensures that DMA doesn't immediately occur upon 1505 * starting the processor core 1506 */ 1507 mem = BA1READ4(sc, CS4280_PCTL); 1508 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1509 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1510 if (init != 0) 1511 sc->sc_prun = 0; 1512 1513 /* Save capture parameter and then write zero. 1514 * this ensures that DMA doesn't immediately occur upon 1515 * starting the processor core 1516 */ 1517 mem = BA1READ4(sc, CS4280_CCTL); 1518 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1519 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1520 if (init != 0) 1521 sc->sc_rrun = 0; 1522 1523 /* Processor Startup Procedure */ 1524 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1525 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1526 1527 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1528 n = 0; 1529 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1530 delay(10); 1531 if (++n > 1000) { 1532 printf("SPCR 1->0 transition timeout\n"); 1533 goto exit; 1534 } 1535 } 1536 1537 n = 0; 1538 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1539 delay(10); 1540 if (++n > 1000) { 1541 printf("SPCS 0->1 transition timeout\n"); 1542 goto exit; 1543 } 1544 } 1545 /* Processor is now running !!! */ 1546 1547 /* Setup volume */ 1548 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1549 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1550 1551 /* Interrupt enable */ 1552 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1553 1554 /* playback interrupt enable */ 1555 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1556 mem |= PFIE_PI_ENABLE; 1557 BA1WRITE4(sc, CS4280_PFIE, mem); 1558 /* capture interrupt enable */ 1559 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1560 mem |= CIE_CI_ENABLE; 1561 BA1WRITE4(sc, CS4280_CIE, mem); 1562 1563 #if NMIDI > 0 1564 /* Reset midi port */ 1565 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1566 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1567 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1568 /* midi interrupt enable */ 1569 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1570 BA0WRITE4(sc, CS4280_MIDCR, mem); 1571 #endif 1572 1573 rv = 0; 1574 1575 exit: 1576 cs4280_clkrun_hack(sc, -1); 1577 return rv; 1578 } 1579 1580 static void 1581 cs4280_clear_fifos(struct cs428x_softc *sc) 1582 { 1583 int pd, cnt, n; 1584 uint32_t mem; 1585 1586 pd = 0; 1587 /* 1588 * If device power down, power up the device and keep power down 1589 * state. 1590 */ 1591 mem = BA0READ4(sc, CS4280_CLKCR1); 1592 if (!(mem & CLKCR1_SWCE)) { 1593 printf("cs4280_clear_fifo: power down found.\n"); 1594 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1595 pd = 1; 1596 } 1597 BA0WRITE4(sc, CS4280_SERBWP, 0); 1598 for (cnt = 0; cnt < 256; cnt++) { 1599 n = 0; 1600 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1601 delay(1000); 1602 if (++n > 1000) { 1603 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1604 break; 1605 } 1606 } 1607 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1608 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1609 } 1610 if (pd) 1611 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1612 } 1613 1614 #if NMIDI > 0 1615 static int 1616 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1617 void (*ointr)(void *), void *arg) 1618 { 1619 struct cs428x_softc *sc; 1620 uint32_t mem; 1621 1622 DPRINTF(("midi_open\n")); 1623 sc = addr; 1624 sc->sc_iintr = iintr; 1625 sc->sc_ointr = ointr; 1626 sc->sc_arg = arg; 1627 1628 /* midi interrupt enable */ 1629 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1630 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1631 BA0WRITE4(sc, CS4280_MIDCR, mem); 1632 #ifdef CS4280_DEBUG 1633 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1634 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1635 return(EINVAL); 1636 } 1637 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1638 #endif 1639 return 0; 1640 } 1641 1642 static void 1643 cs4280_midi_close(void *addr) 1644 { 1645 struct cs428x_softc *sc; 1646 uint32_t mem; 1647 1648 DPRINTF(("midi_close\n")); 1649 sc = addr; 1650 /* give uart a chance to drain */ 1651 kpause("cs0clm", false, hz/10, &sc->sc_intr_lock); 1652 mem = BA0READ4(sc, CS4280_MIDCR); 1653 mem &= ~MIDCR_MASK; 1654 BA0WRITE4(sc, CS4280_MIDCR, mem); 1655 1656 sc->sc_iintr = 0; 1657 sc->sc_ointr = 0; 1658 } 1659 1660 static int 1661 cs4280_midi_output(void *addr, int d) 1662 { 1663 struct cs428x_softc *sc; 1664 uint32_t mem; 1665 int x; 1666 1667 sc = addr; 1668 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1669 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1670 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1671 mem |= d & MIDWP_MASK; 1672 DPRINTFN(5,("midi_output d=0x%08x",d)); 1673 BA0WRITE4(sc, CS4280_MIDWP, mem); 1674 #ifdef DIAGNOSTIC 1675 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1676 DPRINTF(("Bad write data: %d %d", 1677 mem, BA0READ4(sc, CS4280_MIDWP))); 1678 return EIO; 1679 } 1680 #endif 1681 return 0; 1682 } 1683 delay(MIDI_BUSY_DELAY); 1684 } 1685 return EIO; 1686 } 1687 1688 static void 1689 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1690 { 1691 1692 mi->name = "CS4280 MIDI UART"; 1693 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1694 } 1695 1696 #endif /* NMIDI */ 1697 1698 /* DEBUG functions */ 1699 #if CS4280_DEBUG > 10 1700 static int 1701 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1702 uint32_t offset, uint32_t len) 1703 { 1704 uint32_t ctr, data; 1705 int err; 1706 1707 if ((offset & 3) || (len & 3)) 1708 return -1; 1709 1710 err = 0; 1711 len /= sizeof(uint32_t); 1712 for (ctr = 0; ctr < len; ctr++) { 1713 /* I cannot confirm this is the right thing 1714 * on BIG-ENDIAN machines 1715 */ 1716 data = BA1READ4(sc, offset+ctr*4); 1717 if (data != htole32(*(src+ctr))) { 1718 printf("0x%06x: 0x%08x(0x%08x)\n", 1719 offset+ctr*4, data, *(src+ctr)); 1720 *(src+ctr) = data; 1721 ++err; 1722 } 1723 } 1724 return err; 1725 } 1726 1727 static int 1728 cs4280_check_images(struct cs428x_softc *sc) 1729 { 1730 int idx, err; 1731 uint32_t offset; 1732 1733 offset = 0; 1734 err = 0; 1735 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1736 for (idx = 0; idx < 1; ++idx) { 1737 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1738 BA1Struct.memory[idx].offset, 1739 BA1Struct.memory[idx].size); 1740 if (err != 0) { 1741 aprint_error_dev(sc->sc_dev, 1742 "check_image failed at %d\n", idx); 1743 } 1744 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1745 } 1746 return err; 1747 } 1748 1749 #endif /* CS4280_DEBUG */ 1750