1 /* $NetBSD: cs4280.c,v 1.45 2006/11/16 01:33:08 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Cirrus Logic CS4280 (and maybe CS461x) driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pubs/4280.pdf 37 * http://www.cirrus.com/ftp/pubs/4297.pdf 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 40 * 41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with 42 * wss* at pnpbios? 43 * or 44 * sb* at pnpbios? 45 * Since I could not find any documents on handling ISA codec, 46 * clcs does not support those chips. 47 */ 48 49 /* 50 * TODO 51 * Joystick support 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.45 2006/11/16 01:33:08 christos Exp $"); 56 57 #include "midi.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/kernel.h> 62 #include <sys/fcntl.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 68 #include <dev/pci/pcidevs.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/cs4280reg.h> 71 #include <dev/pci/cs4280_image.h> 72 #include <dev/pci/cs428xreg.h> 73 74 #include <sys/audioio.h> 75 #include <dev/audio_if.h> 76 #include <dev/midi_if.h> 77 #include <dev/mulaw.h> 78 #include <dev/auconv.h> 79 80 #include <dev/ic/ac97reg.h> 81 #include <dev/ic/ac97var.h> 82 83 #include <dev/pci/cs428x.h> 84 85 #include <machine/bus.h> 86 #include <sys/bswap.h> 87 88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 90 91 /* IF functions for audio driver */ 92 static int cs4280_match(struct device *, struct cfdata *, void *); 93 static void cs4280_attach(struct device *, struct device *, void *); 94 static int cs4280_intr(void *); 95 static int cs4280_query_encoding(void *, struct audio_encoding *); 96 static int cs4280_set_params(void *, int, int, audio_params_t *, 97 audio_params_t *, stream_filter_list_t *, 98 stream_filter_list_t *); 99 static int cs4280_halt_output(void *); 100 static int cs4280_halt_input(void *); 101 static int cs4280_getdev(void *, struct audio_device *); 102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 103 void *, const audio_params_t *); 104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 105 void *, const audio_params_t *); 106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *); 107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t); 108 #if 0 109 static int cs4280_reset_codec(void *); 110 #endif 111 static enum ac97_host_flags cs4280_flags_codec(void *); 112 113 /* For PowerHook */ 114 static void cs4280_power(int, void *); 115 116 /* Internal functions */ 117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *); 118 static int cs4280_piix4_match(struct pci_attach_args *); 119 static void cs4280_clkrun_hack(struct cs428x_softc *, int); 120 static void cs4280_clkrun_hack_init(struct cs428x_softc *); 121 static void cs4280_set_adc_rate(struct cs428x_softc *, int ); 122 static void cs4280_set_dac_rate(struct cs428x_softc *, int ); 123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t, 124 uint32_t); 125 static int cs4280_download_image(struct cs428x_softc *); 126 static void cs4280_reset(void *); 127 static int cs4280_init(struct cs428x_softc *, int); 128 static void cs4280_clear_fifos(struct cs428x_softc *); 129 130 #if CS4280_DEBUG > 10 131 /* Thease two function is only for checking image loading is succeeded or not. */ 132 static int cs4280_check_images(struct cs428x_softc *); 133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t, 134 uint32_t); 135 #endif 136 137 /* Special cards */ 138 struct cs4280_card_t 139 { 140 pcireg_t id; 141 enum cs428x_flags flags; 142 }; 143 144 #define _card(vend, prod, flags) \ 145 {PCI_ID_CODE(vend, prod), flags} 146 147 static const struct cs4280_card_t cs4280_cards[] = { 148 #if 0 /* untested, from ALSA driver */ 149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020, 150 CS428X_FLAG_INVAC97EAMP), 151 #endif 152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ, 153 CS428X_FLAG_INVAC97EAMP), 154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO, 155 CS428X_FLAG_CLKRUNHACK) 156 }; 157 158 #undef _card 159 160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0])) 161 162 static const struct audio_hw_if cs4280_hw_if = { 163 NULL, /* open */ 164 NULL, /* close */ 165 NULL, 166 cs4280_query_encoding, 167 cs4280_set_params, 168 cs428x_round_blocksize, 169 NULL, 170 NULL, 171 NULL, 172 NULL, 173 NULL, 174 cs4280_halt_output, 175 cs4280_halt_input, 176 NULL, 177 cs4280_getdev, 178 NULL, 179 cs428x_mixer_set_port, 180 cs428x_mixer_get_port, 181 cs428x_query_devinfo, 182 cs428x_malloc, 183 cs428x_free, 184 cs428x_round_buffersize, 185 cs428x_mappage, 186 cs428x_get_props, 187 cs4280_trigger_output, 188 cs4280_trigger_input, 189 NULL, 190 NULL, 191 }; 192 193 #if NMIDI > 0 194 /* Midi Interface */ 195 static int cs4280_midi_open(void *, int, void (*)(void *, int), 196 void (*)(void *), void *); 197 static void cs4280_midi_close(void*); 198 static int cs4280_midi_output(void *, int); 199 static void cs4280_midi_getinfo(void *, struct midi_info *); 200 201 static const struct midi_hw_if cs4280_midi_hw_if = { 202 cs4280_midi_open, 203 cs4280_midi_close, 204 cs4280_midi_output, 205 cs4280_midi_getinfo, 206 0, 207 }; 208 #endif 209 210 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc), 211 cs4280_match, cs4280_attach, NULL, NULL); 212 213 static struct audio_device cs4280_device = { 214 "CS4280", 215 "", 216 "cs4280" 217 }; 218 219 220 static int 221 cs4280_match(struct device *parent, struct cfdata *match, 222 void *aux) 223 { 224 struct pci_attach_args *pa; 225 226 pa = (struct pci_attach_args *)aux; 227 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 228 return 0; 229 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 230 #if 0 /* I can't confirm */ 231 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 232 #endif 233 ) 234 return 1; 235 return 0; 236 } 237 238 static void 239 cs4280_attach(struct device *parent, struct device *self, void *aux) 240 { 241 struct cs428x_softc *sc; 242 struct pci_attach_args *pa; 243 pci_chipset_tag_t pc; 244 const struct cs4280_card_t *cs_card; 245 char const *intrstr; 246 pci_intr_handle_t ih; 247 pcireg_t reg; 248 char devinfo[256]; 249 uint32_t mem; 250 int error; 251 252 sc = (struct cs428x_softc *)self; 253 pa = (struct pci_attach_args *)aux; 254 pc = pa->pa_pc; 255 aprint_naive(": Audio controller\n"); 256 257 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 258 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 259 PCI_REVISION(pa->pa_class)); 260 261 cs_card = cs4280_identify_card(pa); 262 if (cs_card != NULL) { 263 aprint_normal("%s: %s %s\n",sc->sc_dev.dv_xname, 264 pci_findvendor(cs_card->id), 265 pci_findproduct(cs_card->id)); 266 sc->sc_flags = cs_card->flags; 267 } else { 268 sc->sc_flags = CS428X_FLAG_NONE; 269 } 270 271 /* Map I/O register */ 272 if (pci_mapreg_map(pa, PCI_BA0, 273 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 274 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 275 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 276 return; 277 } 278 if (pci_mapreg_map(pa, PCI_BA1, 279 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 280 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 281 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 282 return; 283 } 284 285 sc->sc_dmatag = pa->pa_dmat; 286 287 /* power up chip */ 288 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 289 pci_activate_null)) && error != EOPNOTSUPP) { 290 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 291 error); 292 return; 293 } 294 295 /* Enable the device (set bus master flag) */ 296 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 297 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 298 reg | PCI_COMMAND_MASTER_ENABLE); 299 300 /* LATENCY_TIMER setting */ 301 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 302 if ( PCI_LATTIMER(mem) < 32 ) { 303 mem &= 0xffff00ff; 304 mem |= 0x00002000; 305 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 306 } 307 308 /* CLKRUN hack initialization */ 309 cs4280_clkrun_hack_init(sc); 310 311 /* Map and establish the interrupt. */ 312 if (pci_intr_map(pa, &ih)) { 313 aprint_error("%s: couldn't map interrupt\n", 314 sc->sc_dev.dv_xname); 315 return; 316 } 317 intrstr = pci_intr_string(pc, ih); 318 319 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc); 320 if (sc->sc_ih == NULL) { 321 aprint_error("%s: couldn't establish interrupt", 322 sc->sc_dev.dv_xname); 323 if (intrstr != NULL) 324 aprint_normal(" at %s", intrstr); 325 aprint_normal("\n"); 326 return; 327 } 328 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 329 330 /* Initialization */ 331 if(cs4280_init(sc, 1) != 0) 332 return; 333 334 sc->type = TYPE_CS4280; 335 sc->halt_input = cs4280_halt_input; 336 sc->halt_output = cs4280_halt_output; 337 338 /* setup buffer related parameters */ 339 sc->dma_size = CS4280_DCHUNK; 340 sc->dma_align = CS4280_DALIGN; 341 sc->hw_blocksize = CS4280_ICHUNK; 342 343 /* AC 97 attachment */ 344 sc->host_if.arg = sc; 345 sc->host_if.attach = cs428x_attach_codec; 346 sc->host_if.read = cs4280_read_codec; 347 sc->host_if.write = cs4280_write_codec; 348 #if 0 349 sc->host_if.reset = cs4280_reset_codec; 350 #else 351 sc->host_if.reset = NULL; 352 #endif 353 sc->host_if.flags = cs4280_flags_codec; 354 if (ac97_attach(&sc->host_if, self) != 0) { 355 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 356 return; 357 } 358 359 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 360 361 #if NMIDI > 0 362 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 363 #endif 364 365 sc->sc_suspend = PWR_RESUME; 366 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 367 cs4280_power, sc); 368 } 369 370 /* Interrupt handling function */ 371 static int 372 cs4280_intr(void *p) 373 { 374 /* 375 * XXX 376 * 377 * Since CS4280 has only 4kB DMA buffer and 378 * interrupt occurs every 2kB block, I create dummy buffer 379 * which returns to audio driver and actual DMA buffer 380 * using in DMA transfer. 381 * 382 * 383 * ring buffer in audio.c is pointed by BUFADDR 384 * <------ ring buffer size == 64kB ------> 385 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 386 * |= = = =|= = = =|= = = =|= = = =|= = = =| 387 * | | | | | | <- call audio_intp every 388 * sc->sc_[pr]_count time. 389 * 390 * actual DMA buffer is pointed by KERNADDR 391 * <-> DMA buffer size = 4kB 392 * |= =| 393 * 394 * 395 */ 396 struct cs428x_softc *sc; 397 uint32_t intr, mem; 398 char * empty_dma; 399 int handled; 400 401 sc = p; 402 handled = 0; 403 /* grab interrupt register then clear it */ 404 intr = BA0READ4(sc, CS4280_HISR); 405 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 406 407 /* not for us ? */ 408 if ((intr & HISR_INTENA) == 0) 409 return 0; 410 411 /* Playback Interrupt */ 412 if (intr & HISR_PINT) { 413 handled = 1; 414 mem = BA1READ4(sc, CS4280_PFIE); 415 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 416 if (sc->sc_prun) { 417 if ((sc->sc_pi%sc->sc_pcount) == 0) 418 sc->sc_pintr(sc->sc_parg); 419 /* copy buffer */ 420 ++sc->sc_pi; 421 empty_dma = sc->sc_pdma->addr; 422 if (sc->sc_pi&1) 423 empty_dma += sc->hw_blocksize; 424 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 425 sc->sc_pn += sc->hw_blocksize; 426 if (sc->sc_pn >= sc->sc_pe) 427 sc->sc_pn = sc->sc_ps; 428 } else { 429 printf("%s: unexpected play intr\n", 430 sc->sc_dev.dv_xname); 431 } 432 BA1WRITE4(sc, CS4280_PFIE, mem); 433 } 434 /* Capture Interrupt */ 435 if (intr & HISR_CINT) { 436 int i; 437 int16_t rdata; 438 439 handled = 1; 440 mem = BA1READ4(sc, CS4280_CIE); 441 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 442 443 if (sc->sc_rrun) { 444 ++sc->sc_ri; 445 empty_dma = sc->sc_rdma->addr; 446 if ((sc->sc_ri&1) == 0) 447 empty_dma += sc->hw_blocksize; 448 449 /* 450 * XXX 451 * I think this audio data conversion should be 452 * happend in upper layer, but I put this here 453 * since there is no conversion function available. 454 */ 455 switch(sc->sc_rparam) { 456 case CF_16BIT_STEREO: 457 /* just copy it */ 458 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 459 sc->sc_rn += sc->hw_blocksize; 460 break; 461 case CF_16BIT_MONO: 462 for (i = 0; i < 512; i++) { 463 rdata = *((int16_t *)empty_dma)>>1; 464 empty_dma += 2; 465 rdata += *((int16_t *)empty_dma)>>1; 466 empty_dma += 2; 467 *((int16_t *)sc->sc_rn) = rdata; 468 sc->sc_rn += 2; 469 } 470 break; 471 case CF_8BIT_STEREO: 472 for (i = 0; i < 512; i++) { 473 rdata = *((int16_t*)empty_dma); 474 empty_dma += 2; 475 *sc->sc_rn++ = rdata >> 8; 476 rdata = *((int16_t*)empty_dma); 477 empty_dma += 2; 478 *sc->sc_rn++ = rdata >> 8; 479 } 480 break; 481 case CF_8BIT_MONO: 482 for (i = 0; i < 512; i++) { 483 rdata = *((int16_t*)empty_dma) >>1; 484 empty_dma += 2; 485 rdata += *((int16_t*)empty_dma) >>1; 486 empty_dma += 2; 487 *sc->sc_rn++ = rdata >>8; 488 } 489 break; 490 default: 491 /* Should not reach here */ 492 printf("%s: unknown sc->sc_rparam: %d\n", 493 sc->sc_dev.dv_xname, sc->sc_rparam); 494 } 495 if (sc->sc_rn >= sc->sc_re) 496 sc->sc_rn = sc->sc_rs; 497 } 498 BA1WRITE4(sc, CS4280_CIE, mem); 499 500 if (sc->sc_rrun) { 501 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 502 sc->sc_rintr(sc->sc_rarg); 503 } else { 504 printf("%s: unexpected record intr\n", 505 sc->sc_dev.dv_xname); 506 } 507 } 508 509 #if NMIDI > 0 510 /* Midi port Interrupt */ 511 if (intr & HISR_MIDI) { 512 int data; 513 514 handled = 1; 515 DPRINTF(("i: %d: ", 516 BA0READ4(sc, CS4280_MIDSR))); 517 /* Read the received data */ 518 while ((sc->sc_iintr != NULL) && 519 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 520 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 521 DPRINTF(("r:%x\n",data)); 522 sc->sc_iintr(sc->sc_arg, data); 523 } 524 525 /* Write the data */ 526 #if 1 527 /* XXX: 528 * It seems "Transmit Buffer Full" never activate until EOI 529 * is deliverd. Shall I throw EOI top of this routine ? 530 */ 531 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 532 DPRINTF(("w: ")); 533 if (sc->sc_ointr != NULL) 534 sc->sc_ointr(sc->sc_arg); 535 } 536 #else 537 while ((sc->sc_ointr != NULL) && 538 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 539 DPRINTF(("w: ")); 540 sc->sc_ointr(sc->sc_arg); 541 } 542 #endif 543 DPRINTF(("\n")); 544 } 545 #endif 546 547 return handled; 548 } 549 550 static int 551 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 552 { 553 switch (fp->index) { 554 case 0: 555 strcpy(fp->name, AudioEulinear); 556 fp->encoding = AUDIO_ENCODING_ULINEAR; 557 fp->precision = 8; 558 fp->flags = 0; 559 break; 560 case 1: 561 strcpy(fp->name, AudioEmulaw); 562 fp->encoding = AUDIO_ENCODING_ULAW; 563 fp->precision = 8; 564 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 565 break; 566 case 2: 567 strcpy(fp->name, AudioEalaw); 568 fp->encoding = AUDIO_ENCODING_ALAW; 569 fp->precision = 8; 570 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 571 break; 572 case 3: 573 strcpy(fp->name, AudioEslinear); 574 fp->encoding = AUDIO_ENCODING_SLINEAR; 575 fp->precision = 8; 576 fp->flags = 0; 577 break; 578 case 4: 579 strcpy(fp->name, AudioEslinear_le); 580 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 581 fp->precision = 16; 582 fp->flags = 0; 583 break; 584 case 5: 585 strcpy(fp->name, AudioEulinear_le); 586 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 587 fp->precision = 16; 588 fp->flags = 0; 589 break; 590 case 6: 591 strcpy(fp->name, AudioEslinear_be); 592 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 593 fp->precision = 16; 594 fp->flags = 0; 595 break; 596 case 7: 597 strcpy(fp->name, AudioEulinear_be); 598 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 599 fp->precision = 16; 600 fp->flags = 0; 601 break; 602 default: 603 return EINVAL; 604 } 605 return 0; 606 } 607 608 static int 609 cs4280_set_params(void *addr, int setmode, int usemode, 610 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 611 stream_filter_list_t *rfil) 612 { 613 audio_params_t hw; 614 struct cs428x_softc *sc; 615 struct audio_params *p; 616 stream_filter_list_t *fil; 617 int mode; 618 619 sc = addr; 620 for (mode = AUMODE_RECORD; mode != -1; 621 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 622 if ((setmode & mode) == 0) 623 continue; 624 625 p = mode == AUMODE_PLAY ? play : rec; 626 627 if (p == play) { 628 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n", 629 p->sample_rate, p->precision, p->channels)); 630 /* play back data format may be 8- or 16-bit and 631 * either stereo or mono. 632 * playback rate may range from 8000Hz to 48000Hz 633 */ 634 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 635 (p->precision != 8 && p->precision != 16) || 636 (p->channels != 1 && p->channels != 2) ) { 637 return EINVAL; 638 } 639 } else { 640 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n", 641 p->sample_rate, p->precision, p->channels)); 642 /* capture data format must be 16bit stereo 643 * and sample rate range from 11025Hz to 48000Hz. 644 * 645 * XXX: it looks like to work with 8000Hz, 646 * although data sheets say lower limit is 647 * 11025 Hz. 648 */ 649 650 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 651 (p->precision != 8 && p->precision != 16) || 652 (p->channels != 1 && p->channels != 2) ) { 653 return EINVAL; 654 } 655 } 656 fil = mode == AUMODE_PLAY ? pfil : rfil; 657 hw = *p; 658 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 659 660 /* capturing data is slinear */ 661 switch (p->encoding) { 662 case AUDIO_ENCODING_SLINEAR_BE: 663 if (mode == AUMODE_RECORD && p->precision == 16) { 664 fil->append(fil, swap_bytes, &hw); 665 } 666 break; 667 case AUDIO_ENCODING_SLINEAR_LE: 668 break; 669 case AUDIO_ENCODING_ULINEAR_BE: 670 if (mode == AUMODE_RECORD) { 671 fil->append(fil, p->precision == 16 672 ? swap_bytes_change_sign16 673 : change_sign8, &hw); 674 } 675 break; 676 case AUDIO_ENCODING_ULINEAR_LE: 677 if (mode == AUMODE_RECORD) { 678 fil->append(fil, p->precision == 16 679 ? change_sign16 : change_sign8, 680 &hw); 681 } 682 break; 683 case AUDIO_ENCODING_ULAW: 684 if (mode == AUMODE_PLAY) { 685 hw.precision = 16; 686 hw.validbits = 16; 687 fil->append(fil, mulaw_to_linear16, &hw); 688 } else { 689 fil->append(fil, linear8_to_mulaw, &hw); 690 } 691 break; 692 case AUDIO_ENCODING_ALAW: 693 if (mode == AUMODE_PLAY) { 694 hw.precision = 16; 695 hw.validbits = 16; 696 fil->append(fil, alaw_to_linear16, &hw); 697 } else { 698 fil->append(fil, linear8_to_alaw, &hw); 699 } 700 break; 701 default: 702 return EINVAL; 703 } 704 } 705 706 /* set sample rate */ 707 cs4280_set_dac_rate(sc, play->sample_rate); 708 cs4280_set_adc_rate(sc, rec->sample_rate); 709 return 0; 710 } 711 712 static int 713 cs4280_halt_output(void *addr) 714 { 715 struct cs428x_softc *sc; 716 uint32_t mem; 717 718 sc = addr; 719 mem = BA1READ4(sc, CS4280_PCTL); 720 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 721 sc->sc_prun = 0; 722 cs4280_clkrun_hack(sc, -1); 723 724 return 0; 725 } 726 727 static int 728 cs4280_halt_input(void *addr) 729 { 730 struct cs428x_softc *sc; 731 uint32_t mem; 732 733 sc = addr; 734 mem = BA1READ4(sc, CS4280_CCTL); 735 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 736 sc->sc_rrun = 0; 737 cs4280_clkrun_hack(sc, -1); 738 739 return 0; 740 } 741 742 static int 743 cs4280_getdev(void *addr, struct audio_device *retp) 744 { 745 746 *retp = cs4280_device; 747 return 0; 748 } 749 750 static int 751 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 752 void (*intr)(void *), void *arg, 753 const audio_params_t *param) 754 { 755 struct cs428x_softc *sc; 756 uint32_t pfie, pctl, pdtc; 757 struct cs428x_dma *p; 758 759 sc = addr; 760 #ifdef DIAGNOSTIC 761 if (sc->sc_prun) 762 printf("cs4280_trigger_output: already running\n"); 763 #endif 764 sc->sc_prun = 1; 765 cs4280_clkrun_hack(sc, 1); 766 767 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 768 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 769 sc->sc_pintr = intr; 770 sc->sc_parg = arg; 771 772 /* stop playback DMA */ 773 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK); 774 775 /* setup PDTC */ 776 pdtc = BA1READ4(sc, CS4280_PDTC); 777 pdtc &= ~PDTC_MASK; 778 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 779 BA1WRITE4(sc, CS4280_PDTC, pdtc); 780 781 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 782 param->precision, param->channels, param->encoding)); 783 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 784 continue; 785 if (p == NULL) { 786 printf("cs4280_trigger_output: bad addr %p\n", start); 787 return EINVAL; 788 } 789 if (DMAADDR(p) % sc->dma_align != 0 ) { 790 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 791 "4kB align\n", (ulong)DMAADDR(p)); 792 return EINVAL; 793 } 794 795 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 796 sc->sc_ps = (char *)start; 797 sc->sc_pe = (char *)end; 798 sc->sc_pdma = p; 799 sc->sc_pbuf = KERNADDR(p); 800 sc->sc_pi = 0; 801 sc->sc_pn = sc->sc_ps; 802 if (blksize >= sc->dma_size) { 803 sc->sc_pn = sc->sc_ps + sc->dma_size; 804 memcpy(sc->sc_pbuf, start, sc->dma_size); 805 ++sc->sc_pi; 806 } else { 807 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 808 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 809 } 810 811 /* initiate playback DMA */ 812 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 813 814 /* set PFIE */ 815 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 816 817 if (param->precision == 8) 818 pfie |= PFIE_8BIT; 819 if (param->channels == 1) 820 pfie |= PFIE_MONO; 821 822 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 823 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 824 pfie |= PFIE_SWAPPED; 825 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 826 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 827 pfie |= PFIE_UNSIGNED; 828 829 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 830 831 sc->sc_prate = param->sample_rate; 832 cs4280_set_dac_rate(sc, param->sample_rate); 833 834 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 835 pctl |= sc->pctl; 836 BA1WRITE4(sc, CS4280_PCTL, pctl); 837 return 0; 838 } 839 840 static int 841 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 842 void (*intr)(void *), void *arg, 843 const audio_params_t *param) 844 { 845 struct cs428x_softc *sc; 846 uint32_t cctl, cie; 847 struct cs428x_dma *p; 848 849 sc = addr; 850 #ifdef DIAGNOSTIC 851 if (sc->sc_rrun) 852 printf("cs4280_trigger_input: already running\n"); 853 #endif 854 sc->sc_rrun = 1; 855 cs4280_clkrun_hack(sc, 1); 856 857 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 858 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 859 sc->sc_rintr = intr; 860 sc->sc_rarg = arg; 861 862 /* stop capture DMA */ 863 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 864 865 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 866 continue; 867 if (p == NULL) { 868 printf("cs4280_trigger_input: bad addr %p\n", start); 869 return EINVAL; 870 } 871 if (DMAADDR(p) % sc->dma_align != 0) { 872 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 873 "4kB align\n", (ulong)DMAADDR(p)); 874 return EINVAL; 875 } 876 877 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/ 878 sc->sc_rs = (char *)start; 879 sc->sc_re = (char *)end; 880 sc->sc_rdma = p; 881 sc->sc_rbuf = KERNADDR(p); 882 sc->sc_ri = 0; 883 sc->sc_rn = sc->sc_rs; 884 885 /* initiate capture DMA */ 886 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 887 888 /* setup format information for internal converter */ 889 sc->sc_rparam = 0; 890 if (param->precision == 8) { 891 sc->sc_rparam += CF_8BIT; 892 sc->sc_rcount <<= 1; 893 } 894 if (param->channels == 1) { 895 sc->sc_rparam += CF_MONO; 896 sc->sc_rcount <<= 1; 897 } 898 899 /* set CIE */ 900 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 901 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 902 903 sc->sc_rrate = param->sample_rate; 904 cs4280_set_adc_rate(sc, param->sample_rate); 905 906 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 907 cctl |= sc->cctl; 908 BA1WRITE4(sc, CS4280_CCTL, cctl); 909 return 0; 910 } 911 912 /* Power Hook */ 913 static void 914 cs4280_power(int why, void *v) 915 { 916 static uint32_t pctl = 0, pba = 0, pfie = 0, pdtc = 0; 917 static uint32_t cctl = 0, cba = 0, cie = 0; 918 struct cs428x_softc *sc; 919 920 sc = (struct cs428x_softc *)v; 921 DPRINTF(("%s: cs4280_power why=%d\n", sc->sc_dev.dv_xname, why)); 922 switch (why) { 923 case PWR_SUSPEND: 924 case PWR_STANDBY: 925 sc->sc_suspend = why; 926 927 /* save current playback status */ 928 if (sc->sc_prun) { 929 pctl = BA1READ4(sc, CS4280_PCTL); 930 pfie = BA1READ4(sc, CS4280_PFIE); 931 pba = BA1READ4(sc, CS4280_PBA); 932 pdtc = BA1READ4(sc, CS4280_PDTC); 933 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 934 pctl, pfie, pba, pdtc)); 935 } 936 937 /* save current capture status */ 938 if (sc->sc_rrun) { 939 cctl = BA1READ4(sc, CS4280_CCTL); 940 cie = BA1READ4(sc, CS4280_CIE); 941 cba = BA1READ4(sc, CS4280_CBA); 942 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 943 cctl, cie, cba)); 944 } 945 946 /* Stop DMA */ 947 BA1WRITE4(sc, CS4280_PCTL, pctl & ~PCTL_MASK); 948 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK); 949 break; 950 case PWR_RESUME: 951 if (sc->sc_suspend == PWR_RESUME) { 952 printf("cs4280_power: odd, resume without suspend.\n"); 953 sc->sc_suspend = why; 954 return; 955 } 956 sc->sc_suspend = why; 957 cs4280_init(sc, 0); 958 #if 0 959 cs4280_reset_codec(sc); 960 #endif 961 /* restore ac97 registers */ 962 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 963 964 /* restore DMA related status */ 965 if(sc->sc_prun) { 966 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n", 967 pctl, pfie, pba, pdtc)); 968 cs4280_set_dac_rate(sc, sc->sc_prate); 969 BA1WRITE4(sc, CS4280_PDTC, pdtc); 970 BA1WRITE4(sc, CS4280_PBA, pba); 971 BA1WRITE4(sc, CS4280_PFIE, pfie); 972 BA1WRITE4(sc, CS4280_PCTL, pctl); 973 } 974 975 if (sc->sc_rrun) { 976 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n", 977 cctl, cie, cba)); 978 cs4280_set_adc_rate(sc, sc->sc_rrate); 979 BA1WRITE4(sc, CS4280_CBA, cba); 980 BA1WRITE4(sc, CS4280_CIE, cie); 981 BA1WRITE4(sc, CS4280_CCTL, cctl); 982 } 983 break; 984 case PWR_SOFTSUSPEND: 985 case PWR_SOFTSTANDBY: 986 case PWR_SOFTRESUME: 987 break; 988 } 989 } 990 991 static int 992 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result) 993 { 994 struct cs428x_softc *sc = addr; 995 int rv; 996 997 cs4280_clkrun_hack(sc, 1); 998 rv = cs428x_read_codec(addr, reg, result); 999 cs4280_clkrun_hack(sc, -1); 1000 1001 return rv; 1002 } 1003 1004 static int 1005 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data) 1006 { 1007 struct cs428x_softc *sc = addr; 1008 int rv; 1009 1010 cs4280_clkrun_hack(sc, 1); 1011 rv = cs428x_write_codec(addr, reg, data); 1012 cs4280_clkrun_hack(sc, -1); 1013 1014 return rv; 1015 } 1016 1017 #if 0 /* XXX buggy and not required */ 1018 /* control AC97 codec */ 1019 static int 1020 cs4280_reset_codec(void *addr) 1021 { 1022 struct cs428x_softc *sc; 1023 int n; 1024 1025 sc = addr; 1026 1027 /* Reset codec */ 1028 BA0WRITE4(sc, CS428X_ACCTL, 0); 1029 delay(100); /* delay 100us */ 1030 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1031 1032 /* 1033 * It looks like we do the following procedure, too 1034 */ 1035 1036 /* Enable AC-link sync generation */ 1037 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1038 delay(50*1000); /* XXX delay 50ms */ 1039 1040 /* Assert valid frame signal */ 1041 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1042 1043 /* Wait for valid AC97 input slot */ 1044 n = 0; 1045 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1046 (ACISV_ISV3 | ACISV_ISV4)) { 1047 delay(1000); 1048 if (++n > 1000) { 1049 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1050 return ETIMEDOUT; 1051 } 1052 } 1053 1054 return 0; 1055 } 1056 #endif 1057 1058 static enum ac97_host_flags cs4280_flags_codec(void *addr) 1059 { 1060 struct cs428x_softc *sc; 1061 1062 sc = addr; 1063 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP) 1064 return AC97_HOST_INVERTED_EAMP; 1065 1066 return 0; 1067 } 1068 1069 /* Internal functions */ 1070 1071 static const struct cs4280_card_t * 1072 cs4280_identify_card(struct pci_attach_args *pa) 1073 { 1074 pcireg_t idreg; 1075 u_int16_t i; 1076 1077 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1078 for (i = 0; i < CS4280_CARDS_SIZE; i++) { 1079 if (idreg == cs4280_cards[i].id) 1080 return &cs4280_cards[i]; 1081 } 1082 1083 return NULL; 1084 } 1085 1086 static int 1087 cs4280_piix4_match(struct pci_attach_args *pa) 1088 { 1089 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 1090 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) { 1091 return 1; 1092 } 1093 1094 return 0; 1095 } 1096 1097 static void 1098 cs4280_clkrun_hack(struct cs428x_softc *sc, int change) 1099 { 1100 uint16_t control, val; 1101 1102 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1103 return; 1104 1105 sc->sc_active += change; 1106 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10); 1107 if (!sc->sc_active) 1108 val |= 0x2000; 1109 else 1110 val &= ~0x2000; 1111 if (val != control) 1112 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val); 1113 } 1114 1115 static void 1116 cs4280_clkrun_hack_init(struct cs428x_softc *sc) 1117 { 1118 struct pci_attach_args smbuspa; 1119 uint16_t reg; 1120 pcireg_t port; 1121 1122 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK)) 1123 return; 1124 1125 if (pci_find_device(&smbuspa, cs4280_piix4_match)) { 1126 sc->sc_active = 0; 1127 printf("%s: enabling CLKRUN hack\n", 1128 sc->sc_dev.dv_xname); 1129 1130 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40); 1131 port = reg & 0xffc0; 1132 printf("%s: power management port 0x%x\n", sc->sc_dev.dv_xname, 1133 port); 1134 1135 sc->sc_pm_iot = smbuspa.pa_iot; 1136 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0, 1137 &sc->sc_pm_ioh) == 0) 1138 return; 1139 } 1140 1141 /* handle error */ 1142 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK; 1143 printf("%s: disabling CLKRUN hack\n", sc->sc_dev.dv_xname); 1144 } 1145 1146 static void 1147 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate) 1148 { 1149 /* calculate capture rate: 1150 * 1151 * capture_coefficient_increment = -round(rate*128*65536/48000; 1152 * capture_phase_increment = floor(48000*65536*1024/rate); 1153 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 1154 * cy = floor(cx/200); 1155 * capture_sample_rate_correction = cx - 200*cy; 1156 * capture_delay = ceil(24*48000/rate); 1157 * capture_num_triplets = floor(65536*rate/24000); 1158 * capture_group_length = 24000/GCD(rate, 24000); 1159 * where GCD means "Greatest Common Divisor". 1160 * 1161 * capture_coefficient_increment, capture_phase_increment and 1162 * capture_num_triplets are 32-bit signed quantities. 1163 * capture_sample_rate_correction and capture_group_length are 1164 * 16-bit signed quantities. 1165 * capture_delay is a 14-bit unsigned quantity. 1166 */ 1167 uint32_t cci, cpi, cnt, cx, cy, tmp1; 1168 uint16_t csrc, cgl, cdlay; 1169 1170 /* XXX 1171 * Even though, embedded_audio_spec says capture rate range 11025 to 1172 * 48000, dhwiface.cpp says, 1173 * 1174 * "We can only decimate by up to a factor of 1/9th the hardware rate. 1175 * Return an error if an attempt is made to stray outside that limit." 1176 * 1177 * so assume range as 48000/9 to 48000 1178 */ 1179 1180 if (rate < 8000) 1181 rate = 8000; 1182 if (rate > 48000) 1183 rate = 48000; 1184 1185 cx = rate << 16; 1186 cci = cx / 48000; 1187 cx -= cci * 48000; 1188 cx <<= 7; 1189 cci <<= 7; 1190 cci += cx / 48000; 1191 cci = - cci; 1192 1193 cx = 48000 << 16; 1194 cpi = cx / rate; 1195 cx -= cpi * rate; 1196 cx <<= 10; 1197 cpi <<= 10; 1198 cy = cx / rate; 1199 cpi += cy; 1200 cx -= cy * rate; 1201 1202 cy = cx / 200; 1203 csrc = cx - 200*cy; 1204 1205 cdlay = ((48000 * 24) + rate - 1) / rate; 1206 #if 0 1207 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 1208 #endif 1209 1210 cnt = rate << 16; 1211 cnt /= 24000; 1212 1213 cgl = 1; 1214 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 1215 if (((rate / tmp1) * tmp1) != rate) 1216 cgl *= 2; 1217 } 1218 if (((rate / 3) * 3) != rate) 1219 cgl *= 3; 1220 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 1221 if (((rate / tmp1) * tmp1) != rate) 1222 cgl *= 5; 1223 } 1224 #if 0 1225 /* XXX what manual says */ 1226 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 1227 tmp1 |= csrc<<16; 1228 BA1WRITE4(sc, CS4280_CSRC, tmp1); 1229 #else 1230 /* suggested by cs461x.c (ALSA driver) */ 1231 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 1232 #endif 1233 1234 #if 0 1235 /* I am confused. The sample rate calculation section says 1236 * cci *is* 32-bit signed quantity but in the parameter description 1237 * section, CCI only assigned 16bit. 1238 * I believe size of the variable. 1239 */ 1240 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 1241 tmp1 |= cci<<16; 1242 BA1WRITE4(sc, CS4280_CCI, tmp1); 1243 #else 1244 BA1WRITE4(sc, CS4280_CCI, cci); 1245 #endif 1246 1247 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 1248 tmp1 |= cdlay <<18; 1249 BA1WRITE4(sc, CS4280_CD, tmp1); 1250 1251 BA1WRITE4(sc, CS4280_CPI, cpi); 1252 1253 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 1254 tmp1 |= cgl; 1255 BA1WRITE4(sc, CS4280_CGL, tmp1); 1256 1257 BA1WRITE4(sc, CS4280_CNT, cnt); 1258 1259 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 1260 tmp1 |= cgl; 1261 BA1WRITE4(sc, CS4280_CGC, tmp1); 1262 } 1263 1264 static void 1265 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate) 1266 { 1267 /* 1268 * playback rate may range from 8000Hz to 48000Hz 1269 * 1270 * play_phase_increment = floor(rate*65536*1024/48000) 1271 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 1272 * py=floor(px/200) 1273 * play_sample_rate_correction = px - 200*py 1274 * 1275 * play_phase_increment is a 32bit signed quantity. 1276 * play_sample_rate_correction is a 16bit signed quantity. 1277 */ 1278 int32_t ppi; 1279 int16_t psrc; 1280 uint32_t px, py; 1281 1282 if (rate < 8000) 1283 rate = 8000; 1284 if (rate > 48000) 1285 rate = 48000; 1286 px = rate << 16; 1287 ppi = px/48000; 1288 px -= ppi*48000; 1289 ppi <<= 10; 1290 px <<= 10; 1291 py = px / 48000; 1292 ppi += py; 1293 px -= py*48000; 1294 py = px/200; 1295 px -= py*200; 1296 psrc = px; 1297 #if 0 1298 /* what manual says */ 1299 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 1300 BA1WRITE4(sc, CS4280_PSRC, 1301 ( ((psrc<<16) & PSRC_MASK) | px )); 1302 #else 1303 /* suggested by cs461x.c (ALSA driver) */ 1304 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 1305 #endif 1306 BA1WRITE4(sc, CS4280_PPI, ppi); 1307 } 1308 1309 /* Download Processor Code and Data image */ 1310 static int 1311 cs4280_download(struct cs428x_softc *sc, const uint32_t *src, 1312 uint32_t offset, uint32_t len) 1313 { 1314 uint32_t ctr; 1315 #if CS4280_DEBUG > 10 1316 uint32_t con, data; 1317 uint8_t c0, c1, c2, c3; 1318 #endif 1319 if ((offset & 3) || (len & 3)) 1320 return -1; 1321 1322 len /= sizeof(uint32_t); 1323 for (ctr = 0; ctr < len; ctr++) { 1324 /* XXX: 1325 * I cannot confirm this is the right thing or not 1326 * on BIG-ENDIAN machines. 1327 */ 1328 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 1329 #if CS4280_DEBUG > 10 1330 data = htole32(*(src+ctr)); 1331 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 1332 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 1333 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 1334 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 1335 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0; 1336 if (data != con ) { 1337 printf("0x%06x: write=0x%08x read=0x%08x\n", 1338 offset+ctr*4, data, con); 1339 return -1; 1340 } 1341 #endif 1342 } 1343 return 0; 1344 } 1345 1346 static int 1347 cs4280_download_image(struct cs428x_softc *sc) 1348 { 1349 int idx, err; 1350 uint32_t offset = 0; 1351 1352 err = 0; 1353 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 1354 err = cs4280_download(sc, &BA1Struct.map[offset], 1355 BA1Struct.memory[idx].offset, 1356 BA1Struct.memory[idx].size); 1357 if (err != 0) { 1358 printf("%s: load_image failed at %d\n", 1359 sc->sc_dev.dv_xname, idx); 1360 return -1; 1361 } 1362 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1363 } 1364 return err; 1365 } 1366 1367 /* Processor Soft Reset */ 1368 static void 1369 cs4280_reset(void *sc_) 1370 { 1371 struct cs428x_softc *sc; 1372 1373 sc = sc_; 1374 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1375 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1376 delay(100); 1377 /* Clear RSTSP bit in SPCR */ 1378 BA1WRITE4(sc, CS4280_SPCR, 0); 1379 /* enable DMA reqest */ 1380 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1381 } 1382 1383 static int 1384 cs4280_init(struct cs428x_softc *sc, int init) 1385 { 1386 int n; 1387 uint32_t mem; 1388 int rv; 1389 1390 rv = 1; 1391 cs4280_clkrun_hack(sc, 1); 1392 1393 /* Start PLL out in known state */ 1394 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1395 /* Start serial ports out in known state */ 1396 BA0WRITE4(sc, CS4280_SERMC1, 0); 1397 1398 /* Specify type of CODEC */ 1399 /* XXX should not be here */ 1400 #define SERACC_CODEC_TYPE_1_03 1401 #ifdef SERACC_CODEC_TYPE_1_03 1402 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1403 #else 1404 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1405 #endif 1406 1407 /* Reset codec */ 1408 BA0WRITE4(sc, CS428X_ACCTL, 0); 1409 delay(100); /* delay 100us */ 1410 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN); 1411 1412 /* Enable AC-link sync generation */ 1413 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1414 delay(50*1000); /* delay 50ms */ 1415 1416 /* Set the serial port timing configuration */ 1417 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1418 1419 /* Setup clock control */ 1420 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1421 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1422 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1423 1424 /* Power up the PLL */ 1425 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1426 delay(50*1000); /* delay 50ms */ 1427 1428 /* Turn on clock */ 1429 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1430 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1431 1432 /* Set the serial port FIFO pointer to the 1433 * first sample in FIFO. (not documented) */ 1434 cs4280_clear_fifos(sc); 1435 1436 #if 0 1437 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1438 BA0WRITE4(sc, CS4280_SERBSP, 0); 1439 #endif 1440 1441 /* Configure the serial port */ 1442 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1443 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1444 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1445 1446 /* Wait for CODEC ready */ 1447 n = 0; 1448 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1449 delay(125); 1450 if (++n > 1000) { 1451 printf("%s: codec ready timeout\n", 1452 sc->sc_dev.dv_xname); 1453 goto exit; 1454 } 1455 } 1456 1457 /* Assert valid frame signal */ 1458 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1459 1460 /* Wait for valid AC97 input slot */ 1461 n = 0; 1462 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1463 (ACISV_ISV3 | ACISV_ISV4)) { 1464 delay(1000); 1465 if (++n > 1000) { 1466 printf("AC97 inputs slot ready timeout\n"); 1467 goto exit; 1468 } 1469 } 1470 1471 /* Set AC97 output slot valid signals */ 1472 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1473 1474 /* reset the processor */ 1475 cs4280_reset(sc); 1476 1477 /* Download the image to the processor */ 1478 if (cs4280_download_image(sc) != 0) { 1479 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1480 goto exit; 1481 } 1482 1483 /* Save playback parameter and then write zero. 1484 * this ensures that DMA doesn't immediately occur upon 1485 * starting the processor core 1486 */ 1487 mem = BA1READ4(sc, CS4280_PCTL); 1488 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1489 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1490 if (init != 0) 1491 sc->sc_prun = 0; 1492 1493 /* Save capture parameter and then write zero. 1494 * this ensures that DMA doesn't immediately occur upon 1495 * starting the processor core 1496 */ 1497 mem = BA1READ4(sc, CS4280_CCTL); 1498 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1499 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1500 if (init != 0) 1501 sc->sc_rrun = 0; 1502 1503 /* Processor Startup Procedure */ 1504 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1505 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1506 1507 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1508 n = 0; 1509 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1510 delay(10); 1511 if (++n > 1000) { 1512 printf("SPCR 1->0 transition timeout\n"); 1513 goto exit; 1514 } 1515 } 1516 1517 n = 0; 1518 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1519 delay(10); 1520 if (++n > 1000) { 1521 printf("SPCS 0->1 transition timeout\n"); 1522 goto exit; 1523 } 1524 } 1525 /* Processor is now running !!! */ 1526 1527 /* Setup volume */ 1528 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1529 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1530 1531 /* Interrupt enable */ 1532 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1533 1534 /* playback interrupt enable */ 1535 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1536 mem |= PFIE_PI_ENABLE; 1537 BA1WRITE4(sc, CS4280_PFIE, mem); 1538 /* capture interrupt enable */ 1539 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1540 mem |= CIE_CI_ENABLE; 1541 BA1WRITE4(sc, CS4280_CIE, mem); 1542 1543 #if NMIDI > 0 1544 /* Reset midi port */ 1545 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1546 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1547 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1548 /* midi interrupt enable */ 1549 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1550 BA0WRITE4(sc, CS4280_MIDCR, mem); 1551 #endif 1552 1553 rv = 0; 1554 1555 exit: 1556 cs4280_clkrun_hack(sc, -1); 1557 return rv; 1558 } 1559 1560 static void 1561 cs4280_clear_fifos(struct cs428x_softc *sc) 1562 { 1563 int pd, cnt, n; 1564 uint32_t mem; 1565 1566 pd = 0; 1567 /* 1568 * If device power down, power up the device and keep power down 1569 * state. 1570 */ 1571 mem = BA0READ4(sc, CS4280_CLKCR1); 1572 if (!(mem & CLKCR1_SWCE)) { 1573 printf("cs4280_clear_fifo: power down found.\n"); 1574 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1575 pd = 1; 1576 } 1577 BA0WRITE4(sc, CS4280_SERBWP, 0); 1578 for (cnt = 0; cnt < 256; cnt++) { 1579 n = 0; 1580 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1581 delay(1000); 1582 if (++n > 1000) { 1583 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1584 break; 1585 } 1586 } 1587 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1588 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1589 } 1590 if (pd) 1591 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1592 } 1593 1594 #if NMIDI > 0 1595 static int 1596 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int), 1597 void (*ointr)(void *), void *arg) 1598 { 1599 struct cs428x_softc *sc; 1600 uint32_t mem; 1601 1602 DPRINTF(("midi_open\n")); 1603 sc = addr; 1604 sc->sc_iintr = iintr; 1605 sc->sc_ointr = ointr; 1606 sc->sc_arg = arg; 1607 1608 /* midi interrupt enable */ 1609 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1610 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1611 BA0WRITE4(sc, CS4280_MIDCR, mem); 1612 #ifdef CS4280_DEBUG 1613 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1614 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1615 return(EINVAL); 1616 } 1617 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1618 #endif 1619 return 0; 1620 } 1621 1622 static void 1623 cs4280_midi_close(void *addr) 1624 { 1625 struct cs428x_softc *sc; 1626 uint32_t mem; 1627 1628 DPRINTF(("midi_close\n")); 1629 sc = addr; 1630 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */ 1631 mem = BA0READ4(sc, CS4280_MIDCR); 1632 mem &= ~MIDCR_MASK; 1633 BA0WRITE4(sc, CS4280_MIDCR, mem); 1634 1635 sc->sc_iintr = 0; 1636 sc->sc_ointr = 0; 1637 } 1638 1639 static int 1640 cs4280_midi_output(void *addr, int d) 1641 { 1642 struct cs428x_softc *sc; 1643 uint32_t mem; 1644 int x; 1645 1646 sc = addr; 1647 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1648 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1649 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1650 mem |= d & MIDWP_MASK; 1651 DPRINTFN(5,("midi_output d=0x%08x",d)); 1652 BA0WRITE4(sc, CS4280_MIDWP, mem); 1653 #ifdef DIAGNOSTIC 1654 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1655 DPRINTF(("Bad write data: %d %d", 1656 mem, BA0READ4(sc, CS4280_MIDWP))); 1657 return EIO; 1658 } 1659 #endif 1660 return 0; 1661 } 1662 delay(MIDI_BUSY_DELAY); 1663 } 1664 return EIO; 1665 } 1666 1667 static void 1668 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1669 { 1670 1671 mi->name = "CS4280 MIDI UART"; 1672 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1673 } 1674 1675 #endif /* NMIDI */ 1676 1677 /* DEBUG functions */ 1678 #if CS4280_DEBUG > 10 1679 static int 1680 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src, 1681 uint32_t offset, uint32_t len) 1682 { 1683 uint32_t ctr, data; 1684 int err; 1685 1686 if ((offset & 3) || (len & 3)) 1687 return -1; 1688 1689 err = 0; 1690 len /= sizeof(uint32_t); 1691 for (ctr = 0; ctr < len; ctr++) { 1692 /* I cannot confirm this is the right thing 1693 * on BIG-ENDIAN machines 1694 */ 1695 data = BA1READ4(sc, offset+ctr*4); 1696 if (data != htole32(*(src+ctr))) { 1697 printf("0x%06x: 0x%08x(0x%08x)\n", 1698 offset+ctr*4, data, *(src+ctr)); 1699 *(src+ctr) = data; 1700 ++err; 1701 } 1702 } 1703 return err; 1704 } 1705 1706 static int 1707 cs4280_check_images(struct cs428x_softc *sc) 1708 { 1709 int idx, err; 1710 uint32_t offset; 1711 1712 offset = 0; 1713 err = 0; 1714 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/ 1715 for (idx = 0; idx < 1; ++idx) { 1716 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 1717 BA1Struct.memory[idx].offset, 1718 BA1Struct.memory[idx].size); 1719 if (err != 0) { 1720 printf("%s: check_image failed at %d\n", 1721 sc->sc_dev.dv_xname, idx); 1722 } 1723 offset += BA1Struct.memory[idx].size / sizeof(uint32_t); 1724 } 1725 return err; 1726 } 1727 1728 #endif /* CS4280_DEBUG */ 1729