1 /* $NetBSD: coram.c,v 1.9 2011/08/29 14:47:08 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.9 2011/08/29 14:47:08 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 40 #include <dev/dtv/dtvif.h> 41 42 #include <dev/pci/cx23885reg.h> 43 #include <dev/pci/coramvar.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/at24cxxvar.h> 50 51 #include <dev/i2c/cx24227var.h> 52 #include <dev/i2c/mt2131var.h> 53 54 /* #define CORAM_DEBUG */ 55 /* #define CORAM_ATTACH_I2C */ 56 57 static const struct coram_board coram_boards[] = { 58 { PCI_VENDOR_HAUPPAUGE, 0x7911, "Hauppauge HVR-1250" }, 59 }; 60 61 static int coram_match(device_t, cfdata_t, void *); 62 static void coram_attach(device_t, device_t, void *); 63 static int coram_detach(device_t, int); 64 static int coram_rescan(device_t, const char *, const int *); 65 static void coram_childdet(device_t, device_t); 66 static bool coram_resume(device_t, const pmf_qual_t *); 67 static int coram_intr(void *); 68 static const struct coram_board * coram_board_lookup(uint16_t, uint16_t); 69 70 static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t, 71 const void *, size_t, void *, size_t, int); 72 static int coram_iic_acquire_bus(void *, int); 73 static void coram_iic_release_bus(void *, int); 74 static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 75 const void *, size_t, void *, size_t, int); 76 static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t, 77 const void *, size_t, void *, size_t, int); 78 79 static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *); 80 static int coram_dtv_open(void *, int); 81 static void coram_dtv_close(void *); 82 static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *); 83 static fe_status_t coram_dtv_get_status(void *); 84 static uint16_t coram_dtv_get_signal_strength(void *); 85 static uint16_t coram_dtv_get_snr(void *); 86 static int coram_dtv_start_transfer(void *, void (*)(void *, const struct dtv_payload *), void *); 87 static int coram_dtv_stop_transfer(void *); 88 89 static int coram_mpeg_attach(struct coram_softc *); 90 static int coram_mpeg_detach(struct coram_softc *, int); 91 static int coram_mpeg_reset(struct coram_softc *); 92 static void * coram_mpeg_malloc(struct coram_softc *, size_t); 93 static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *); 94 static void coram_mpeg_free(struct coram_softc *, void *); 95 static int coram_mpeg_halt(struct coram_softc *); 96 static int coram_freemem(struct coram_softc *, struct coram_dma *); 97 static int coram_mpeg_trigger(struct coram_softc *, void *); 98 static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t); 99 static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t); 100 static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t); 101 static int coram_mpeg_intr(struct coram_softc *); 102 103 CFATTACH_DECL2_NEW(coram, sizeof(struct coram_softc), 104 coram_match, coram_attach, coram_detach, NULL, 105 coram_rescan, coram_childdet); 106 107 #define CORAM_SRAM_CH6 0 108 109 #define CORAM_TS_PKTSIZE (188 * 8) 110 111 static struct coram_sram_ch coram_sram_chs[] = { 112 [CORAM_SRAM_CH6] = { 113 .csc_cmds= 0x10140, 114 .csc_iq = 0x10500, 115 .csc_iqsz = 0x40, 116 .csc_cdt = 0x10600, 117 .csc_cdtsz = 0x10, 118 .csc_fifo = 0x6000, 119 .csc_fifosz = 0x1000, 120 .csc_risc = 0x10800, 121 .csc_riscsz = 0x800, 122 .csc_ptr1 = DMA5_PTR1, 123 .csc_ptr2 = DMA5_PTR2, 124 .csc_cnt1 = DMA5_CNT1, 125 .csc_cnt2 = DMA5_CNT2, 126 }, 127 }; 128 129 static const struct dtv_hw_if coram_dtv_if = { 130 .get_devinfo = coram_dtv_get_devinfo, 131 .open = coram_dtv_open, 132 .close = coram_dtv_close, 133 .set_tuner = coram_dtv_set_tuner, 134 .get_status = coram_dtv_get_status, 135 .get_signal_strength = coram_dtv_get_signal_strength, 136 .get_snr = coram_dtv_get_snr, 137 .start_transfer = coram_dtv_start_transfer, 138 .stop_transfer = coram_dtv_stop_transfer, 139 }; 140 141 static int 142 coram_match(device_t parent, cfdata_t match, void *v) 143 { 144 const struct pci_attach_args *pa = v; 145 pcireg_t subid; 146 147 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT) 148 return 0; 149 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX23885) 150 return 0; 151 152 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 153 if (coram_board_lookup(PCI_VENDOR(subid), PCI_PRODUCT(subid)) == NULL) 154 return 0; 155 156 return 1; 157 } 158 159 static void 160 coram_attach(device_t parent, device_t self, void *v) 161 { 162 struct coram_softc *sc = device_private(self); 163 const struct pci_attach_args *pa = v; 164 pci_intr_handle_t ih; 165 pcireg_t reg; 166 char devinfo[256]; 167 const char *intrstr; 168 struct coram_iic_softc *cic; 169 uint32_t value; 170 int i; 171 #ifdef CORAM_ATTACH_I2C 172 struct i2cbus_attach_args iba; 173 #endif 174 175 sc->sc_dev = self; 176 177 aprint_naive("\n"); 178 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 179 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 180 181 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 182 sc->sc_board = coram_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)); 183 KASSERT(sc->sc_board != NULL); 184 185 if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0, 186 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) { 187 aprint_error_dev(self, "couldn't map memory space\n"); 188 return; 189 } 190 191 sc->sc_dmat = pa->pa_dmat; 192 sc->sc_pc = pa->pa_pc; 193 194 if (pci_intr_map(pa, &ih)) { 195 aprint_error_dev(self, "couldn't map interrupt\n"); 196 return; 197 } 198 intrstr = pci_intr_string(pa->pa_pc, ih); 199 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_VM, 200 coram_intr, (void *)self); 201 if (sc->sc_ih == NULL) { 202 aprint_error_dev(self, "couldn't establish interrupt"); 203 if (intrstr != NULL) 204 aprint_error(" at %s", intrstr); 205 aprint_error("\n"); 206 return; 207 } 208 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 209 210 /* set master */ 211 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 212 reg |= PCI_COMMAND_MASTER_ENABLE; 213 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg); 214 215 /* I2C */ 216 for(i = 0; i < I2C_NUM; i++) { 217 cic = &sc->sc_iic[i]; 218 219 cic->cic_sc = sc; 220 if(bus_space_subregion(sc->sc_memt, sc->sc_memh, I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh)) 221 panic("failed to subregion i2c"); 222 223 mutex_init(&cic->cic_busmutex, MUTEX_DRIVER, IPL_NONE); 224 cic->cic_i2c.ic_cookie = cic; 225 cic->cic_i2c.ic_acquire_bus = coram_iic_acquire_bus; 226 cic->cic_i2c.ic_release_bus = coram_iic_release_bus; 227 cic->cic_i2c.ic_exec = coram_iic_exec; 228 229 #ifdef CORAM_ATTACH_I2C 230 /* attach iic(4) */ 231 memset(&iba, 0, sizeof(iba)); 232 iba.iba_tag = &cic->cic_i2c; 233 iba.iba_type = I2C_TYPE_SMBUS; 234 cic->cic_i2cdev = config_found_ia(self, "i2cbus", 235 &iba, iicbus_print); 236 #endif 237 } 238 239 /* HVR1250 GPIO */ 240 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010); 241 #if 1 242 value &= ~0x00010001; 243 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 244 delay(5000); 245 #endif 246 value |= 0x00010001; 247 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value); 248 249 #if 0 250 int i; 251 uint8_t foo[256]; 252 uint8_t bar; 253 bar = 0; 254 // seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256); 255 256 iic_acquire_bus(&sc->sc_i2c, I2C_F_POLL); 257 iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256, I2C_F_POLL); 258 iic_release_bus(&sc->sc_i2c, I2C_F_POLL); 259 260 printf("\n"); 261 for ( i = 0; i < 256; i++) { 262 if ( (i % 8) == 0 ) 263 printf("%02x: ", i); 264 265 printf("%02x", foo[i]); 266 267 if ( (i % 8) == 7 ) 268 printf("\n"); 269 else 270 printf(" "); 271 } 272 printf("\n"); 273 #endif 274 275 sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19); 276 if (sc->sc_demod == NULL) 277 aprint_error_dev(self, "couldn't open cx24227\n"); 278 sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61); 279 if (sc->sc_tuner == NULL) 280 aprint_error_dev(self, "couldn't open mt2131\n"); 281 282 coram_mpeg_attach(sc); 283 284 if (!pmf_device_register(self, NULL, coram_resume)) 285 aprint_error_dev(self, "couldn't establish power handler\n"); 286 287 return; 288 } 289 290 static int 291 coram_detach(device_t self, int flags) 292 { 293 struct coram_softc *sc = device_private(self); 294 struct coram_iic_softc *cic; 295 unsigned int i; 296 int error; 297 298 error = coram_mpeg_detach(sc, flags); 299 if (error) 300 return error; 301 302 if (sc->sc_tuner) 303 mt2131_close(sc->sc_tuner); 304 if (sc->sc_demod) 305 cx24227_close(sc->sc_demod); 306 for (i = 0; i < I2C_NUM; i++) { 307 cic = &sc->sc_iic[i]; 308 if (cic->cic_i2cdev) 309 config_detach(cic->cic_i2cdev, flags); 310 mutex_destroy(&cic->cic_busmutex); 311 } 312 pmf_device_deregister(self); 313 314 if (sc->sc_mems) 315 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 316 if (sc->sc_ih) 317 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 318 319 return 0; 320 } 321 322 static int 323 coram_rescan(device_t self, const char *ifattr, const int *locs) 324 { 325 struct coram_softc *sc = device_private(self); 326 struct dtv_attach_args daa; 327 328 daa.hw = &coram_dtv_if; 329 daa.priv = sc; 330 331 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL) 332 sc->sc_dtvdev = config_found_ia(sc->sc_dev, "dtvbus", 333 &daa, dtv_print); 334 335 return 0; 336 } 337 338 static void 339 coram_childdet(device_t self, device_t child) 340 { 341 struct coram_softc *sc = device_private(self); 342 struct coram_iic_softc *cic; 343 unsigned int i; 344 345 if (sc->sc_dtvdev == child) 346 sc->sc_dtvdev = NULL; 347 348 for (i = 0; i < I2C_NUM; i++) { 349 cic = &sc->sc_iic[i]; 350 if (cic->cic_i2cdev == child) 351 cic->cic_i2cdev = NULL; 352 } 353 } 354 355 static int 356 coram_intr(void *v) 357 { 358 device_t self = v; 359 struct coram_softc *sc; 360 uint32_t val; 361 362 sc = device_private(self); 363 364 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT ); 365 if (val == 0) 366 return 0; /* not ours */ 367 368 /* vid c */ 369 if (val & __BIT(2)) 370 coram_mpeg_intr(sc); 371 372 if (val & ~__BIT(2)) 373 printf("%s %08x\n", __func__, val); 374 375 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val); 376 377 return 1; 378 } 379 380 static const struct coram_board * 381 coram_board_lookup(uint16_t vendor, uint16_t product) 382 { 383 unsigned int i; 384 385 for (i = 0; i < __arraycount(coram_boards); i++) { 386 if (coram_boards[i].vendor == vendor && 387 coram_boards[i].product == product) { 388 return &coram_boards[i]; 389 } 390 } 391 392 return NULL; 393 } 394 395 #define CXDTV_TS_RISCI2 (1 << 4) 396 #define CXDTV_TS_RISCI1 (1 << 0) 397 398 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2) 399 400 static int 401 coram_mpeg_intr(struct coram_softc *sc) 402 { 403 struct dtv_payload payload; 404 uint32_t s, m, v; 405 int i; 406 407 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT); 408 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 409 410 if ((s & m) == 0) 411 return 0; 412 413 if ( (s & ~CXDTV_TS_RISCI) != 0 ) { 414 printf("%s: unexpected TS IS %08x\n", 415 device_xname(sc->sc_dev), s); 416 417 printf("cmds:\n"); 418 for(i = 0; i < 20; i++) 419 { 420 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4)); 421 printf("%06x %08x\n", 0x10140+(i*4), v); 422 } 423 } 424 425 if (sc->sc_dtvsubmitcb == NULL) 426 goto done; 427 428 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) { 429 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 430 0, CORAM_TS_PKTSIZE, 431 BUS_DMASYNC_POSTREAD); 432 payload.data = KERNADDR(sc->sc_dma); 433 payload.size = CORAM_TS_PKTSIZE; 434 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 435 } 436 437 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) { 438 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map, 439 CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE, 440 BUS_DMASYNC_POSTREAD); 441 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE; 442 payload.size = CORAM_TS_PKTSIZE; 443 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload); 444 } 445 446 done: 447 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s); 448 449 return 1; 450 } 451 452 static bool 453 coram_resume(device_t dv, const pmf_qual_t *qual) 454 { 455 struct coram_softc *sc; 456 sc = device_private(dv); 457 458 return true; 459 } 460 461 static int 462 coram_iic_acquire_bus(void *cookie, int flags) 463 { 464 struct coram_iic_softc *cic; 465 466 cic = cookie; 467 468 if (flags & I2C_F_POLL) { 469 while (mutex_tryenter(&cic->cic_busmutex) == 0) 470 delay(50); 471 return 0; 472 } 473 474 mutex_enter(&cic->cic_busmutex); 475 476 return 0; 477 } 478 479 static void 480 coram_iic_release_bus(void *cookie, int flags) 481 { 482 struct coram_iic_softc *cic; 483 484 cic = cookie; 485 486 mutex_exit(&cic->cic_busmutex); 487 488 return; 489 } 490 491 /* I2C Bus */ 492 493 #define I2C_ADDR 0x0000 494 #define I2C_WDATA 0x0004 495 #define I2C_CTRL 0x0008 496 #define I2C_RDATA 0x000c 497 #define I2C_STAT 0x0010 498 499 #define I2C_EXTEND (1 << 3) 500 #define I2C_NOSTOP (1 << 4) 501 502 static int 503 coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 504 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 505 { 506 struct coram_iic_softc *cic; 507 int ret; 508 509 cic = cookie; 510 511 if(cmdlen) { 512 ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 513 if(ret) 514 return ret; 515 } 516 517 if(len) { 518 ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags); 519 if(ret) 520 return ret; 521 } 522 523 524 return 0; 525 526 } 527 528 static int 529 coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 530 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 531 { 532 uint8_t *rb; 533 uint32_t ctrl; 534 int bn; 535 536 rb = buf; 537 538 for ( bn = 0; bn < len; bn++) { 539 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1; 540 if ( bn < len - 1 ) 541 ctrl |= I2C_NOSTOP | I2C_EXTEND; 542 543 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25); 544 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 545 546 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 547 I2C_STAT) & 0x02)) { 548 delay(25); 549 } 550 if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, 551 I2C_STAT) & 0x01) == 0x00) { 552 // printf("%s %d no ack\n", __func__, bn); 553 return EIO; 554 } 555 556 rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA); 557 558 } 559 560 return 0; 561 } 562 563 static int 564 coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr, 565 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 566 { 567 const uint8_t *wb; 568 uint32_t wdata, addrreg, ctrl; 569 int bn; 570 571 wb = cmdbuf; 572 573 addrreg = (addr << 25) | wb[0]; 574 wdata = wb[0]; 575 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 576 577 if ( cmdlen > 1 ) 578 ctrl |= I2C_NOSTOP | I2C_EXTEND; 579 else if (len) 580 ctrl |= I2C_NOSTOP; 581 582 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 583 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 584 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 585 586 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 587 delay(25); } 588 589 for ( bn = 1; bn < cmdlen; bn++) { 590 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2); 591 wdata = wb[bn]; 592 593 if ( bn < cmdlen - 1 ) 594 ctrl |= I2C_NOSTOP | I2C_EXTEND; 595 else if (len) 596 ctrl |= I2C_NOSTOP; 597 598 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg); 599 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata); 600 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl); 601 602 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) { 603 delay(25); } 604 } 605 606 return 0; 607 } 608 609 static int 610 coram_mpeg_attach(struct coram_softc *sc) 611 { 612 struct coram_sram_ch *ch; 613 614 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 615 616 sc->sc_riscbufsz = ch->csc_riscsz; 617 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP); 618 619 if ( sc->sc_riscbuf == NULL ) 620 panic("riscbuf null"); 621 622 coram_mpeg_reset(sc); 623 624 sc->sc_tsbuf = NULL; 625 626 coram_rescan(sc->sc_dev, NULL, NULL); 627 628 return (sc->sc_dtvdev != NULL); 629 } 630 631 static int 632 coram_mpeg_detach(struct coram_softc *sc, int flags) 633 { 634 struct coram_sram_ch *ch = &coram_sram_chs[CORAM_SRAM_CH6]; 635 int error; 636 637 if (sc->sc_dtvdev) { 638 error = config_detach(sc->sc_dtvdev, flags); 639 if (error) 640 return error; 641 } 642 if (sc->sc_riscbuf) { 643 kmem_free(sc->sc_riscbuf, ch->csc_riscsz); 644 } 645 646 return 0; 647 } 648 649 static void 650 coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info) 651 { 652 struct coram_softc *sc = cookie; 653 654 memset(info, 0, sizeof(*info)); 655 strlcpy(info->name, sc->sc_board->name, sizeof(info->name)); 656 info->type = FE_ATSC; 657 info->frequency_min = 54000000; 658 info->frequency_max = 858000000; 659 info->frequency_stepsize = 62500; 660 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB; 661 } 662 663 static int 664 coram_dtv_open(void *cookie, int flags) 665 { 666 struct coram_softc *sc = cookie; 667 668 #ifdef CORAM_DEBUG 669 device_printf(sc->sc_dev, "%s\n", __func__); 670 #endif 671 672 //KASSERT(sc->sc_tsbuf == NULL); 673 674 if (sc->sc_tuner == NULL || sc->sc_demod == NULL) 675 return ENXIO; 676 677 coram_mpeg_reset(sc); 678 679 /* allocate two alternating DMA areas for MPEG TS packets */ 680 sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2); 681 682 if (sc->sc_tsbuf == NULL) 683 return ENOMEM; 684 685 return 0; 686 } 687 688 static void 689 coram_dtv_close(void *cookie) 690 { 691 struct coram_softc *sc = cookie; 692 693 #ifdef CORAM_DEBUG 694 device_printf(sc->sc_dev, "%s\n", __func__); 695 #endif 696 697 coram_mpeg_halt(sc); 698 699 if (sc->sc_tsbuf != NULL) { 700 coram_mpeg_free(sc, sc->sc_tsbuf); 701 sc->sc_tsbuf = NULL; 702 } 703 } 704 705 static int 706 coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params) 707 { 708 struct coram_softc *sc = cookie; 709 710 KASSERT(sc->sc_tuner != NULL); 711 mt2131_tune_dtv(sc->sc_tuner, params); 712 KASSERT(sc->sc_demod != NULL); 713 return cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation); 714 } 715 716 static fe_status_t 717 coram_dtv_get_status(void *cookie) 718 { 719 struct coram_softc *sc = cookie; 720 721 if (sc->sc_demod == NULL) 722 return ENXIO; 723 724 return cx24227_get_dtv_status(sc->sc_demod);; 725 } 726 727 static uint16_t 728 coram_dtv_get_signal_strength(void *cookie) 729 { 730 return 0; 731 } 732 733 static uint16_t 734 coram_dtv_get_snr(void *cookie) 735 { 736 return 0; 737 } 738 739 static int 740 coram_dtv_start_transfer(void *cookie, 741 void (*cb)(void *, const struct dtv_payload *), void *arg) 742 { 743 struct coram_softc *sc = cookie; 744 745 #ifdef CORAM_DEBUG 746 device_printf(sc->sc_dev, "%s\n", __func__); 747 #endif 748 749 sc->sc_dtvsubmitcb = cb; 750 sc->sc_dtvsubmitarg = arg; 751 752 coram_mpeg_trigger(sc, sc->sc_tsbuf); 753 754 return 0; 755 } 756 757 static int 758 coram_dtv_stop_transfer(void *cookie) 759 { 760 struct coram_softc *sc = cookie; 761 762 #ifdef CORAM_DEBUG 763 device_printf(sc->sc_dev, "%s\n", __func__); 764 #endif 765 766 coram_mpeg_halt(sc); 767 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 768 769 sc->sc_dtvsubmitcb = NULL; 770 sc->sc_dtvsubmitarg = NULL; 771 772 return 0; 773 } 774 775 776 static int 777 coram_mpeg_reset(struct coram_softc *sc) 778 { 779 uint32_t v; 780 781 v = (uint32_t)-1; 782 783 /* hold RISC in reset */ 784 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0); 785 786 /* disable fifo + risc */ 787 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 788 789 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0); 790 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0); 791 792 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0); 793 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0); 794 795 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 796 797 return 0; 798 } 799 800 static void * 801 coram_mpeg_malloc(struct coram_softc *sc, size_t size) 802 { 803 struct coram_dma *p; 804 int err; 805 806 p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP); 807 if ( p == NULL ) 808 return NULL; 809 err = coram_allocmem(sc, size, 16, p); 810 if (err) { 811 kmem_free(p, sizeof(struct coram_dma)); 812 return NULL; 813 } 814 815 p->next = sc->sc_dma; 816 sc->sc_dma = p; 817 818 return KERNADDR(p); 819 } 820 821 static int 822 coram_allocmem(struct coram_softc *sc, size_t size, size_t align, 823 struct coram_dma *p) 824 { 825 int err; 826 827 p->size = size; 828 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, 829 p->segs, sizeof(p->segs) / sizeof(p->segs[0]), 830 &p->nsegs, BUS_DMA_NOWAIT); 831 if (err) 832 return err; 833 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size, 834 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 835 if (err) 836 goto free; 837 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, 838 BUS_DMA_NOWAIT, &p->map); 839 if (err) 840 goto unmap; 841 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL, 842 BUS_DMA_NOWAIT); 843 if (err) 844 goto destroy; 845 846 return 0; 847 destroy: 848 bus_dmamap_destroy(sc->sc_dmat, p->map); 849 unmap: 850 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 851 free: 852 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 853 854 return err; 855 } 856 857 static int 858 coram_mpeg_halt(struct coram_softc *sc) 859 { 860 uint32_t v; 861 862 #ifdef CORAM_DEBUG 863 device_printf(sc->sc_dev, "%s\n", __func__); 864 #endif 865 866 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 867 868 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 869 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 870 v & __BIT(2)); 871 872 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 873 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 874 v & 0); 875 876 return 0; 877 } 878 879 static void 880 coram_mpeg_free(struct coram_softc *sc, void *addr) 881 { 882 struct coram_dma *p; 883 struct coram_dma **pp; 884 885 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next) 886 if (KERNADDR(p) == addr) { 887 coram_freemem(sc, p); 888 *pp = p->next; 889 kmem_free(p, sizeof(struct coram_dma)); 890 return; 891 } 892 893 printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr); 894 return; 895 } 896 897 static int 898 coram_freemem(struct coram_softc *sc, struct coram_dma *p) 899 { 900 bus_dmamap_unload(sc->sc_dmat, p->map); 901 bus_dmamap_destroy(sc->sc_dmat, p->map); 902 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); 903 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs); 904 905 return 0; 906 } 907 908 static int 909 coram_mpeg_trigger(struct coram_softc *sc, void *buf) 910 { 911 struct coram_dma *p; 912 struct coram_sram_ch *ch; 913 uint32_t v; 914 915 ch = &coram_sram_chs[CORAM_SRAM_CH6]; 916 917 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next) 918 continue; 919 if (p == NULL) { 920 printf("%s: coram_mpeg_trigger: bad addr %p\n", 921 device_xname(sc->sc_dev), buf); 922 return ENOENT; 923 } 924 925 /* disable fifo + risc */ 926 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0); 927 928 coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1); 929 coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE); 930 931 /* let me hope this bit is the same as on the 2388[0-3] */ 932 /* software reset */ 933 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040); 934 delay (100*1000); 935 936 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE); 937 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4); 938 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1); 939 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0); 940 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12); 941 delay (100*1000); 942 943 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL); 944 v &= ~0x4; /* Clear TS2_SOP_OE */ 945 bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v); 946 947 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK); 948 v |= 0x111111; 949 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v); 950 951 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL); 952 v |= 0x11; /* Enable RISC controller and FIFO */ 953 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v); 954 955 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2); 956 v |= __BIT(5); /* Enable RISC controller */ 957 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v); 958 959 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK); 960 v |= 0x001f00; 961 v |= 0x04; 962 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v); 963 964 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 965 #ifdef CORAM_DEBUG 966 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 967 #endif 968 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 969 #ifdef CORAM_DEBUG 970 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 971 #endif 972 delay(100*1000); 973 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL); 974 #ifdef CORAM_DEBUG 975 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v); 976 #endif 977 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS); 978 #ifdef CORAM_DEBUG 979 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v); 980 #endif 981 982 return 0; 983 } 984 985 static int 986 coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines) 987 { 988 uint32_t *rm; 989 uint32_t size; 990 991 size = 1 + (bpl * lines) / PAGE_SIZE + lines; 992 size += 2; 993 994 if (sc->sc_riscbuf == NULL) { 995 return ENOMEM; 996 } 997 998 rm = (uint32_t *)sc->sc_riscbuf; 999 coram_risc_field(sc, rm, bpl); 1000 1001 return 0; 1002 } 1003 1004 static int 1005 coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl) 1006 { 1007 struct coram_dma *p; 1008 1009 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next) 1010 continue; 1011 if (p == NULL) { 1012 printf("%s: coram_risc_field: bad addr %p\n", 1013 device_xname(sc->sc_dev), sc->sc_tsbuf); 1014 return ENOENT; 1015 } 1016 1017 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz); 1018 1019 rm = sc->sc_riscbuf; 1020 1021 /* htole32 will be done when program is copied to chip sram */ 1022 1023 /* XXX */ 1024 *(rm++) = (CX_RISC_SYNC|0); 1025 1026 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl); 1027 *(rm++) = (DMAADDR(p) + 0 * bpl); 1028 *(rm++) = 0; /* high dword */ 1029 1030 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl); 1031 *(rm++) = (DMAADDR(p) + 1 * bpl); 1032 *(rm++) = 0; 1033 1034 *(rm++) = (CX_RISC_JUMP|1); 1035 *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4); 1036 *(rm++) = 0; 1037 1038 return 0; 1039 } 1040 1041 static int 1042 coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc, 1043 uint32_t bpl) 1044 { 1045 unsigned int i, lines; 1046 uint32_t cdt; 1047 1048 /* XXX why round? */ 1049 bpl = (bpl + 7) & ~7; 1050 cdt = csc->csc_cdt; 1051 lines = csc->csc_fifosz / bpl; 1052 #ifdef CORAM_DEBUG 1053 printf("%s %d lines\n", __func__, lines); 1054 #endif 1055 1056 /* fill in CDT */ 1057 for (i = 0; i < lines; i++) { 1058 #ifdef CORAM_DEBUG 1059 printf("CDT ent %08x, %08x\n", cdt + (16 * i), 1060 csc->csc_fifo + (bpl * i)); 1061 #endif 1062 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1063 cdt + (16 * i), csc->csc_fifo + (bpl * i)); 1064 } 1065 1066 /* copy program */ 1067 /* converts program to little endian as it goes into sram */ 1068 bus_space_write_region_4(sc->sc_memt, sc->sc_memh, 1069 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2); 1070 1071 /* fill in CMDS */ 1072 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1073 csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc); 1074 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1075 csc->csc_cmds + CMDS_O_IRPC + 4, 0); 1076 1077 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1078 csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt); 1079 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1080 csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */ 1081 1082 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1083 csc->csc_cmds + CMDS_O_IQB, csc->csc_iq); 1084 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1085 csc->csc_cmds + CMDS_O_IQS, 1086 CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) ); 1087 1088 /* zero rest of CMDS */ 1089 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20); 1090 1091 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1092 csc->csc_ptr1, csc->csc_fifo); 1093 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1094 csc->csc_ptr2, cdt); 1095 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1096 csc->csc_cnt2, (lines * 16) >> 3); 1097 bus_space_write_4(sc->sc_memt, sc->sc_memh, 1098 csc->csc_cnt1, (bpl >> 3) - 1); 1099 1100 return 0; 1101 } 1102 1103 MODULE(MODULE_CLASS_DRIVER, coram, "cx24227,mt2131,pci"); 1104 1105 #ifdef _MODULE 1106 #include "ioconf.c" 1107 #endif 1108 1109 static int 1110 coram_modcmd(modcmd_t cmd, void *v) 1111 { 1112 int error = 0; 1113 1114 switch (cmd) { 1115 case MODULE_CMD_INIT: 1116 #ifdef _MODULE 1117 error = config_init_component(cfdriver_ioconf_coram, 1118 cfattach_ioconf_coram, cfdata_ioconf_coram); 1119 #endif 1120 return error; 1121 case MODULE_CMD_FINI: 1122 #ifdef _MODULE 1123 error = config_fini_component(cfdriver_ioconf_coram, 1124 cfattach_ioconf_coram, cfdata_ioconf_coram); 1125 #endif 1126 return error; 1127 default: 1128 return ENOTTY; 1129 } 1130 } 1131