1 /* $NetBSD: auich.c,v 1.82 2004/11/17 15:19:30 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.82 2004/11/17 15:19:30 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 187 struct ac97_codec_if *codec_if; 188 struct ac97_host_if host_if; 189 190 /* DMA scatter-gather lists. */ 191 bus_dmamap_t sc_cddmamap; 192 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 193 194 struct auich_cdata *sc_cdata; 195 196 struct auich_ring { 197 int qptr; 198 struct auich_dmalist *dmalist; 199 200 u_int32_t start, p, end; 201 int blksize; 202 203 void (*intr)(void *); 204 void *arg; 205 } pcmo, pcmi, mici; 206 207 struct auich_dma *sc_dmas; 208 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 /* Power Management */ 216 void *sc_powerhook; 217 int sc_suspend; 218 219 /* sysctl */ 220 struct sysctllog *sc_log; 221 uint32_t sc_ac97_clock; 222 int sc_ac97_clock_mib; 223 224 #define AUICH_NFORMATS 3 225 struct audio_format sc_formats[AUICH_NFORMATS]; 226 struct audio_encoding_set *sc_encodings; 227 }; 228 229 /* Debug */ 230 #ifdef AUICH_DEBUG 231 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 232 int auich_debug = 0xfffe; 233 #define ICH_DEBUG_CODECIO 0x0001 234 #define ICH_DEBUG_DMA 0x0002 235 #define ICH_DEBUG_INTR 0x0004 236 #else 237 #define DPRINTF(x,y) /* nothing */ 238 #endif 239 240 static int auich_match(struct device *, struct cfdata *, void *); 241 static void auich_attach(struct device *, struct device *, void *); 242 static int auich_detach(struct device *, int); 243 static int auich_activate(struct device *, enum devact); 244 static int auich_intr(void *); 245 246 CFATTACH_DECL(auich, sizeof(struct auich_softc), 247 auich_match, auich_attach, auich_detach, auich_activate); 248 249 static int auich_open(void *, int); 250 static void auich_close(void *); 251 static int auich_query_encoding(void *, struct audio_encoding *); 252 static int auich_set_params(void *, int, int, struct audio_params *, 253 struct audio_params *); 254 static int auich_round_blocksize(void *, int); 255 static int auich_halt_output(void *); 256 static int auich_halt_input(void *); 257 static int auich_getdev(void *, struct audio_device *); 258 static int auich_set_port(void *, mixer_ctrl_t *); 259 static int auich_get_port(void *, mixer_ctrl_t *); 260 static int auich_query_devinfo(void *, mixer_devinfo_t *); 261 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 262 static void auich_freem(void *, void *, struct malloc_type *); 263 static size_t auich_round_buffersize(void *, int, size_t); 264 static paddr_t auich_mappage(void *, void *, off_t, int); 265 static int auich_get_props(void *); 266 static int auich_trigger_output(void *, void *, void *, int, 267 void (*)(void *), void *, struct audio_params *); 268 static int auich_trigger_input(void *, void *, void *, int, 269 void (*)(void *), void *, struct audio_params *); 270 271 static int auich_alloc_cdata(struct auich_softc *); 272 273 static int auich_allocmem(struct auich_softc *, size_t, size_t, 274 struct auich_dma *); 275 static int auich_freemem(struct auich_softc *, struct auich_dma *); 276 277 static void auich_powerhook(int, void *); 278 static int auich_set_rate(struct auich_softc *, int, u_long); 279 static int auich_sysctl_verify(SYSCTLFN_ARGS); 280 static void auich_finish_attach(struct device *); 281 static void auich_calibrate(struct auich_softc *); 282 283 static int auich_attach_codec(void *, struct ac97_codec_if *); 284 static int auich_read_codec(void *, u_int8_t, u_int16_t *); 285 static int auich_write_codec(void *, u_int8_t, u_int16_t); 286 static int auich_reset_codec(void *); 287 288 const struct audio_hw_if auich_hw_if = { 289 auich_open, 290 auich_close, 291 NULL, /* drain */ 292 auich_query_encoding, 293 auich_set_params, 294 auich_round_blocksize, 295 NULL, /* commit_setting */ 296 NULL, /* init_output */ 297 NULL, /* init_input */ 298 NULL, /* start_output */ 299 NULL, /* start_input */ 300 auich_halt_output, 301 auich_halt_input, 302 NULL, /* speaker_ctl */ 303 auich_getdev, 304 NULL, /* getfd */ 305 auich_set_port, 306 auich_get_port, 307 auich_query_devinfo, 308 auich_allocm, 309 auich_freem, 310 auich_round_buffersize, 311 auich_mappage, 312 auich_get_props, 313 auich_trigger_output, 314 auich_trigger_input, 315 NULL, /* dev_ioctl */ 316 }; 317 318 #define AUICH_FORMATS_4CH 1 319 #define AUICH_FORMATS_6CH 2 320 static const struct audio_format auich_formats[AUICH_NFORMATS] = { 321 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 322 2, AUFMT_STEREO, 0, {8000, 48000}}, 323 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 324 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 325 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 326 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 327 }; 328 329 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 330 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 331 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 332 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 333 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 334 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 335 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 336 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 337 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 338 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 339 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 340 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 341 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 342 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 343 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 344 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 345 346 static const struct auich_devtype { 347 pcireg_t id; 348 const char *name; 349 const char *shortname; /* must be less than 11 characters */ 350 } auich_devices[] = { 351 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 352 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 353 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 354 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 355 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 356 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 357 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 358 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 359 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 360 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 361 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 362 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 363 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 364 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 365 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 366 { 0, NULL, NULL }, 367 }; 368 369 static const struct auich_devtype * 370 auich_lookup(struct pci_attach_args *pa) 371 { 372 const struct auich_devtype *d; 373 374 for (d = auich_devices; d->name != NULL; d++) { 375 if (pa->pa_id == d->id) 376 return (d); 377 } 378 379 return (NULL); 380 } 381 382 static int 383 auich_match(struct device *parent, struct cfdata *match, void *aux) 384 { 385 struct pci_attach_args *pa = aux; 386 387 if (auich_lookup(pa) != NULL) 388 return (1); 389 390 return (0); 391 } 392 393 static void 394 auich_attach(struct device *parent, struct device *self, void *aux) 395 { 396 struct auich_softc *sc = (struct auich_softc *)self; 397 struct pci_attach_args *pa = aux; 398 pci_intr_handle_t ih; 399 pcireg_t v; 400 const char *intrstr; 401 const struct auich_devtype *d; 402 struct sysctlnode *node; 403 int err, node_mib, i; 404 405 aprint_naive(": Audio controller\n"); 406 407 d = auich_lookup(pa); 408 if (d == NULL) 409 panic("auich_attach: impossible"); 410 411 sc->sc_pc = pa->pa_pc; 412 sc->sc_pt = pa->pa_tag; 413 414 aprint_normal(": %s\n", d->name); 415 416 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6) { 417 /* 418 * Use native mode for ICH4/ICH5/ICH6 419 */ 420 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 421 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 422 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 423 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 424 v | ICH_CFG_IOSE); 425 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 426 0, &sc->iot, &sc->mix_ioh, NULL, 427 &sc->mix_size)) { 428 aprint_error("%s: can't map codec i/o space\n", 429 sc->sc_dev.dv_xname); 430 return; 431 } 432 } 433 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 434 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 435 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 436 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 437 v | ICH_CFG_IOSE); 438 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 439 0, &sc->iot, &sc->aud_ioh, NULL, 440 &sc->aud_size)) { 441 aprint_error("%s: can't map device i/o space\n", 442 sc->sc_dev.dv_xname); 443 return; 444 } 445 } 446 } else { 447 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 448 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 449 aprint_error("%s: can't map codec i/o space\n", 450 sc->sc_dev.dv_xname); 451 return; 452 } 453 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 454 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 455 aprint_error("%s: can't map device i/o space\n", 456 sc->sc_dev.dv_xname); 457 return; 458 } 459 } 460 sc->dmat = pa->pa_dmat; 461 462 /* enable bus mastering */ 463 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 464 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 465 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 466 467 /* Map and establish the interrupt. */ 468 if (pci_intr_map(pa, &ih)) { 469 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 470 return; 471 } 472 intrstr = pci_intr_string(pa->pa_pc, ih); 473 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 474 auich_intr, sc); 475 if (sc->sc_ih == NULL) { 476 aprint_error("%s: can't establish interrupt", 477 sc->sc_dev.dv_xname); 478 if (intrstr != NULL) 479 aprint_normal(" at %s", intrstr); 480 aprint_normal("\n"); 481 return; 482 } 483 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 484 485 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 486 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 487 "0x%02x", PCI_REVISION(pa->pa_class)); 488 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 489 490 /* SiS 7012 needs special handling */ 491 if (d->id == PCIID_SIS7012) { 492 sc->sc_sts_reg = ICH_PICB; 493 sc->sc_sample_shift = 0; 494 } else { 495 sc->sc_sts_reg = ICH_STS; 496 sc->sc_sample_shift = 1; 497 } 498 499 /* Workaround for a 440MX B-stepping erratum */ 500 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 501 if (d->id == PCIID_440MX) { 502 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 503 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 504 } 505 506 /* Set up DMA lists. */ 507 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 508 auich_alloc_cdata(sc); 509 510 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 511 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 512 513 sc->host_if.arg = sc; 514 sc->host_if.attach = auich_attach_codec; 515 sc->host_if.read = auich_read_codec; 516 sc->host_if.write = auich_write_codec; 517 sc->host_if.reset = auich_reset_codec; 518 519 if (ac97_attach(&sc->host_if) != 0) 520 return; 521 522 /* setup audio_format */ 523 memcpy(sc->sc_formats, auich_formats, sizeof(auich_formats)); 524 if (!AC97_IS_4CH(sc->codec_if)) 525 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_4CH]); 526 if (!AC97_IS_6CH(sc->codec_if)) 527 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_6CH]); 528 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 529 for (i = 0; i < AUICH_NFORMATS; i++) { 530 sc->sc_formats[i].frequency_type = 1; 531 sc->sc_formats[i].frequency[0] = 48000; 532 } 533 } 534 535 if (0 != auconv_create_encodings(sc->sc_formats, AUICH_NFORMATS, 536 &sc->sc_encodings)) { 537 return; 538 } 539 540 /* Watch for power change */ 541 sc->sc_suspend = PWR_RESUME; 542 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 543 544 config_interrupts(self, auich_finish_attach); 545 546 /* sysctl setup */ 547 if (AC97_IS_FIXED_RATE(sc->codec_if)) 548 return; 549 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 550 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 551 CTL_HW, CTL_EOL); 552 if (err != 0) 553 goto sysctl_err; 554 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 555 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 556 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 557 if (err != 0) 558 goto sysctl_err; 559 node_mib = node->sysctl_num; 560 /* passing the sc address instead of &sc->sc_ac97_clock */ 561 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 562 CTLTYPE_INT, "ac97rate", 563 SYSCTL_DESCR("AC'97 codec link rate"), 564 auich_sysctl_verify, 0, sc, 0, 565 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 566 if (err != 0) 567 goto sysctl_err; 568 sc->sc_ac97_clock_mib = node->sysctl_num; 569 570 return; 571 572 sysctl_err: 573 printf("%s: failed to add sysctl nodes. (%d)\n", 574 sc->sc_dev.dv_xname, err); 575 return; /* failure of sysctl is not fatal. */ 576 } 577 578 static int 579 auich_activate(struct device *self, enum devact act) 580 { 581 struct auich_softc *sc; 582 int ret; 583 584 sc = (struct auich_softc *)self; 585 ret = 0; 586 switch (act) { 587 case DVACT_ACTIVATE: 588 return EOPNOTSUPP; 589 case DVACT_DEACTIVATE: 590 if (sc->sc_audiodev != NULL) 591 ret = config_deactivate(sc->sc_audiodev); 592 return ret; 593 } 594 return EOPNOTSUPP; 595 } 596 597 static int 598 auich_detach(struct device *self, int flags) 599 { 600 struct auich_softc *sc; 601 602 sc = (struct auich_softc *)self; 603 604 /* audio */ 605 if (sc->sc_audiodev != NULL) 606 config_detach(sc->sc_audiodev, flags); 607 608 /* sysctl */ 609 sysctl_teardown(&sc->sc_log); 610 611 /* audio_encoding_set */ 612 auconv_delete_encodings(sc->sc_encodings); 613 614 /* ac97 */ 615 if (sc->codec_if != NULL) 616 sc->codec_if->vtbl->detach(sc->codec_if); 617 618 /* PCI */ 619 if (sc->sc_ih != NULL) 620 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 621 if (sc->mix_size != 0) 622 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 623 if (sc->aud_size != 0) 624 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 625 return 0; 626 } 627 628 static int 629 auich_sysctl_verify(SYSCTLFN_ARGS) 630 { 631 int error, tmp; 632 struct sysctlnode node; 633 struct auich_softc *sc; 634 635 node = *rnode; 636 sc = rnode->sysctl_data; 637 tmp = sc->sc_ac97_clock; 638 node.sysctl_data = &tmp; 639 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 640 if (error || newp == NULL) 641 return error; 642 643 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 644 if (tmp < 48000 || tmp > 96000) 645 return EINVAL; 646 sc->sc_ac97_clock = tmp; 647 } 648 649 return 0; 650 } 651 652 static void 653 auich_finish_attach(struct device *self) 654 { 655 struct auich_softc *sc = (void *)self; 656 657 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 658 auich_calibrate(sc); 659 660 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 661 } 662 663 #define ICH_CODECIO_INTERVAL 10 664 static int 665 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 666 { 667 struct auich_softc *sc = v; 668 int i; 669 uint32_t status; 670 671 /* wait for an access semaphore */ 672 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 673 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 674 DELAY(ICH_CODECIO_INTERVAL)); 675 676 if (i > 0) { 677 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 678 DPRINTF(ICH_DEBUG_CODECIO, 679 ("auich_read_codec(%x, %x)\n", reg, *val)); 680 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 681 if (status & ICH_RCS) { 682 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 683 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 684 *val = 0xffff; 685 DPRINTF(ICH_DEBUG_CODECIO, 686 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 687 return -1; 688 } 689 return 0; 690 } else { 691 DPRINTF(ICH_DEBUG_CODECIO, 692 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 693 return -1; 694 } 695 } 696 697 static int 698 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 699 { 700 struct auich_softc *sc = v; 701 int i; 702 703 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 704 /* wait for an access semaphore */ 705 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 706 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 707 DELAY(ICH_CODECIO_INTERVAL)); 708 709 if (i > 0) { 710 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 711 return 0; 712 } else { 713 DPRINTF(ICH_DEBUG_CODECIO, 714 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 715 return -1; 716 } 717 } 718 719 static int 720 auich_attach_codec(void *v, struct ac97_codec_if *cif) 721 { 722 struct auich_softc *sc = v; 723 724 sc->codec_if = cif; 725 return 0; 726 } 727 728 static int 729 auich_reset_codec(void *v) 730 { 731 struct auich_softc *sc = v; 732 int i; 733 uint32_t control, status; 734 735 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 736 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 737 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 738 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 739 740 for (i = 500000; i >= 0; i--) { 741 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 742 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 743 break; 744 DELAY(1); 745 } 746 if (i <= 0) { 747 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 748 return ETIMEDOUT; 749 } 750 #ifdef DEBUG 751 if (status & ICH_SCR) 752 printf("%s: The 2nd codec is ready.\n", 753 sc->sc_dev.dv_xname); 754 if (status & ICH_S2CR) 755 printf("%s: The 3rd codec is ready.\n", 756 sc->sc_dev.dv_xname); 757 #endif 758 return 0; 759 } 760 761 static int 762 auich_open(void *v, int flags) 763 { 764 return 0; 765 } 766 767 static void 768 auich_close(void *v) 769 { 770 } 771 772 static int 773 auich_query_encoding(void *v, struct audio_encoding *aep) 774 { 775 struct auich_softc *sc; 776 777 sc = (struct auich_softc *)v; 778 return auconv_query_encoding(sc->sc_encodings, aep); 779 } 780 781 static int 782 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 783 { 784 int ret; 785 u_long ratetmp; 786 787 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 788 ratetmp = srate; 789 if (mode == AUMODE_RECORD) 790 return sc->codec_if->vtbl->set_rate(sc->codec_if, 791 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 792 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 793 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 794 if (ret) 795 return ret; 796 ratetmp = srate; 797 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 798 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 799 if (ret) 800 return ret; 801 ratetmp = srate; 802 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 803 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 804 return ret; 805 } 806 807 static int 808 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 809 struct audio_params *rec) 810 { 811 struct auich_softc *sc = v; 812 struct audio_params *p; 813 int mode, index; 814 u_int32_t control; 815 816 for (mode = AUMODE_RECORD; mode != -1; 817 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 818 if ((setmode & mode) == 0) 819 continue; 820 821 p = mode == AUMODE_PLAY ? play : rec; 822 if (p == NULL) 823 continue; 824 825 if (p->sample_rate < 8000 || 826 p->sample_rate > 48000) 827 return (EINVAL); 828 829 index = auconv_set_converter(sc->sc_formats, AUICH_NFORMATS, 830 mode, p, TRUE); 831 if (index < 0) 832 return EINVAL; 833 if (sc->sc_formats[index].frequency_type != 1 834 && auich_set_rate(sc, mode, p->hw_sample_rate)) 835 return EINVAL; 836 if (mode == AUMODE_PLAY) { 837 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 838 control &= ~ICH_PCM246_MASK; 839 if (p->hw_channels == 4) { 840 control |= ICH_PCM4; 841 } else if (p->hw_channels == 6) { 842 control |= ICH_PCM6; 843 } 844 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 845 } 846 } 847 848 return (0); 849 } 850 851 static int 852 auich_round_blocksize(void *v, int blk) 853 { 854 855 return (blk & ~0x3f); /* keep good alignment */ 856 } 857 858 static int 859 auich_halt_output(void *v) 860 { 861 struct auich_softc *sc = v; 862 863 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 864 865 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 866 sc->pcmo.intr = NULL; 867 868 return (0); 869 } 870 871 static int 872 auich_halt_input(void *v) 873 { 874 struct auich_softc *sc = v; 875 876 DPRINTF(ICH_DEBUG_DMA, 877 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 878 879 /* XXX halt both unless known otherwise */ 880 881 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 882 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 883 sc->pcmi.intr = NULL; 884 885 return (0); 886 } 887 888 static int 889 auich_getdev(void *v, struct audio_device *adp) 890 { 891 struct auich_softc *sc = v; 892 893 *adp = sc->sc_audev; 894 return (0); 895 } 896 897 static int 898 auich_set_port(void *v, mixer_ctrl_t *cp) 899 { 900 struct auich_softc *sc = v; 901 902 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 903 } 904 905 static int 906 auich_get_port(void *v, mixer_ctrl_t *cp) 907 { 908 struct auich_softc *sc = v; 909 910 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 911 } 912 913 static int 914 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 915 { 916 struct auich_softc *sc = v; 917 918 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 919 } 920 921 static void * 922 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 923 int flags) 924 { 925 struct auich_softc *sc = v; 926 struct auich_dma *p; 927 int error; 928 929 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 930 return (NULL); 931 932 p = malloc(sizeof(*p), pool, flags|M_ZERO); 933 if (p == NULL) 934 return (NULL); 935 936 error = auich_allocmem(sc, size, 0, p); 937 if (error) { 938 free(p, pool); 939 return (NULL); 940 } 941 942 p->next = sc->sc_dmas; 943 sc->sc_dmas = p; 944 945 return (KERNADDR(p)); 946 } 947 948 static void 949 auich_freem(void *v, void *ptr, struct malloc_type *pool) 950 { 951 struct auich_softc *sc = v; 952 struct auich_dma *p, **pp; 953 954 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 955 if (KERNADDR(p) == ptr) { 956 auich_freemem(sc, p); 957 *pp = p->next; 958 free(p, pool); 959 return; 960 } 961 } 962 } 963 964 static size_t 965 auich_round_buffersize(void *v, int direction, size_t size) 966 { 967 968 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 969 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 970 971 return size; 972 } 973 974 static paddr_t 975 auich_mappage(void *v, void *mem, off_t off, int prot) 976 { 977 struct auich_softc *sc = v; 978 struct auich_dma *p; 979 980 if (off < 0) 981 return (-1); 982 983 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 984 ; 985 if (!p) 986 return (-1); 987 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 988 off, prot, BUS_DMA_WAITOK)); 989 } 990 991 static int 992 auich_get_props(void *v) 993 { 994 struct auich_softc *sc = v; 995 int props; 996 997 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 998 /* 999 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1000 * rate because of aurateconv. Applications can't know what rate the 1001 * device can process in the case of mmap(). 1002 */ 1003 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 1004 props |= AUDIO_PROP_MMAP; 1005 return props; 1006 } 1007 1008 static int 1009 auich_intr(void *v) 1010 { 1011 struct auich_softc *sc = v; 1012 int ret = 0, gsts; 1013 1014 #ifdef DIAGNOSTIC 1015 int csts; 1016 #endif 1017 1018 #ifdef DIAGNOSTIC 1019 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1020 if (csts & PCI_STATUS_MASTER_ABORT) { 1021 printf("auich_intr: PCI master abort\n"); 1022 } 1023 #endif 1024 1025 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 1026 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1027 1028 if (gsts & ICH_POINT) { 1029 int sts; 1030 1031 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1032 ICH_PCMO + sc->sc_sts_reg); 1033 DPRINTF(ICH_DEBUG_INTR, 1034 ("auich_intr: osts=0x%x\n", sts)); 1035 1036 if (sts & ICH_FIFOE) 1037 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1038 1039 if (sts & ICH_BCIS) { 1040 struct auich_dmalist *q; 1041 int blksize, qptr, i; 1042 1043 blksize = sc->pcmo.blksize; 1044 qptr = sc->pcmo.qptr; 1045 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1046 ICH_PCMO + ICH_CIV); 1047 1048 while (qptr != i) { 1049 q = &sc->pcmo.dmalist[qptr]; 1050 1051 q->base = sc->pcmo.p; 1052 q->len = (blksize >> sc->sc_sample_shift) | 1053 ICH_DMAF_IOC; 1054 DPRINTF(ICH_DEBUG_INTR, 1055 ("auich_intr: %p, %p = %x @ 0x%x\n", 1056 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1057 1058 sc->pcmo.p += blksize; 1059 if (sc->pcmo.p >= sc->pcmo.end) 1060 sc->pcmo.p = sc->pcmo.start; 1061 1062 qptr = (qptr + 1) & ICH_LVI_MASK; 1063 if (sc->pcmo.intr) 1064 sc->pcmo.intr(sc->pcmo.arg); 1065 } 1066 1067 sc->pcmo.qptr = qptr; 1068 bus_space_write_1(sc->iot, sc->aud_ioh, 1069 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1070 } 1071 1072 /* int ack */ 1073 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1074 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1075 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1076 ret++; 1077 } 1078 1079 if (gsts & ICH_PIINT) { 1080 int sts; 1081 1082 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1083 ICH_PCMI + sc->sc_sts_reg); 1084 DPRINTF(ICH_DEBUG_INTR, 1085 ("auich_intr: ists=0x%x\n", sts)); 1086 1087 if (sts & ICH_FIFOE) 1088 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1089 1090 if (sts & ICH_BCIS) { 1091 struct auich_dmalist *q; 1092 int blksize, qptr, i; 1093 1094 blksize = sc->pcmi.blksize; 1095 qptr = sc->pcmi.qptr; 1096 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1097 ICH_PCMI + ICH_CIV); 1098 1099 while (qptr != i) { 1100 q = &sc->pcmi.dmalist[qptr]; 1101 1102 q->base = sc->pcmi.p; 1103 q->len = (blksize >> sc->sc_sample_shift) | 1104 ICH_DMAF_IOC; 1105 DPRINTF(ICH_DEBUG_INTR, 1106 ("auich_intr: %p, %p = %x @ 0x%x\n", 1107 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1108 1109 sc->pcmi.p += blksize; 1110 if (sc->pcmi.p >= sc->pcmi.end) 1111 sc->pcmi.p = sc->pcmi.start; 1112 1113 qptr = (qptr + 1) & ICH_LVI_MASK; 1114 if (sc->pcmi.intr) 1115 sc->pcmi.intr(sc->pcmi.arg); 1116 } 1117 1118 sc->pcmi.qptr = qptr; 1119 bus_space_write_1(sc->iot, sc->aud_ioh, 1120 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1121 } 1122 1123 /* int ack */ 1124 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1125 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1126 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1127 ret++; 1128 } 1129 1130 if (gsts & ICH_MIINT) { 1131 int sts; 1132 1133 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1134 ICH_MICI + sc->sc_sts_reg); 1135 DPRINTF(ICH_DEBUG_INTR, 1136 ("auich_intr: ists=0x%x\n", sts)); 1137 1138 if (sts & ICH_FIFOE) 1139 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1140 1141 /* TODO mic input DMA */ 1142 1143 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1144 } 1145 1146 return ret; 1147 } 1148 1149 static int 1150 auich_trigger_output(void *v, void *start, void *end, int blksize, 1151 void (*intr)(void *), void *arg, struct audio_params *param) 1152 { 1153 struct auich_softc *sc = v; 1154 struct auich_dmalist *q; 1155 struct auich_dma *p; 1156 size_t size; 1157 int qptr; 1158 #ifdef DIAGNOSTIC 1159 int csts; 1160 #endif 1161 1162 DPRINTF(ICH_DEBUG_DMA, 1163 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1164 start, end, blksize, intr, arg, param)); 1165 1166 sc->pcmo.intr = intr; 1167 sc->pcmo.arg = arg; 1168 #ifdef DIAGNOSTIC 1169 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1170 if (csts & PCI_STATUS_MASTER_ABORT) { 1171 printf("auich_trigger_output: PCI master abort\n"); 1172 } 1173 #endif 1174 1175 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1176 ; 1177 if (!p) { 1178 printf("auich_trigger_output: bad addr %p\n", start); 1179 return (EINVAL); 1180 } 1181 1182 size = (size_t)((caddr_t)end - (caddr_t)start); 1183 1184 /* 1185 * The logic behind this is: 1186 * setup one buffer to play, then LVI dump out the rest 1187 * to the scatter-gather chain. 1188 */ 1189 sc->pcmo.start = DMAADDR(p); 1190 sc->pcmo.p = sc->pcmo.start; 1191 sc->pcmo.end = sc->pcmo.start + size; 1192 sc->pcmo.blksize = blksize; 1193 1194 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1195 q = &sc->pcmo.dmalist[qptr]; 1196 1197 q->base = sc->pcmo.p; 1198 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1199 1200 sc->pcmo.p += blksize; 1201 if (sc->pcmo.p >= sc->pcmo.end) 1202 sc->pcmo.p = sc->pcmo.start; 1203 } 1204 1205 sc->pcmo.qptr = qptr = 0; 1206 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1207 (qptr - 1) & ICH_LVI_MASK); 1208 1209 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1210 sc->sc_cddma + ICH_PCMO_OFF(0)); 1211 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1212 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1213 1214 return (0); 1215 } 1216 1217 static int 1218 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1219 void *v; 1220 void *start, *end; 1221 int blksize; 1222 void (*intr)(void *); 1223 void *arg; 1224 struct audio_params *param; 1225 { 1226 struct auich_softc *sc = v; 1227 struct auich_dmalist *q; 1228 struct auich_dma *p; 1229 size_t size; 1230 int qptr; 1231 #ifdef DIAGNOSTIC 1232 int csts; 1233 #endif 1234 1235 DPRINTF(ICH_DEBUG_DMA, 1236 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1237 start, end, blksize, intr, arg, param)); 1238 1239 sc->pcmi.intr = intr; 1240 sc->pcmi.arg = arg; 1241 1242 #ifdef DIAGNOSTIC 1243 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1244 if (csts & PCI_STATUS_MASTER_ABORT) { 1245 printf("auich_trigger_input: PCI master abort\n"); 1246 } 1247 #endif 1248 1249 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1250 ; 1251 if (!p) { 1252 printf("auich_trigger_input: bad addr %p\n", start); 1253 return (EINVAL); 1254 } 1255 1256 size = (size_t)((caddr_t)end - (caddr_t)start); 1257 1258 /* 1259 * The logic behind this is: 1260 * setup one buffer to play, then LVI dump out the rest 1261 * to the scatter-gather chain. 1262 */ 1263 sc->pcmi.start = DMAADDR(p); 1264 sc->pcmi.p = sc->pcmi.start; 1265 sc->pcmi.end = sc->pcmi.start + size; 1266 sc->pcmi.blksize = blksize; 1267 1268 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1269 q = &sc->pcmi.dmalist[qptr]; 1270 1271 q->base = sc->pcmi.p; 1272 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1273 1274 sc->pcmi.p += blksize; 1275 if (sc->pcmi.p >= sc->pcmi.end) 1276 sc->pcmi.p = sc->pcmi.start; 1277 } 1278 1279 sc->pcmi.qptr = qptr = 0; 1280 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1281 (qptr - 1) & ICH_LVI_MASK); 1282 1283 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1284 sc->sc_cddma + ICH_PCMI_OFF(0)); 1285 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1286 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1287 1288 return (0); 1289 } 1290 1291 static int 1292 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1293 struct auich_dma *p) 1294 { 1295 int error; 1296 1297 p->size = size; 1298 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1299 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1300 &p->nsegs, BUS_DMA_NOWAIT); 1301 if (error) 1302 return (error); 1303 1304 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1305 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1306 if (error) 1307 goto free; 1308 1309 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1310 0, BUS_DMA_NOWAIT, &p->map); 1311 if (error) 1312 goto unmap; 1313 1314 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1315 BUS_DMA_NOWAIT); 1316 if (error) 1317 goto destroy; 1318 return (0); 1319 1320 destroy: 1321 bus_dmamap_destroy(sc->dmat, p->map); 1322 unmap: 1323 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1324 free: 1325 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1326 return (error); 1327 } 1328 1329 static int 1330 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1331 { 1332 1333 bus_dmamap_unload(sc->dmat, p->map); 1334 bus_dmamap_destroy(sc->dmat, p->map); 1335 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1336 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1337 return (0); 1338 } 1339 1340 static int 1341 auich_alloc_cdata(struct auich_softc *sc) 1342 { 1343 bus_dma_segment_t seg; 1344 int error, rseg; 1345 1346 /* 1347 * Allocate the control data structure, and create and load the 1348 * DMA map for it. 1349 */ 1350 if ((error = bus_dmamem_alloc(sc->dmat, 1351 sizeof(struct auich_cdata), 1352 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1353 printf("%s: unable to allocate control data, error = %d\n", 1354 sc->sc_dev.dv_xname, error); 1355 goto fail_0; 1356 } 1357 1358 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1359 sizeof(struct auich_cdata), 1360 (caddr_t *) &sc->sc_cdata, 1361 sc->sc_dmamap_flags)) != 0) { 1362 printf("%s: unable to map control data, error = %d\n", 1363 sc->sc_dev.dv_xname, error); 1364 goto fail_1; 1365 } 1366 1367 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1368 sizeof(struct auich_cdata), 0, 0, 1369 &sc->sc_cddmamap)) != 0) { 1370 printf("%s: unable to create control data DMA map, " 1371 "error = %d\n", sc->sc_dev.dv_xname, error); 1372 goto fail_2; 1373 } 1374 1375 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1376 sc->sc_cdata, sizeof(struct auich_cdata), 1377 NULL, 0)) != 0) { 1378 printf("%s: unable tp load control data DMA map, " 1379 "error = %d\n", sc->sc_dev.dv_xname, error); 1380 goto fail_3; 1381 } 1382 1383 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1384 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1385 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1386 1387 return (0); 1388 1389 fail_3: 1390 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1391 fail_2: 1392 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1393 sizeof(struct auich_cdata)); 1394 fail_1: 1395 bus_dmamem_free(sc->dmat, &seg, rseg); 1396 fail_0: 1397 return (error); 1398 } 1399 1400 static void 1401 auich_powerhook(int why, void *addr) 1402 { 1403 struct auich_softc *sc = (struct auich_softc *)addr; 1404 1405 switch (why) { 1406 case PWR_SUSPEND: 1407 case PWR_STANDBY: 1408 /* Power down */ 1409 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1410 sc->sc_suspend = why; 1411 break; 1412 1413 case PWR_RESUME: 1414 /* Wake up */ 1415 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1416 if (sc->sc_suspend == PWR_RESUME) { 1417 printf("%s: resume without suspend.\n", 1418 sc->sc_dev.dv_xname); 1419 sc->sc_suspend = why; 1420 return; 1421 } 1422 sc->sc_suspend = why; 1423 auich_reset_codec(sc); 1424 DELAY(1000); 1425 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1426 break; 1427 1428 case PWR_SOFTSUSPEND: 1429 case PWR_SOFTSTANDBY: 1430 case PWR_SOFTRESUME: 1431 break; 1432 } 1433 } 1434 1435 /* 1436 * Calibrate card (some boards are overclocked and need scaling) 1437 */ 1438 static void 1439 auich_calibrate(struct auich_softc *sc) 1440 { 1441 struct timeval t1, t2; 1442 uint8_t ociv, nciv; 1443 uint64_t wait_us; 1444 uint32_t actual_48k_rate, bytes, ac97rate; 1445 void *temp_buffer; 1446 struct auich_dma *p; 1447 u_long rate; 1448 1449 /* 1450 * Grab audio from input for fixed interval and compare how 1451 * much we actually get with what we expect. Interval needs 1452 * to be sufficiently short that no interrupts are 1453 * generated. 1454 */ 1455 1456 /* Force the codec to a known state first. */ 1457 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1458 rate = sc->sc_ac97_clock = 48000; 1459 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1460 &rate); 1461 1462 /* Setup a buffer */ 1463 bytes = 64000; 1464 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1465 1466 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1467 ; 1468 if (p == NULL) { 1469 printf("auich_calibrate: bad address %p\n", temp_buffer); 1470 return; 1471 } 1472 sc->pcmi.dmalist[0].base = DMAADDR(p); 1473 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1474 1475 /* 1476 * our data format is stereo, 16 bit so each sample is 4 bytes. 1477 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1478 * we're going to start recording with interrupts disabled and measure 1479 * the time taken for one block to complete. we know the block size, 1480 * we know the time in microseconds, we calculate the sample rate: 1481 * 1482 * actual_rate [bps] = bytes / (time [s] * 4) 1483 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1484 * actual_rate [Hz] = (bytes * 250000) / time [us] 1485 */ 1486 1487 /* prepare */ 1488 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1489 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1490 sc->sc_cddma + ICH_PCMI_OFF(0)); 1491 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1492 (0 - 1) & ICH_LVI_MASK); 1493 1494 /* start */ 1495 microtime(&t1); 1496 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1497 1498 /* wait */ 1499 nciv = ociv; 1500 do { 1501 microtime(&t2); 1502 if (t2.tv_sec - t1.tv_sec > 1) 1503 break; 1504 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1505 ICH_PCMI + ICH_CIV); 1506 } while (nciv == ociv); 1507 microtime(&t2); 1508 1509 /* stop */ 1510 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1511 1512 /* reset */ 1513 DELAY(100); 1514 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1515 1516 /* turn time delta into us */ 1517 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1518 1519 auich_freem(sc, temp_buffer, M_DEVBUF); 1520 1521 if (nciv == ociv) { 1522 printf("%s: ac97 link rate calibration timed out after %" 1523 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1524 return; 1525 } 1526 1527 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1528 1529 if (actual_48k_rate < 50000) 1530 ac97rate = 48000; 1531 else 1532 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1533 1534 printf("%s: measured ac97 link rate at %d Hz", 1535 sc->sc_dev.dv_xname, actual_48k_rate); 1536 if (ac97rate != actual_48k_rate) 1537 printf(", will use %d Hz", ac97rate); 1538 printf("\n"); 1539 1540 sc->sc_ac97_clock = ac97rate; 1541 } 1542