1 /* $NetBSD: auich.c,v 1.129 2009/03/17 19:38:34 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 2000 Michael Shalayeff 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 51 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 52 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 53 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 55 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 56 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 57 * THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 60 */ 61 62 /* 63 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 64 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 77 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 79 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 82 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 83 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 84 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 85 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 86 * SUCH DAMAGE. 87 * 88 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 89 */ 90 91 92 /* #define AUICH_DEBUG */ 93 /* 94 * AC'97 audio found on Intel 810/820/440MX chipsets. 95 * http://developer.intel.com/design/chipsets/datashts/290655.htm 96 * http://developer.intel.com/design/chipsets/manuals/298028.htm 97 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 98 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 99 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 100 * AMD8111: 101 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 102 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 103 * 104 * TODO: 105 * - Add support for the dedicated microphone input. 106 * 107 * NOTE: 108 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 109 * It causes PCI master abort and hangups until cold reboot. 110 * http://www.intel.com/design/chipsets/specupdt/245051.htm 111 */ 112 113 #include <sys/cdefs.h> 114 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.129 2009/03/17 19:38:34 dyoung Exp $"); 115 116 #include <sys/param.h> 117 #include <sys/systm.h> 118 #include <sys/kernel.h> 119 #include <sys/malloc.h> 120 #include <sys/device.h> 121 #include <sys/fcntl.h> 122 #include <sys/proc.h> 123 #include <sys/sysctl.h> 124 125 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 126 127 #include <dev/pci/pcidevs.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/auichreg.h> 130 131 #include <sys/audioio.h> 132 #include <dev/audio_if.h> 133 #include <dev/mulaw.h> 134 #include <dev/auconv.h> 135 136 #include <sys/bus.h> 137 138 #include <dev/ic/ac97reg.h> 139 #include <dev/ic/ac97var.h> 140 141 struct auich_dma { 142 bus_dmamap_t map; 143 void *addr; 144 bus_dma_segment_t segs[1]; 145 int nsegs; 146 size_t size; 147 struct auich_dma *next; 148 }; 149 150 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 151 #define KERNADDR(p) ((void *)((p)->addr)) 152 153 struct auich_cdata { 154 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 155 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 156 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 157 }; 158 159 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 160 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 161 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 162 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 163 164 struct auich_softc { 165 device_t sc_dev; 166 void *sc_ih; 167 168 device_t sc_audiodev; 169 audio_device_t sc_audev; 170 171 pci_chipset_tag_t sc_pc; 172 pcitag_t sc_pt; 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_size_t mix_size; 176 bus_space_handle_t aud_ioh; 177 bus_size_t aud_size; 178 bus_dma_tag_t dmat; 179 pci_intr_handle_t intrh; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 int sc_codecnum; 184 int sc_codectype; 185 enum ac97_host_flags sc_codecflags; 186 bool sc_spdif; 187 188 /* DMA scatter-gather lists. */ 189 bus_dmamap_t sc_cddmamap; 190 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 191 192 struct auich_cdata *sc_cdata; 193 194 struct auich_ring { 195 int qptr; 196 struct auich_dmalist *dmalist; 197 198 uint32_t start, p, end; 199 int blksize; 200 201 void (*intr)(void *); 202 void *arg; 203 } pcmo, pcmi, mici; 204 205 struct auich_dma *sc_dmas; 206 207 /* SiS 7012 hack */ 208 int sc_sample_shift; 209 int sc_sts_reg; 210 /* 440MX workaround */ 211 int sc_dmamap_flags; 212 /* Native mode? */ 213 int sc_native_mode; 214 215 /* sysctl */ 216 struct sysctllog *sc_log; 217 uint32_t sc_ac97_clock; 218 int sc_ac97_clock_mib; 219 220 int sc_modem_offset; 221 222 #define AUICH_AUDIO_NFORMATS 3 223 #define AUICH_MODEM_NFORMATS 1 224 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 225 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 226 struct audio_encoding_set *sc_encodings; 227 struct audio_encoding_set *sc_spdif_encodings; 228 }; 229 230 /* Debug */ 231 #ifdef AUICH_DEBUG 232 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 233 int auich_debug = 0xfffe; 234 #define ICH_DEBUG_CODECIO 0x0001 235 #define ICH_DEBUG_DMA 0x0002 236 #define ICH_DEBUG_INTR 0x0004 237 #else 238 #define DPRINTF(x,y) /* nothing */ 239 #endif 240 241 static int auich_match(device_t, cfdata_t, void *); 242 static void auich_attach(device_t, device_t, void *); 243 static int auich_detach(device_t, int); 244 static void auich_childdet(device_t, device_t); 245 static int auich_activate(device_t, enum devact); 246 static int auich_intr(void *); 247 248 CFATTACH_DECL2_NEW(auich, sizeof(struct auich_softc), 249 auich_match, auich_attach, auich_detach, auich_activate, NULL, 250 auich_childdet); 251 252 static int auich_open(void *, int); 253 static void auich_close(void *); 254 static int auich_query_encoding(void *, struct audio_encoding *); 255 static int auich_set_params(void *, int, int, audio_params_t *, 256 audio_params_t *, stream_filter_list_t *, 257 stream_filter_list_t *); 258 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 259 static void auich_halt_pipe(struct auich_softc *, int); 260 static int auich_halt_output(void *); 261 static int auich_halt_input(void *); 262 static int auich_getdev(void *, struct audio_device *); 263 static int auich_set_port(void *, mixer_ctrl_t *); 264 static int auich_get_port(void *, mixer_ctrl_t *); 265 static int auich_query_devinfo(void *, mixer_devinfo_t *); 266 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 267 static void auich_freem(void *, void *, struct malloc_type *); 268 static size_t auich_round_buffersize(void *, int, size_t); 269 static paddr_t auich_mappage(void *, void *, off_t, int); 270 static int auich_get_props(void *); 271 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 272 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 273 static int auich_trigger_output(void *, void *, void *, int, 274 void (*)(void *), void *, const audio_params_t *); 275 static int auich_trigger_input(void *, void *, void *, int, 276 void (*)(void *), void *, const audio_params_t *); 277 static int auich_powerstate(void *, int); 278 279 static int auich_alloc_cdata(struct auich_softc *); 280 281 static int auich_allocmem(struct auich_softc *, size_t, size_t, 282 struct auich_dma *); 283 static int auich_freemem(struct auich_softc *, struct auich_dma *); 284 285 static bool auich_resume(device_t PMF_FN_PROTO); 286 static int auich_set_rate(struct auich_softc *, int, u_long); 287 static int auich_sysctl_verify(SYSCTLFN_ARGS); 288 static void auich_finish_attach(device_t); 289 static void auich_calibrate(struct auich_softc *); 290 static void auich_clear_cas(struct auich_softc *); 291 292 static int auich_attach_codec(void *, struct ac97_codec_if *); 293 static int auich_read_codec(void *, uint8_t, uint16_t *); 294 static int auich_write_codec(void *, uint8_t, uint16_t); 295 static int auich_reset_codec(void *); 296 static enum ac97_host_flags auich_flags_codec(void *); 297 static void auich_spdif_event(void *, bool); 298 299 static const struct audio_hw_if auich_hw_if = { 300 auich_open, 301 auich_close, 302 NULL, /* drain */ 303 auich_query_encoding, 304 auich_set_params, 305 auich_round_blocksize, 306 NULL, /* commit_setting */ 307 NULL, /* init_output */ 308 NULL, /* init_input */ 309 NULL, /* start_output */ 310 NULL, /* start_input */ 311 auich_halt_output, 312 auich_halt_input, 313 NULL, /* speaker_ctl */ 314 auich_getdev, 315 NULL, /* getfd */ 316 auich_set_port, 317 auich_get_port, 318 auich_query_devinfo, 319 auich_allocm, 320 auich_freem, 321 auich_round_buffersize, 322 auich_mappage, 323 auich_get_props, 324 auich_trigger_output, 325 auich_trigger_input, 326 NULL, /* dev_ioctl */ 327 auich_powerstate, 328 }; 329 330 #define AUICH_FORMATS_1CH 0 331 #define AUICH_FORMATS_4CH 1 332 #define AUICH_FORMATS_6CH 2 333 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 334 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 335 2, AUFMT_STEREO, 0, {8000, 48000}}, 336 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 337 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 338 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 339 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 340 }; 341 342 #define AUICH_SPDIF_NFORMATS 1 343 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 344 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 345 2, AUFMT_STEREO, 1, {48000}}, 346 }; 347 348 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 349 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 350 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 351 }; 352 353 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 354 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 355 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 356 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 357 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 358 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 359 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 360 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 361 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 362 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 363 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 364 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 365 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 366 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 367 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 368 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 369 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 370 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 371 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 372 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 373 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 374 375 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 376 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 377 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 378 379 struct auich_devtype { 380 pcireg_t id; 381 const char *name; 382 const char *shortname; /* must be less than 11 characters */ 383 }; 384 385 static const struct auich_devtype auich_audio_devices[] = { 386 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 387 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 388 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 389 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 390 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 391 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 392 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 393 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 394 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 395 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 396 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 397 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 398 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 399 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 400 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 401 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 402 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 403 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 404 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 405 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 406 { 0, NULL, NULL }, 407 }; 408 409 static const struct auich_devtype auich_modem_devices[] = { 410 #ifdef AUICH_ATTACH_MODEM 411 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 412 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 413 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 414 #endif 415 { 0, NULL, NULL }, 416 }; 417 418 static const struct auich_devtype * 419 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 420 { 421 const struct auich_devtype *d; 422 423 for (d = auich_devices; d->name != NULL; d++) { 424 if (pa->pa_id == d->id) 425 return d; 426 } 427 428 return NULL; 429 } 430 431 static int 432 auich_match(device_t parent, cfdata_t match, void *aux) 433 { 434 struct pci_attach_args *pa; 435 436 pa = aux; 437 if (auich_lookup(pa, auich_audio_devices) != NULL) 438 return 1; 439 if (auich_lookup(pa, auich_modem_devices) != NULL) 440 return 1; 441 442 return 0; 443 } 444 445 static void 446 auich_attach(device_t parent, device_t self, void *aux) 447 { 448 struct auich_softc *sc = device_private(self); 449 struct pci_attach_args *pa; 450 pcireg_t v, subdev; 451 const char *intrstr; 452 const struct auich_devtype *d; 453 const struct sysctlnode *node, *node_ac97clock; 454 int err, node_mib, i; 455 456 sc->sc_dev = self; 457 pa = aux; 458 459 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 460 sc->sc_modem_offset = 0x10; 461 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 462 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 463 sc->sc_modem_offset = 0; 464 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 465 } else 466 panic("auich_attach: impossible"); 467 468 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 469 aprint_naive(": Audio controller\n"); 470 else 471 aprint_naive(": Modem controller\n"); 472 473 sc->sc_pc = pa->pa_pc; 474 sc->sc_pt = pa->pa_tag; 475 476 aprint_normal(": %s\n", d->name); 477 478 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 479 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 480 || d->id == PCIID_ICH4MODEM) { 481 sc->sc_native_mode = 1; 482 /* 483 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 484 */ 485 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 486 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 487 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 488 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 489 v | ICH_CFG_IOSE); 490 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 491 0, &sc->iot, &sc->mix_ioh, NULL, 492 &sc->mix_size)) { 493 aprint_error_dev(self, "can't map codec i/o space\n"); 494 return; 495 } 496 } 497 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 498 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 499 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 500 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 501 v | ICH_CFG_IOSE); 502 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 503 0, &sc->iot, &sc->aud_ioh, NULL, 504 &sc->aud_size)) { 505 aprint_error_dev(self, "can't map device i/o space\n"); 506 return; 507 } 508 } 509 } else { 510 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 511 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 512 aprint_error_dev(self, "can't map codec i/o space\n"); 513 return; 514 } 515 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 516 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 517 aprint_error_dev(self, "can't map device i/o space\n"); 518 return; 519 } 520 } 521 sc->dmat = pa->pa_dmat; 522 523 /* enable bus mastering */ 524 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 525 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 526 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 527 528 /* Map and establish the interrupt. */ 529 if (pci_intr_map(pa, &sc->intrh)) { 530 aprint_error_dev(self, "can't map interrupt\n"); 531 return; 532 } 533 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 534 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 535 auich_intr, sc); 536 if (sc->sc_ih == NULL) { 537 aprint_error_dev(self, "can't establish interrupt"); 538 if (intrstr != NULL) 539 aprint_normal(" at %s", intrstr); 540 aprint_normal("\n"); 541 return; 542 } 543 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 544 545 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 546 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 547 "0x%02x", PCI_REVISION(pa->pa_class)); 548 strlcpy(sc->sc_audev.config, device_xname(self), MAX_AUDIO_DEV_LEN); 549 550 /* SiS 7012 needs special handling */ 551 if (d->id == PCIID_SIS7012) { 552 sc->sc_sts_reg = ICH_PICB; 553 sc->sc_sample_shift = 0; 554 /* Un-mute output. From Linux. */ 555 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 556 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 557 ICH_SIS_CTL_UNMUTE); 558 } else { 559 sc->sc_sts_reg = ICH_STS; 560 sc->sc_sample_shift = 1; 561 } 562 563 /* Workaround for a 440MX B-stepping erratum */ 564 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 565 if (d->id == PCIID_440MX) { 566 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 567 aprint_normal_dev(self, "DMA bug workaround enabled\n"); 568 } 569 570 /* Set up DMA lists. */ 571 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 572 auich_alloc_cdata(sc); 573 574 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 575 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 576 577 /* Modem codecs are always the secondary codec on ICH */ 578 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 579 580 sc->host_if.arg = sc; 581 sc->host_if.attach = auich_attach_codec; 582 sc->host_if.read = auich_read_codec; 583 sc->host_if.write = auich_write_codec; 584 sc->host_if.reset = auich_reset_codec; 585 sc->host_if.flags = auich_flags_codec; 586 sc->host_if.spdif_event = auich_spdif_event; 587 588 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 589 switch (subdev) { 590 case 0x202f161f: /* Gateway 7326GZ */ 591 case 0x203a161f: /* Gateway 4028GZ */ 592 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 593 case 0x8144104d: /* Sony VAIO PCG-TR* */ 594 case 0x8197104d: /* Sony S1XP */ 595 case 0x81c0104d: /* Sony VAIO type T */ 596 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 597 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 598 break; 599 default: 600 sc->sc_codecflags = 0; 601 break; 602 } 603 604 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 605 return; 606 sc->codec_if->vtbl->unlock(sc->codec_if); 607 608 /* setup audio_format */ 609 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 610 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 611 if (!AC97_IS_4CH(sc->codec_if)) 612 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 613 if (!AC97_IS_6CH(sc->codec_if)) 614 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 615 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 616 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 617 sc->sc_audio_formats[i].frequency_type = 1; 618 sc->sc_audio_formats[i].frequency[0] = 48000; 619 } 620 } 621 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 622 &sc->sc_encodings)) 623 return; 624 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 625 &sc->sc_spdif_encodings)) 626 return; 627 } else { 628 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 629 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 630 &sc->sc_encodings)) 631 return; 632 } 633 634 /* Watch for power change */ 635 if (!pmf_device_register(self, NULL, auich_resume)) 636 aprint_error_dev(self, "couldn't establish power handler\n"); 637 638 config_interrupts(self, auich_finish_attach); 639 640 /* sysctl setup */ 641 if (AC97_IS_FIXED_RATE(sc->codec_if) && 642 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 643 return; 644 645 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 646 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 647 CTL_HW, CTL_EOL); 648 if (err != 0) 649 goto sysctl_err; 650 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 651 CTLTYPE_NODE, device_xname(self), NULL, NULL, 0, 652 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 653 if (err != 0) 654 goto sysctl_err; 655 node_mib = node->sysctl_num; 656 657 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 658 /* passing the sc address instead of &sc->sc_ac97_clock */ 659 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 660 CTLFLAG_READWRITE, 661 CTLTYPE_INT, "ac97rate", 662 SYSCTL_DESCR("AC'97 codec link rate"), 663 auich_sysctl_verify, 0, sc, 0, 664 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 665 if (err != 0) 666 goto sysctl_err; 667 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 668 } 669 670 return; 671 672 sysctl_err: 673 printf("%s: failed to add sysctl nodes. (%d)\n", 674 device_xname(self), err); 675 return; /* failure of sysctl is not fatal. */ 676 } 677 678 static int 679 auich_activate(device_t self, enum devact act) 680 { 681 struct auich_softc *sc = device_private(self); 682 int ret; 683 684 ret = 0; 685 switch (act) { 686 case DVACT_ACTIVATE: 687 return EOPNOTSUPP; 688 case DVACT_DEACTIVATE: 689 if (sc->sc_audiodev != NULL) 690 ret = config_deactivate(sc->sc_audiodev); 691 return ret; 692 } 693 return EOPNOTSUPP; 694 } 695 696 static void 697 auich_childdet(device_t self, device_t child) 698 { 699 struct auich_softc *sc = device_private(self); 700 701 KASSERT(sc->sc_audiodev == child); 702 sc->sc_audiodev = NULL; 703 } 704 705 static int 706 auich_detach(device_t self, int flags) 707 { 708 struct auich_softc *sc = device_private(self); 709 710 /* audio */ 711 if (sc->sc_audiodev != NULL) 712 config_detach(sc->sc_audiodev, flags); 713 714 /* sysctl */ 715 sysctl_teardown(&sc->sc_log); 716 717 /* audio_encoding_set */ 718 auconv_delete_encodings(sc->sc_encodings); 719 auconv_delete_encodings(sc->sc_spdif_encodings); 720 721 /* ac97 */ 722 if (sc->codec_if != NULL) 723 sc->codec_if->vtbl->detach(sc->codec_if); 724 725 /* PCI */ 726 if (sc->sc_ih != NULL) 727 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 728 if (sc->mix_size != 0) 729 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 730 if (sc->aud_size != 0) 731 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 732 return 0; 733 } 734 735 static int 736 auich_sysctl_verify(SYSCTLFN_ARGS) 737 { 738 int error, tmp; 739 struct sysctlnode node; 740 struct auich_softc *sc; 741 742 node = *rnode; 743 sc = rnode->sysctl_data; 744 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 745 tmp = sc->sc_ac97_clock; 746 node.sysctl_data = &tmp; 747 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 748 if (error || newp == NULL) 749 return error; 750 751 if (tmp < 48000 || tmp > 96000) 752 return EINVAL; 753 sc->sc_ac97_clock = tmp; 754 } 755 756 return 0; 757 } 758 759 static void 760 auich_finish_attach(device_t self) 761 { 762 struct auich_softc *sc = device_private(self); 763 764 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 765 auich_calibrate(sc); 766 767 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, sc->sc_dev); 768 769 return; 770 } 771 772 #define ICH_CODECIO_INTERVAL 10 773 static int 774 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 775 { 776 struct auich_softc *sc; 777 int i; 778 uint32_t status; 779 780 sc = v; 781 /* wait for an access semaphore */ 782 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 783 bus_space_read_1(sc->iot, sc->aud_ioh, 784 ICH_CAS + sc->sc_modem_offset) & 1; 785 DELAY(ICH_CODECIO_INTERVAL)); 786 787 if (i > 0) { 788 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 789 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 790 DPRINTF(ICH_DEBUG_CODECIO, 791 ("auich_read_codec(%x, %x)\n", reg, *val)); 792 status = bus_space_read_4(sc->iot, sc->aud_ioh, 793 ICH_GSTS + sc->sc_modem_offset); 794 if (status & ICH_RCS) { 795 bus_space_write_4(sc->iot, sc->aud_ioh, 796 ICH_GSTS + sc->sc_modem_offset, 797 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 798 *val = 0xffff; 799 DPRINTF(ICH_DEBUG_CODECIO, 800 ("%s: read_codec error\n", device_xname(sc->sc_dev))); 801 if (reg == AC97_REG_GPIO_STATUS) 802 auich_clear_cas(sc); 803 return -1; 804 } 805 if (reg == AC97_REG_GPIO_STATUS) 806 auich_clear_cas(sc); 807 return 0; 808 } else { 809 aprint_normal_dev(sc->sc_dev, "read_codec timeout\n"); 810 if (reg == AC97_REG_GPIO_STATUS) 811 auich_clear_cas(sc); 812 return -1; 813 } 814 } 815 816 static int 817 auich_write_codec(void *v, uint8_t reg, uint16_t val) 818 { 819 struct auich_softc *sc; 820 int i; 821 822 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 823 sc = v; 824 /* wait for an access semaphore */ 825 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 826 bus_space_read_1(sc->iot, sc->aud_ioh, 827 ICH_CAS + sc->sc_modem_offset) & 1; 828 DELAY(ICH_CODECIO_INTERVAL)); 829 830 if (i > 0) { 831 bus_space_write_2(sc->iot, sc->mix_ioh, 832 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 833 return 0; 834 } else { 835 aprint_normal_dev(sc->sc_dev, "write_codec timeout\n"); 836 return -1; 837 } 838 } 839 840 static int 841 auich_attach_codec(void *v, struct ac97_codec_if *cif) 842 { 843 struct auich_softc *sc; 844 845 sc = v; 846 sc->codec_if = cif; 847 848 return 0; 849 } 850 851 static int 852 auich_reset_codec(void *v) 853 { 854 struct auich_softc *sc; 855 int i; 856 uint32_t control, status; 857 858 sc = v; 859 control = bus_space_read_4(sc->iot, sc->aud_ioh, 860 ICH_GCTRL + sc->sc_modem_offset); 861 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 862 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 863 } else { 864 control &= ~ICH_ACLSO; 865 control |= ICH_GIE; 866 } 867 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 868 bus_space_write_4(sc->iot, sc->aud_ioh, 869 ICH_GCTRL + sc->sc_modem_offset, control); 870 871 for (i = 500000; i >= 0; i--) { 872 status = bus_space_read_4(sc->iot, sc->aud_ioh, 873 ICH_GSTS + sc->sc_modem_offset); 874 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 875 break; 876 DELAY(1); 877 } 878 if (i <= 0) { 879 aprint_error_dev(sc->sc_dev, "auich_reset_codec: time out\n"); 880 return ETIMEDOUT; 881 } 882 #ifdef AUICH_DEBUG 883 if (status & ICH_SCR) 884 printf("%s: The 2nd codec is ready.\n", 885 device_xname(sc->sc_dev)); 886 if (status & ICH_S2CR) 887 printf("%s: The 3rd codec is ready.\n", 888 device_xname(sc->sc_dev)); 889 #endif 890 return 0; 891 } 892 893 static enum ac97_host_flags 894 auich_flags_codec(void *v) 895 { 896 struct auich_softc *sc = v; 897 return sc->sc_codecflags; 898 } 899 900 static void 901 auich_spdif_event(void *addr, bool flag) 902 { 903 struct auich_softc *sc; 904 905 sc = addr; 906 sc->sc_spdif = flag; 907 } 908 909 static int 910 auich_open(void *addr, int flags) 911 { 912 struct auich_softc *sc; 913 914 sc = (struct auich_softc *)addr; 915 sc->codec_if->vtbl->lock(sc->codec_if); 916 return 0; 917 } 918 919 static void 920 auich_close(void *addr) 921 { 922 struct auich_softc *sc; 923 924 sc = (struct auich_softc *)addr; 925 sc->codec_if->vtbl->unlock(sc->codec_if); 926 } 927 928 static int 929 auich_query_encoding(void *v, struct audio_encoding *aep) 930 { 931 struct auich_softc *sc; 932 933 sc = (struct auich_softc *)v; 934 return auconv_query_encoding( 935 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 936 } 937 938 static int 939 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 940 { 941 int ret; 942 u_int ratetmp; 943 944 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 945 ratetmp = srate; 946 if (mode == AUMODE_RECORD) 947 return sc->codec_if->vtbl->set_rate(sc->codec_if, 948 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 949 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 950 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 951 if (ret) 952 return ret; 953 ratetmp = srate; 954 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 955 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 956 if (ret) 957 return ret; 958 ratetmp = srate; 959 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 960 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 961 return ret; 962 } 963 964 static int 965 auich_set_params(void *v, int setmode, int usemode, 966 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 967 stream_filter_list_t *rfil) 968 { 969 struct auich_softc *sc; 970 audio_params_t *p; 971 stream_filter_list_t *fil; 972 int mode, index; 973 uint32_t control; 974 975 sc = v; 976 for (mode = AUMODE_RECORD; mode != -1; 977 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 978 if ((setmode & mode) == 0) 979 continue; 980 981 p = mode == AUMODE_PLAY ? play : rec; 982 fil = mode == AUMODE_PLAY ? pfil : rfil; 983 if (p == NULL) 984 continue; 985 986 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 987 if (p->sample_rate < 8000 || 988 p->sample_rate > 48000) 989 return EINVAL; 990 991 if (!sc->sc_spdif) 992 index = auconv_set_converter(sc->sc_audio_formats, 993 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 994 else 995 index = auconv_set_converter(auich_spdif_formats, 996 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 997 } else { 998 if (p->sample_rate != 8000 && p->sample_rate != 16000) 999 return EINVAL; 1000 index = auconv_set_converter(sc->sc_modem_formats, 1001 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1002 } 1003 if (index < 0) 1004 return EINVAL; 1005 if (fil->req_size > 0) 1006 p = &fil->filters[0].param; 1007 /* p represents HW encoding */ 1008 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1009 if (sc->sc_audio_formats[index].frequency_type != 1 1010 && auich_set_rate(sc, mode, p->sample_rate)) 1011 return EINVAL; 1012 } else { 1013 if (sc->sc_modem_formats[index].frequency_type != 1 1014 && auich_set_rate(sc, mode, p->sample_rate)) 1015 return EINVAL; 1016 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1017 p->sample_rate); 1018 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1019 } 1020 if (mode == AUMODE_PLAY && 1021 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1022 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1023 ICH_GCTRL + sc->sc_modem_offset); 1024 control &= ~ICH_PCM246_MASK; 1025 if (p->channels == 4) { 1026 control |= ICH_PCM4; 1027 } else if (p->channels == 6) { 1028 control |= ICH_PCM6; 1029 } 1030 bus_space_write_4(sc->iot, sc->aud_ioh, 1031 ICH_GCTRL + sc->sc_modem_offset, control); 1032 } 1033 } 1034 1035 return 0; 1036 } 1037 1038 static int 1039 auich_round_blocksize(void *v, int blk, int mode, 1040 const audio_params_t *param) 1041 { 1042 1043 return blk & ~0x3f; /* keep good alignment */ 1044 } 1045 1046 static void 1047 auich_halt_pipe(struct auich_softc *sc, int pipe) 1048 { 1049 int i; 1050 uint32_t status; 1051 1052 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1053 for (i = 0; i < 100; i++) { 1054 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1055 if (status & ICH_DCH) 1056 break; 1057 DELAY(1); 1058 } 1059 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1060 1061 #if AUICH_DEBUG 1062 if (i > 0) 1063 printf("auich_halt_pipe: halt took %d cycles\n", i); 1064 #endif 1065 } 1066 1067 static int 1068 auich_halt_output(void *v) 1069 { 1070 struct auich_softc *sc; 1071 1072 sc = v; 1073 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", device_xname(sc->sc_dev))); 1074 1075 auich_halt_pipe(sc, ICH_PCMO); 1076 sc->pcmo.intr = NULL; 1077 1078 return 0; 1079 } 1080 1081 static int 1082 auich_halt_input(void *v) 1083 { 1084 struct auich_softc *sc; 1085 1086 sc = v; 1087 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", device_xname(sc->sc_dev))); 1088 1089 auich_halt_pipe(sc, ICH_PCMI); 1090 sc->pcmi.intr = NULL; 1091 1092 return 0; 1093 } 1094 1095 static int 1096 auich_getdev(void *v, struct audio_device *adp) 1097 { 1098 struct auich_softc *sc; 1099 1100 sc = v; 1101 *adp = sc->sc_audev; 1102 return 0; 1103 } 1104 1105 static int 1106 auich_set_port(void *v, mixer_ctrl_t *cp) 1107 { 1108 struct auich_softc *sc; 1109 1110 sc = v; 1111 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1112 } 1113 1114 static int 1115 auich_get_port(void *v, mixer_ctrl_t *cp) 1116 { 1117 struct auich_softc *sc; 1118 1119 sc = v; 1120 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1121 } 1122 1123 static int 1124 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1125 { 1126 struct auich_softc *sc; 1127 1128 sc = v; 1129 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1130 } 1131 1132 static void * 1133 auich_allocm(void *v, int direction, size_t size, 1134 struct malloc_type *pool, int flags) 1135 { 1136 struct auich_softc *sc; 1137 struct auich_dma *p; 1138 int error; 1139 1140 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1141 return NULL; 1142 1143 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1144 if (p == NULL) 1145 return NULL; 1146 1147 sc = v; 1148 error = auich_allocmem(sc, size, 0, p); 1149 if (error) { 1150 free(p, pool); 1151 return NULL; 1152 } 1153 1154 p->next = sc->sc_dmas; 1155 sc->sc_dmas = p; 1156 1157 return KERNADDR(p); 1158 } 1159 1160 static void 1161 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1162 { 1163 struct auich_softc *sc; 1164 struct auich_dma *p, **pp; 1165 1166 sc = v; 1167 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1168 if (KERNADDR(p) == ptr) { 1169 auich_freemem(sc, p); 1170 *pp = p->next; 1171 free(p, pool); 1172 return; 1173 } 1174 } 1175 } 1176 1177 static size_t 1178 auich_round_buffersize(void *v, int direction, size_t size) 1179 { 1180 1181 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1182 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1183 1184 return size; 1185 } 1186 1187 static paddr_t 1188 auich_mappage(void *v, void *mem, off_t off, int prot) 1189 { 1190 struct auich_softc *sc; 1191 struct auich_dma *p; 1192 1193 if (off < 0) 1194 return -1; 1195 sc = v; 1196 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1197 continue; 1198 if (!p) 1199 return -1; 1200 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1201 off, prot, BUS_DMA_WAITOK); 1202 } 1203 1204 static int 1205 auich_get_props(void *v) 1206 { 1207 struct auich_softc *sc; 1208 int props; 1209 1210 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1211 sc = v; 1212 /* 1213 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1214 * rate because of aurateconv. Applications can't know what rate the 1215 * device can process in the case of mmap(). 1216 */ 1217 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1218 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1219 props |= AUDIO_PROP_MMAP; 1220 return props; 1221 } 1222 1223 static int 1224 auich_intr(void *v) 1225 { 1226 struct auich_softc *sc; 1227 int ret, gsts; 1228 #ifdef DIAGNOSTIC 1229 int csts; 1230 #endif 1231 1232 sc = v; 1233 1234 if (!device_has_power(sc->sc_dev)) 1235 return (0); 1236 1237 ret = 0; 1238 #ifdef DIAGNOSTIC 1239 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1240 if (csts & PCI_STATUS_MASTER_ABORT) { 1241 printf("auich_intr: PCI master abort\n"); 1242 } 1243 #endif 1244 1245 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1246 ICH_GSTS + sc->sc_modem_offset); 1247 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1248 1249 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1250 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1251 int sts; 1252 1253 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1254 ICH_PCMO + sc->sc_sts_reg); 1255 DPRINTF(ICH_DEBUG_INTR, 1256 ("auich_intr: osts=0x%x\n", sts)); 1257 1258 if (sts & ICH_FIFOE) 1259 printf("%s: fifo underrun\n", device_xname(sc->sc_dev)); 1260 1261 if (sts & ICH_BCIS) 1262 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1263 1264 /* int ack */ 1265 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1266 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1267 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1268 bus_space_write_4(sc->iot, sc->aud_ioh, 1269 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1270 else 1271 bus_space_write_4(sc->iot, sc->aud_ioh, 1272 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1273 ret++; 1274 } 1275 1276 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1277 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1278 int sts; 1279 1280 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1281 ICH_PCMI + sc->sc_sts_reg); 1282 DPRINTF(ICH_DEBUG_INTR, 1283 ("auich_intr: ists=0x%x\n", sts)); 1284 1285 if (sts & ICH_FIFOE) 1286 printf("%s: fifo overrun\n", device_xname(sc->sc_dev)); 1287 1288 if (sts & ICH_BCIS) 1289 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1290 1291 /* int ack */ 1292 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1293 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1294 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1295 bus_space_write_4(sc->iot, sc->aud_ioh, 1296 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1297 else 1298 bus_space_write_4(sc->iot, sc->aud_ioh, 1299 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1300 ret++; 1301 } 1302 1303 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1304 int sts; 1305 1306 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1307 ICH_MICI + sc->sc_sts_reg); 1308 DPRINTF(ICH_DEBUG_INTR, 1309 ("auich_intr: ists=0x%x\n", sts)); 1310 1311 if (sts & ICH_FIFOE) 1312 printf("%s: fifo overrun\n", device_xname(sc->sc_dev)); 1313 1314 if (sts & ICH_BCIS) 1315 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1316 1317 /* int ack */ 1318 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1319 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1320 bus_space_write_4(sc->iot, sc->aud_ioh, 1321 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1322 ret++; 1323 } 1324 1325 #ifdef AUICH_MODEM_DEBUG 1326 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1327 printf("%s: gsts=0x%x\n", device_xname(sc->sc_dev), gsts); 1328 /* int ack */ 1329 bus_space_write_4(sc->iot, sc->aud_ioh, 1330 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1331 ret++; 1332 } 1333 #endif 1334 1335 return ret; 1336 } 1337 1338 static void 1339 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1340 { 1341 int blksize, qptr; 1342 struct auich_dmalist *q; 1343 1344 blksize = ring->blksize; 1345 1346 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1347 q = &ring->dmalist[qptr]; 1348 q->base = ring->p; 1349 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1350 1351 ring->p += blksize; 1352 if (ring->p >= ring->end) 1353 ring->p = ring->start; 1354 } 1355 ring->qptr = 0; 1356 1357 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1358 (qptr - 1) & ICH_LVI_MASK); 1359 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1360 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1361 } 1362 1363 static void 1364 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1365 { 1366 int blksize, qptr, nqptr; 1367 struct auich_dmalist *q; 1368 1369 blksize = ring->blksize; 1370 qptr = ring->qptr; 1371 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1372 1373 while (qptr != nqptr) { 1374 q = &ring->dmalist[qptr]; 1375 q->base = ring->p; 1376 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1377 1378 DPRINTF(ICH_DEBUG_INTR, 1379 ("auich_intr: %p, %p = %x @ 0x%x\n", 1380 &ring->dmalist[qptr], q, q->len, q->base)); 1381 1382 ring->p += blksize; 1383 if (ring->p >= ring->end) 1384 ring->p = ring->start; 1385 1386 qptr = (qptr + 1) & ICH_LVI_MASK; 1387 if (ring->intr) 1388 ring->intr(ring->arg); 1389 } 1390 ring->qptr = qptr; 1391 1392 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1393 (qptr - 1) & ICH_LVI_MASK); 1394 } 1395 1396 static int 1397 auich_trigger_output(void *v, void *start, void *end, int blksize, 1398 void (*intr)(void *), void *arg, const audio_params_t *param) 1399 { 1400 struct auich_softc *sc; 1401 struct auich_dma *p; 1402 size_t size; 1403 1404 DPRINTF(ICH_DEBUG_DMA, 1405 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1406 start, end, blksize, intr, arg, param)); 1407 sc = v; 1408 1409 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1410 continue; 1411 if (!p) { 1412 printf("auich_trigger_output: bad addr %p\n", start); 1413 return EINVAL; 1414 } 1415 1416 size = (size_t)((char *)end - (char *)start); 1417 1418 sc->pcmo.intr = intr; 1419 sc->pcmo.arg = arg; 1420 sc->pcmo.start = DMAADDR(p); 1421 sc->pcmo.p = sc->pcmo.start; 1422 sc->pcmo.end = sc->pcmo.start + size; 1423 sc->pcmo.blksize = blksize; 1424 1425 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1426 sc->sc_cddma + ICH_PCMO_OFF(0)); 1427 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1428 1429 return 0; 1430 } 1431 1432 static int 1433 auich_trigger_input(void *v, void *start, void *end, int blksize, 1434 void (*intr)(void *), void *arg, const audio_params_t *param) 1435 { 1436 struct auich_softc *sc; 1437 struct auich_dma *p; 1438 size_t size; 1439 1440 DPRINTF(ICH_DEBUG_DMA, 1441 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1442 start, end, blksize, intr, arg, param)); 1443 sc = v; 1444 1445 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1446 continue; 1447 if (!p) { 1448 printf("auich_trigger_input: bad addr %p\n", start); 1449 return EINVAL; 1450 } 1451 1452 size = (size_t)((char *)end - (char *)start); 1453 1454 sc->pcmi.intr = intr; 1455 sc->pcmi.arg = arg; 1456 sc->pcmi.start = DMAADDR(p); 1457 sc->pcmi.p = sc->pcmi.start; 1458 sc->pcmi.end = sc->pcmi.start + size; 1459 sc->pcmi.blksize = blksize; 1460 1461 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1462 sc->sc_cddma + ICH_PCMI_OFF(0)); 1463 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1464 1465 return 0; 1466 } 1467 1468 static int 1469 auich_powerstate(void *v, int state) 1470 { 1471 return 0; 1472 } 1473 1474 static int 1475 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1476 struct auich_dma *p) 1477 { 1478 int error; 1479 1480 p->size = size; 1481 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1482 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1483 &p->nsegs, BUS_DMA_NOWAIT); 1484 if (error) 1485 return error; 1486 1487 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1488 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1489 if (error) 1490 goto free; 1491 1492 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1493 0, BUS_DMA_NOWAIT, &p->map); 1494 if (error) 1495 goto unmap; 1496 1497 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1498 BUS_DMA_NOWAIT); 1499 if (error) 1500 goto destroy; 1501 return 0; 1502 1503 destroy: 1504 bus_dmamap_destroy(sc->dmat, p->map); 1505 unmap: 1506 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1507 free: 1508 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1509 return error; 1510 } 1511 1512 static int 1513 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1514 { 1515 1516 bus_dmamap_unload(sc->dmat, p->map); 1517 bus_dmamap_destroy(sc->dmat, p->map); 1518 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1519 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1520 return 0; 1521 } 1522 1523 static int 1524 auich_alloc_cdata(struct auich_softc *sc) 1525 { 1526 bus_dma_segment_t seg; 1527 int error, rseg; 1528 1529 /* 1530 * Allocate the control data structure, and create and load the 1531 * DMA map for it. 1532 */ 1533 if ((error = bus_dmamem_alloc(sc->dmat, 1534 sizeof(struct auich_cdata), 1535 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1536 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", error); 1537 goto fail_0; 1538 } 1539 1540 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1541 sizeof(struct auich_cdata), 1542 (void **) &sc->sc_cdata, 1543 sc->sc_dmamap_flags)) != 0) { 1544 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", error); 1545 goto fail_1; 1546 } 1547 1548 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1549 sizeof(struct auich_cdata), 0, 0, 1550 &sc->sc_cddmamap)) != 0) { 1551 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1552 "error = %d\n", error); 1553 goto fail_2; 1554 } 1555 1556 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1557 sc->sc_cdata, sizeof(struct auich_cdata), 1558 NULL, 0)) != 0) { 1559 aprint_error_dev(sc->sc_dev, "unable tp load control data DMA map, " 1560 "error = %d\n", error); 1561 goto fail_3; 1562 } 1563 1564 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1565 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1566 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1567 1568 return 0; 1569 1570 fail_3: 1571 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1572 fail_2: 1573 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1574 sizeof(struct auich_cdata)); 1575 fail_1: 1576 bus_dmamem_free(sc->dmat, &seg, rseg); 1577 fail_0: 1578 return error; 1579 } 1580 1581 static bool 1582 auich_resume(device_t dv PMF_FN_ARGS) 1583 { 1584 struct auich_softc *sc = device_private(dv); 1585 pcireg_t v; 1586 1587 if (sc->sc_native_mode) { 1588 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG); 1589 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG, 1590 v | ICH_CFG_IOSE); 1591 } 1592 1593 auich_reset_codec(sc); 1594 DELAY(1000); 1595 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1596 1597 return true; 1598 } 1599 1600 /* 1601 * Calibrate card (some boards are overclocked and need scaling) 1602 */ 1603 static void 1604 auich_calibrate(struct auich_softc *sc) 1605 { 1606 struct timeval t1, t2; 1607 uint8_t ociv, nciv; 1608 uint64_t wait_us; 1609 uint32_t actual_48k_rate, bytes, ac97rate; 1610 void *temp_buffer; 1611 struct auich_dma *p; 1612 u_int rate; 1613 1614 /* 1615 * Grab audio from input for fixed interval and compare how 1616 * much we actually get with what we expect. Interval needs 1617 * to be sufficiently short that no interrupts are 1618 * generated. 1619 */ 1620 1621 /* Force the codec to a known state first. */ 1622 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1623 rate = sc->sc_ac97_clock = 48000; 1624 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1625 &rate); 1626 1627 /* Setup a buffer */ 1628 bytes = 64000; 1629 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1630 1631 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1632 continue; 1633 if (p == NULL) { 1634 printf("auich_calibrate: bad address %p\n", temp_buffer); 1635 return; 1636 } 1637 sc->pcmi.dmalist[0].base = DMAADDR(p); 1638 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1639 1640 /* 1641 * our data format is stereo, 16 bit so each sample is 4 bytes. 1642 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1643 * we're going to start recording with interrupts disabled and measure 1644 * the time taken for one block to complete. we know the block size, 1645 * we know the time in microseconds, we calculate the sample rate: 1646 * 1647 * actual_rate [bps] = bytes / (time [s] * 4) 1648 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1649 * actual_rate [Hz] = (bytes * 250000) / time [us] 1650 */ 1651 1652 /* prepare */ 1653 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1654 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1655 sc->sc_cddma + ICH_PCMI_OFF(0)); 1656 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1657 (0 - 1) & ICH_LVI_MASK); 1658 1659 /* start */ 1660 microtime(&t1); 1661 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1662 1663 /* wait */ 1664 nciv = ociv; 1665 do { 1666 microtime(&t2); 1667 if (t2.tv_sec - t1.tv_sec > 1) 1668 break; 1669 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1670 ICH_PCMI + ICH_CIV); 1671 } while (nciv == ociv); 1672 microtime(&t2); 1673 1674 /* stop */ 1675 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1676 1677 /* reset */ 1678 DELAY(100); 1679 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1680 1681 /* turn time delta into us */ 1682 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1683 1684 auich_freem(sc, temp_buffer, M_DEVBUF); 1685 1686 if (nciv == ociv) { 1687 printf("%s: ac97 link rate calibration timed out after %" 1688 PRIu64 " us\n", device_xname(sc->sc_dev), wait_us); 1689 return; 1690 } 1691 1692 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1693 1694 if (actual_48k_rate < 50000) 1695 ac97rate = 48000; 1696 else 1697 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1698 1699 printf("%s: measured ac97 link rate at %d Hz", 1700 device_xname(sc->sc_dev), actual_48k_rate); 1701 if (ac97rate != actual_48k_rate) 1702 printf(", will use %d Hz", ac97rate); 1703 printf("\n"); 1704 1705 sc->sc_ac97_clock = ac97rate; 1706 } 1707 1708 static void 1709 auich_clear_cas(struct auich_softc *sc) 1710 { 1711 /* Clear the codec access semaphore */ 1712 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1713 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1714 1715 return; 1716 } 1717