1 /* $NetBSD: auich.c,v 1.148 2015/05/24 22:03:02 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 2000 Michael Shalayeff 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 51 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 52 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 53 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 55 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 56 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 57 * THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 60 */ 61 62 /* 63 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 64 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 77 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 79 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 82 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 83 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 84 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 85 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 86 * SUCH DAMAGE. 87 * 88 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 89 */ 90 91 92 /* #define AUICH_DEBUG */ 93 /* 94 * AC'97 audio found on Intel 810/820/440MX chipsets. 95 * http://developer.intel.com/design/chipsets/datashts/290655.htm 96 * http://developer.intel.com/design/chipsets/manuals/298028.htm 97 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 98 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 99 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 100 * AMD8111: 101 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 102 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 103 * 104 * TODO: 105 * - Add support for the dedicated microphone input. 106 * 107 * NOTE: 108 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 109 * It causes PCI master abort and hangups until cold reboot. 110 * http://www.intel.com/design/chipsets/specupdt/245051.htm 111 */ 112 113 #include <sys/cdefs.h> 114 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.148 2015/05/24 22:03:02 christos Exp $"); 115 116 #include <sys/param.h> 117 #include <sys/systm.h> 118 #include <sys/kernel.h> 119 #include <sys/kmem.h> 120 #include <sys/device.h> 121 #include <sys/fcntl.h> 122 #include <sys/proc.h> 123 #include <sys/sysctl.h> 124 #include <sys/audioio.h> 125 #include <sys/bus.h> 126 #include <sys/rndsource.h> 127 128 #include <dev/pci/pcidevs.h> 129 #include <dev/pci/pcivar.h> 130 #include <dev/pci/auichreg.h> 131 132 #include <dev/audio_if.h> 133 #include <dev/mulaw.h> 134 #include <dev/auconv.h> 135 136 #include <dev/ic/ac97reg.h> 137 #include <dev/ic/ac97var.h> 138 139 struct auich_dma { 140 bus_dmamap_t map; 141 void *addr; 142 bus_dma_segment_t segs[1]; 143 int nsegs; 144 size_t size; 145 struct auich_dma *next; 146 }; 147 148 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 149 #define KERNADDR(p) ((void *)((p)->addr)) 150 151 struct auich_cdata { 152 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 153 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 154 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 155 }; 156 157 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 158 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 159 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 160 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 161 162 struct auich_softc { 163 device_t sc_dev; 164 void *sc_ih; 165 kmutex_t sc_lock; 166 kmutex_t sc_intr_lock; 167 168 device_t sc_audiodev; 169 audio_device_t sc_audev; 170 171 pci_chipset_tag_t sc_pc; 172 pcitag_t sc_pt; 173 bus_space_tag_t iot; 174 bus_space_handle_t mix_ioh; 175 bus_size_t mix_size; 176 bus_space_handle_t aud_ioh; 177 bus_size_t aud_size; 178 bus_dma_tag_t dmat; 179 pci_intr_handle_t intrh; 180 181 struct ac97_codec_if *codec_if; 182 struct ac97_host_if host_if; 183 int sc_codecnum; 184 int sc_codectype; 185 int sc_fixedrate; 186 enum ac97_host_flags sc_codecflags; 187 bool sc_spdif; 188 189 /* multi-channel control bits */ 190 int sc_pcm246_mask; 191 int sc_pcm2; 192 int sc_pcm4; 193 int sc_pcm6; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 /* flags */ 220 int sc_iose :1, 221 :31; 222 223 /* sysctl */ 224 struct sysctllog *sc_log; 225 uint32_t sc_ac97_clock; 226 int sc_ac97_clock_mib; 227 228 int sc_modem_offset; 229 230 #define AUICH_AUDIO_NFORMATS 3 231 #define AUICH_MODEM_NFORMATS 1 232 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 233 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 234 struct audio_encoding_set *sc_encodings; 235 struct audio_encoding_set *sc_spdif_encodings; 236 237 int sc_cas_been_used; 238 }; 239 240 /* Debug */ 241 #ifdef AUICH_DEBUG 242 #define DPRINTF(l,x) do { if (auich_debug & (l)) aprint_normal_dev x; } while(0) 243 int auich_debug = 0xfffe; 244 #define ICH_DEBUG_CODECIO 0x0001 245 #define ICH_DEBUG_DMA 0x0002 246 #define ICH_DEBUG_INTR 0x0004 247 #else 248 #define DPRINTF(x,y) /* nothing */ 249 #endif 250 251 static int auich_match(device_t, cfdata_t, void *); 252 static void auich_attach(device_t, device_t, void *); 253 static int auich_detach(device_t, int); 254 static void auich_childdet(device_t, device_t); 255 static int auich_intr(void *); 256 257 CFATTACH_DECL2_NEW(auich, sizeof(struct auich_softc), 258 auich_match, auich_attach, auich_detach, NULL, NULL, auich_childdet); 259 260 static int auich_open(void *, int); 261 static void auich_close(void *); 262 static int auich_query_encoding(void *, struct audio_encoding *); 263 static int auich_set_params(void *, int, int, audio_params_t *, 264 audio_params_t *, stream_filter_list_t *, 265 stream_filter_list_t *); 266 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 267 static void auich_halt_pipe(struct auich_softc *, int); 268 static int auich_halt_output(void *); 269 static int auich_halt_input(void *); 270 static int auich_getdev(void *, struct audio_device *); 271 static int auich_set_port(void *, mixer_ctrl_t *); 272 static int auich_get_port(void *, mixer_ctrl_t *); 273 static int auich_query_devinfo(void *, mixer_devinfo_t *); 274 static void *auich_allocm(void *, int, size_t); 275 static void auich_freem(void *, void *, size_t); 276 static size_t auich_round_buffersize(void *, int, size_t); 277 static paddr_t auich_mappage(void *, void *, off_t, int); 278 static int auich_get_props(void *); 279 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 280 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 281 static int auich_trigger_output(void *, void *, void *, int, 282 void (*)(void *), void *, const audio_params_t *); 283 static int auich_trigger_input(void *, void *, void *, int, 284 void (*)(void *), void *, const audio_params_t *); 285 static void auich_get_locks(void *, kmutex_t **, kmutex_t **); 286 287 static int auich_alloc_cdata(struct auich_softc *); 288 289 static int auich_allocmem(struct auich_softc *, size_t, size_t, 290 struct auich_dma *); 291 static int auich_freemem(struct auich_softc *, struct auich_dma *); 292 293 static bool auich_resume(device_t, const pmf_qual_t *); 294 static int auich_set_rate(struct auich_softc *, int, u_long); 295 static int auich_sysctl_verify(SYSCTLFN_ARGS); 296 static void auich_finish_attach(device_t); 297 static void auich_calibrate(struct auich_softc *); 298 static void auich_clear_cas(struct auich_softc *); 299 300 static int auich_attach_codec(void *, struct ac97_codec_if *); 301 static int auich_read_codec(void *, uint8_t, uint16_t *); 302 static int auich_write_codec(void *, uint8_t, uint16_t); 303 static int auich_reset_codec(void *); 304 static enum ac97_host_flags auich_flags_codec(void *); 305 static void auich_spdif_event(void *, bool); 306 307 static const struct audio_hw_if auich_hw_if = { 308 auich_open, 309 auich_close, 310 NULL, /* drain */ 311 auich_query_encoding, 312 auich_set_params, 313 auich_round_blocksize, 314 NULL, /* commit_setting */ 315 NULL, /* init_output */ 316 NULL, /* init_input */ 317 NULL, /* start_output */ 318 NULL, /* start_input */ 319 auich_halt_output, 320 auich_halt_input, 321 NULL, /* speaker_ctl */ 322 auich_getdev, 323 NULL, /* getfd */ 324 auich_set_port, 325 auich_get_port, 326 auich_query_devinfo, 327 auich_allocm, 328 auich_freem, 329 auich_round_buffersize, 330 auich_mappage, 331 auich_get_props, 332 auich_trigger_output, 333 auich_trigger_input, 334 NULL, /* dev_ioctl */ 335 auich_get_locks, 336 }; 337 338 #define AUICH_FORMATS_1CH 0 339 #define AUICH_FORMATS_4CH 1 340 #define AUICH_FORMATS_6CH 2 341 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 342 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 343 2, AUFMT_STEREO, 0, {8000, 48000}}, 344 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 345 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 346 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 347 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 348 }; 349 350 #define AUICH_SPDIF_NFORMATS 1 351 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 352 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 353 2, AUFMT_STEREO, 1, {48000}}, 354 }; 355 356 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 357 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 358 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 359 }; 360 361 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 362 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 363 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 364 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 365 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 366 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 367 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 368 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 369 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 370 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 371 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 372 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 373 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 374 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 375 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 376 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 377 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 378 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 379 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 380 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 381 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 382 383 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 384 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 385 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 386 387 struct auich_devtype { 388 pcireg_t id; 389 const char *name; 390 const char *shortname; /* must be less than 11 characters */ 391 }; 392 393 static const struct auich_devtype auich_audio_devices[] = { 394 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 395 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 396 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 397 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 398 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 399 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 400 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 401 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 402 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 403 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 404 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 405 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 406 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 407 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 408 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 409 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 410 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 411 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 412 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 413 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 414 { 0, NULL, NULL }, 415 }; 416 417 static const struct auich_devtype auich_modem_devices[] = { 418 #ifdef AUICH_ATTACH_MODEM 419 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 420 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 421 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 422 #endif 423 { 0, NULL, NULL }, 424 }; 425 426 static const struct auich_devtype * 427 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 428 { 429 const struct auich_devtype *d; 430 431 for (d = auich_devices; d->name != NULL; d++) { 432 if (pa->pa_id == d->id) 433 return d; 434 } 435 436 return NULL; 437 } 438 439 static int 440 auich_match(device_t parent, cfdata_t match, void *aux) 441 { 442 struct pci_attach_args *pa; 443 444 pa = aux; 445 if (auich_lookup(pa, auich_audio_devices) != NULL) 446 return 1; 447 if (auich_lookup(pa, auich_modem_devices) != NULL) 448 return 1; 449 450 return 0; 451 } 452 453 static void 454 auich_attach(device_t parent, device_t self, void *aux) 455 { 456 struct auich_softc *sc = device_private(self); 457 struct pci_attach_args *pa; 458 pcireg_t v, subdev; 459 const char *intrstr; 460 const struct auich_devtype *d; 461 const struct sysctlnode *node, *node_ac97clock; 462 int err, node_mib, i; 463 char intrbuf[PCI_INTRSTR_LEN]; 464 465 sc->sc_dev = self; 466 pa = aux; 467 468 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 469 sc->sc_modem_offset = 0x10; 470 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 471 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 472 sc->sc_modem_offset = 0; 473 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 474 } else 475 panic("auich_attach: impossible"); 476 477 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 478 aprint_naive(": Audio controller\n"); 479 else 480 aprint_naive(": Modem controller\n"); 481 482 sc->sc_pc = pa->pa_pc; 483 sc->sc_pt = pa->pa_tag; 484 485 aprint_normal(": %s\n", d->name); 486 487 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 488 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 489 || d->id == PCIID_ICH4MODEM) { 490 /* 491 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 492 */ 493 494 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 495 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 496 goto retry_map; 497 } 498 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 499 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 500 goto retry_map; 501 } 502 goto map_done; 503 } else 504 goto non_native_map; 505 506 retry_map: 507 sc->sc_iose = 1; 508 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 509 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 510 v | ICH_CFG_IOSE); 511 512 non_native_map: 513 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 514 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 515 aprint_error_dev(self, "can't map codec i/o space\n"); 516 return; 517 } 518 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 519 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 520 aprint_error_dev(self, "can't map device i/o space\n"); 521 return; 522 } 523 524 map_done: 525 sc->dmat = pa->pa_dmat; 526 527 /* enable bus mastering */ 528 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 529 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 530 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 531 532 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 533 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 534 535 /* Map and establish the interrupt. */ 536 if (pci_intr_map(pa, &sc->intrh)) { 537 aprint_error_dev(self, "can't map interrupt\n"); 538 return; 539 } 540 intrstr = pci_intr_string(pa->pa_pc, sc->intrh, intrbuf, sizeof(intrbuf)); 541 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 542 auich_intr, sc); 543 if (sc->sc_ih == NULL) { 544 aprint_error_dev(self, "can't establish interrupt"); 545 if (intrstr != NULL) 546 aprint_error(" at %s", intrstr); 547 aprint_error("\n"); 548 return; 549 } 550 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 551 552 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 553 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 554 "0x%02x", PCI_REVISION(pa->pa_class)); 555 strlcpy(sc->sc_audev.config, device_xname(self), MAX_AUDIO_DEV_LEN); 556 557 /* SiS 7012 needs special handling */ 558 if (d->id == PCIID_SIS7012) { 559 sc->sc_sts_reg = ICH_PICB; 560 sc->sc_sample_shift = 0; 561 sc->sc_pcm246_mask = ICH_SIS_PCM246_MASK; 562 sc->sc_pcm2 = ICH_SIS_PCM2; 563 sc->sc_pcm4 = ICH_SIS_PCM4; 564 sc->sc_pcm6 = ICH_SIS_PCM6; 565 /* Un-mute output. From Linux. */ 566 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 567 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 568 ICH_SIS_CTL_UNMUTE); 569 } else { 570 sc->sc_sts_reg = ICH_STS; 571 sc->sc_sample_shift = 1; 572 sc->sc_pcm246_mask = ICH_PCM246_MASK; 573 sc->sc_pcm2 = ICH_PCM2; 574 sc->sc_pcm4 = ICH_PCM4; 575 sc->sc_pcm6 = ICH_PCM6; 576 } 577 578 /* Workaround for a 440MX B-stepping erratum */ 579 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 580 if (d->id == PCIID_440MX) { 581 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 582 aprint_normal_dev(self, "DMA bug workaround enabled\n"); 583 } 584 585 /* Set up DMA lists. */ 586 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 587 auich_alloc_cdata(sc); 588 589 DPRINTF(ICH_DEBUG_DMA, (sc->sc_dev, "%s: lists %p %p %p\n", 590 __func__, sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 591 592 /* Modem codecs are always the secondary codec on ICH */ 593 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 594 595 sc->host_if.arg = sc; 596 sc->host_if.attach = auich_attach_codec; 597 sc->host_if.read = auich_read_codec; 598 sc->host_if.write = auich_write_codec; 599 sc->host_if.reset = auich_reset_codec; 600 sc->host_if.flags = auich_flags_codec; 601 sc->host_if.spdif_event = auich_spdif_event; 602 603 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 604 switch (subdev) { 605 case 0x202f161f: /* Gateway 7326GZ */ 606 case 0x203a161f: /* Gateway 4028GZ */ 607 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 608 case 0x8144104d: /* Sony VAIO PCG-TR* */ 609 case 0x8197104d: /* Sony S1XP */ 610 case 0x81c0104d: /* Sony VAIO type T */ 611 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 612 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 613 break; 614 default: 615 sc->sc_codecflags = 0; 616 break; 617 } 618 619 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype, 620 &sc->sc_lock) != 0) 621 return; 622 623 mutex_enter(&sc->sc_lock); 624 sc->codec_if->vtbl->unlock(sc->codec_if); 625 sc->sc_fixedrate = AC97_IS_FIXED_RATE(sc->codec_if); 626 627 /* setup audio_format */ 628 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 629 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 630 if (!AC97_IS_4CH(sc->codec_if)) 631 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 632 if (!AC97_IS_6CH(sc->codec_if)) 633 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 634 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 635 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 636 sc->sc_audio_formats[i].frequency_type = 1; 637 sc->sc_audio_formats[i].frequency[0] = 48000; 638 } 639 } 640 mutex_exit(&sc->sc_lock); 641 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 642 &sc->sc_encodings)) 643 return; 644 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 645 &sc->sc_spdif_encodings)) 646 return; 647 } else { 648 mutex_exit(&sc->sc_lock); 649 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 650 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 651 &sc->sc_encodings)) 652 return; 653 } 654 655 /* Watch for power change */ 656 if (!pmf_device_register(self, NULL, auich_resume)) 657 aprint_error_dev(self, "couldn't establish power handler\n"); 658 659 config_interrupts(self, auich_finish_attach); 660 661 /* sysctl setup */ 662 if (sc->sc_fixedrate && sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 663 return; 664 665 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 666 CTLTYPE_NODE, device_xname(self), NULL, NULL, 0, 667 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 668 if (err != 0) 669 goto sysctl_err; 670 node_mib = node->sysctl_num; 671 672 if (!sc->sc_fixedrate) { 673 /* passing the sc address instead of &sc->sc_ac97_clock */ 674 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 675 CTLFLAG_READWRITE, 676 CTLTYPE_INT, "ac97rate", 677 SYSCTL_DESCR("AC'97 codec link rate"), 678 auich_sysctl_verify, 0, (void *)sc, 0, 679 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 680 if (err != 0) 681 goto sysctl_err; 682 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 683 } 684 685 return; 686 687 sysctl_err: 688 aprint_error_dev(self, "failed to add sysctl nodes. (%d)\n", err); 689 return; /* failure of sysctl is not fatal. */ 690 } 691 692 static void 693 auich_childdet(device_t self, device_t child) 694 { 695 struct auich_softc *sc = device_private(self); 696 697 KASSERT(sc->sc_audiodev == child); 698 sc->sc_audiodev = NULL; 699 } 700 701 static int 702 auich_detach(device_t self, int flags) 703 { 704 struct auich_softc *sc = device_private(self); 705 706 /* audio */ 707 if (sc->sc_audiodev != NULL) 708 config_detach(sc->sc_audiodev, flags); 709 710 /* sysctl */ 711 sysctl_teardown(&sc->sc_log); 712 713 mutex_enter(&sc->sc_lock); 714 715 /* audio_encoding_set */ 716 auconv_delete_encodings(sc->sc_encodings); 717 auconv_delete_encodings(sc->sc_spdif_encodings); 718 719 /* ac97 */ 720 if (sc->codec_if != NULL) 721 sc->codec_if->vtbl->detach(sc->codec_if); 722 723 mutex_exit(&sc->sc_lock); 724 mutex_destroy(&sc->sc_lock); 725 mutex_destroy(&sc->sc_intr_lock); 726 727 /* PCI */ 728 if (sc->sc_ih != NULL) 729 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 730 if (sc->mix_size != 0) 731 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 732 if (sc->aud_size != 0) 733 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 734 return 0; 735 } 736 737 static int 738 auich_sysctl_verify(SYSCTLFN_ARGS) 739 { 740 int error, tmp; 741 struct sysctlnode node; 742 struct auich_softc *sc; 743 744 node = *rnode; 745 sc = rnode->sysctl_data; 746 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 747 tmp = sc->sc_ac97_clock; 748 node.sysctl_data = &tmp; 749 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 750 if (error || newp == NULL) 751 return error; 752 753 if (tmp < 48000 || tmp > 96000) 754 return EINVAL; 755 mutex_enter(&sc->sc_lock); 756 sc->sc_ac97_clock = tmp; 757 mutex_exit(&sc->sc_lock); 758 } 759 760 return 0; 761 } 762 763 static void 764 auich_finish_attach(device_t self) 765 { 766 struct auich_softc *sc = device_private(self); 767 768 mutex_enter(&sc->sc_lock); 769 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 770 auich_calibrate(sc); 771 mutex_exit(&sc->sc_lock); 772 773 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, sc->sc_dev); 774 775 return; 776 } 777 778 #define ICH_CODECIO_INTERVAL 10 779 static int 780 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 781 { 782 struct auich_softc *sc; 783 int i; 784 uint32_t status; 785 786 sc = v; 787 /* wait for an access semaphore */ 788 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 789 bus_space_read_1(sc->iot, sc->aud_ioh, 790 ICH_CAS + sc->sc_modem_offset) & 1; 791 DELAY(ICH_CODECIO_INTERVAL)); 792 793 /* 794 * Be permissive in first attempt. If previous instances of 795 * this routine were interrupted precisely at this point (after 796 * access is granted by CAS but before a command is sent), 797 * they could have left hardware in an inconsistent state where 798 * a command is expected and therefore semaphore wait would hit 799 * the timeout. 800 */ 801 if (!sc->sc_cas_been_used && i <= 0) 802 i = 1; 803 sc->sc_cas_been_used = 1; 804 805 if (i > 0) { 806 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 807 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 808 DPRINTF(ICH_DEBUG_CODECIO, 809 (sc->sc_dev, "%s(%x, %x)\n", __func__, reg, *val)); 810 status = bus_space_read_4(sc->iot, sc->aud_ioh, 811 ICH_GSTS + sc->sc_modem_offset); 812 if (status & ICH_RCS) { 813 bus_space_write_4(sc->iot, sc->aud_ioh, 814 ICH_GSTS + sc->sc_modem_offset, 815 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 816 *val = 0xffff; 817 DPRINTF(ICH_DEBUG_CODECIO, 818 (sc->sc_dev, "%s: read_codec error\n", __func__)); 819 if (reg == AC97_REG_GPIO_STATUS) 820 auich_clear_cas(sc); 821 return -1; 822 } 823 if (reg == AC97_REG_GPIO_STATUS) 824 auich_clear_cas(sc); 825 return 0; 826 } else { 827 aprint_normal_dev(sc->sc_dev, "read_codec timeout\n"); 828 if (reg == AC97_REG_GPIO_STATUS) 829 auich_clear_cas(sc); 830 return -1; 831 } 832 } 833 834 static int 835 auich_write_codec(void *v, uint8_t reg, uint16_t val) 836 { 837 struct auich_softc *sc; 838 int i; 839 840 sc = v; 841 DPRINTF(ICH_DEBUG_CODECIO, (sc->sc_dev, "%s(%x, %x)\n", 842 __func__, reg, val)); 843 /* wait for an access semaphore */ 844 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 845 bus_space_read_1(sc->iot, sc->aud_ioh, 846 ICH_CAS + sc->sc_modem_offset) & 1; 847 DELAY(ICH_CODECIO_INTERVAL)); 848 849 /* Be permissive in first attempt (see comments in auich_read_codec) */ 850 if (!sc->sc_cas_been_used && i <= 0) 851 i = 1; 852 sc->sc_cas_been_used = 1; 853 854 if (i > 0) { 855 bus_space_write_2(sc->iot, sc->mix_ioh, 856 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 857 return 0; 858 } else { 859 aprint_normal_dev(sc->sc_dev, "write_codec timeout\n"); 860 return -1; 861 } 862 } 863 864 static int 865 auich_attach_codec(void *v, struct ac97_codec_if *cif) 866 { 867 struct auich_softc *sc; 868 869 sc = v; 870 sc->codec_if = cif; 871 872 return 0; 873 } 874 875 static int 876 auich_reset_codec(void *v) 877 { 878 struct auich_softc *sc; 879 int i; 880 uint32_t control, status; 881 882 sc = v; 883 control = bus_space_read_4(sc->iot, sc->aud_ioh, 884 ICH_GCTRL + sc->sc_modem_offset); 885 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 886 control &= ~(ICH_ACLSO | sc->sc_pcm246_mask); 887 } else { 888 control &= ~ICH_ACLSO; 889 control |= ICH_GIE; 890 } 891 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 892 bus_space_write_4(sc->iot, sc->aud_ioh, 893 ICH_GCTRL + sc->sc_modem_offset, control); 894 895 for (i = 500000; i >= 0; i--) { 896 status = bus_space_read_4(sc->iot, sc->aud_ioh, 897 ICH_GSTS + sc->sc_modem_offset); 898 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 899 break; 900 DELAY(1); 901 } 902 if (i <= 0) { 903 aprint_error_dev(sc->sc_dev, "auich_reset_codec: time out\n"); 904 return ETIMEDOUT; 905 } 906 #ifdef AUICH_DEBUG 907 if (status & ICH_SCR) 908 aprint_normal_dev(sc->sc_dev, "The 2nd codec is ready.\n"); 909 if (status & ICH_S2CR) 910 aprint_normal_dev(sc->sc_dev, "The 3rd codec is ready.\n"); 911 #endif 912 return 0; 913 } 914 915 static enum ac97_host_flags 916 auich_flags_codec(void *v) 917 { 918 struct auich_softc *sc = v; 919 return sc->sc_codecflags; 920 } 921 922 static void 923 auich_spdif_event(void *addr, bool flag) 924 { 925 struct auich_softc *sc; 926 927 sc = addr; 928 sc->sc_spdif = flag; 929 } 930 931 static int 932 auich_open(void *addr, int flags) 933 { 934 struct auich_softc *sc; 935 936 sc = (struct auich_softc *)addr; 937 mutex_spin_exit(&sc->sc_intr_lock); 938 sc->codec_if->vtbl->lock(sc->codec_if); 939 mutex_spin_enter(&sc->sc_intr_lock); 940 return 0; 941 } 942 943 static void 944 auich_close(void *addr) 945 { 946 struct auich_softc *sc; 947 948 sc = (struct auich_softc *)addr; 949 mutex_spin_exit(&sc->sc_intr_lock); 950 sc->codec_if->vtbl->unlock(sc->codec_if); 951 mutex_spin_enter(&sc->sc_intr_lock); 952 } 953 954 static int 955 auich_query_encoding(void *v, struct audio_encoding *aep) 956 { 957 struct auich_softc *sc; 958 959 sc = (struct auich_softc *)v; 960 return auconv_query_encoding( 961 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 962 } 963 964 static int 965 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 966 { 967 int ret; 968 u_int ratetmp; 969 970 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 971 ratetmp = srate; 972 if (mode == AUMODE_RECORD) 973 return sc->codec_if->vtbl->set_rate(sc->codec_if, 974 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 975 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 976 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 977 if (ret) 978 return ret; 979 ratetmp = srate; 980 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 981 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 982 if (ret) 983 return ret; 984 ratetmp = srate; 985 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 986 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 987 return ret; 988 } 989 990 static int 991 auich_set_params(void *v, int setmode, int usemode, 992 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 993 stream_filter_list_t *rfil) 994 { 995 struct auich_softc *sc; 996 audio_params_t *p; 997 stream_filter_list_t *fil; 998 int mode, index; 999 uint32_t control; 1000 1001 sc = v; 1002 for (mode = AUMODE_RECORD; mode != -1; 1003 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1004 if ((setmode & mode) == 0) 1005 continue; 1006 1007 p = mode == AUMODE_PLAY ? play : rec; 1008 fil = mode == AUMODE_PLAY ? pfil : rfil; 1009 if (p == NULL) 1010 continue; 1011 1012 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1013 if (p->sample_rate < 8000 || 1014 p->sample_rate > 48000) 1015 return EINVAL; 1016 1017 if (!sc->sc_spdif) 1018 index = auconv_set_converter(sc->sc_audio_formats, 1019 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 1020 else 1021 index = auconv_set_converter(auich_spdif_formats, 1022 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 1023 } else { 1024 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1025 return EINVAL; 1026 index = auconv_set_converter(sc->sc_modem_formats, 1027 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1028 } 1029 if (index < 0) 1030 return EINVAL; 1031 if (fil->req_size > 0) 1032 p = &fil->filters[0].param; 1033 /* p represents HW encoding */ 1034 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1035 if (sc->sc_audio_formats[index].frequency_type != 1 1036 && auich_set_rate(sc, mode, p->sample_rate)) 1037 return EINVAL; 1038 } else { 1039 if (sc->sc_modem_formats[index].frequency_type != 1 1040 && auich_set_rate(sc, mode, p->sample_rate)) 1041 return EINVAL; 1042 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1043 p->sample_rate); 1044 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1045 } 1046 if (mode == AUMODE_PLAY && 1047 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1048 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1049 ICH_GCTRL + sc->sc_modem_offset); 1050 control &= ~sc->sc_pcm246_mask; 1051 if (p->channels == 4) { 1052 control |= sc->sc_pcm4; 1053 } else if (p->channels == 6) { 1054 control |= sc->sc_pcm6; 1055 } 1056 bus_space_write_4(sc->iot, sc->aud_ioh, 1057 ICH_GCTRL + sc->sc_modem_offset, control); 1058 } 1059 } 1060 1061 return 0; 1062 } 1063 1064 static int 1065 auich_round_blocksize(void *v, int blk, int mode, 1066 const audio_params_t *param) 1067 { 1068 1069 return blk & ~0x3f; /* keep good alignment */ 1070 } 1071 1072 static void 1073 auich_halt_pipe(struct auich_softc *sc, int pipe) 1074 { 1075 int i; 1076 uint32_t status; 1077 1078 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1079 for (i = 0; i < 100; i++) { 1080 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1081 if (status & ICH_DCH) 1082 break; 1083 DELAY(1); 1084 } 1085 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1086 1087 #if AUICH_DEBUG 1088 if (i > 0) 1089 aprint_normal_dev(sc->sc_dev, "%s: halt took %d cycles\n", 1090 __func__, i); 1091 #endif 1092 } 1093 1094 static int 1095 auich_halt_output(void *v) 1096 { 1097 struct auich_softc *sc; 1098 1099 sc = v; 1100 DPRINTF(ICH_DEBUG_DMA, (sc->sc_dev, "%s\n", __func__)); 1101 1102 auich_halt_pipe(sc, ICH_PCMO); 1103 sc->pcmo.intr = NULL; 1104 1105 return 0; 1106 } 1107 1108 static int 1109 auich_halt_input(void *v) 1110 { 1111 struct auich_softc *sc; 1112 1113 sc = v; 1114 DPRINTF(ICH_DEBUG_DMA, (sc->sc_dev, "%s\n", __func__)); 1115 1116 auich_halt_pipe(sc, ICH_PCMI); 1117 sc->pcmi.intr = NULL; 1118 1119 return 0; 1120 } 1121 1122 static int 1123 auich_getdev(void *v, struct audio_device *adp) 1124 { 1125 struct auich_softc *sc; 1126 1127 sc = v; 1128 *adp = sc->sc_audev; 1129 return 0; 1130 } 1131 1132 static int 1133 auich_set_port(void *v, mixer_ctrl_t *cp) 1134 { 1135 struct auich_softc *sc; 1136 1137 sc = v; 1138 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1139 } 1140 1141 static int 1142 auich_get_port(void *v, mixer_ctrl_t *cp) 1143 { 1144 struct auich_softc *sc; 1145 1146 sc = v; 1147 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1148 } 1149 1150 static int 1151 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1152 { 1153 struct auich_softc *sc; 1154 1155 sc = v; 1156 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1157 } 1158 1159 static void * 1160 auich_allocm(void *v, int direction, size_t size) 1161 { 1162 struct auich_softc *sc; 1163 struct auich_dma *p; 1164 int error; 1165 1166 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1167 return NULL; 1168 1169 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1170 if (p == NULL) 1171 return NULL; 1172 1173 sc = v; 1174 error = auich_allocmem(sc, size, 0, p); 1175 if (error) { 1176 kmem_free(p, sizeof(*p)); 1177 return NULL; 1178 } 1179 1180 p->next = sc->sc_dmas; 1181 sc->sc_dmas = p; 1182 1183 return KERNADDR(p); 1184 } 1185 1186 static void 1187 auich_freem(void *v, void *ptr, size_t size) 1188 { 1189 struct auich_softc *sc; 1190 struct auich_dma *p, **pp; 1191 1192 sc = v; 1193 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1194 if (KERNADDR(p) == ptr) { 1195 auich_freemem(sc, p); 1196 *pp = p->next; 1197 kmem_free(p, sizeof(*p)); 1198 return; 1199 } 1200 } 1201 } 1202 1203 static size_t 1204 auich_round_buffersize(void *v, int direction, size_t size) 1205 { 1206 1207 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1208 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1209 1210 return size; 1211 } 1212 1213 static paddr_t 1214 auich_mappage(void *v, void *mem, off_t off, int prot) 1215 { 1216 struct auich_softc *sc; 1217 struct auich_dma *p; 1218 1219 if (off < 0) 1220 return -1; 1221 sc = v; 1222 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1223 continue; 1224 if (!p) 1225 return -1; 1226 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1227 off, prot, BUS_DMA_WAITOK); 1228 } 1229 1230 static int 1231 auich_get_props(void *v) 1232 { 1233 struct auich_softc *sc; 1234 int props; 1235 1236 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1237 sc = v; 1238 /* 1239 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1240 * rate because of aurateconv. Applications can't know what rate the 1241 * device can process in the case of mmap(). 1242 */ 1243 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1244 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1245 props |= AUDIO_PROP_MMAP; 1246 return props; 1247 } 1248 1249 static int 1250 auich_intr(void *v) 1251 { 1252 struct auich_softc *sc; 1253 int ret, gsts; 1254 #ifdef DIAGNOSTIC 1255 int csts; 1256 #endif 1257 1258 sc = v; 1259 1260 if (!device_has_power(sc->sc_dev)) 1261 return (0); 1262 1263 mutex_spin_enter(&sc->sc_intr_lock); 1264 1265 ret = 0; 1266 #ifdef DIAGNOSTIC 1267 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1268 if (csts & PCI_STATUS_MASTER_ABORT) { 1269 aprint_error_dev(sc->sc_dev, "%s: PCI master abort\n", 1270 __func__); 1271 } 1272 #endif 1273 1274 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1275 ICH_GSTS + sc->sc_modem_offset); 1276 DPRINTF(ICH_DEBUG_INTR, (sc->sc_dev, "%s: gsts=0x%x\n", 1277 __func__, gsts)); 1278 1279 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1280 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1281 int sts; 1282 1283 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1284 ICH_PCMO + sc->sc_sts_reg); 1285 DPRINTF(ICH_DEBUG_INTR, 1286 (sc->sc_dev, "%s: osts=0x%x\n", __func__, sts)); 1287 1288 if (sts & ICH_FIFOE) 1289 aprint_error_dev(sc->sc_dev, "%s: fifo underrun\n", 1290 __func__); 1291 1292 if (sts & ICH_BCIS) 1293 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1294 1295 /* int ack */ 1296 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1297 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1298 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1299 bus_space_write_4(sc->iot, sc->aud_ioh, 1300 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1301 else 1302 bus_space_write_4(sc->iot, sc->aud_ioh, 1303 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1304 ret++; 1305 } 1306 1307 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1308 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1309 int sts; 1310 1311 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1312 ICH_PCMI + sc->sc_sts_reg); 1313 DPRINTF(ICH_DEBUG_INTR, 1314 (sc->sc_dev, "%s: ists=0x%x\n", __func__, sts)); 1315 1316 if (sts & ICH_FIFOE) 1317 aprint_error_dev(sc->sc_dev, "%s: fifo overrun\n", 1318 __func__); 1319 1320 if (sts & ICH_BCIS) 1321 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1322 1323 /* int ack */ 1324 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1325 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1326 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1327 bus_space_write_4(sc->iot, sc->aud_ioh, 1328 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1329 else 1330 bus_space_write_4(sc->iot, sc->aud_ioh, 1331 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1332 ret++; 1333 } 1334 1335 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1336 int sts; 1337 1338 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1339 ICH_MICI + sc->sc_sts_reg); 1340 DPRINTF(ICH_DEBUG_INTR, 1341 (sc->sc_dev, "%s: ists=0x%x\n", __func__, sts)); 1342 1343 if (sts & ICH_FIFOE) 1344 aprint_error_dev(sc->sc_dev, "%s: fifo overrun\n", 1345 __func__); 1346 1347 if (sts & ICH_BCIS) 1348 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1349 1350 /* int ack */ 1351 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1352 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1353 bus_space_write_4(sc->iot, sc->aud_ioh, 1354 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1355 ret++; 1356 } 1357 1358 #ifdef AUICH_MODEM_DEBUG 1359 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1360 aprint_normal_dev(sc->sc_dev, "gsts=0x%x\n", gsts); 1361 /* int ack */ 1362 bus_space_write_4(sc->iot, sc->aud_ioh, 1363 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1364 ret++; 1365 } 1366 #endif 1367 1368 mutex_spin_exit(&sc->sc_intr_lock); 1369 1370 return ret; 1371 } 1372 1373 static void 1374 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1375 { 1376 int blksize, qptr; 1377 struct auich_dmalist *q; 1378 1379 blksize = ring->blksize; 1380 1381 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1382 q = &ring->dmalist[qptr]; 1383 q->base = ring->p; 1384 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1385 1386 ring->p += blksize; 1387 if (ring->p >= ring->end) 1388 ring->p = ring->start; 1389 } 1390 ring->qptr = 0; 1391 1392 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1393 (qptr - 1) & ICH_LVI_MASK); 1394 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1395 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1396 } 1397 1398 static void 1399 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1400 { 1401 int blksize, qptr, nqptr; 1402 struct auich_dmalist *q; 1403 1404 blksize = ring->blksize; 1405 qptr = ring->qptr; 1406 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1407 1408 while (qptr != nqptr) { 1409 q = &ring->dmalist[qptr]; 1410 q->base = ring->p; 1411 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1412 1413 DPRINTF(ICH_DEBUG_INTR, 1414 (sc->sc_dev, "%s: %p, %p = %x @ 0x%x\n", __func__, 1415 &ring->dmalist[qptr], q, q->len, q->base)); 1416 1417 ring->p += blksize; 1418 if (ring->p >= ring->end) 1419 ring->p = ring->start; 1420 1421 qptr = (qptr + 1) & ICH_LVI_MASK; 1422 if (ring->intr) 1423 ring->intr(ring->arg); 1424 } 1425 ring->qptr = qptr; 1426 1427 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1428 (qptr - 1) & ICH_LVI_MASK); 1429 } 1430 1431 static int 1432 auich_trigger_output(void *v, void *start, void *end, int blksize, 1433 void (*intr)(void *), void *arg, const audio_params_t *param) 1434 { 1435 struct auich_softc *sc; 1436 struct auich_dma *p; 1437 size_t size; 1438 1439 sc = v; 1440 DPRINTF(ICH_DEBUG_DMA, 1441 (sc->sc_dev, "%s(%p, %p, %d, %p, %p, %p)\n", __func__, 1442 start, end, blksize, intr, arg, param)); 1443 1444 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1445 continue; 1446 if (!p) { 1447 aprint_error_dev(sc->sc_dev, "%s: bad addr %p\n", __func__, 1448 start); 1449 return EINVAL; 1450 } 1451 1452 size = (size_t)((char *)end - (char *)start); 1453 1454 sc->pcmo.intr = intr; 1455 sc->pcmo.arg = arg; 1456 sc->pcmo.start = DMAADDR(p); 1457 sc->pcmo.p = sc->pcmo.start; 1458 sc->pcmo.end = sc->pcmo.start + size; 1459 sc->pcmo.blksize = blksize; 1460 1461 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1462 sc->sc_cddma + ICH_PCMO_OFF(0)); 1463 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1464 1465 return 0; 1466 } 1467 1468 static int 1469 auich_trigger_input(void *v, void *start, void *end, int blksize, 1470 void (*intr)(void *), void *arg, const audio_params_t *param) 1471 { 1472 struct auich_softc *sc; 1473 struct auich_dma *p; 1474 size_t size; 1475 1476 sc = v; 1477 DPRINTF(ICH_DEBUG_DMA, 1478 (sc->sc_dev, "%s(%p, %p, %d, %p, %p, %p)\n", __func__, 1479 start, end, blksize, intr, arg, param)); 1480 1481 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1482 continue; 1483 if (!p) { 1484 aprint_error_dev(sc->sc_dev, "%s: bad addr %p\n", __func__, 1485 start); 1486 return EINVAL; 1487 } 1488 1489 size = (size_t)((char *)end - (char *)start); 1490 1491 sc->pcmi.intr = intr; 1492 sc->pcmi.arg = arg; 1493 sc->pcmi.start = DMAADDR(p); 1494 sc->pcmi.p = sc->pcmi.start; 1495 sc->pcmi.end = sc->pcmi.start + size; 1496 sc->pcmi.blksize = blksize; 1497 1498 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1499 sc->sc_cddma + ICH_PCMI_OFF(0)); 1500 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1501 1502 return 0; 1503 } 1504 1505 static int 1506 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1507 struct auich_dma *p) 1508 { 1509 int error; 1510 1511 p->size = size; 1512 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1513 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1514 &p->nsegs, BUS_DMA_WAITOK); 1515 if (error) 1516 return error; 1517 1518 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1519 &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags); 1520 if (error) 1521 goto free; 1522 1523 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1524 0, BUS_DMA_WAITOK, &p->map); 1525 if (error) 1526 goto unmap; 1527 1528 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1529 BUS_DMA_WAITOK); 1530 if (error) 1531 goto destroy; 1532 return 0; 1533 1534 destroy: 1535 bus_dmamap_destroy(sc->dmat, p->map); 1536 unmap: 1537 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1538 free: 1539 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1540 return error; 1541 } 1542 1543 static int 1544 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1545 { 1546 1547 bus_dmamap_unload(sc->dmat, p->map); 1548 bus_dmamap_destroy(sc->dmat, p->map); 1549 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1550 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1551 return 0; 1552 } 1553 1554 static int 1555 auich_alloc_cdata(struct auich_softc *sc) 1556 { 1557 bus_dma_segment_t seg; 1558 int error, rseg; 1559 1560 /* 1561 * Allocate the control data structure, and create and load the 1562 * DMA map for it. 1563 */ 1564 if ((error = bus_dmamem_alloc(sc->dmat, 1565 sizeof(struct auich_cdata), 1566 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1567 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", error); 1568 goto fail_0; 1569 } 1570 1571 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1572 sizeof(struct auich_cdata), 1573 (void **) &sc->sc_cdata, 1574 sc->sc_dmamap_flags)) != 0) { 1575 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", error); 1576 goto fail_1; 1577 } 1578 1579 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1580 sizeof(struct auich_cdata), 0, 0, 1581 &sc->sc_cddmamap)) != 0) { 1582 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1583 "error = %d\n", error); 1584 goto fail_2; 1585 } 1586 1587 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1588 sc->sc_cdata, sizeof(struct auich_cdata), 1589 NULL, 0)) != 0) { 1590 aprint_error_dev(sc->sc_dev, "unable tp load control data DMA map, " 1591 "error = %d\n", error); 1592 goto fail_3; 1593 } 1594 1595 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1596 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1597 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1598 1599 return 0; 1600 1601 fail_3: 1602 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1603 fail_2: 1604 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1605 sizeof(struct auich_cdata)); 1606 fail_1: 1607 bus_dmamem_free(sc->dmat, &seg, rseg); 1608 fail_0: 1609 return error; 1610 } 1611 1612 static bool 1613 auich_resume(device_t dv, const pmf_qual_t *qual) 1614 { 1615 struct auich_softc *sc = device_private(dv); 1616 pcireg_t v; 1617 1618 mutex_enter(&sc->sc_lock); 1619 mutex_spin_enter(&sc->sc_intr_lock); 1620 1621 if (sc->sc_iose) { 1622 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG); 1623 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG, 1624 v | ICH_CFG_IOSE); 1625 } 1626 1627 auich_reset_codec(sc); 1628 mutex_spin_exit(&sc->sc_intr_lock); 1629 DELAY(1000); 1630 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1631 mutex_exit(&sc->sc_lock); 1632 1633 return true; 1634 } 1635 1636 /* 1637 * Calibrate card (some boards are overclocked and need scaling) 1638 */ 1639 static void 1640 auich_calibrate(struct auich_softc *sc) 1641 { 1642 struct timeval t1, t2; 1643 uint8_t ociv, nciv; 1644 uint64_t wait_us; 1645 uint32_t actual_48k_rate, bytes, ac97rate; 1646 void *temp_buffer; 1647 struct auich_dma *p; 1648 u_int rate; 1649 1650 /* 1651 * Grab audio from input for fixed interval and compare how 1652 * much we actually get with what we expect. Interval needs 1653 * to be sufficiently short that no interrupts are 1654 * generated. 1655 */ 1656 1657 /* Force the codec to a known state first. */ 1658 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1659 rate = sc->sc_ac97_clock = 48000; 1660 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1661 &rate); 1662 1663 /* Setup a buffer */ 1664 bytes = 64000; 1665 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes); 1666 1667 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1668 continue; 1669 if (p == NULL) { 1670 aprint_error_dev(sc->sc_dev, "%s: bad address %p\n", 1671 __func__, temp_buffer); 1672 return; 1673 } 1674 sc->pcmi.dmalist[0].base = DMAADDR(p); 1675 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1676 1677 /* 1678 * our data format is stereo, 16 bit so each sample is 4 bytes. 1679 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1680 * we're going to start recording with interrupts disabled and measure 1681 * the time taken for one block to complete. we know the block size, 1682 * we know the time in microseconds, we calculate the sample rate: 1683 * 1684 * actual_rate [bps] = bytes / (time [s] * 4) 1685 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1686 * actual_rate [Hz] = (bytes * 250000) / time [us] 1687 */ 1688 1689 /* prepare */ 1690 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1691 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1692 sc->sc_cddma + ICH_PCMI_OFF(0)); 1693 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1694 (0 - 1) & ICH_LVI_MASK); 1695 1696 /* start */ 1697 kpreempt_disable(); 1698 microtime(&t1); 1699 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1700 1701 /* wait */ 1702 nciv = ociv; 1703 do { 1704 microtime(&t2); 1705 if (t2.tv_sec - t1.tv_sec > 1) 1706 break; 1707 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1708 ICH_PCMI + ICH_CIV); 1709 } while (nciv == ociv); 1710 microtime(&t2); 1711 1712 /* stop */ 1713 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1714 kpreempt_enable(); 1715 1716 /* reset */ 1717 DELAY(100); 1718 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1719 1720 /* turn time delta into us */ 1721 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1722 1723 auich_freem(sc, temp_buffer, bytes); 1724 1725 if (nciv == ociv) { 1726 aprint_error_dev(sc->sc_dev, "ac97 link rate calibration " 1727 "timed out after %" PRIu64 " us\n", wait_us); 1728 return; 1729 } 1730 1731 if (wait_us == 0) { 1732 /* Can happen with emulated hardware */ 1733 aprint_error_dev(sc->sc_dev, "abnormal zero delay during " 1734 "calibration\n"); 1735 return; 1736 } 1737 1738 rnd_add_data(NULL, &wait_us, sizeof(wait_us), 1); 1739 1740 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1741 1742 if (actual_48k_rate < 50000) 1743 ac97rate = 48000; 1744 else 1745 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1746 1747 aprint_verbose_dev(sc->sc_dev, "measured ac97 link rate at %d Hz", 1748 actual_48k_rate); 1749 if (ac97rate != actual_48k_rate) 1750 aprint_verbose(", will use %d Hz", ac97rate); 1751 aprint_verbose("\n"); 1752 1753 sc->sc_ac97_clock = ac97rate; 1754 } 1755 1756 static void 1757 auich_clear_cas(struct auich_softc *sc) 1758 { 1759 /* Clear the codec access semaphore */ 1760 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1761 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1762 1763 return; 1764 } 1765 1766 static void 1767 auich_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread) 1768 { 1769 struct auich_softc *sc; 1770 1771 sc = addr; 1772 *intr = &sc->sc_intr_lock; 1773 *thread = &sc->sc_lock; 1774 } 1775