1 /* $NetBSD: auich.c,v 1.125 2008/04/10 19:13:36 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.125 2008/04/10 19:13:36 cegger Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <sys/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 void *addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 pci_chipset_tag_t sc_pc; 179 pcitag_t sc_pt; 180 bus_space_tag_t iot; 181 bus_space_handle_t mix_ioh; 182 bus_size_t mix_size; 183 bus_space_handle_t aud_ioh; 184 bus_size_t aud_size; 185 bus_dma_tag_t dmat; 186 pci_intr_handle_t intrh; 187 188 struct ac97_codec_if *codec_if; 189 struct ac97_host_if host_if; 190 int sc_codecnum; 191 int sc_codectype; 192 enum ac97_host_flags sc_codecflags; 193 bool sc_spdif; 194 195 /* DMA scatter-gather lists. */ 196 bus_dmamap_t sc_cddmamap; 197 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 198 199 struct auich_cdata *sc_cdata; 200 201 struct auich_ring { 202 int qptr; 203 struct auich_dmalist *dmalist; 204 205 uint32_t start, p, end; 206 int blksize; 207 208 void (*intr)(void *); 209 void *arg; 210 } pcmo, pcmi, mici; 211 212 struct auich_dma *sc_dmas; 213 214 /* SiS 7012 hack */ 215 int sc_sample_shift; 216 int sc_sts_reg; 217 /* 440MX workaround */ 218 int sc_dmamap_flags; 219 /* Native mode? */ 220 int sc_native_mode; 221 222 /* sysctl */ 223 struct sysctllog *sc_log; 224 uint32_t sc_ac97_clock; 225 int sc_ac97_clock_mib; 226 227 int sc_modem_offset; 228 229 #define AUICH_AUDIO_NFORMATS 3 230 #define AUICH_MODEM_NFORMATS 1 231 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 232 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 233 struct audio_encoding_set *sc_encodings; 234 struct audio_encoding_set *sc_spdif_encodings; 235 }; 236 237 /* Debug */ 238 #ifdef AUICH_DEBUG 239 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 240 int auich_debug = 0xfffe; 241 #define ICH_DEBUG_CODECIO 0x0001 242 #define ICH_DEBUG_DMA 0x0002 243 #define ICH_DEBUG_INTR 0x0004 244 #else 245 #define DPRINTF(x,y) /* nothing */ 246 #endif 247 248 static int auich_match(struct device *, struct cfdata *, void *); 249 static void auich_attach(struct device *, struct device *, void *); 250 static int auich_detach(struct device *, int); 251 static int auich_activate(struct device *, enum devact); 252 static int auich_intr(void *); 253 254 CFATTACH_DECL(auich, sizeof(struct auich_softc), 255 auich_match, auich_attach, auich_detach, auich_activate); 256 257 static int auich_open(void *, int); 258 static void auich_close(void *); 259 static int auich_query_encoding(void *, struct audio_encoding *); 260 static int auich_set_params(void *, int, int, audio_params_t *, 261 audio_params_t *, stream_filter_list_t *, 262 stream_filter_list_t *); 263 static int auich_round_blocksize(void *, int, int, const audio_params_t *); 264 static void auich_halt_pipe(struct auich_softc *, int); 265 static int auich_halt_output(void *); 266 static int auich_halt_input(void *); 267 static int auich_getdev(void *, struct audio_device *); 268 static int auich_set_port(void *, mixer_ctrl_t *); 269 static int auich_get_port(void *, mixer_ctrl_t *); 270 static int auich_query_devinfo(void *, mixer_devinfo_t *); 271 static void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 272 static void auich_freem(void *, void *, struct malloc_type *); 273 static size_t auich_round_buffersize(void *, int, size_t); 274 static paddr_t auich_mappage(void *, void *, off_t, int); 275 static int auich_get_props(void *); 276 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 277 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 278 static int auich_trigger_output(void *, void *, void *, int, 279 void (*)(void *), void *, const audio_params_t *); 280 static int auich_trigger_input(void *, void *, void *, int, 281 void (*)(void *), void *, const audio_params_t *); 282 static int auich_powerstate(void *, int); 283 284 static int auich_alloc_cdata(struct auich_softc *); 285 286 static int auich_allocmem(struct auich_softc *, size_t, size_t, 287 struct auich_dma *); 288 static int auich_freemem(struct auich_softc *, struct auich_dma *); 289 290 static bool auich_resume(device_t PMF_FN_PROTO); 291 static int auich_set_rate(struct auich_softc *, int, u_long); 292 static int auich_sysctl_verify(SYSCTLFN_ARGS); 293 static void auich_finish_attach(struct device *); 294 static void auich_calibrate(struct auich_softc *); 295 static void auich_clear_cas(struct auich_softc *); 296 297 static int auich_attach_codec(void *, struct ac97_codec_if *); 298 static int auich_read_codec(void *, uint8_t, uint16_t *); 299 static int auich_write_codec(void *, uint8_t, uint16_t); 300 static int auich_reset_codec(void *); 301 static enum ac97_host_flags auich_flags_codec(void *); 302 static void auich_spdif_event(void *, bool); 303 304 static const struct audio_hw_if auich_hw_if = { 305 auich_open, 306 auich_close, 307 NULL, /* drain */ 308 auich_query_encoding, 309 auich_set_params, 310 auich_round_blocksize, 311 NULL, /* commit_setting */ 312 NULL, /* init_output */ 313 NULL, /* init_input */ 314 NULL, /* start_output */ 315 NULL, /* start_input */ 316 auich_halt_output, 317 auich_halt_input, 318 NULL, /* speaker_ctl */ 319 auich_getdev, 320 NULL, /* getfd */ 321 auich_set_port, 322 auich_get_port, 323 auich_query_devinfo, 324 auich_allocm, 325 auich_freem, 326 auich_round_buffersize, 327 auich_mappage, 328 auich_get_props, 329 auich_trigger_output, 330 auich_trigger_input, 331 NULL, /* dev_ioctl */ 332 auich_powerstate, 333 }; 334 335 #define AUICH_FORMATS_1CH 0 336 #define AUICH_FORMATS_4CH 1 337 #define AUICH_FORMATS_6CH 2 338 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 339 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 340 2, AUFMT_STEREO, 0, {8000, 48000}}, 341 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 342 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 343 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 344 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 345 }; 346 347 #define AUICH_SPDIF_NFORMATS 1 348 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 349 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 350 2, AUFMT_STEREO, 1, {48000}}, 351 }; 352 353 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 354 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 355 1, AUFMT_MONAURAL, 0, {8000, 16000}}, 356 }; 357 358 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 359 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 360 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 361 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 362 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 363 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 364 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 365 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 366 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 367 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 368 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 369 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 370 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 371 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 372 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 373 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 374 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 375 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 376 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 377 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 378 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 379 380 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 381 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 382 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 383 384 struct auich_devtype { 385 pcireg_t id; 386 const char *name; 387 const char *shortname; /* must be less than 11 characters */ 388 }; 389 390 static const struct auich_devtype auich_audio_devices[] = { 391 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 392 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 393 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 394 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 395 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 396 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 397 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 398 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 399 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 400 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 401 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 402 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 403 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 404 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 405 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 406 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 407 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 408 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 409 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 410 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 411 { 0, NULL, NULL }, 412 }; 413 414 static const struct auich_devtype auich_modem_devices[] = { 415 #ifdef AUICH_ATTACH_MODEM 416 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 417 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 418 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 419 #endif 420 { 0, NULL, NULL }, 421 }; 422 423 static const struct auich_devtype * 424 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 425 { 426 const struct auich_devtype *d; 427 428 for (d = auich_devices; d->name != NULL; d++) { 429 if (pa->pa_id == d->id) 430 return d; 431 } 432 433 return NULL; 434 } 435 436 static int 437 auich_match(struct device *parent, struct cfdata *match, 438 void *aux) 439 { 440 struct pci_attach_args *pa; 441 442 pa = aux; 443 if (auich_lookup(pa, auich_audio_devices) != NULL) 444 return 1; 445 if (auich_lookup(pa, auich_modem_devices) != NULL) 446 return 1; 447 448 return 0; 449 } 450 451 static void 452 auich_attach(struct device *parent, struct device *self, void *aux) 453 { 454 struct auich_softc *sc; 455 struct pci_attach_args *pa; 456 pcireg_t v, subdev; 457 const char *intrstr; 458 const struct auich_devtype *d; 459 const struct sysctlnode *node, *node_ac97clock; 460 int err, node_mib, i; 461 462 sc = (struct auich_softc *)self; 463 pa = aux; 464 465 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 466 sc->sc_modem_offset = 0x10; 467 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 468 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 469 sc->sc_modem_offset = 0; 470 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 471 } else 472 panic("auich_attach: impossible"); 473 474 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 475 aprint_naive(": Audio controller\n"); 476 else 477 aprint_naive(": Modem controller\n"); 478 479 sc->sc_pc = pa->pa_pc; 480 sc->sc_pt = pa->pa_tag; 481 482 aprint_normal(": %s\n", d->name); 483 484 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 485 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 486 || d->id == PCIID_ICH4MODEM) { 487 sc->sc_native_mode = 1; 488 /* 489 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 490 */ 491 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 492 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 493 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 494 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 495 v | ICH_CFG_IOSE); 496 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 497 0, &sc->iot, &sc->mix_ioh, NULL, 498 &sc->mix_size)) { 499 aprint_error_dev(&sc->sc_dev, "can't map codec i/o space\n"); 500 return; 501 } 502 } 503 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 504 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 505 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 506 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 507 v | ICH_CFG_IOSE); 508 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 509 0, &sc->iot, &sc->aud_ioh, NULL, 510 &sc->aud_size)) { 511 aprint_error_dev(&sc->sc_dev, "can't map device i/o space\n"); 512 return; 513 } 514 } 515 } else { 516 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 517 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 518 aprint_error_dev(&sc->sc_dev, "can't map codec i/o space\n"); 519 return; 520 } 521 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 522 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 523 aprint_error_dev(&sc->sc_dev, "can't map device i/o space\n"); 524 return; 525 } 526 } 527 sc->dmat = pa->pa_dmat; 528 529 /* enable bus mastering */ 530 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 531 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 532 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 533 534 /* Map and establish the interrupt. */ 535 if (pci_intr_map(pa, &sc->intrh)) { 536 aprint_error_dev(&sc->sc_dev, "can't map interrupt\n"); 537 return; 538 } 539 intrstr = pci_intr_string(pa->pa_pc, sc->intrh); 540 sc->sc_ih = pci_intr_establish(pa->pa_pc, sc->intrh, IPL_AUDIO, 541 auich_intr, sc); 542 if (sc->sc_ih == NULL) { 543 aprint_error_dev(&sc->sc_dev, "can't establish interrupt"); 544 if (intrstr != NULL) 545 aprint_normal(" at %s", intrstr); 546 aprint_normal("\n"); 547 return; 548 } 549 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 550 551 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 552 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 553 "0x%02x", PCI_REVISION(pa->pa_class)); 554 strlcpy(sc->sc_audev.config, device_xname(&sc->sc_dev), MAX_AUDIO_DEV_LEN); 555 556 /* SiS 7012 needs special handling */ 557 if (d->id == PCIID_SIS7012) { 558 sc->sc_sts_reg = ICH_PICB; 559 sc->sc_sample_shift = 0; 560 /* Un-mute output. From Linux. */ 561 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 562 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 563 ICH_SIS_CTL_UNMUTE); 564 } else { 565 sc->sc_sts_reg = ICH_STS; 566 sc->sc_sample_shift = 1; 567 } 568 569 /* Workaround for a 440MX B-stepping erratum */ 570 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 571 if (d->id == PCIID_440MX) { 572 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 573 printf("%s: DMA bug workaround enabled\n", device_xname(&sc->sc_dev)); 574 } 575 576 /* Set up DMA lists. */ 577 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 578 auich_alloc_cdata(sc); 579 580 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 581 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 582 583 /* Modem codecs are always the secondary codec on ICH */ 584 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 585 586 sc->host_if.arg = sc; 587 sc->host_if.attach = auich_attach_codec; 588 sc->host_if.read = auich_read_codec; 589 sc->host_if.write = auich_write_codec; 590 sc->host_if.reset = auich_reset_codec; 591 sc->host_if.flags = auich_flags_codec; 592 sc->host_if.spdif_event = auich_spdif_event; 593 594 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 595 switch (subdev) { 596 case 0x202f161f: /* Gateway 7326GZ */ 597 case 0x203a161f: /* Gateway 4028GZ */ 598 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 599 case 0x8144104d: /* Sony VAIO PCG-TR* */ 600 case 0x8197104d: /* Sony S1XP */ 601 case 0x81c0104d: /* Sony VAIO type T */ 602 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 603 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 604 break; 605 default: 606 sc->sc_codecflags = 0; 607 break; 608 } 609 610 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype) != 0) 611 return; 612 sc->codec_if->vtbl->unlock(sc->codec_if); 613 614 /* setup audio_format */ 615 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 616 memcpy(sc->sc_audio_formats, auich_audio_formats, sizeof(auich_audio_formats)); 617 if (!AC97_IS_4CH(sc->codec_if)) 618 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 619 if (!AC97_IS_6CH(sc->codec_if)) 620 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 621 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 622 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 623 sc->sc_audio_formats[i].frequency_type = 1; 624 sc->sc_audio_formats[i].frequency[0] = 48000; 625 } 626 } 627 if (0 != auconv_create_encodings(sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 628 &sc->sc_encodings)) 629 return; 630 if (0 != auconv_create_encodings(auich_spdif_formats, AUICH_SPDIF_NFORMATS, 631 &sc->sc_spdif_encodings)) 632 return; 633 } else { 634 memcpy(sc->sc_modem_formats, auich_modem_formats, sizeof(auich_modem_formats)); 635 if (0 != auconv_create_encodings(sc->sc_modem_formats, AUICH_MODEM_NFORMATS, 636 &sc->sc_encodings)) 637 return; 638 } 639 640 /* Watch for power change */ 641 if (!pmf_device_register(self, NULL, auich_resume)) 642 aprint_error_dev(self, "couldn't establish power handler\n"); 643 644 config_interrupts(self, auich_finish_attach); 645 646 /* sysctl setup */ 647 if (AC97_IS_FIXED_RATE(sc->codec_if) && 648 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 649 return; 650 651 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 652 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 653 CTL_HW, CTL_EOL); 654 if (err != 0) 655 goto sysctl_err; 656 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 657 CTLTYPE_NODE, device_xname(&sc->sc_dev), NULL, NULL, 0, 658 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 659 if (err != 0) 660 goto sysctl_err; 661 node_mib = node->sysctl_num; 662 663 if (!AC97_IS_FIXED_RATE(sc->codec_if)) { 664 /* passing the sc address instead of &sc->sc_ac97_clock */ 665 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 666 CTLFLAG_READWRITE, 667 CTLTYPE_INT, "ac97rate", 668 SYSCTL_DESCR("AC'97 codec link rate"), 669 auich_sysctl_verify, 0, sc, 0, 670 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 671 if (err != 0) 672 goto sysctl_err; 673 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 674 } 675 676 return; 677 678 sysctl_err: 679 printf("%s: failed to add sysctl nodes. (%d)\n", 680 device_xname(&sc->sc_dev), err); 681 return; /* failure of sysctl is not fatal. */ 682 } 683 684 static int 685 auich_activate(struct device *self, enum devact act) 686 { 687 struct auich_softc *sc; 688 int ret; 689 690 sc = (struct auich_softc *)self; 691 ret = 0; 692 switch (act) { 693 case DVACT_ACTIVATE: 694 return EOPNOTSUPP; 695 case DVACT_DEACTIVATE: 696 if (sc->sc_audiodev != NULL) 697 ret = config_deactivate(sc->sc_audiodev); 698 return ret; 699 } 700 return EOPNOTSUPP; 701 } 702 703 static int 704 auich_detach(struct device *self, int flags) 705 { 706 struct auich_softc *sc; 707 708 sc = (struct auich_softc *)self; 709 710 /* audio */ 711 if (sc->sc_audiodev != NULL) 712 config_detach(sc->sc_audiodev, flags); 713 714 /* sysctl */ 715 sysctl_teardown(&sc->sc_log); 716 717 /* audio_encoding_set */ 718 auconv_delete_encodings(sc->sc_encodings); 719 auconv_delete_encodings(sc->sc_spdif_encodings); 720 721 /* ac97 */ 722 if (sc->codec_if != NULL) 723 sc->codec_if->vtbl->detach(sc->codec_if); 724 725 /* PCI */ 726 if (sc->sc_ih != NULL) 727 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 728 if (sc->mix_size != 0) 729 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 730 if (sc->aud_size != 0) 731 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 732 return 0; 733 } 734 735 static int 736 auich_sysctl_verify(SYSCTLFN_ARGS) 737 { 738 int error, tmp; 739 struct sysctlnode node; 740 struct auich_softc *sc; 741 742 node = *rnode; 743 sc = rnode->sysctl_data; 744 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 745 tmp = sc->sc_ac97_clock; 746 node.sysctl_data = &tmp; 747 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 748 if (error || newp == NULL) 749 return error; 750 751 if (tmp < 48000 || tmp > 96000) 752 return EINVAL; 753 sc->sc_ac97_clock = tmp; 754 } 755 756 return 0; 757 } 758 759 static void 760 auich_finish_attach(struct device *self) 761 { 762 struct auich_softc *sc; 763 764 sc = (void *)self; 765 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 766 auich_calibrate(sc); 767 768 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 769 770 return; 771 } 772 773 #define ICH_CODECIO_INTERVAL 10 774 static int 775 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 776 { 777 struct auich_softc *sc; 778 int i; 779 uint32_t status; 780 781 sc = v; 782 /* wait for an access semaphore */ 783 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 784 bus_space_read_1(sc->iot, sc->aud_ioh, 785 ICH_CAS + sc->sc_modem_offset) & 1; 786 DELAY(ICH_CODECIO_INTERVAL)); 787 788 if (i > 0) { 789 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 790 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 791 DPRINTF(ICH_DEBUG_CODECIO, 792 ("auich_read_codec(%x, %x)\n", reg, *val)); 793 status = bus_space_read_4(sc->iot, sc->aud_ioh, 794 ICH_GSTS + sc->sc_modem_offset); 795 if (status & ICH_RCS) { 796 bus_space_write_4(sc->iot, sc->aud_ioh, 797 ICH_GSTS + sc->sc_modem_offset, 798 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 799 *val = 0xffff; 800 DPRINTF(ICH_DEBUG_CODECIO, 801 ("%s: read_codec error\n", device_xname(&sc->sc_dev))); 802 if (reg == AC97_REG_GPIO_STATUS) 803 auich_clear_cas(sc); 804 return -1; 805 } 806 if (reg == AC97_REG_GPIO_STATUS) 807 auich_clear_cas(sc); 808 return 0; 809 } else { 810 aprint_normal_dev(&sc->sc_dev, "read_codec timeout\n"); 811 if (reg == AC97_REG_GPIO_STATUS) 812 auich_clear_cas(sc); 813 return -1; 814 } 815 } 816 817 static int 818 auich_write_codec(void *v, uint8_t reg, uint16_t val) 819 { 820 struct auich_softc *sc; 821 int i; 822 823 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 824 sc = v; 825 /* wait for an access semaphore */ 826 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 827 bus_space_read_1(sc->iot, sc->aud_ioh, 828 ICH_CAS + sc->sc_modem_offset) & 1; 829 DELAY(ICH_CODECIO_INTERVAL)); 830 831 if (i > 0) { 832 bus_space_write_2(sc->iot, sc->mix_ioh, 833 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 834 return 0; 835 } else { 836 aprint_normal_dev(&sc->sc_dev, "write_codec timeout\n"); 837 return -1; 838 } 839 } 840 841 static int 842 auich_attach_codec(void *v, struct ac97_codec_if *cif) 843 { 844 struct auich_softc *sc; 845 846 sc = v; 847 sc->codec_if = cif; 848 849 return 0; 850 } 851 852 static int 853 auich_reset_codec(void *v) 854 { 855 struct auich_softc *sc; 856 int i; 857 uint32_t control, status; 858 859 sc = v; 860 control = bus_space_read_4(sc->iot, sc->aud_ioh, 861 ICH_GCTRL + sc->sc_modem_offset); 862 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 863 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 864 } else { 865 control &= ~ICH_ACLSO; 866 control |= ICH_GIE; 867 } 868 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 869 bus_space_write_4(sc->iot, sc->aud_ioh, 870 ICH_GCTRL + sc->sc_modem_offset, control); 871 872 for (i = 500000; i >= 0; i--) { 873 status = bus_space_read_4(sc->iot, sc->aud_ioh, 874 ICH_GSTS + sc->sc_modem_offset); 875 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 876 break; 877 DELAY(1); 878 } 879 if (i <= 0) { 880 aprint_error_dev(&sc->sc_dev, "auich_reset_codec: time out\n"); 881 return ETIMEDOUT; 882 } 883 #ifdef AUICH_DEBUG 884 if (status & ICH_SCR) 885 printf("%s: The 2nd codec is ready.\n", 886 device_xname(&sc->sc_dev)); 887 if (status & ICH_S2CR) 888 printf("%s: The 3rd codec is ready.\n", 889 device_xname(&sc->sc_dev)); 890 #endif 891 return 0; 892 } 893 894 static enum ac97_host_flags 895 auich_flags_codec(void *v) 896 { 897 struct auich_softc *sc = v; 898 return sc->sc_codecflags; 899 } 900 901 static void 902 auich_spdif_event(void *addr, bool flag) 903 { 904 struct auich_softc *sc; 905 906 sc = addr; 907 sc->sc_spdif = flag; 908 } 909 910 static int 911 auich_open(void *addr, int flags) 912 { 913 struct auich_softc *sc; 914 915 sc = (struct auich_softc *)addr; 916 sc->codec_if->vtbl->lock(sc->codec_if); 917 return 0; 918 } 919 920 static void 921 auich_close(void *addr) 922 { 923 struct auich_softc *sc; 924 925 sc = (struct auich_softc *)addr; 926 sc->codec_if->vtbl->unlock(sc->codec_if); 927 } 928 929 static int 930 auich_query_encoding(void *v, struct audio_encoding *aep) 931 { 932 struct auich_softc *sc; 933 934 sc = (struct auich_softc *)v; 935 return auconv_query_encoding( 936 sc->sc_spdif ? sc->sc_spdif_encodings : sc->sc_encodings, aep); 937 } 938 939 static int 940 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 941 { 942 int ret; 943 u_int ratetmp; 944 945 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 946 ratetmp = srate; 947 if (mode == AUMODE_RECORD) 948 return sc->codec_if->vtbl->set_rate(sc->codec_if, 949 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 950 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 951 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 952 if (ret) 953 return ret; 954 ratetmp = srate; 955 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 956 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 957 if (ret) 958 return ret; 959 ratetmp = srate; 960 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 961 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 962 return ret; 963 } 964 965 static int 966 auich_set_params(void *v, int setmode, int usemode, 967 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 968 stream_filter_list_t *rfil) 969 { 970 struct auich_softc *sc; 971 audio_params_t *p; 972 stream_filter_list_t *fil; 973 int mode, index; 974 uint32_t control; 975 976 sc = v; 977 for (mode = AUMODE_RECORD; mode != -1; 978 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 979 if ((setmode & mode) == 0) 980 continue; 981 982 p = mode == AUMODE_PLAY ? play : rec; 983 fil = mode == AUMODE_PLAY ? pfil : rfil; 984 if (p == NULL) 985 continue; 986 987 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 988 if (p->sample_rate < 8000 || 989 p->sample_rate > 48000) 990 return EINVAL; 991 992 if (!sc->sc_spdif) 993 index = auconv_set_converter(sc->sc_audio_formats, 994 AUICH_AUDIO_NFORMATS, mode, p, TRUE, fil); 995 else 996 index = auconv_set_converter(auich_spdif_formats, 997 AUICH_SPDIF_NFORMATS, mode, p, TRUE, fil); 998 } else { 999 if (p->sample_rate != 8000 && p->sample_rate != 16000) 1000 return EINVAL; 1001 index = auconv_set_converter(sc->sc_modem_formats, 1002 AUICH_MODEM_NFORMATS, mode, p, TRUE, fil); 1003 } 1004 if (index < 0) 1005 return EINVAL; 1006 if (fil->req_size > 0) 1007 p = &fil->filters[0].param; 1008 /* p represents HW encoding */ 1009 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1010 if (sc->sc_audio_formats[index].frequency_type != 1 1011 && auich_set_rate(sc, mode, p->sample_rate)) 1012 return EINVAL; 1013 } else { 1014 if (sc->sc_modem_formats[index].frequency_type != 1 1015 && auich_set_rate(sc, mode, p->sample_rate)) 1016 return EINVAL; 1017 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1018 p->sample_rate); 1019 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1020 } 1021 if (mode == AUMODE_PLAY && 1022 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1023 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1024 ICH_GCTRL + sc->sc_modem_offset); 1025 control &= ~ICH_PCM246_MASK; 1026 if (p->channels == 4) { 1027 control |= ICH_PCM4; 1028 } else if (p->channels == 6) { 1029 control |= ICH_PCM6; 1030 } 1031 bus_space_write_4(sc->iot, sc->aud_ioh, 1032 ICH_GCTRL + sc->sc_modem_offset, control); 1033 } 1034 } 1035 1036 return 0; 1037 } 1038 1039 static int 1040 auich_round_blocksize(void *v, int blk, int mode, 1041 const audio_params_t *param) 1042 { 1043 1044 return blk & ~0x3f; /* keep good alignment */ 1045 } 1046 1047 static void 1048 auich_halt_pipe(struct auich_softc *sc, int pipe) 1049 { 1050 int i; 1051 uint32_t status; 1052 1053 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1054 for (i = 0; i < 100; i++) { 1055 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1056 if (status & ICH_DCH) 1057 break; 1058 DELAY(1); 1059 } 1060 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1061 1062 #if AUICH_DEBUG 1063 if (i > 0) 1064 printf("auich_halt_pipe: halt took %d cycles\n", i); 1065 #endif 1066 } 1067 1068 static int 1069 auich_halt_output(void *v) 1070 { 1071 struct auich_softc *sc; 1072 1073 sc = v; 1074 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", device_xname(&sc->sc_dev))); 1075 1076 auich_halt_pipe(sc, ICH_PCMO); 1077 sc->pcmo.intr = NULL; 1078 1079 return 0; 1080 } 1081 1082 static int 1083 auich_halt_input(void *v) 1084 { 1085 struct auich_softc *sc; 1086 1087 sc = v; 1088 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_input\n", device_xname(&sc->sc_dev))); 1089 1090 auich_halt_pipe(sc, ICH_PCMI); 1091 sc->pcmi.intr = NULL; 1092 1093 return 0; 1094 } 1095 1096 static int 1097 auich_getdev(void *v, struct audio_device *adp) 1098 { 1099 struct auich_softc *sc; 1100 1101 sc = v; 1102 *adp = sc->sc_audev; 1103 return 0; 1104 } 1105 1106 static int 1107 auich_set_port(void *v, mixer_ctrl_t *cp) 1108 { 1109 struct auich_softc *sc; 1110 1111 sc = v; 1112 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1113 } 1114 1115 static int 1116 auich_get_port(void *v, mixer_ctrl_t *cp) 1117 { 1118 struct auich_softc *sc; 1119 1120 sc = v; 1121 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1122 } 1123 1124 static int 1125 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1126 { 1127 struct auich_softc *sc; 1128 1129 sc = v; 1130 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1131 } 1132 1133 static void * 1134 auich_allocm(void *v, int direction, size_t size, 1135 struct malloc_type *pool, int flags) 1136 { 1137 struct auich_softc *sc; 1138 struct auich_dma *p; 1139 int error; 1140 1141 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1142 return NULL; 1143 1144 p = malloc(sizeof(*p), pool, flags|M_ZERO); 1145 if (p == NULL) 1146 return NULL; 1147 1148 sc = v; 1149 error = auich_allocmem(sc, size, 0, p); 1150 if (error) { 1151 free(p, pool); 1152 return NULL; 1153 } 1154 1155 p->next = sc->sc_dmas; 1156 sc->sc_dmas = p; 1157 1158 return KERNADDR(p); 1159 } 1160 1161 static void 1162 auich_freem(void *v, void *ptr, struct malloc_type *pool) 1163 { 1164 struct auich_softc *sc; 1165 struct auich_dma *p, **pp; 1166 1167 sc = v; 1168 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1169 if (KERNADDR(p) == ptr) { 1170 auich_freemem(sc, p); 1171 *pp = p->next; 1172 free(p, pool); 1173 return; 1174 } 1175 } 1176 } 1177 1178 static size_t 1179 auich_round_buffersize(void *v, int direction, size_t size) 1180 { 1181 1182 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1183 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1184 1185 return size; 1186 } 1187 1188 static paddr_t 1189 auich_mappage(void *v, void *mem, off_t off, int prot) 1190 { 1191 struct auich_softc *sc; 1192 struct auich_dma *p; 1193 1194 if (off < 0) 1195 return -1; 1196 sc = v; 1197 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 1198 continue; 1199 if (!p) 1200 return -1; 1201 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1202 off, prot, BUS_DMA_WAITOK); 1203 } 1204 1205 static int 1206 auich_get_props(void *v) 1207 { 1208 struct auich_softc *sc; 1209 int props; 1210 1211 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1212 sc = v; 1213 /* 1214 * Even if the codec is fixed-rate, set_param() succeeds for any sample 1215 * rate because of aurateconv. Applications can't know what rate the 1216 * device can process in the case of mmap(). 1217 */ 1218 if (!AC97_IS_FIXED_RATE(sc->codec_if) || 1219 sc->sc_codectype == AC97_CODEC_TYPE_MODEM) 1220 props |= AUDIO_PROP_MMAP; 1221 return props; 1222 } 1223 1224 static int 1225 auich_intr(void *v) 1226 { 1227 struct auich_softc *sc; 1228 int ret, gsts; 1229 #ifdef DIAGNOSTIC 1230 int csts; 1231 #endif 1232 1233 sc = v; 1234 1235 if (!device_has_power(&sc->sc_dev)) 1236 return (0); 1237 1238 ret = 0; 1239 #ifdef DIAGNOSTIC 1240 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1241 if (csts & PCI_STATUS_MASTER_ABORT) { 1242 printf("auich_intr: PCI master abort\n"); 1243 } 1244 #endif 1245 1246 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1247 ICH_GSTS + sc->sc_modem_offset); 1248 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 1249 1250 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1251 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1252 int sts; 1253 1254 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1255 ICH_PCMO + sc->sc_sts_reg); 1256 DPRINTF(ICH_DEBUG_INTR, 1257 ("auich_intr: osts=0x%x\n", sts)); 1258 1259 if (sts & ICH_FIFOE) 1260 printf("%s: fifo underrun\n", device_xname(&sc->sc_dev)); 1261 1262 if (sts & ICH_BCIS) 1263 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1264 1265 /* int ack */ 1266 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1267 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1268 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1269 bus_space_write_4(sc->iot, sc->aud_ioh, 1270 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1271 else 1272 bus_space_write_4(sc->iot, sc->aud_ioh, 1273 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1274 ret++; 1275 } 1276 1277 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1278 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1279 int sts; 1280 1281 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1282 ICH_PCMI + sc->sc_sts_reg); 1283 DPRINTF(ICH_DEBUG_INTR, 1284 ("auich_intr: ists=0x%x\n", sts)); 1285 1286 if (sts & ICH_FIFOE) 1287 printf("%s: fifo overrun\n", device_xname(&sc->sc_dev)); 1288 1289 if (sts & ICH_BCIS) 1290 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1291 1292 /* int ack */ 1293 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1294 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1295 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1296 bus_space_write_4(sc->iot, sc->aud_ioh, 1297 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1298 else 1299 bus_space_write_4(sc->iot, sc->aud_ioh, 1300 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1301 ret++; 1302 } 1303 1304 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1305 int sts; 1306 1307 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1308 ICH_MICI + sc->sc_sts_reg); 1309 DPRINTF(ICH_DEBUG_INTR, 1310 ("auich_intr: ists=0x%x\n", sts)); 1311 1312 if (sts & ICH_FIFOE) 1313 printf("%s: fifo overrun\n", device_xname(&sc->sc_dev)); 1314 1315 if (sts & ICH_BCIS) 1316 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1317 1318 /* int ack */ 1319 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1320 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1321 bus_space_write_4(sc->iot, sc->aud_ioh, 1322 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1323 ret++; 1324 } 1325 1326 #ifdef AUICH_MODEM_DEBUG 1327 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1328 printf("%s: gsts=0x%x\n", device_xname(&sc->sc_dev), gsts); 1329 /* int ack */ 1330 bus_space_write_4(sc->iot, sc->aud_ioh, 1331 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1332 ret++; 1333 } 1334 #endif 1335 1336 return ret; 1337 } 1338 1339 static void 1340 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1341 { 1342 int blksize, qptr; 1343 struct auich_dmalist *q; 1344 1345 blksize = ring->blksize; 1346 1347 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1348 q = &ring->dmalist[qptr]; 1349 q->base = ring->p; 1350 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1351 1352 ring->p += blksize; 1353 if (ring->p >= ring->end) 1354 ring->p = ring->start; 1355 } 1356 ring->qptr = 0; 1357 1358 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1359 (qptr - 1) & ICH_LVI_MASK); 1360 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1361 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1362 } 1363 1364 static void 1365 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1366 { 1367 int blksize, qptr, nqptr; 1368 struct auich_dmalist *q; 1369 1370 blksize = ring->blksize; 1371 qptr = ring->qptr; 1372 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1373 1374 while (qptr != nqptr) { 1375 q = &ring->dmalist[qptr]; 1376 q->base = ring->p; 1377 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1378 1379 DPRINTF(ICH_DEBUG_INTR, 1380 ("auich_intr: %p, %p = %x @ 0x%x\n", 1381 &ring->dmalist[qptr], q, q->len, q->base)); 1382 1383 ring->p += blksize; 1384 if (ring->p >= ring->end) 1385 ring->p = ring->start; 1386 1387 qptr = (qptr + 1) & ICH_LVI_MASK; 1388 if (ring->intr) 1389 ring->intr(ring->arg); 1390 } 1391 ring->qptr = qptr; 1392 1393 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1394 (qptr - 1) & ICH_LVI_MASK); 1395 } 1396 1397 static int 1398 auich_trigger_output(void *v, void *start, void *end, int blksize, 1399 void (*intr)(void *), void *arg, const audio_params_t *param) 1400 { 1401 struct auich_softc *sc; 1402 struct auich_dma *p; 1403 size_t size; 1404 1405 DPRINTF(ICH_DEBUG_DMA, 1406 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1407 start, end, blksize, intr, arg, param)); 1408 sc = v; 1409 1410 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1411 continue; 1412 if (!p) { 1413 printf("auich_trigger_output: bad addr %p\n", start); 1414 return EINVAL; 1415 } 1416 1417 size = (size_t)((char *)end - (char *)start); 1418 1419 sc->pcmo.intr = intr; 1420 sc->pcmo.arg = arg; 1421 sc->pcmo.start = DMAADDR(p); 1422 sc->pcmo.p = sc->pcmo.start; 1423 sc->pcmo.end = sc->pcmo.start + size; 1424 sc->pcmo.blksize = blksize; 1425 1426 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1427 sc->sc_cddma + ICH_PCMO_OFF(0)); 1428 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1429 1430 return 0; 1431 } 1432 1433 static int 1434 auich_trigger_input(void *v, void *start, void *end, int blksize, 1435 void (*intr)(void *), void *arg, const audio_params_t *param) 1436 { 1437 struct auich_softc *sc; 1438 struct auich_dma *p; 1439 size_t size; 1440 1441 DPRINTF(ICH_DEBUG_DMA, 1442 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1443 start, end, blksize, intr, arg, param)); 1444 sc = v; 1445 1446 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1447 continue; 1448 if (!p) { 1449 printf("auich_trigger_input: bad addr %p\n", start); 1450 return EINVAL; 1451 } 1452 1453 size = (size_t)((char *)end - (char *)start); 1454 1455 sc->pcmi.intr = intr; 1456 sc->pcmi.arg = arg; 1457 sc->pcmi.start = DMAADDR(p); 1458 sc->pcmi.p = sc->pcmi.start; 1459 sc->pcmi.end = sc->pcmi.start + size; 1460 sc->pcmi.blksize = blksize; 1461 1462 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1463 sc->sc_cddma + ICH_PCMI_OFF(0)); 1464 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1465 1466 return 0; 1467 } 1468 1469 static int 1470 auich_powerstate(void *v, int state) 1471 { 1472 return 0; 1473 } 1474 1475 static int 1476 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1477 struct auich_dma *p) 1478 { 1479 int error; 1480 1481 p->size = size; 1482 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1483 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1484 &p->nsegs, BUS_DMA_NOWAIT); 1485 if (error) 1486 return error; 1487 1488 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1489 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1490 if (error) 1491 goto free; 1492 1493 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1494 0, BUS_DMA_NOWAIT, &p->map); 1495 if (error) 1496 goto unmap; 1497 1498 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1499 BUS_DMA_NOWAIT); 1500 if (error) 1501 goto destroy; 1502 return 0; 1503 1504 destroy: 1505 bus_dmamap_destroy(sc->dmat, p->map); 1506 unmap: 1507 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1508 free: 1509 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1510 return error; 1511 } 1512 1513 static int 1514 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1515 { 1516 1517 bus_dmamap_unload(sc->dmat, p->map); 1518 bus_dmamap_destroy(sc->dmat, p->map); 1519 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1520 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1521 return 0; 1522 } 1523 1524 static int 1525 auich_alloc_cdata(struct auich_softc *sc) 1526 { 1527 bus_dma_segment_t seg; 1528 int error, rseg; 1529 1530 /* 1531 * Allocate the control data structure, and create and load the 1532 * DMA map for it. 1533 */ 1534 if ((error = bus_dmamem_alloc(sc->dmat, 1535 sizeof(struct auich_cdata), 1536 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1537 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", error); 1538 goto fail_0; 1539 } 1540 1541 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1542 sizeof(struct auich_cdata), 1543 (void **) &sc->sc_cdata, 1544 sc->sc_dmamap_flags)) != 0) { 1545 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", error); 1546 goto fail_1; 1547 } 1548 1549 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1550 sizeof(struct auich_cdata), 0, 0, 1551 &sc->sc_cddmamap)) != 0) { 1552 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 1553 "error = %d\n", error); 1554 goto fail_2; 1555 } 1556 1557 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1558 sc->sc_cdata, sizeof(struct auich_cdata), 1559 NULL, 0)) != 0) { 1560 aprint_error_dev(&sc->sc_dev, "unable tp load control data DMA map, " 1561 "error = %d\n", error); 1562 goto fail_3; 1563 } 1564 1565 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1566 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1567 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1568 1569 return 0; 1570 1571 fail_3: 1572 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1573 fail_2: 1574 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1575 sizeof(struct auich_cdata)); 1576 fail_1: 1577 bus_dmamem_free(sc->dmat, &seg, rseg); 1578 fail_0: 1579 return error; 1580 } 1581 1582 static bool 1583 auich_resume(device_t dv PMF_FN_ARGS) 1584 { 1585 struct auich_softc *sc = device_private(dv); 1586 pcireg_t v; 1587 1588 if (sc->sc_native_mode) { 1589 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG); 1590 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG, 1591 v | ICH_CFG_IOSE); 1592 } 1593 1594 auich_reset_codec(sc); 1595 DELAY(1000); 1596 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1597 1598 return true; 1599 } 1600 1601 /* 1602 * Calibrate card (some boards are overclocked and need scaling) 1603 */ 1604 static void 1605 auich_calibrate(struct auich_softc *sc) 1606 { 1607 struct timeval t1, t2; 1608 uint8_t ociv, nciv; 1609 uint64_t wait_us; 1610 uint32_t actual_48k_rate, bytes, ac97rate; 1611 void *temp_buffer; 1612 struct auich_dma *p; 1613 u_int rate; 1614 1615 /* 1616 * Grab audio from input for fixed interval and compare how 1617 * much we actually get with what we expect. Interval needs 1618 * to be sufficiently short that no interrupts are 1619 * generated. 1620 */ 1621 1622 /* Force the codec to a known state first. */ 1623 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1624 rate = sc->sc_ac97_clock = 48000; 1625 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1626 &rate); 1627 1628 /* Setup a buffer */ 1629 bytes = 64000; 1630 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1631 1632 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1633 continue; 1634 if (p == NULL) { 1635 printf("auich_calibrate: bad address %p\n", temp_buffer); 1636 return; 1637 } 1638 sc->pcmi.dmalist[0].base = DMAADDR(p); 1639 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1640 1641 /* 1642 * our data format is stereo, 16 bit so each sample is 4 bytes. 1643 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1644 * we're going to start recording with interrupts disabled and measure 1645 * the time taken for one block to complete. we know the block size, 1646 * we know the time in microseconds, we calculate the sample rate: 1647 * 1648 * actual_rate [bps] = bytes / (time [s] * 4) 1649 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1650 * actual_rate [Hz] = (bytes * 250000) / time [us] 1651 */ 1652 1653 /* prepare */ 1654 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1655 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1656 sc->sc_cddma + ICH_PCMI_OFF(0)); 1657 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1658 (0 - 1) & ICH_LVI_MASK); 1659 1660 /* start */ 1661 microtime(&t1); 1662 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1663 1664 /* wait */ 1665 nciv = ociv; 1666 do { 1667 microtime(&t2); 1668 if (t2.tv_sec - t1.tv_sec > 1) 1669 break; 1670 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1671 ICH_PCMI + ICH_CIV); 1672 } while (nciv == ociv); 1673 microtime(&t2); 1674 1675 /* stop */ 1676 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1677 1678 /* reset */ 1679 DELAY(100); 1680 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1681 1682 /* turn time delta into us */ 1683 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1684 1685 auich_freem(sc, temp_buffer, M_DEVBUF); 1686 1687 if (nciv == ociv) { 1688 printf("%s: ac97 link rate calibration timed out after %" 1689 PRIu64 " us\n", device_xname(&sc->sc_dev), wait_us); 1690 return; 1691 } 1692 1693 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1694 1695 if (actual_48k_rate < 50000) 1696 ac97rate = 48000; 1697 else 1698 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1699 1700 printf("%s: measured ac97 link rate at %d Hz", 1701 device_xname(&sc->sc_dev), actual_48k_rate); 1702 if (ac97rate != actual_48k_rate) 1703 printf(", will use %d Hz", ac97rate); 1704 printf("\n"); 1705 1706 sc->sc_ac97_clock = ac97rate; 1707 } 1708 1709 static void 1710 auich_clear_cas(struct auich_softc *sc) 1711 { 1712 /* Clear the codec access semaphore */ 1713 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1714 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1715 1716 return; 1717 } 1718