1 /* $NetBSD: auich.c,v 1.80 2004/11/13 15:00:48 kent Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* 70 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 71 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 72 * All rights reserved. 73 * 74 * Redistribution and use in source and binary forms, with or without 75 * modification, are permitted provided that the following conditions 76 * are met: 77 * 1. Redistributions of source code must retain the above copyright 78 * notice, this list of conditions and the following disclaimer. 79 * 2. Redistributions in binary form must reproduce the above copyright 80 * notice, this list of conditions and the following disclaimer in the 81 * documentation and/or other materials provided with the distribution. 82 * 83 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 84 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 85 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 86 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 87 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 88 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 89 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 90 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 91 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 92 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 93 * SUCH DAMAGE. 94 * 95 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 96 */ 97 98 99 /* #define AUICH_DEBUG */ 100 /* 101 * AC'97 audio found on Intel 810/820/440MX chipsets. 102 * http://developer.intel.com/design/chipsets/datashts/290655.htm 103 * http://developer.intel.com/design/chipsets/manuals/298028.htm 104 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 105 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 106 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 107 * AMD8111: 108 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 109 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 110 * 111 * TODO: 112 * - Add support for the dedicated microphone input. 113 * 114 * NOTE: 115 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 116 * It causes PCI master abort and hangups until cold reboot. 117 * http://www.intel.com/design/chipsets/specupdt/245051.htm 118 */ 119 120 #include <sys/cdefs.h> 121 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.80 2004/11/13 15:00:48 kent Exp $"); 122 123 #include <sys/param.h> 124 #include <sys/systm.h> 125 #include <sys/kernel.h> 126 #include <sys/malloc.h> 127 #include <sys/device.h> 128 #include <sys/fcntl.h> 129 #include <sys/proc.h> 130 #include <sys/sysctl.h> 131 132 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 133 134 #include <dev/pci/pcidevs.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/auichreg.h> 137 138 #include <sys/audioio.h> 139 #include <dev/audio_if.h> 140 #include <dev/mulaw.h> 141 #include <dev/auconv.h> 142 143 #include <machine/bus.h> 144 145 #include <dev/ic/ac97reg.h> 146 #include <dev/ic/ac97var.h> 147 148 struct auich_dma { 149 bus_dmamap_t map; 150 caddr_t addr; 151 bus_dma_segment_t segs[1]; 152 int nsegs; 153 size_t size; 154 struct auich_dma *next; 155 }; 156 157 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 158 #define KERNADDR(p) ((void *)((p)->addr)) 159 160 struct auich_cdata { 161 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 162 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 164 }; 165 166 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 167 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 168 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 169 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 170 171 struct auich_softc { 172 struct device sc_dev; 173 void *sc_ih; 174 175 struct device *sc_audiodev; 176 audio_device_t sc_audev; 177 178 bus_space_tag_t iot; 179 bus_space_handle_t mix_ioh; 180 bus_space_handle_t aud_ioh; 181 bus_dma_tag_t dmat; 182 183 struct ac97_codec_if *codec_if; 184 struct ac97_host_if host_if; 185 186 /* DMA scatter-gather lists. */ 187 bus_dmamap_t sc_cddmamap; 188 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 189 190 struct auich_cdata *sc_cdata; 191 192 struct auich_ring { 193 int qptr; 194 struct auich_dmalist *dmalist; 195 196 u_int32_t start, p, end; 197 int blksize; 198 199 void (*intr)(void *); 200 void *arg; 201 } pcmo, pcmi, mici; 202 203 struct auich_dma *sc_dmas; 204 205 #ifdef DIAGNOSTIC 206 pci_chipset_tag_t sc_pc; 207 pcitag_t sc_pt; 208 #endif 209 /* SiS 7012 hack */ 210 int sc_sample_shift; 211 int sc_sts_reg; 212 /* 440MX workaround */ 213 int sc_dmamap_flags; 214 215 216 /* Power Management */ 217 void *sc_powerhook; 218 int sc_suspend; 219 220 /* sysctl */ 221 struct sysctllog *sc_log; 222 uint32_t sc_ac97_clock; 223 int sc_ac97_clock_mib; 224 225 #define AUICH_NFORMATS 3 226 struct audio_format sc_formats[AUICH_NFORMATS]; 227 struct audio_encoding_set *sc_encodings; 228 }; 229 230 /* Debug */ 231 #ifdef AUICH_DEBUG 232 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 233 int auich_debug = 0xfffe; 234 #define ICH_DEBUG_CODECIO 0x0001 235 #define ICH_DEBUG_DMA 0x0002 236 #define ICH_DEBUG_INTR 0x0004 237 #else 238 #define DPRINTF(x,y) /* nothing */ 239 #endif 240 241 int auich_match(struct device *, struct cfdata *, void *); 242 void auich_attach(struct device *, struct device *, void *); 243 int auich_intr(void *); 244 245 CFATTACH_DECL(auich, sizeof(struct auich_softc), 246 auich_match, auich_attach, NULL, NULL); 247 248 int auich_open(void *, int); 249 void auich_close(void *); 250 int auich_query_encoding(void *, struct audio_encoding *); 251 int auich_set_params(void *, int, int, struct audio_params *, 252 struct audio_params *); 253 int auich_round_blocksize(void *, int); 254 int auich_halt_output(void *); 255 int auich_halt_input(void *); 256 int auich_getdev(void *, struct audio_device *); 257 int auich_set_port(void *, mixer_ctrl_t *); 258 int auich_get_port(void *, mixer_ctrl_t *); 259 int auich_query_devinfo(void *, mixer_devinfo_t *); 260 void *auich_allocm(void *, int, size_t, struct malloc_type *, int); 261 void auich_freem(void *, void *, struct malloc_type *); 262 size_t auich_round_buffersize(void *, int, size_t); 263 paddr_t auich_mappage(void *, void *, off_t, int); 264 int auich_get_props(void *); 265 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 266 void *, struct audio_params *); 267 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 268 void *, struct audio_params *); 269 270 int auich_alloc_cdata(struct auich_softc *); 271 272 int auich_allocmem(struct auich_softc *, size_t, size_t, 273 struct auich_dma *); 274 int auich_freemem(struct auich_softc *, struct auich_dma *); 275 276 void auich_powerhook(int, void *); 277 int auich_set_rate(struct auich_softc *, int, u_long); 278 static int auich_sysctl_verify(SYSCTLFN_ARGS); 279 void auich_finish_attach(struct device *); 280 void auich_calibrate(struct auich_softc *); 281 282 283 const struct audio_hw_if auich_hw_if = { 284 auich_open, 285 auich_close, 286 NULL, /* drain */ 287 auich_query_encoding, 288 auich_set_params, 289 auich_round_blocksize, 290 NULL, /* commit_setting */ 291 NULL, /* init_output */ 292 NULL, /* init_input */ 293 NULL, /* start_output */ 294 NULL, /* start_input */ 295 auich_halt_output, 296 auich_halt_input, 297 NULL, /* speaker_ctl */ 298 auich_getdev, 299 NULL, /* getfd */ 300 auich_set_port, 301 auich_get_port, 302 auich_query_devinfo, 303 auich_allocm, 304 auich_freem, 305 auich_round_buffersize, 306 auich_mappage, 307 auich_get_props, 308 auich_trigger_output, 309 auich_trigger_input, 310 NULL, /* dev_ioctl */ 311 }; 312 313 int auich_attach_codec(void *, struct ac97_codec_if *); 314 int auich_read_codec(void *, u_int8_t, u_int16_t *); 315 int auich_write_codec(void *, u_int8_t, u_int16_t); 316 int auich_reset_codec(void *); 317 318 #define AUICH_FORMATS_4CH 1 319 #define AUICH_FORMATS_6CH 2 320 static const struct audio_format auich_formats[AUICH_NFORMATS] = { 321 {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 322 2, AUFMT_STEREO, 0, {8000, 48000}}, 323 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 324 4, AUFMT_SURROUND4, 0, {8000, 48000}}, 325 {NULL, AUMODE_PLAY, AUDIO_ENCODING_SLINEAR_LE, 16, 16, 326 6, AUFMT_DOLBY_5_1, 0, {8000, 48000}}, 327 }; 328 329 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 330 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 331 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 332 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 333 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 334 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 335 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 336 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 337 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 338 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 339 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 340 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 341 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 342 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 343 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 344 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 345 346 static const struct auich_devtype { 347 pcireg_t id; 348 const char *name; 349 const char *shortname; /* must be less than 11 characters */ 350 } auich_devices[] = { 351 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 352 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 353 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 354 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 355 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 356 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 357 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 358 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 359 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 360 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 361 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 362 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 363 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 364 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 365 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 366 { 0, NULL, NULL }, 367 }; 368 369 static const struct auich_devtype * 370 auich_lookup(struct pci_attach_args *pa) 371 { 372 const struct auich_devtype *d; 373 374 for (d = auich_devices; d->name != NULL; d++) { 375 if (pa->pa_id == d->id) 376 return (d); 377 } 378 379 return (NULL); 380 } 381 382 int 383 auich_match(struct device *parent, struct cfdata *match, void *aux) 384 { 385 struct pci_attach_args *pa = aux; 386 387 if (auich_lookup(pa) != NULL) 388 return (1); 389 390 return (0); 391 } 392 393 void 394 auich_attach(struct device *parent, struct device *self, void *aux) 395 { 396 struct auich_softc *sc = (struct auich_softc *)self; 397 struct pci_attach_args *pa = aux; 398 pci_intr_handle_t ih; 399 bus_size_t mix_size, aud_size; 400 pcireg_t v; 401 const char *intrstr; 402 const struct auich_devtype *d; 403 struct sysctlnode *node; 404 int err, node_mib, i; 405 406 aprint_naive(": Audio controller\n"); 407 408 d = auich_lookup(pa); 409 if (d == NULL) 410 panic("auich_attach: impossible"); 411 412 #ifdef DIAGNOSTIC 413 sc->sc_pc = pa->pa_pc; 414 sc->sc_pt = pa->pa_tag; 415 #endif 416 417 aprint_normal(": %s\n", d->name); 418 419 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6) { 420 /* 421 * Use native mode for ICH4/ICH5/ICH6 422 */ 423 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 424 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 425 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 426 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 427 v | ICH_CFG_IOSE); 428 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 429 0, &sc->iot, &sc->mix_ioh, NULL, 430 &mix_size)) { 431 aprint_error("%s: can't map codec i/o space\n", 432 sc->sc_dev.dv_xname); 433 return; 434 } 435 } 436 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 437 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 438 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 439 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 440 v | ICH_CFG_IOSE); 441 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 442 0, &sc->iot, &sc->aud_ioh, NULL, 443 &aud_size)) { 444 aprint_error("%s: can't map device i/o space\n", 445 sc->sc_dev.dv_xname); 446 return; 447 } 448 } 449 } else { 450 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 451 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 452 aprint_error("%s: can't map codec i/o space\n", 453 sc->sc_dev.dv_xname); 454 return; 455 } 456 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 457 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 458 aprint_error("%s: can't map device i/o space\n", 459 sc->sc_dev.dv_xname); 460 return; 461 } 462 } 463 sc->dmat = pa->pa_dmat; 464 465 /* enable bus mastering */ 466 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 467 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 468 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 469 470 /* Map and establish the interrupt. */ 471 if (pci_intr_map(pa, &ih)) { 472 aprint_error("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 473 return; 474 } 475 intrstr = pci_intr_string(pa->pa_pc, ih); 476 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 477 auich_intr, sc); 478 if (sc->sc_ih == NULL) { 479 aprint_error("%s: can't establish interrupt", 480 sc->sc_dev.dv_xname); 481 if (intrstr != NULL) 482 aprint_normal(" at %s", intrstr); 483 aprint_normal("\n"); 484 return; 485 } 486 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 487 488 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 489 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 490 "0x%02x", PCI_REVISION(pa->pa_class)); 491 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, MAX_AUDIO_DEV_LEN); 492 493 /* SiS 7012 needs special handling */ 494 if (d->id == PCIID_SIS7012) { 495 sc->sc_sts_reg = ICH_PICB; 496 sc->sc_sample_shift = 0; 497 } else { 498 sc->sc_sts_reg = ICH_STS; 499 sc->sc_sample_shift = 1; 500 } 501 502 /* Workaround for a 440MX B-stepping erratum */ 503 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 504 if (d->id == PCIID_440MX) { 505 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 506 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 507 } 508 509 /* Set up DMA lists. */ 510 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 511 auich_alloc_cdata(sc); 512 513 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 514 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 515 516 sc->host_if.arg = sc; 517 sc->host_if.attach = auich_attach_codec; 518 sc->host_if.read = auich_read_codec; 519 sc->host_if.write = auich_write_codec; 520 sc->host_if.reset = auich_reset_codec; 521 522 if (ac97_attach(&sc->host_if) != 0) 523 return; 524 525 /* setup audio_format */ 526 memcpy(sc->sc_formats, auich_formats, sizeof(auich_formats)); 527 if (!AC97_IS_4CH(sc->codec_if)) 528 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_4CH]); 529 if (!AC97_IS_6CH(sc->codec_if)) 530 AUFMT_INVALIDATE(&sc->sc_formats[AUICH_FORMATS_6CH]); 531 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 532 for (i = 0; i < AUICH_NFORMATS; i++) { 533 sc->sc_formats[i].frequency_type = 1; 534 sc->sc_formats[i].frequency[0] = 48000; 535 } 536 } 537 538 if (0 != auconv_create_encodings(sc->sc_formats, AUICH_NFORMATS, 539 &sc->sc_encodings)) { 540 return; 541 } 542 543 /* Watch for power change */ 544 sc->sc_suspend = PWR_RESUME; 545 sc->sc_powerhook = powerhook_establish(auich_powerhook, sc); 546 547 config_interrupts(self, auich_finish_attach); 548 549 /* sysctl setup */ 550 if (AC97_IS_FIXED_RATE(sc->codec_if)) 551 return; 552 err = sysctl_createv(&sc->sc_log, 0, NULL, NULL, 0, 553 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, 554 CTL_HW, CTL_EOL); 555 if (err != 0) 556 goto sysctl_err; 557 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 558 CTLTYPE_NODE, sc->sc_dev.dv_xname, NULL, NULL, 0, 559 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 560 if (err != 0) 561 goto sysctl_err; 562 node_mib = node->sysctl_num; 563 /* passing the sc address instead of &sc->sc_ac97_clock */ 564 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, CTLFLAG_READWRITE, 565 CTLTYPE_INT, "ac97rate", 566 SYSCTL_DESCR("AC'97 codec link rate"), 567 auich_sysctl_verify, 0, sc, 0, 568 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 569 if (err != 0) 570 goto sysctl_err; 571 sc->sc_ac97_clock_mib = node->sysctl_num; 572 573 return; 574 575 sysctl_err: 576 printf("%s: failed to add sysctl nodes. (%d)\n", 577 sc->sc_dev.dv_xname, err); 578 return; /* failure of sysctl is not fatal. */ 579 } 580 581 #if 0 582 int 583 auich_detach(struct device *self, int flags) 584 { 585 struct auich_softc *sc; 586 587 sc = (struct auich_softc *)self; 588 /* sysctl */ 589 sysctl_teardown(&sc->sc_log); 590 /* audio */ 591 if (sc->sc_audiodev != NULL) 592 config_detach(sc->sc_audiodev, flags); 593 /* XXX ac97 */ 594 /* XXX memory */ 595 return 0; 596 } 597 #endif 598 599 static int 600 auich_sysctl_verify(SYSCTLFN_ARGS) 601 { 602 int error, tmp; 603 struct sysctlnode node; 604 struct auich_softc *sc; 605 606 node = *rnode; 607 sc = rnode->sysctl_data; 608 tmp = sc->sc_ac97_clock; 609 node.sysctl_data = &tmp; 610 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 611 if (error || newp == NULL) 612 return error; 613 614 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 615 if (tmp < 48000 || tmp > 96000) 616 return EINVAL; 617 sc->sc_ac97_clock = tmp; 618 } 619 620 return 0; 621 } 622 623 void 624 auich_finish_attach(struct device *self) 625 { 626 struct auich_softc *sc = (void *)self; 627 628 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 629 auich_calibrate(sc); 630 631 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 632 } 633 634 #define ICH_CODECIO_INTERVAL 10 635 int 636 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 637 { 638 struct auich_softc *sc = v; 639 int i; 640 uint32_t status; 641 642 /* wait for an access semaphore */ 643 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 644 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 645 DELAY(ICH_CODECIO_INTERVAL)); 646 647 if (i > 0) { 648 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 649 DPRINTF(ICH_DEBUG_CODECIO, 650 ("auich_read_codec(%x, %x)\n", reg, *val)); 651 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 652 if (status & ICH_RCS) { 653 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, 654 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 655 *val = 0xffff; 656 DPRINTF(ICH_DEBUG_CODECIO, 657 ("%s: read_codec error\n", sc->sc_dev.dv_xname)); 658 return -1; 659 } 660 return 0; 661 } else { 662 DPRINTF(ICH_DEBUG_CODECIO, 663 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 664 return -1; 665 } 666 } 667 668 int 669 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 670 { 671 struct auich_softc *sc = v; 672 int i; 673 674 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 675 /* wait for an access semaphore */ 676 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 677 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; 678 DELAY(ICH_CODECIO_INTERVAL)); 679 680 if (i > 0) { 681 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 682 return 0; 683 } else { 684 DPRINTF(ICH_DEBUG_CODECIO, 685 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 686 return -1; 687 } 688 } 689 690 int 691 auich_attach_codec(void *v, struct ac97_codec_if *cif) 692 { 693 struct auich_softc *sc = v; 694 695 sc->codec_if = cif; 696 return 0; 697 } 698 699 int 700 auich_reset_codec(void *v) 701 { 702 struct auich_softc *sc = v; 703 int i; 704 uint32_t control, status; 705 706 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 707 control &= ~(ICH_ACLSO | ICH_PCM246_MASK); 708 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 709 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 710 711 for (i = 500000; i >= 0; i--) { 712 status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 713 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 714 break; 715 DELAY(1); 716 } 717 if (i <= 0) { 718 printf("%s: auich_reset_codec: time out\n", sc->sc_dev.dv_xname); 719 return ETIMEDOUT; 720 } 721 #ifdef DEBUG 722 if (status & ICH_SCR) 723 printf("%s: The 2nd codec is ready.\n", 724 sc->sc_dev.dv_xname); 725 if (status & ICH_S2CR) 726 printf("%s: The 3rd codec is ready.\n", 727 sc->sc_dev.dv_xname); 728 #endif 729 return 0; 730 } 731 732 int 733 auich_open(void *v, int flags) 734 { 735 return 0; 736 } 737 738 void 739 auich_close(void *v) 740 { 741 } 742 743 int 744 auich_query_encoding(void *v, struct audio_encoding *aep) 745 { 746 struct auich_softc *sc; 747 748 sc = (struct auich_softc *)v; 749 return auconv_query_encoding(sc->sc_encodings, aep); 750 } 751 752 int 753 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 754 { 755 int ret; 756 u_long ratetmp; 757 758 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 759 ratetmp = srate; 760 if (mode == AUMODE_RECORD) 761 return sc->codec_if->vtbl->set_rate(sc->codec_if, 762 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 763 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 764 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 765 if (ret) 766 return ret; 767 ratetmp = srate; 768 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 769 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 770 if (ret) 771 return ret; 772 ratetmp = srate; 773 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 774 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 775 return ret; 776 } 777 778 int 779 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 780 struct audio_params *rec) 781 { 782 struct auich_softc *sc = v; 783 struct audio_params *p; 784 int mode, index; 785 u_int32_t control; 786 787 for (mode = AUMODE_RECORD; mode != -1; 788 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 789 if ((setmode & mode) == 0) 790 continue; 791 792 p = mode == AUMODE_PLAY ? play : rec; 793 if (p == NULL) 794 continue; 795 796 if (p->sample_rate < 8000 || 797 p->sample_rate > 48000) 798 return (EINVAL); 799 800 index = auconv_set_converter(sc->sc_formats, AUICH_NFORMATS, 801 mode, p, TRUE); 802 if (index < 0) 803 return EINVAL; 804 if (sc->sc_formats[index].frequency_type != 1 805 && auich_set_rate(sc, mode, p->hw_sample_rate)) 806 return EINVAL; 807 if (mode == AUMODE_PLAY) { 808 control = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GCTRL); 809 control &= ~ICH_PCM246_MASK; 810 if (p->hw_channels == 4) { 811 control |= ICH_PCM4; 812 } else if (p->hw_channels == 6) { 813 control |= ICH_PCM6; 814 } 815 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, control); 816 } 817 } 818 819 return (0); 820 } 821 822 int 823 auich_round_blocksize(void *v, int blk) 824 { 825 826 return (blk & ~0x3f); /* keep good alignment */ 827 } 828 829 int 830 auich_halt_output(void *v) 831 { 832 struct auich_softc *sc = v; 833 834 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 835 836 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 837 sc->pcmo.intr = NULL; 838 839 return (0); 840 } 841 842 int 843 auich_halt_input(void *v) 844 { 845 struct auich_softc *sc = v; 846 847 DPRINTF(ICH_DEBUG_DMA, 848 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 849 850 /* XXX halt both unless known otherwise */ 851 852 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 853 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 854 sc->pcmi.intr = NULL; 855 856 return (0); 857 } 858 859 int 860 auich_getdev(void *v, struct audio_device *adp) 861 { 862 struct auich_softc *sc = v; 863 864 *adp = sc->sc_audev; 865 return (0); 866 } 867 868 int 869 auich_set_port(void *v, mixer_ctrl_t *cp) 870 { 871 struct auich_softc *sc = v; 872 873 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 874 } 875 876 int 877 auich_get_port(void *v, mixer_ctrl_t *cp) 878 { 879 struct auich_softc *sc = v; 880 881 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 882 } 883 884 int 885 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 886 { 887 struct auich_softc *sc = v; 888 889 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 890 } 891 892 void * 893 auich_allocm(void *v, int direction, size_t size, struct malloc_type *pool, 894 int flags) 895 { 896 struct auich_softc *sc = v; 897 struct auich_dma *p; 898 int error; 899 900 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 901 return (NULL); 902 903 p = malloc(sizeof(*p), pool, flags|M_ZERO); 904 if (p == NULL) 905 return (NULL); 906 907 error = auich_allocmem(sc, size, 0, p); 908 if (error) { 909 free(p, pool); 910 return (NULL); 911 } 912 913 p->next = sc->sc_dmas; 914 sc->sc_dmas = p; 915 916 return (KERNADDR(p)); 917 } 918 919 void 920 auich_freem(void *v, void *ptr, struct malloc_type *pool) 921 { 922 struct auich_softc *sc = v; 923 struct auich_dma *p, **pp; 924 925 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 926 if (KERNADDR(p) == ptr) { 927 auich_freemem(sc, p); 928 *pp = p->next; 929 free(p, pool); 930 return; 931 } 932 } 933 } 934 935 size_t 936 auich_round_buffersize(void *v, int direction, size_t size) 937 { 938 939 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 940 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 941 942 return size; 943 } 944 945 paddr_t 946 auich_mappage(void *v, void *mem, off_t off, int prot) 947 { 948 struct auich_softc *sc = v; 949 struct auich_dma *p; 950 951 if (off < 0) 952 return (-1); 953 954 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 955 ; 956 if (!p) 957 return (-1); 958 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 959 off, prot, BUS_DMA_WAITOK)); 960 } 961 962 int 963 auich_get_props(void *v) 964 { 965 struct auich_softc *sc = v; 966 int props; 967 968 props = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 969 /* 970 * Even if the codec is fixed-rate, set_param() succeeds for any sample 971 * rate because of aurateconv. Applications can't know what rate the 972 * device can process in the case of mmap(). 973 */ 974 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 975 props |= AUDIO_PROP_MMAP; 976 return props; 977 } 978 979 int 980 auich_intr(void *v) 981 { 982 struct auich_softc *sc = v; 983 int ret = 0, gsts; 984 985 #ifdef DIAGNOSTIC 986 int csts; 987 #endif 988 989 #ifdef DIAGNOSTIC 990 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 991 if (csts & PCI_STATUS_MASTER_ABORT) { 992 printf("auich_intr: PCI master abort\n"); 993 } 994 #endif 995 996 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS); 997 DPRINTF(ICH_DEBUG_INTR, ("auich_intr: gsts=0x%x\n", gsts)); 998 999 if (gsts & ICH_POINT) { 1000 int sts; 1001 1002 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1003 ICH_PCMO + sc->sc_sts_reg); 1004 DPRINTF(ICH_DEBUG_INTR, 1005 ("auich_intr: osts=0x%x\n", sts)); 1006 1007 if (sts & ICH_FIFOE) 1008 printf("%s: fifo underrun\n", sc->sc_dev.dv_xname); 1009 1010 if (sts & ICH_BCIS) { 1011 struct auich_dmalist *q; 1012 int blksize, qptr, i; 1013 1014 blksize = sc->pcmo.blksize; 1015 qptr = sc->pcmo.qptr; 1016 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1017 ICH_PCMO + ICH_CIV); 1018 1019 while (qptr != i) { 1020 q = &sc->pcmo.dmalist[qptr]; 1021 1022 q->base = sc->pcmo.p; 1023 q->len = (blksize >> sc->sc_sample_shift) | 1024 ICH_DMAF_IOC; 1025 DPRINTF(ICH_DEBUG_INTR, 1026 ("auich_intr: %p, %p = %x @ 0x%x\n", 1027 &sc->pcmo.dmalist[i], q, q->len, q->base)); 1028 1029 sc->pcmo.p += blksize; 1030 if (sc->pcmo.p >= sc->pcmo.end) 1031 sc->pcmo.p = sc->pcmo.start; 1032 1033 qptr = (qptr + 1) & ICH_LVI_MASK; 1034 if (sc->pcmo.intr) 1035 sc->pcmo.intr(sc->pcmo.arg); 1036 } 1037 1038 sc->pcmo.qptr = qptr; 1039 bus_space_write_1(sc->iot, sc->aud_ioh, 1040 ICH_PCMO + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1041 } 1042 1043 /* int ack */ 1044 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1045 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1046 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 1047 ret++; 1048 } 1049 1050 if (gsts & ICH_PIINT) { 1051 int sts; 1052 1053 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1054 ICH_PCMI + sc->sc_sts_reg); 1055 DPRINTF(ICH_DEBUG_INTR, 1056 ("auich_intr: ists=0x%x\n", sts)); 1057 1058 if (sts & ICH_FIFOE) 1059 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1060 1061 if (sts & ICH_BCIS) { 1062 struct auich_dmalist *q; 1063 int blksize, qptr, i; 1064 1065 blksize = sc->pcmi.blksize; 1066 qptr = sc->pcmi.qptr; 1067 i = bus_space_read_1(sc->iot, sc->aud_ioh, 1068 ICH_PCMI + ICH_CIV); 1069 1070 while (qptr != i) { 1071 q = &sc->pcmi.dmalist[qptr]; 1072 1073 q->base = sc->pcmi.p; 1074 q->len = (blksize >> sc->sc_sample_shift) | 1075 ICH_DMAF_IOC; 1076 DPRINTF(ICH_DEBUG_INTR, 1077 ("auich_intr: %p, %p = %x @ 0x%x\n", 1078 &sc->pcmi.dmalist[i], q, q->len, q->base)); 1079 1080 sc->pcmi.p += blksize; 1081 if (sc->pcmi.p >= sc->pcmi.end) 1082 sc->pcmi.p = sc->pcmi.start; 1083 1084 qptr = (qptr + 1) & ICH_LVI_MASK; 1085 if (sc->pcmi.intr) 1086 sc->pcmi.intr(sc->pcmi.arg); 1087 } 1088 1089 sc->pcmi.qptr = qptr; 1090 bus_space_write_1(sc->iot, sc->aud_ioh, 1091 ICH_PCMI + ICH_LVI, (qptr - 1) & ICH_LVI_MASK); 1092 } 1093 1094 /* int ack */ 1095 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1096 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1097 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_PIINT); 1098 ret++; 1099 } 1100 1101 if (gsts & ICH_MIINT) { 1102 int sts; 1103 1104 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1105 ICH_MICI + sc->sc_sts_reg); 1106 DPRINTF(ICH_DEBUG_INTR, 1107 ("auich_intr: ists=0x%x\n", sts)); 1108 1109 if (sts & ICH_FIFOE) 1110 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 1111 1112 /* TODO mic input DMA */ 1113 1114 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 1115 } 1116 1117 return ret; 1118 } 1119 1120 int 1121 auich_trigger_output(void *v, void *start, void *end, int blksize, 1122 void (*intr)(void *), void *arg, struct audio_params *param) 1123 { 1124 struct auich_softc *sc = v; 1125 struct auich_dmalist *q; 1126 struct auich_dma *p; 1127 size_t size; 1128 int qptr; 1129 #ifdef DIAGNOSTIC 1130 int csts; 1131 #endif 1132 1133 DPRINTF(ICH_DEBUG_DMA, 1134 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 1135 start, end, blksize, intr, arg, param)); 1136 1137 sc->pcmo.intr = intr; 1138 sc->pcmo.arg = arg; 1139 #ifdef DIAGNOSTIC 1140 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1141 if (csts & PCI_STATUS_MASTER_ABORT) { 1142 printf("auich_trigger_output: PCI master abort\n"); 1143 } 1144 #endif 1145 1146 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1147 ; 1148 if (!p) { 1149 printf("auich_trigger_output: bad addr %p\n", start); 1150 return (EINVAL); 1151 } 1152 1153 size = (size_t)((caddr_t)end - (caddr_t)start); 1154 1155 /* 1156 * The logic behind this is: 1157 * setup one buffer to play, then LVI dump out the rest 1158 * to the scatter-gather chain. 1159 */ 1160 sc->pcmo.start = DMAADDR(p); 1161 sc->pcmo.p = sc->pcmo.start; 1162 sc->pcmo.end = sc->pcmo.start + size; 1163 sc->pcmo.blksize = blksize; 1164 1165 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1166 q = &sc->pcmo.dmalist[qptr]; 1167 1168 q->base = sc->pcmo.p; 1169 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1170 1171 sc->pcmo.p += blksize; 1172 if (sc->pcmo.p >= sc->pcmo.end) 1173 sc->pcmo.p = sc->pcmo.start; 1174 } 1175 1176 sc->pcmo.qptr = qptr = 0; 1177 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 1178 (qptr - 1) & ICH_LVI_MASK); 1179 1180 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1181 sc->sc_cddma + ICH_PCMO_OFF(0)); 1182 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 1183 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1184 1185 return (0); 1186 } 1187 1188 int 1189 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1190 void *v; 1191 void *start, *end; 1192 int blksize; 1193 void (*intr)(void *); 1194 void *arg; 1195 struct audio_params *param; 1196 { 1197 struct auich_softc *sc = v; 1198 struct auich_dmalist *q; 1199 struct auich_dma *p; 1200 size_t size; 1201 int qptr; 1202 #ifdef DIAGNOSTIC 1203 int csts; 1204 #endif 1205 1206 DPRINTF(ICH_DEBUG_DMA, 1207 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 1208 start, end, blksize, intr, arg, param)); 1209 1210 sc->pcmi.intr = intr; 1211 sc->pcmi.arg = arg; 1212 1213 #ifdef DIAGNOSTIC 1214 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1215 if (csts & PCI_STATUS_MASTER_ABORT) { 1216 printf("auich_trigger_input: PCI master abort\n"); 1217 } 1218 #endif 1219 1220 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1221 ; 1222 if (!p) { 1223 printf("auich_trigger_input: bad addr %p\n", start); 1224 return (EINVAL); 1225 } 1226 1227 size = (size_t)((caddr_t)end - (caddr_t)start); 1228 1229 /* 1230 * The logic behind this is: 1231 * setup one buffer to play, then LVI dump out the rest 1232 * to the scatter-gather chain. 1233 */ 1234 sc->pcmi.start = DMAADDR(p); 1235 sc->pcmi.p = sc->pcmi.start; 1236 sc->pcmi.end = sc->pcmi.start + size; 1237 sc->pcmi.blksize = blksize; 1238 1239 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1240 q = &sc->pcmi.dmalist[qptr]; 1241 1242 q->base = sc->pcmi.p; 1243 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1244 1245 sc->pcmi.p += blksize; 1246 if (sc->pcmi.p >= sc->pcmi.end) 1247 sc->pcmi.p = sc->pcmi.start; 1248 } 1249 1250 sc->pcmi.qptr = qptr = 0; 1251 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1252 (qptr - 1) & ICH_LVI_MASK); 1253 1254 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1255 sc->sc_cddma + ICH_PCMI_OFF(0)); 1256 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1257 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1258 1259 return (0); 1260 } 1261 1262 int 1263 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1264 struct auich_dma *p) 1265 { 1266 int error; 1267 1268 p->size = size; 1269 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1270 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1271 &p->nsegs, BUS_DMA_NOWAIT); 1272 if (error) 1273 return (error); 1274 1275 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1276 &p->addr, BUS_DMA_NOWAIT|sc->sc_dmamap_flags); 1277 if (error) 1278 goto free; 1279 1280 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1281 0, BUS_DMA_NOWAIT, &p->map); 1282 if (error) 1283 goto unmap; 1284 1285 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1286 BUS_DMA_NOWAIT); 1287 if (error) 1288 goto destroy; 1289 return (0); 1290 1291 destroy: 1292 bus_dmamap_destroy(sc->dmat, p->map); 1293 unmap: 1294 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1295 free: 1296 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1297 return (error); 1298 } 1299 1300 int 1301 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1302 { 1303 1304 bus_dmamap_unload(sc->dmat, p->map); 1305 bus_dmamap_destroy(sc->dmat, p->map); 1306 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1307 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1308 return (0); 1309 } 1310 1311 int 1312 auich_alloc_cdata(struct auich_softc *sc) 1313 { 1314 bus_dma_segment_t seg; 1315 int error, rseg; 1316 1317 /* 1318 * Allocate the control data structure, and create and load the 1319 * DMA map for it. 1320 */ 1321 if ((error = bus_dmamem_alloc(sc->dmat, 1322 sizeof(struct auich_cdata), 1323 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1324 printf("%s: unable to allocate control data, error = %d\n", 1325 sc->sc_dev.dv_xname, error); 1326 goto fail_0; 1327 } 1328 1329 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1330 sizeof(struct auich_cdata), 1331 (caddr_t *) &sc->sc_cdata, 1332 sc->sc_dmamap_flags)) != 0) { 1333 printf("%s: unable to map control data, error = %d\n", 1334 sc->sc_dev.dv_xname, error); 1335 goto fail_1; 1336 } 1337 1338 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1339 sizeof(struct auich_cdata), 0, 0, 1340 &sc->sc_cddmamap)) != 0) { 1341 printf("%s: unable to create control data DMA map, " 1342 "error = %d\n", sc->sc_dev.dv_xname, error); 1343 goto fail_2; 1344 } 1345 1346 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1347 sc->sc_cdata, sizeof(struct auich_cdata), 1348 NULL, 0)) != 0) { 1349 printf("%s: unable tp load control data DMA map, " 1350 "error = %d\n", sc->sc_dev.dv_xname, error); 1351 goto fail_3; 1352 } 1353 1354 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1355 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1356 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1357 1358 return (0); 1359 1360 fail_3: 1361 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1362 fail_2: 1363 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1364 sizeof(struct auich_cdata)); 1365 fail_1: 1366 bus_dmamem_free(sc->dmat, &seg, rseg); 1367 fail_0: 1368 return (error); 1369 } 1370 1371 void 1372 auich_powerhook(int why, void *addr) 1373 { 1374 struct auich_softc *sc = (struct auich_softc *)addr; 1375 1376 switch (why) { 1377 case PWR_SUSPEND: 1378 case PWR_STANDBY: 1379 /* Power down */ 1380 DPRINTF(1, ("%s: power down\n", sc->sc_dev.dv_xname)); 1381 sc->sc_suspend = why; 1382 break; 1383 1384 case PWR_RESUME: 1385 /* Wake up */ 1386 DPRINTF(1, ("%s: power resume\n", sc->sc_dev.dv_xname)); 1387 if (sc->sc_suspend == PWR_RESUME) { 1388 printf("%s: resume without suspend.\n", 1389 sc->sc_dev.dv_xname); 1390 sc->sc_suspend = why; 1391 return; 1392 } 1393 sc->sc_suspend = why; 1394 auich_reset_codec(sc); 1395 DELAY(1000); 1396 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1397 break; 1398 1399 case PWR_SOFTSUSPEND: 1400 case PWR_SOFTSTANDBY: 1401 case PWR_SOFTRESUME: 1402 break; 1403 } 1404 } 1405 1406 /* 1407 * Calibrate card (some boards are overclocked and need scaling) 1408 */ 1409 void 1410 auich_calibrate(struct auich_softc *sc) 1411 { 1412 struct timeval t1, t2; 1413 uint8_t ociv, nciv; 1414 uint64_t wait_us; 1415 uint32_t actual_48k_rate, bytes, ac97rate; 1416 void *temp_buffer; 1417 struct auich_dma *p; 1418 u_long rate; 1419 1420 /* 1421 * Grab audio from input for fixed interval and compare how 1422 * much we actually get with what we expect. Interval needs 1423 * to be sufficiently short that no interrupts are 1424 * generated. 1425 */ 1426 1427 /* Force the codec to a known state first. */ 1428 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1429 rate = sc->sc_ac97_clock = 48000; 1430 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1431 &rate); 1432 1433 /* Setup a buffer */ 1434 bytes = 64000; 1435 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes, M_DEVBUF, M_WAITOK); 1436 1437 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1438 ; 1439 if (p == NULL) { 1440 printf("auich_calibrate: bad address %p\n", temp_buffer); 1441 return; 1442 } 1443 sc->pcmi.dmalist[0].base = DMAADDR(p); 1444 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1445 1446 /* 1447 * our data format is stereo, 16 bit so each sample is 4 bytes. 1448 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1449 * we're going to start recording with interrupts disabled and measure 1450 * the time taken for one block to complete. we know the block size, 1451 * we know the time in microseconds, we calculate the sample rate: 1452 * 1453 * actual_rate [bps] = bytes / (time [s] * 4) 1454 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1455 * actual_rate [Hz] = (bytes * 250000) / time [us] 1456 */ 1457 1458 /* prepare */ 1459 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1460 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1461 sc->sc_cddma + ICH_PCMI_OFF(0)); 1462 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1463 (0 - 1) & ICH_LVI_MASK); 1464 1465 /* start */ 1466 microtime(&t1); 1467 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1468 1469 /* wait */ 1470 nciv = ociv; 1471 do { 1472 microtime(&t2); 1473 if (t2.tv_sec - t1.tv_sec > 1) 1474 break; 1475 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1476 ICH_PCMI + ICH_CIV); 1477 } while (nciv == ociv); 1478 microtime(&t2); 1479 1480 /* stop */ 1481 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1482 1483 /* reset */ 1484 DELAY(100); 1485 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1486 1487 /* turn time delta into us */ 1488 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1489 1490 auich_freem(sc, temp_buffer, M_DEVBUF); 1491 1492 if (nciv == ociv) { 1493 printf("%s: ac97 link rate calibration timed out after %" 1494 PRIu64 " us\n", sc->sc_dev.dv_xname, wait_us); 1495 return; 1496 } 1497 1498 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1499 1500 if (actual_48k_rate < 50000) 1501 ac97rate = 48000; 1502 else 1503 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1504 1505 printf("%s: measured ac97 link rate at %d Hz", 1506 sc->sc_dev.dv_xname, actual_48k_rate); 1507 if (ac97rate != actual_48k_rate) 1508 printf(", will use %d Hz", ac97rate); 1509 printf("\n"); 1510 1511 sc->sc_ac97_clock = ac97rate; 1512 } 1513