1 /* $NetBSD: auich.c,v 1.8 2002/01/14 01:29:13 augustss Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 2000 Michael Shalayeff 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 58 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 59 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 60 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 62 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 63 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 64 * THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 67 */ 68 69 /* #define ICH_DEBUG */ 70 /* 71 * AC'97 audio found on Intel 810/820/440MX chipsets. 72 * http://developer.intel.com/design/chipsets/datashts/290655.htm 73 * http://developer.intel.com/design/chipsets/manuals/298028.htm 74 * 75 * TODO: 76 * 77 * - Probe codecs for supported sample rates. 78 * 79 * - Add support for the microphone input. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.8 2002/01/14 01:29:13 augustss Exp $"); 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kernel.h> 88 #include <sys/malloc.h> 89 #include <sys/device.h> 90 #include <sys/fcntl.h> 91 #include <sys/proc.h> 92 93 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/auichreg.h> 98 99 #include <sys/audioio.h> 100 #include <dev/audio_if.h> 101 #include <dev/mulaw.h> 102 #include <dev/auconv.h> 103 104 #include <machine/bus.h> 105 106 #include <dev/ic/ac97reg.h> 107 #include <dev/ic/ac97var.h> 108 109 struct auich_dma { 110 bus_dmamap_t map; 111 caddr_t addr; 112 bus_dma_segment_t segs[1]; 113 int nsegs; 114 size_t size; 115 struct auich_dma *next; 116 }; 117 118 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 119 #define KERNADDR(p) ((void *)((p)->addr)) 120 121 struct auich_cdata { 122 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 123 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 124 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 125 }; 126 127 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 128 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 129 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 130 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 131 132 struct auich_softc { 133 struct device sc_dev; 134 void *sc_ih; 135 136 audio_device_t sc_audev; 137 138 bus_space_tag_t iot; 139 bus_space_handle_t mix_ioh; 140 bus_space_handle_t aud_ioh; 141 bus_dma_tag_t dmat; 142 143 struct ac97_codec_if *codec_if; 144 struct ac97_host_if host_if; 145 146 /* DMA scatter-gather lists. */ 147 bus_dmamap_t sc_cddmamap; 148 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 149 150 struct auich_cdata *sc_cdata; 151 #define dmalist_pcmo sc_cdata->ic_dmalist_pcmo 152 #define dmalist_pcmi sc_cdata->ic_dmalist_pcmi 153 #define dmalist_mici sc_cdata->ic_dmalist_mici 154 155 int ptr_pcmo, 156 ptr_pcmi, 157 ptr_mici; 158 159 /* i/o buffer pointers */ 160 u_int32_t pcmo_start, pcmo_p, pcmo_end; 161 int pcmo_blksize, pcmo_fifoe; 162 163 u_int32_t pcmi_start, pcmi_p, pcmi_end; 164 int pcmi_blksize, pcmi_fifoe; 165 166 u_int32_t mici_start, mici_p, mici_end; 167 int mici_blksize, mici_fifoe; 168 169 struct auich_dma *sc_dmas; 170 171 void (*sc_pintr)(void *); 172 void *sc_parg; 173 174 void (*sc_rintr)(void *); 175 void *sc_rarg; 176 }; 177 178 /* Debug */ 179 #ifdef AUDIO_DEBUG 180 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 181 int auich_debug = 0xfffe; 182 #define ICH_DEBUG_CODECIO 0x0001 183 #define ICH_DEBUG_DMA 0x0002 184 #define ICH_DEBUG_PARAM 0x0004 185 #else 186 #define DPRINTF(x,y) /* nothing */ 187 #endif 188 189 int auich_match(struct device *, struct cfdata *, void *); 190 void auich_attach(struct device *, struct device *, void *); 191 int auich_intr(void *); 192 193 struct cfattach auich_ca = { 194 sizeof(struct auich_softc), auich_match, auich_attach 195 }; 196 197 int auich_open(void *, int); 198 void auich_close(void *); 199 int auich_query_encoding(void *, struct audio_encoding *); 200 int auich_set_params(void *, int, int, struct audio_params *, 201 struct audio_params *); 202 int auich_round_blocksize(void *, int); 203 int auich_halt_output(void *); 204 int auich_halt_input(void *); 205 int auich_getdev(void *, struct audio_device *); 206 int auich_set_port(void *, mixer_ctrl_t *); 207 int auich_get_port(void *, mixer_ctrl_t *); 208 int auich_query_devinfo(void *, mixer_devinfo_t *); 209 void *auich_allocm(void *, int, size_t, int, int); 210 void auich_freem(void *, void *, int); 211 size_t auich_round_buffersize(void *, int, size_t); 212 paddr_t auich_mappage(void *, void *, off_t, int); 213 int auich_get_props(void *); 214 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 215 void *, struct audio_params *); 216 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 217 void *, struct audio_params *); 218 219 int auich_alloc_cdata(struct auich_softc *); 220 221 int auich_allocmem(struct auich_softc *, size_t, size_t, 222 struct auich_dma *); 223 int auich_freemem(struct auich_softc *, struct auich_dma *); 224 225 struct audio_hw_if auich_hw_if = { 226 auich_open, 227 auich_close, 228 NULL, /* drain */ 229 auich_query_encoding, 230 auich_set_params, 231 auich_round_blocksize, 232 NULL, /* commit_setting */ 233 NULL, /* init_output */ 234 NULL, /* init_input */ 235 NULL, /* start_output */ 236 NULL, /* start_input */ 237 auich_halt_output, 238 auich_halt_input, 239 NULL, /* speaker_ctl */ 240 auich_getdev, 241 NULL, /* getfd */ 242 auich_set_port, 243 auich_get_port, 244 auich_query_devinfo, 245 auich_allocm, 246 auich_freem, 247 auich_round_buffersize, 248 auich_mappage, 249 auich_get_props, 250 auich_trigger_output, 251 auich_trigger_input, 252 NULL, /* dev_ioctl */ 253 }; 254 255 int auich_attach_codec(void *, struct ac97_codec_if *); 256 int auich_read_codec(void *, u_int8_t, u_int16_t *); 257 int auich_write_codec(void *, u_int8_t, u_int16_t); 258 void auich_reset_codec(void *); 259 260 static const struct auich_devtype { 261 int product; 262 const char *name; 263 const char *shortname; 264 } auich_devices[] = { 265 { PCI_PRODUCT_INTEL_82801AA_ACA, 266 "i82801AA (ICH) AC-97 Audio", "ICH" }, 267 { PCI_PRODUCT_INTEL_82801AB_ACA, 268 "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 269 { PCI_PRODUCT_INTEL_82801BA_ACA, 270 "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 271 { PCI_PRODUCT_INTEL_82440MX_ACA, 272 "i82440MX AC-97 Audio", "440MX" }, 273 { PCI_PRODUCT_INTEL_82801CA_AC, 274 "i82801CA AC-97 Audio", "i830M" }, 275 276 { 0, 277 NULL, NULL }, 278 }; 279 280 static const struct auich_devtype * 281 auich_lookup(struct pci_attach_args *pa) 282 { 283 const struct auich_devtype *d; 284 285 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) 286 return (NULL); 287 288 for (d = auich_devices; d->name != NULL; d++) { 289 if (PCI_PRODUCT(pa->pa_id) == d->product) 290 return (d); 291 } 292 293 return (NULL); 294 } 295 296 int 297 auich_match(struct device *parent, struct cfdata *match, void *aux) 298 { 299 struct pci_attach_args *pa = aux; 300 301 if (auich_lookup(pa) != NULL) 302 return (1); 303 304 return (0); 305 } 306 307 void 308 auich_attach(struct device *parent, struct device *self, void *aux) 309 { 310 struct auich_softc *sc = (struct auich_softc *)self; 311 struct pci_attach_args *pa = aux; 312 pci_intr_handle_t ih; 313 bus_size_t mix_size, aud_size; 314 pcireg_t csr; 315 const char *intrstr; 316 const struct auich_devtype *d; 317 318 d = auich_lookup(pa); 319 if (d == NULL) 320 panic("auich_attach: impossible"); 321 322 printf(": %s\n", d->name); 323 324 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 325 &sc->iot, &sc->mix_ioh, NULL, &mix_size)) { 326 printf("%s: can't map codec i/o space\n", 327 sc->sc_dev.dv_xname); 328 return; 329 } 330 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 331 &sc->iot, &sc->aud_ioh, NULL, &aud_size)) { 332 printf("%s: can't map device i/o space\n", 333 sc->sc_dev.dv_xname); 334 return; 335 } 336 sc->dmat = pa->pa_dmat; 337 338 /* enable bus mastering */ 339 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 340 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 341 csr | PCI_COMMAND_MASTER_ENABLE); 342 343 /* Map and establish the interrupt. */ 344 if (pci_intr_map(pa, &ih)) { 345 printf("%s: can't map interrupt\n", sc->sc_dev.dv_xname); 346 return; 347 } 348 intrstr = pci_intr_string(pa->pa_pc, ih); 349 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, 350 auich_intr, sc); 351 if (sc->sc_ih == NULL) { 352 printf("%s: can't establish interrupt", sc->sc_dev.dv_xname); 353 if (intrstr != NULL) 354 printf(" at %s", intrstr); 355 printf("\n"); 356 return; 357 } 358 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 359 360 sprintf(sc->sc_audev.name, "%s AC97", d->shortname); 361 sprintf(sc->sc_audev.version, "0x%02x", PCI_REVISION(pa->pa_class)); 362 strcpy(sc->sc_audev.config, sc->sc_dev.dv_xname); 363 364 /* Set up DMA lists. */ 365 sc->ptr_pcmo = sc->ptr_pcmi = sc->ptr_mici = 0; 366 auich_alloc_cdata(sc); 367 368 DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 369 sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici)); 370 371 /* Reset codec and AC'97 */ 372 auich_reset_codec(sc); 373 374 sc->host_if.arg = sc; 375 sc->host_if.attach = auich_attach_codec; 376 sc->host_if.read = auich_read_codec; 377 sc->host_if.write = auich_write_codec; 378 sc->host_if.reset = auich_reset_codec; 379 380 if (ac97_attach(&sc->host_if) != 0) 381 return; 382 383 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 384 } 385 386 int 387 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 388 { 389 struct auich_softc *sc = v; 390 int i; 391 392 /* wait for an access semaphore */ 393 for (i = ICH_SEMATIMO; i-- && 394 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; DELAY(1)); 395 396 if (i > 0) { 397 *val = bus_space_read_2(sc->iot, sc->mix_ioh, reg); 398 DPRINTF(ICH_DEBUG_CODECIO, 399 ("auich_read_codec(%x, %x)\n", reg, *val)); 400 401 return 0; 402 } else { 403 DPRINTF(ICH_DEBUG_CODECIO, 404 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 405 return -1; 406 } 407 } 408 409 int 410 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 411 { 412 struct auich_softc *sc = v; 413 int i; 414 415 DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val)); 416 417 /* wait for an access semaphore */ 418 for (i = ICH_SEMATIMO; i-- && 419 bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1; DELAY(1)); 420 421 if (i > 0) { 422 bus_space_write_2(sc->iot, sc->mix_ioh, reg, val); 423 return 0; 424 } else { 425 DPRINTF(ICH_DEBUG_CODECIO, 426 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 427 return -1; 428 } 429 } 430 431 int 432 auich_attach_codec(void *v, struct ac97_codec_if *cif) 433 { 434 struct auich_softc *sc = v; 435 436 sc->codec_if = cif; 437 return 0; 438 } 439 440 void 441 auich_reset_codec(void *v) 442 { 443 struct auich_softc *sc = v; 444 445 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, 0); 446 DELAY(10); 447 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_GCTRL, ICH_CRESET); 448 } 449 450 int 451 auich_open(void *v, int flags) 452 { 453 454 return 0; 455 } 456 457 void 458 auich_close(void *v) 459 { 460 struct auich_softc *sc = v; 461 462 auich_halt_output(sc); 463 auich_halt_input(sc); 464 465 sc->sc_pintr = NULL; 466 sc->sc_rintr = NULL; 467 } 468 469 int 470 auich_query_encoding(void *v, struct audio_encoding *aep) 471 { 472 473 #if 0 /* XXX Not until we emulate it. */ 474 switch (aep->index) { 475 case 0: 476 strcpy(aep->name, AudioEulinear); 477 aep->encoding = AUDIO_ENCODING_ULINEAR; 478 aep->precision = 8; 479 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 480 return (0); 481 #else 482 switch (aep->index + 1) { 483 #endif 484 case 1: 485 strcpy(aep->name, AudioEmulaw); 486 aep->encoding = AUDIO_ENCODING_ULAW; 487 aep->precision = 8; 488 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 489 return (0); 490 case 2: 491 strcpy(aep->name, AudioEalaw); 492 aep->encoding = AUDIO_ENCODING_ALAW; 493 aep->precision = 8; 494 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 495 return (0); 496 case 3: 497 strcpy(aep->name, AudioEslinear); 498 aep->encoding = AUDIO_ENCODING_SLINEAR; 499 aep->precision = 8; 500 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 501 return (0); 502 case 4: 503 strcpy(aep->name, AudioEslinear_le); 504 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 505 aep->precision = 16; 506 aep->flags = 0; 507 return (0); 508 case 5: 509 strcpy(aep->name, AudioEulinear_le); 510 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 511 aep->precision = 16; 512 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 513 return (0); 514 case 6: 515 strcpy(aep->name, AudioEslinear_be); 516 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 517 aep->precision = 16; 518 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 519 return (0); 520 case 7: 521 strcpy(aep->name, AudioEulinear_be); 522 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 523 aep->precision = 16; 524 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 525 return (0); 526 default: 527 return (EINVAL); 528 } 529 } 530 531 int 532 auich_set_params(void *v, int setmode, int usemode, struct audio_params *play, 533 struct audio_params *rec) 534 { 535 struct auich_softc *sc = v; 536 struct audio_params *p; 537 int mode; 538 u_int16_t val, rate, inout; 539 540 for (mode = AUMODE_RECORD; mode != -1; 541 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 542 if ((setmode & mode) == 0) 543 continue; 544 545 p = mode == AUMODE_PLAY ? play : rec; 546 if (p == NULL) 547 continue; 548 549 inout = mode == AUMODE_PLAY ? ICH_PM_PCMO : ICH_PM_PCMI; 550 551 /* 552 * XXX NEED TO DETERMINE WHICH RATES THE CODEC SUPPORTS! 553 */ 554 if (p->sample_rate != 48000) 555 return (EINVAL); 556 557 p->factor = 1; 558 p->sw_code = NULL; 559 switch (p->encoding) { 560 case AUDIO_ENCODING_SLINEAR_BE: 561 if (p->precision == 16) 562 p->sw_code = swap_bytes; 563 else { 564 if (mode == AUMODE_PLAY) 565 p->sw_code = linear8_to_linear16_le; 566 else 567 p->sw_code = linear16_to_linear8_le; 568 } 569 break; 570 571 case AUDIO_ENCODING_SLINEAR_LE: 572 if (p->precision != 16) { 573 if (mode == AUMODE_PLAY) 574 p->sw_code = linear8_to_linear16_le; 575 else 576 p->sw_code = linear16_to_linear8_le; 577 } 578 break; 579 580 case AUDIO_ENCODING_ULINEAR_BE: 581 if (p->precision == 16) { 582 if (mode == AUMODE_PLAY) 583 p->sw_code = 584 swap_bytes_change_sign16_le; 585 else 586 p->sw_code = 587 change_sign16_swap_bytes_le; 588 } else { 589 /* 590 * XXX ulinear8_to_slinear16_le 591 */ 592 return (EINVAL); 593 } 594 break; 595 596 case AUDIO_ENCODING_ULINEAR_LE: 597 if (p->precision == 16) 598 p->sw_code = change_sign16_le; 599 else { 600 /* 601 * XXX ulinear8_to_slinear16_le 602 */ 603 return (EINVAL); 604 } 605 break; 606 607 case AUDIO_ENCODING_ULAW: 608 if (mode == AUMODE_PLAY) { 609 p->factor = 2; 610 p->sw_code = mulaw_to_slinear16_le; 611 } else { 612 /* 613 * XXX slinear16_le_to_mulaw 614 */ 615 return (EINVAL); 616 } 617 break; 618 619 case AUDIO_ENCODING_ALAW: 620 if (mode == AUMODE_PLAY) { 621 p->factor = 2; 622 p->sw_code = alaw_to_slinear16_le; 623 } else { 624 /* 625 * XXX slinear16_le_to_alaw 626 */ 627 return (EINVAL); 628 } 629 break; 630 631 default: 632 return (EINVAL); 633 } 634 635 auich_read_codec(sc, AC97_REG_POWER, &val); 636 auich_write_codec(sc, AC97_REG_POWER, val | inout); 637 638 auich_write_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, 639 p->sample_rate); 640 auich_read_codec(sc, AC97_REG_PCM_FRONT_DAC_RATE, &rate); 641 p->sample_rate = rate; 642 643 auich_write_codec(sc, AC97_REG_POWER, val); 644 } 645 646 return (0); 647 } 648 649 int 650 auich_round_blocksize(void *v, int blk) 651 { 652 653 return (blk & ~0x3f); /* keep good alignment */ 654 } 655 656 int 657 auich_halt_output(void *v) 658 { 659 struct auich_softc *sc = v; 660 661 DPRINTF(ICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 662 663 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, ICH_RR); 664 665 return (0); 666 } 667 668 int 669 auich_halt_input(void *v) 670 { 671 struct auich_softc *sc = v; 672 673 DPRINTF(ICH_DEBUG_DMA, 674 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 675 676 /* XXX halt both unless known otherwise */ 677 678 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 679 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_MICI + ICH_CTRL, ICH_RR); 680 681 return (0); 682 } 683 684 int 685 auich_getdev(void *v, struct audio_device *adp) 686 { 687 struct auich_softc *sc = v; 688 689 *adp = sc->sc_audev; 690 return (0); 691 } 692 693 int 694 auich_set_port(void *v, mixer_ctrl_t *cp) 695 { 696 struct auich_softc *sc = v; 697 698 return (sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp)); 699 } 700 701 int 702 auich_get_port(void *v, mixer_ctrl_t *cp) 703 { 704 struct auich_softc *sc = v; 705 706 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 707 } 708 709 int 710 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 711 { 712 struct auich_softc *sc = v; 713 714 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp)); 715 } 716 717 void * 718 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 719 { 720 struct auich_softc *sc = v; 721 struct auich_dma *p; 722 int error; 723 724 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 725 return (NULL); 726 727 p = malloc(sizeof(*p), pool, flags|M_ZERO); 728 if (p == NULL) 729 return (NULL); 730 731 error = auich_allocmem(sc, size, 0, p); 732 if (error) { 733 free(p, pool); 734 return (NULL); 735 } 736 737 p->next = sc->sc_dmas; 738 sc->sc_dmas = p; 739 740 return (KERNADDR(p)); 741 } 742 743 void 744 auich_freem(void *v, void *ptr, int pool) 745 { 746 struct auich_softc *sc = v; 747 struct auich_dma *p, **pp; 748 749 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 750 if (KERNADDR(p) == ptr) { 751 auich_freemem(sc, p); 752 *pp = p->next; 753 free(p, pool); 754 return; 755 } 756 } 757 } 758 759 size_t 760 auich_round_buffersize(void *v, int direction, size_t size) 761 { 762 763 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 764 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 765 766 return size; 767 } 768 769 paddr_t 770 auich_mappage(void *v, void *mem, off_t off, int prot) 771 { 772 struct auich_softc *sc = v; 773 struct auich_dma *p; 774 775 if (off < 0) 776 return (-1); 777 778 for (p = sc->sc_dmas; p && KERNADDR(p) != mem; p = p->next) 779 ; 780 if (!p) 781 return (-1); 782 return (bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 783 off, prot, BUS_DMA_WAITOK)); 784 } 785 786 int 787 auich_get_props(void *v) 788 { 789 790 return (AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | 791 AUDIO_PROP_FULLDUPLEX); 792 } 793 794 int 795 auich_intr(void *v) 796 { 797 struct auich_softc *sc = v; 798 int ret = 0, sts, gsts, i, qptr; 799 800 gsts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_GSTS); 801 DPRINTF(ICH_DEBUG_DMA, ("auich_intr: gsts=0x%x\n", gsts)); 802 803 if (gsts & ICH_POINT) { 804 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMO+ICH_STS); 805 DPRINTF(ICH_DEBUG_DMA, 806 ("auich_intr: osts=0x%x\n", sts)); 807 808 if (sts & ICH_FIFOE) { 809 printf("%s: fifo underrun # %u\n", 810 sc->sc_dev.dv_xname, ++sc->pcmo_fifoe); 811 } 812 813 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CIV); 814 if (sts & (ICH_LVBCI | ICH_CELV)) { 815 struct auich_dmalist *q; 816 817 qptr = sc->ptr_pcmo; 818 819 while (qptr != i) { 820 q = &sc->dmalist_pcmo[qptr]; 821 822 q->base = sc->pcmo_p; 823 q->len = (sc->pcmo_blksize / 2) | ICH_DMAF_IOC; 824 DPRINTF(ICH_DEBUG_DMA, 825 ("auich_intr: %p, %p = %x @ 0x%x\n", 826 &sc->dmalist_pcmo[i], q, 827 sc->pcmo_blksize / 2, sc->pcmo_p)); 828 829 sc->pcmo_p += sc->pcmo_blksize; 830 if (sc->pcmo_p >= sc->pcmo_end) 831 sc->pcmo_p = sc->pcmo_start; 832 833 if (++qptr == ICH_DMALIST_MAX) 834 qptr = 0; 835 } 836 837 sc->ptr_pcmo = qptr; 838 bus_space_write_1(sc->iot, sc->aud_ioh, 839 ICH_PCMO + ICH_LVI, 840 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 841 } 842 843 if (sts & ICH_BCIS && sc->sc_pintr) 844 sc->sc_pintr(sc->sc_parg); 845 846 /* int ack */ 847 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_STS, 848 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 849 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 850 ret++; 851 } 852 853 if (gsts & ICH_PIINT) { 854 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_PCMI+ICH_STS); 855 DPRINTF(ICH_DEBUG_DMA, 856 ("auich_intr: ists=0x%x\n", sts)); 857 858 if (sts & ICH_FIFOE) { 859 printf("%s: fifo overrun # %u\n", 860 sc->sc_dev.dv_xname, ++sc->pcmi_fifoe); 861 } 862 863 i = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 864 if (sts & (ICH_LVBCI | ICH_CELV)) { 865 struct auich_dmalist *q; 866 867 qptr = sc->ptr_pcmi; 868 869 while (qptr != i) { 870 q = &sc->dmalist_pcmi[qptr]; 871 872 q->base = sc->pcmi_p; 873 q->len = (sc->pcmi_blksize / 2) | ICH_DMAF_IOC; 874 DPRINTF(ICH_DEBUG_DMA, 875 ("auich_intr: %p, %p = %x @ 0x%x\n", 876 &sc->dmalist_pcmi[i], q, 877 sc->pcmi_blksize / 2, sc->pcmi_p)); 878 879 sc->pcmi_p += sc->pcmi_blksize; 880 if (sc->pcmi_p >= sc->pcmi_end) 881 sc->pcmi_p = sc->pcmi_start; 882 883 if (++qptr == ICH_DMALIST_MAX) 884 qptr = 0; 885 } 886 887 sc->ptr_pcmi = qptr; 888 bus_space_write_1(sc->iot, sc->aud_ioh, 889 ICH_PCMI + ICH_LVI, 890 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 891 } 892 893 if (sts & ICH_BCIS && sc->sc_rintr) 894 sc->sc_rintr(sc->sc_rarg); 895 896 /* int ack */ 897 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_STS, 898 sts & (ICH_LVBCI | ICH_CELV | ICH_BCIS | ICH_FIFOE)); 899 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_POINT); 900 ret++; 901 } 902 903 if (gsts & ICH_MIINT) { 904 sts = bus_space_read_2(sc->iot, sc->aud_ioh, ICH_MICI+ICH_STS); 905 DPRINTF(ICH_DEBUG_DMA, 906 ("auich_intr: ists=0x%x\n", sts)); 907 if (sts & ICH_FIFOE) 908 printf("%s: fifo overrun\n", sc->sc_dev.dv_xname); 909 910 /* TODO mic input dma */ 911 912 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_GSTS, ICH_MIINT); 913 } 914 915 return ret; 916 } 917 918 int 919 auich_trigger_output(void *v, void *start, void *end, int blksize, 920 void (*intr)(void *), void *arg, struct audio_params *param) 921 { 922 struct auich_softc *sc = v; 923 struct auich_dmalist *q; 924 struct auich_dma *p; 925 size_t size; 926 927 DPRINTF(ICH_DEBUG_DMA, 928 ("auich_trigger_output(%p, %p, %d, %p, %p, %p)\n", 929 start, end, blksize, intr, arg, param)); 930 931 sc->sc_pintr = intr; 932 sc->sc_parg = arg; 933 934 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 935 ; 936 if (!p) { 937 printf("auich_trigger_output: bad addr %p\n", start); 938 return (EINVAL); 939 } 940 941 size = (size_t)((caddr_t)end - (caddr_t)start); 942 943 /* 944 * The logic behind this is: 945 * setup one buffer to play, then LVI dump out the rest 946 * to the scatter-gather chain. 947 */ 948 sc->pcmo_start = DMAADDR(p); 949 sc->pcmo_p = sc->pcmo_start + blksize; 950 sc->pcmo_end = sc->pcmo_start + size; 951 sc->pcmo_blksize = blksize; 952 953 sc->ptr_pcmo = 0; 954 q = &sc->dmalist_pcmo[sc->ptr_pcmo]; 955 q->base = sc->pcmo_start; 956 q->len = (blksize / 2) | ICH_DMAF_IOC; 957 if (++sc->ptr_pcmo == ICH_DMALIST_MAX) 958 sc->ptr_pcmo = 0; 959 960 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 961 sc->sc_cddma + ICH_PCMO_OFF(0)); 962 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_CTRL, 963 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 964 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_LVI, 965 (sc->ptr_pcmo - 1) & ICH_LVI_MASK); 966 967 return (0); 968 } 969 970 int 971 auich_trigger_input(v, start, end, blksize, intr, arg, param) 972 void *v; 973 void *start, *end; 974 int blksize; 975 void (*intr)(void *); 976 void *arg; 977 struct audio_params *param; 978 { 979 struct auich_softc *sc = v; 980 struct auich_dmalist *q; 981 struct auich_dma *p; 982 size_t size; 983 984 DPRINTF(ICH_DEBUG_DMA, 985 ("auich_trigger_input(%p, %p, %d, %p, %p, %p)\n", 986 start, end, blksize, intr, arg, param)); 987 988 sc->sc_rintr = intr; 989 sc->sc_rarg = arg; 990 991 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 992 ; 993 if (!p) { 994 printf("auich_trigger_input: bad addr %p\n", start); 995 return (EINVAL); 996 } 997 998 size = (size_t)((caddr_t)end - (caddr_t)start); 999 1000 /* 1001 * The logic behind this is: 1002 * setup one buffer to play, then LVI dump out the rest 1003 * to the scatter-gather chain. 1004 */ 1005 sc->pcmi_start = DMAADDR(p); 1006 sc->pcmi_p = sc->pcmi_start + blksize; 1007 sc->pcmi_end = sc->pcmi_start + size; 1008 sc->pcmi_blksize = blksize; 1009 1010 sc->ptr_pcmi = 0; 1011 q = &sc->dmalist_pcmi[sc->ptr_pcmi]; 1012 q->base = sc->pcmi_start; 1013 q->len = (blksize / 2) | ICH_DMAF_IOC; 1014 if (++sc->ptr_pcmi == ICH_DMALIST_MAX) 1015 sc->ptr_pcmi = 0; 1016 1017 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1018 sc->sc_cddma + ICH_PCMI_OFF(0)); 1019 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 1020 ICH_IOCE | ICH_FEIE | ICH_LVBIE | ICH_RPBM); 1021 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1022 (sc->ptr_pcmi - 1) & ICH_LVI_MASK); 1023 1024 return (0); 1025 } 1026 1027 int 1028 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1029 struct auich_dma *p) 1030 { 1031 int error; 1032 1033 p->size = size; 1034 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1035 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1036 &p->nsegs, BUS_DMA_NOWAIT); 1037 if (error) 1038 return (error); 1039 1040 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1041 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1042 if (error) 1043 goto free; 1044 1045 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1046 0, BUS_DMA_NOWAIT, &p->map); 1047 if (error) 1048 goto unmap; 1049 1050 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1051 BUS_DMA_NOWAIT); 1052 if (error) 1053 goto destroy; 1054 return (0); 1055 1056 destroy: 1057 bus_dmamap_destroy(sc->dmat, p->map); 1058 unmap: 1059 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1060 free: 1061 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1062 return (error); 1063 } 1064 1065 int 1066 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1067 { 1068 1069 bus_dmamap_unload(sc->dmat, p->map); 1070 bus_dmamap_destroy(sc->dmat, p->map); 1071 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1072 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1073 return (0); 1074 } 1075 1076 int 1077 auich_alloc_cdata(struct auich_softc *sc) 1078 { 1079 bus_dma_segment_t seg; 1080 int error, rseg; 1081 1082 /* 1083 * Allocate the control data structure, and create and load the 1084 * DMA map for it. 1085 */ 1086 if ((error = bus_dmamem_alloc(sc->dmat, 1087 sizeof(struct auich_cdata), 1088 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1089 printf("%s: unable to allocate control data, error = %d\n", 1090 sc->sc_dev.dv_xname, error); 1091 goto fail_0; 1092 } 1093 1094 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1095 sizeof(struct auich_cdata), 1096 (caddr_t *) &sc->sc_cdata, 1097 BUS_DMA_COHERENT)) != 0) { 1098 printf("%s: unable to map control data, error = %d\n", 1099 sc->sc_dev.dv_xname, error); 1100 goto fail_1; 1101 } 1102 1103 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1104 sizeof(struct auich_cdata), 0, 0, 1105 &sc->sc_cddmamap)) != 0) { 1106 printf("%s: unable to create control data DMA map, " 1107 "error = %d\n", sc->sc_dev.dv_xname, error); 1108 goto fail_2; 1109 } 1110 1111 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1112 sc->sc_cdata, sizeof(struct auich_cdata), 1113 NULL, 0)) != 0) { 1114 printf("%s: unable tp load control data DMA map, " 1115 "error = %d\n", sc->sc_dev.dv_xname, error); 1116 goto fail_3; 1117 } 1118 1119 return (0); 1120 1121 fail_3: 1122 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1123 fail_2: 1124 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1125 sizeof(struct auich_cdata)); 1126 fail_1: 1127 bus_dmamem_free(sc->dmat, &seg, rseg); 1128 fail_0: 1129 return (error); 1130 } 1131