1 /* $NetBSD: auich.c,v 1.159 2020/02/29 06:34:30 isaki Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2004, 2005, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 2000 Michael Shalayeff 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 51 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 52 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 53 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 55 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 56 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 57 * THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * from OpenBSD: ich.c,v 1.3 2000/08/11 06:17:18 mickey Exp 60 */ 61 62 /* 63 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp> 64 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org> 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 77 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 79 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 82 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 83 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 84 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 85 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF 86 * SUCH DAMAGE. 87 * 88 * auich_calibrate() was from FreeBSD: ich.c,v 1.22 2002/06/27 22:36:01 scottl Exp 89 */ 90 91 92 /* #define AUICH_DEBUG */ 93 /* 94 * AC'97 audio found on Intel 810/820/440MX chipsets. 95 * http://developer.intel.com/design/chipsets/datashts/290655.htm 96 * http://developer.intel.com/design/chipsets/manuals/298028.htm 97 * ICH3:http://www.intel.com/design/chipsets/datashts/290716.htm 98 * ICH4:http://www.intel.com/design/chipsets/datashts/290744.htm 99 * ICH5:http://www.intel.com/design/chipsets/datashts/252516.htm 100 * AMD8111: 101 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24674.pdf 102 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25720.pdf 103 * 104 * TODO: 105 * - Add support for the dedicated microphone input. 106 * 107 * NOTE: 108 * - The 440MX B-stepping at running 100MHz has a hardware erratum. 109 * It causes PCI master abort and hangups until cold reboot. 110 * http://www.intel.com/design/chipsets/specupdt/245051.htm 111 */ 112 113 #include <sys/cdefs.h> 114 __KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.159 2020/02/29 06:34:30 isaki Exp $"); 115 116 #include <sys/param.h> 117 #include <sys/systm.h> 118 #include <sys/kernel.h> 119 #include <sys/kmem.h> 120 #include <sys/device.h> 121 #include <sys/fcntl.h> 122 #include <sys/proc.h> 123 #include <sys/sysctl.h> 124 #include <sys/audioio.h> 125 #include <sys/bus.h> 126 #include <sys/rndsource.h> 127 128 #include <dev/pci/pcidevs.h> 129 #include <dev/pci/pcivar.h> 130 #include <dev/pci/auichreg.h> 131 132 #include <dev/audio/audio_if.h> 133 134 #include <dev/ic/ac97reg.h> 135 #include <dev/ic/ac97var.h> 136 137 struct auich_dma { 138 bus_dmamap_t map; 139 void *addr; 140 bus_dma_segment_t segs[1]; 141 int nsegs; 142 size_t size; 143 struct auich_dma *next; 144 }; 145 146 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 147 #define KERNADDR(p) ((void *)((p)->addr)) 148 149 struct auich_cdata { 150 struct auich_dmalist ic_dmalist_pcmo[ICH_DMALIST_MAX]; 151 struct auich_dmalist ic_dmalist_pcmi[ICH_DMALIST_MAX]; 152 struct auich_dmalist ic_dmalist_mici[ICH_DMALIST_MAX]; 153 }; 154 155 #define ICH_CDOFF(x) offsetof(struct auich_cdata, x) 156 #define ICH_PCMO_OFF(x) ICH_CDOFF(ic_dmalist_pcmo[(x)]) 157 #define ICH_PCMI_OFF(x) ICH_CDOFF(ic_dmalist_pcmi[(x)]) 158 #define ICH_MICI_OFF(x) ICH_CDOFF(ic_dmalist_mici[(x)]) 159 160 struct auich_softc { 161 device_t sc_dev; 162 void *sc_ih; 163 kmutex_t sc_lock; 164 kmutex_t sc_intr_lock; 165 166 device_t sc_audiodev; 167 audio_device_t sc_audev; 168 169 pci_chipset_tag_t sc_pc; 170 pcitag_t sc_pt; 171 bus_space_tag_t iot; 172 bus_space_handle_t mix_ioh; 173 bus_size_t mix_size; 174 bus_space_handle_t aud_ioh; 175 bus_size_t aud_size; 176 bus_dma_tag_t dmat; 177 pci_intr_handle_t intrh; 178 179 struct ac97_codec_if *codec_if; 180 struct ac97_host_if host_if; 181 int sc_codecnum; 182 int sc_codectype; 183 int sc_fixedrate; 184 enum ac97_host_flags sc_codecflags; 185 bool sc_spdif; 186 187 /* multi-channel control bits */ 188 int sc_pcm246_mask; 189 int sc_pcm2; 190 int sc_pcm4; 191 int sc_pcm6; 192 193 /* DMA scatter-gather lists. */ 194 bus_dmamap_t sc_cddmamap; 195 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 196 197 struct auich_cdata *sc_cdata; 198 199 struct auich_ring { 200 int qptr; 201 struct auich_dmalist *dmalist; 202 203 uint32_t start, p, end; 204 int blksize; 205 206 void (*intr)(void *); 207 void *arg; 208 } pcmo, pcmi, mici; 209 210 struct auich_dma *sc_dmas; 211 212 /* SiS 7012 hack */ 213 int sc_sample_shift; 214 int sc_sts_reg; 215 /* 440MX workaround */ 216 int sc_dmamap_flags; 217 /* flags */ 218 u_int sc_iose :1, 219 :31; 220 221 /* sysctl */ 222 struct sysctllog *sc_log; 223 uint32_t sc_ac97_clock; 224 int sc_ac97_clock_mib; 225 226 int sc_modem_offset; 227 228 #define AUICH_AUDIO_NFORMATS 3 229 #define AUICH_MODEM_NFORMATS 1 230 struct audio_format sc_audio_formats[AUICH_AUDIO_NFORMATS]; 231 struct audio_format sc_modem_formats[AUICH_MODEM_NFORMATS]; 232 233 int sc_cas_been_used; 234 }; 235 236 /* Debug */ 237 #ifdef AUICH_DEBUG 238 #define DPRINTF(l,x) do { if (auich_debug & (l)) aprint_normal_dev x; } while(0) 239 int auich_debug = 0xfffe; 240 #define ICH_DEBUG_CODECIO 0x0001 241 #define ICH_DEBUG_DMA 0x0002 242 #define ICH_DEBUG_INTR 0x0004 243 #else 244 #define DPRINTF(x,y) /* nothing */ 245 #endif 246 247 static int auich_match(device_t, cfdata_t, void *); 248 static void auich_attach(device_t, device_t, void *); 249 static int auich_detach(device_t, int); 250 static void auich_childdet(device_t, device_t); 251 static int auich_intr(void *); 252 253 CFATTACH_DECL2_NEW(auich, sizeof(struct auich_softc), 254 auich_match, auich_attach, auich_detach, NULL, NULL, auich_childdet); 255 256 static int auich_open(void *, int); 257 static void auich_close(void *); 258 static int auich_query_format(void *, struct audio_format_query *); 259 static int auich_set_format(void *, int, 260 const audio_params_t *, const audio_params_t *, 261 audio_filter_reg_t *, audio_filter_reg_t *); 262 static void auich_halt_pipe(struct auich_softc *, int); 263 static int auich_halt_output(void *); 264 static int auich_halt_input(void *); 265 static int auich_getdev(void *, struct audio_device *); 266 static int auich_set_port(void *, mixer_ctrl_t *); 267 static int auich_get_port(void *, mixer_ctrl_t *); 268 static int auich_query_devinfo(void *, mixer_devinfo_t *); 269 static void *auich_allocm(void *, int, size_t); 270 static void auich_freem(void *, void *, size_t); 271 static size_t auich_round_buffersize(void *, int, size_t); 272 static int auich_get_props(void *); 273 static void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 274 static void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 275 static int auich_trigger_output(void *, void *, void *, int, 276 void (*)(void *), void *, const audio_params_t *); 277 static int auich_trigger_input(void *, void *, void *, int, 278 void (*)(void *), void *, const audio_params_t *); 279 static void auich_get_locks(void *, kmutex_t **, kmutex_t **); 280 281 static int auich_alloc_cdata(struct auich_softc *); 282 283 static int auich_allocmem(struct auich_softc *, size_t, size_t, 284 struct auich_dma *); 285 static int auich_freemem(struct auich_softc *, struct auich_dma *); 286 287 static bool auich_resume(device_t, const pmf_qual_t *); 288 static int auich_set_rate(struct auich_softc *, int, u_long); 289 static int auich_sysctl_verify(SYSCTLFN_ARGS); 290 static void auich_finish_attach(device_t); 291 static void auich_calibrate(struct auich_softc *); 292 static void auich_clear_cas(struct auich_softc *); 293 294 static int auich_attach_codec(void *, struct ac97_codec_if *); 295 static int auich_read_codec(void *, uint8_t, uint16_t *); 296 static int auich_write_codec(void *, uint8_t, uint16_t); 297 static int auich_reset_codec(void *); 298 static enum ac97_host_flags auich_flags_codec(void *); 299 static void auich_spdif_event(void *, bool); 300 301 static const struct audio_hw_if auich_hw_if = { 302 .open = auich_open, 303 .close = auich_close, 304 .query_format = auich_query_format, 305 .set_format = auich_set_format, 306 .halt_output = auich_halt_output, 307 .halt_input = auich_halt_input, 308 .getdev = auich_getdev, 309 .set_port = auich_set_port, 310 .get_port = auich_get_port, 311 .query_devinfo = auich_query_devinfo, 312 .allocm = auich_allocm, 313 .freem = auich_freem, 314 .round_buffersize = auich_round_buffersize, 315 .get_props = auich_get_props, 316 .trigger_output = auich_trigger_output, 317 .trigger_input = auich_trigger_input, 318 .get_locks = auich_get_locks, 319 }; 320 321 #define AUICH_FORMATS_1CH 0 322 #define AUICH_FORMATS_4CH 1 323 #define AUICH_FORMATS_6CH 2 324 #define AUICH_FORMAT(aumode, ch, chmask) \ 325 { \ 326 .mode = (aumode), \ 327 .encoding = AUDIO_ENCODING_SLINEAR_LE, \ 328 .validbits = 16, \ 329 .precision = 16, \ 330 .channels = (ch), \ 331 .channel_mask = (chmask), \ 332 .frequency_type = 0, \ 333 .frequency = { 8000, 48000 }, \ 334 } 335 static const struct audio_format auich_audio_formats[AUICH_AUDIO_NFORMATS] = { 336 AUICH_FORMAT(AUMODE_PLAY | AUMODE_RECORD, 2, AUFMT_STEREO), 337 AUICH_FORMAT(AUMODE_PLAY , 4, AUFMT_SURROUND4), 338 AUICH_FORMAT(AUMODE_PLAY , 6, AUFMT_DOLBY_5_1), 339 }; 340 341 #define AUICH_SPDIF_NFORMATS 1 342 static const struct audio_format auich_spdif_formats[AUICH_SPDIF_NFORMATS] = { 343 { 344 .mode = AUMODE_PLAY | AUMODE_RECORD, 345 .encoding = AUDIO_ENCODING_SLINEAR_LE, 346 .validbits = 16, 347 .precision = 16, 348 .channels = 2, 349 .channel_mask = AUFMT_STEREO, 350 .frequency_type = 1, 351 .frequency = { 48000 }, 352 }, 353 }; 354 355 static const struct audio_format auich_modem_formats[AUICH_MODEM_NFORMATS] = { 356 { 357 .mode = AUMODE_PLAY | AUMODE_RECORD, 358 .encoding = AUDIO_ENCODING_SLINEAR_LE, 359 .validbits = 16, 360 .precision = 16, 361 .channels = 1, 362 .channel_mask = AUFMT_MONAURAL, 363 .frequency_type = 2, 364 .frequency = { 8000, 16000 }, 365 }, 366 }; 367 368 #define PCI_ID_CODE0(v, p) PCI_ID_CODE(PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p) 369 #define PCIID_ICH PCI_ID_CODE0(INTEL, 82801AA_ACA) 370 #define PCIID_ICH0 PCI_ID_CODE0(INTEL, 82801AB_ACA) 371 #define PCIID_ICH2 PCI_ID_CODE0(INTEL, 82801BA_ACA) 372 #define PCIID_440MX PCI_ID_CODE0(INTEL, 82440MX_ACA) 373 #define PCIID_ICH3 PCI_ID_CODE0(INTEL, 82801CA_AC) 374 #define PCIID_ICH4 PCI_ID_CODE0(INTEL, 82801DB_AC) 375 #define PCIID_ICH5 PCI_ID_CODE0(INTEL, 82801EB_AC) 376 #define PCIID_ICH6 PCI_ID_CODE0(INTEL, 82801FB_AC) 377 #define PCIID_ICH7 PCI_ID_CODE0(INTEL, 82801G_ACA) 378 #define PCIID_I6300ESB PCI_ID_CODE0(INTEL, 6300ESB_ACA) 379 #define PCIID_SIS7012 PCI_ID_CODE0(SIS, 7012_AC) 380 #define PCIID_NFORCE PCI_ID_CODE0(NVIDIA, NFORCE_MCP_AC) 381 #define PCIID_NFORCE2 PCI_ID_CODE0(NVIDIA, NFORCE2_MCPT_AC) 382 #define PCIID_NFORCE2_400 PCI_ID_CODE0(NVIDIA, NFORCE2_400_MCPT_AC) 383 #define PCIID_NFORCE3 PCI_ID_CODE0(NVIDIA, NFORCE3_MCPT_AC) 384 #define PCIID_NFORCE3_250 PCI_ID_CODE0(NVIDIA, NFORCE3_250_MCPT_AC) 385 #define PCIID_NFORCE4 PCI_ID_CODE0(NVIDIA, NFORCE4_AC) 386 #define PCIID_NFORCE430 PCI_ID_CODE0(NVIDIA, NFORCE430_AC) 387 #define PCIID_AMD768 PCI_ID_CODE0(AMD, PBC768_AC) 388 #define PCIID_AMD8111 PCI_ID_CODE0(AMD, PBC8111_AC) 389 390 #define PCIID_ICH3MODEM PCI_ID_CODE0(INTEL, 82801CA_MOD) 391 #define PCIID_ICH4MODEM PCI_ID_CODE0(INTEL, 82801DB_MOD) 392 #define PCIID_ICH6MODEM PCI_ID_CODE0(INTEL, 82801FB_ACM) 393 394 struct auich_devtype { 395 pcireg_t id; 396 const char *name; 397 const char *shortname; /* must be less than 11 characters */ 398 }; 399 400 static const struct auich_devtype auich_audio_devices[] = { 401 { PCIID_ICH, "i82801AA (ICH) AC-97 Audio", "ICH" }, 402 { PCIID_ICH0, "i82801AB (ICH0) AC-97 Audio", "ICH0" }, 403 { PCIID_ICH2, "i82801BA (ICH2) AC-97 Audio", "ICH2" }, 404 { PCIID_440MX, "i82440MX AC-97 Audio", "440MX" }, 405 { PCIID_ICH3, "i82801CA (ICH3) AC-97 Audio", "ICH3" }, 406 { PCIID_ICH4, "i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" }, 407 { PCIID_ICH5, "i82801EB (ICH5) AC-97 Audio", "ICH5" }, 408 { PCIID_ICH6, "i82801FB (ICH6) AC-97 Audio", "ICH6" }, 409 { PCIID_ICH7, "i82801GB/GR (ICH7) AC-97 Audio", "ICH7" }, 410 { PCIID_I6300ESB, "Intel 6300ESB AC-97 Audio", "I6300ESB" }, 411 { PCIID_SIS7012, "SiS 7012 AC-97 Audio", "SiS7012" }, 412 { PCIID_NFORCE, "nForce MCP AC-97 Audio", "nForce" }, 413 { PCIID_NFORCE2, "nForce2 MCP-T AC-97 Audio", "nForce2" }, 414 { PCIID_NFORCE2_400, "nForce2 400 MCP-T AC-97 Audio", "nForce2" }, 415 { PCIID_NFORCE3, "nForce3 MCP-T AC-97 Audio", "nForce3" }, 416 { PCIID_NFORCE3_250, "nForce3 250 MCP-T AC-97 Audio", "nForce3" }, 417 { PCIID_NFORCE4, "nForce4 AC-97 Audio", "nForce4" }, 418 { PCIID_NFORCE430, "nForce430 (MCP51) AC-97 Audio", "nForce430" }, 419 { PCIID_AMD768, "AMD768 AC-97 Audio", "AMD768" }, 420 { PCIID_AMD8111,"AMD8111 AC-97 Audio", "AMD8111" }, 421 { 0, NULL, NULL }, 422 }; 423 424 static const struct auich_devtype auich_modem_devices[] = { 425 #ifdef AUICH_ATTACH_MODEM 426 { PCIID_ICH3MODEM, "i82801CA (ICH3) AC-97 Modem", "ICH3MODEM" }, 427 { PCIID_ICH4MODEM, "i82801DB (ICH4) AC-97 Modem", "ICH4MODEM" }, 428 { PCIID_ICH6MODEM, "i82801FB (ICH6) AC-97 Modem", "ICH6MODEM" }, 429 #endif 430 { 0, NULL, NULL }, 431 }; 432 433 static const struct auich_devtype * 434 auich_lookup(struct pci_attach_args *pa, const struct auich_devtype *auich_devices) 435 { 436 const struct auich_devtype *d; 437 438 for (d = auich_devices; d->name != NULL; d++) { 439 if (pa->pa_id == d->id) 440 return d; 441 } 442 443 return NULL; 444 } 445 446 static int 447 auich_match(device_t parent, cfdata_t match, void *aux) 448 { 449 struct pci_attach_args *pa; 450 451 pa = aux; 452 if (auich_lookup(pa, auich_audio_devices) != NULL) 453 return 1; 454 if (auich_lookup(pa, auich_modem_devices) != NULL) 455 return 1; 456 457 return 0; 458 } 459 460 static void 461 auich_attach(device_t parent, device_t self, void *aux) 462 { 463 struct auich_softc *sc = device_private(self); 464 struct pci_attach_args *pa; 465 pcireg_t v, subdev; 466 const char *intrstr; 467 const struct auich_devtype *d; 468 const struct sysctlnode *node, *node_ac97clock; 469 int err, node_mib, i; 470 char intrbuf[PCI_INTRSTR_LEN]; 471 472 sc->sc_dev = self; 473 pa = aux; 474 475 if ((d = auich_lookup(pa, auich_modem_devices)) != NULL) { 476 sc->sc_modem_offset = 0x10; 477 sc->sc_codectype = AC97_CODEC_TYPE_MODEM; 478 } else if ((d = auich_lookup(pa, auich_audio_devices)) != NULL) { 479 sc->sc_modem_offset = 0; 480 sc->sc_codectype = AC97_CODEC_TYPE_AUDIO; 481 } else 482 panic("auich_attach: impossible"); 483 484 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 485 aprint_naive(": Audio controller\n"); 486 else 487 aprint_naive(": Modem controller\n"); 488 489 sc->sc_pc = pa->pa_pc; 490 sc->sc_pt = pa->pa_tag; 491 492 aprint_normal(": %s\n", d->name); 493 494 if (d->id == PCIID_ICH4 || d->id == PCIID_ICH5 || d->id == PCIID_ICH6 495 || d->id == PCIID_ICH7 || d->id == PCIID_I6300ESB 496 || d->id == PCIID_ICH4MODEM) { 497 /* 498 * Use native mode for Intel 6300ESB and ICH4/ICH5/ICH6/ICH7 499 */ 500 501 if (pci_mapreg_map(pa, ICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 502 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 503 goto retry_map; 504 } 505 if (pci_mapreg_map(pa, ICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 506 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 507 goto retry_map; 508 } 509 goto map_done; 510 } else 511 goto non_native_map; 512 513 retry_map: 514 sc->sc_iose = 1; 515 v = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_CFG); 516 pci_conf_write(pa->pa_pc, pa->pa_tag, ICH_CFG, 517 v | ICH_CFG_IOSE); 518 519 non_native_map: 520 if (pci_mapreg_map(pa, ICH_NAMBAR, PCI_MAPREG_TYPE_IO, 0, 521 &sc->iot, &sc->mix_ioh, NULL, &sc->mix_size)) { 522 aprint_error_dev(self, "can't map codec i/o space\n"); 523 return; 524 } 525 if (pci_mapreg_map(pa, ICH_NABMBAR, PCI_MAPREG_TYPE_IO, 0, 526 &sc->iot, &sc->aud_ioh, NULL, &sc->aud_size)) { 527 aprint_error_dev(self, "can't map device i/o space\n"); 528 return; 529 } 530 531 map_done: 532 sc->dmat = pa->pa_dmat; 533 534 /* enable bus mastering */ 535 v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 536 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 537 v | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_BACKTOBACK_ENABLE); 538 539 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 540 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 541 542 /* Map and establish the interrupt. */ 543 if (pci_intr_map(pa, &sc->intrh)) { 544 aprint_error_dev(self, "can't map interrupt\n"); 545 return; 546 } 547 intrstr = pci_intr_string(pa->pa_pc, sc->intrh, intrbuf, sizeof(intrbuf)); 548 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, sc->intrh, IPL_AUDIO, 549 auich_intr, sc, device_xname(sc->sc_dev)); 550 if (sc->sc_ih == NULL) { 551 aprint_error_dev(self, "can't establish interrupt"); 552 if (intrstr != NULL) 553 aprint_error(" at %s", intrstr); 554 aprint_error("\n"); 555 return; 556 } 557 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 558 559 snprintf(sc->sc_audev.name, MAX_AUDIO_DEV_LEN, "%s AC97", d->shortname); 560 snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN, 561 "0x%02x", PCI_REVISION(pa->pa_class)); 562 strlcpy(sc->sc_audev.config, device_xname(self), MAX_AUDIO_DEV_LEN); 563 564 /* SiS 7012 needs special handling */ 565 if (d->id == PCIID_SIS7012) { 566 sc->sc_sts_reg = ICH_PICB; 567 sc->sc_sample_shift = 0; 568 sc->sc_pcm246_mask = ICH_SIS_PCM246_MASK; 569 sc->sc_pcm2 = ICH_SIS_PCM2; 570 sc->sc_pcm4 = ICH_SIS_PCM4; 571 sc->sc_pcm6 = ICH_SIS_PCM6; 572 /* Un-mute output. From Linux. */ 573 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 574 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 575 ICH_SIS_CTL_UNMUTE); 576 } else { 577 sc->sc_sts_reg = ICH_STS; 578 sc->sc_sample_shift = 1; 579 sc->sc_pcm246_mask = ICH_PCM246_MASK; 580 sc->sc_pcm2 = ICH_PCM2; 581 sc->sc_pcm4 = ICH_PCM4; 582 sc->sc_pcm6 = ICH_PCM6; 583 } 584 585 /* Workaround for a 440MX B-stepping erratum */ 586 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 587 if (d->id == PCIID_440MX) { 588 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 589 aprint_normal_dev(self, "DMA bug workaround enabled\n"); 590 } 591 592 /* Set up DMA lists. */ 593 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 594 auich_alloc_cdata(sc); 595 596 DPRINTF(ICH_DEBUG_DMA, (sc->sc_dev, "%s: lists %p %p %p\n", 597 __func__, sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 598 599 /* Modem codecs are always the secondary codec on ICH */ 600 sc->sc_codecnum = sc->sc_codectype == AC97_CODEC_TYPE_MODEM ? 1 : 0; 601 602 sc->host_if.arg = sc; 603 sc->host_if.attach = auich_attach_codec; 604 sc->host_if.read = auich_read_codec; 605 sc->host_if.write = auich_write_codec; 606 sc->host_if.reset = auich_reset_codec; 607 sc->host_if.flags = auich_flags_codec; 608 sc->host_if.spdif_event = auich_spdif_event; 609 610 subdev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 611 switch (subdev) { 612 case 0x202f161f: /* Gateway 7326GZ */ 613 case 0x203a161f: /* Gateway 4028GZ */ 614 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */ 615 case 0x8144104d: /* Sony VAIO PCG-TR* */ 616 case 0x8197104d: /* Sony S1XP */ 617 case 0x81c0104d: /* Sony VAIO type T */ 618 case 0x81c5104d: /* Sony VAIO VGN-B1XP */ 619 sc->sc_codecflags = AC97_HOST_INVERTED_EAMP; 620 break; 621 default: 622 sc->sc_codecflags = 0; 623 break; 624 } 625 626 if (ac97_attach_type(&sc->host_if, self, sc->sc_codectype, 627 &sc->sc_lock) != 0) 628 return; 629 630 mutex_enter(&sc->sc_lock); 631 sc->codec_if->vtbl->unlock(sc->codec_if); 632 sc->sc_fixedrate = AC97_IS_FIXED_RATE(sc->codec_if); 633 634 /* setup audio_format */ 635 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 636 memcpy(sc->sc_audio_formats, auich_audio_formats, 637 sizeof(auich_audio_formats)); 638 if (!AC97_IS_4CH(sc->codec_if)) 639 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_4CH]); 640 if (!AC97_IS_6CH(sc->codec_if)) 641 AUFMT_INVALIDATE(&sc->sc_audio_formats[AUICH_FORMATS_6CH]); 642 if (AC97_IS_FIXED_RATE(sc->codec_if)) { 643 for (i = 0; i < AUICH_AUDIO_NFORMATS; i++) { 644 sc->sc_audio_formats[i].frequency_type = 1; 645 sc->sc_audio_formats[i].frequency[0] = 48000; 646 } 647 } 648 mutex_exit(&sc->sc_lock); 649 } else { 650 mutex_exit(&sc->sc_lock); 651 memcpy(sc->sc_modem_formats, auich_modem_formats, 652 sizeof(auich_modem_formats)); 653 } 654 655 /* Watch for power change */ 656 if (!pmf_device_register(self, NULL, auich_resume)) 657 aprint_error_dev(self, "couldn't establish power handler\n"); 658 659 config_interrupts(self, auich_finish_attach); 660 661 /* sysctl setup */ 662 if (sc->sc_fixedrate && sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 663 return; 664 665 err = sysctl_createv(&sc->sc_log, 0, NULL, &node, 0, 666 CTLTYPE_NODE, device_xname(self), NULL, NULL, 0, 667 NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 668 if (err != 0) 669 goto sysctl_err; 670 node_mib = node->sysctl_num; 671 672 if (!sc->sc_fixedrate) { 673 /* passing the sc address instead of &sc->sc_ac97_clock */ 674 err = sysctl_createv(&sc->sc_log, 0, NULL, &node_ac97clock, 675 CTLFLAG_READWRITE, 676 CTLTYPE_INT, "ac97rate", 677 SYSCTL_DESCR("AC'97 codec link rate"), 678 auich_sysctl_verify, 0, (void *)sc, 0, 679 CTL_HW, node_mib, CTL_CREATE, CTL_EOL); 680 if (err != 0) 681 goto sysctl_err; 682 sc->sc_ac97_clock_mib = node_ac97clock->sysctl_num; 683 } 684 685 return; 686 687 sysctl_err: 688 aprint_error_dev(self, "failed to add sysctl nodes. (%d)\n", err); 689 return; /* failure of sysctl is not fatal. */ 690 } 691 692 static void 693 auich_childdet(device_t self, device_t child) 694 { 695 struct auich_softc *sc = device_private(self); 696 697 KASSERT(sc->sc_audiodev == child); 698 sc->sc_audiodev = NULL; 699 } 700 701 static int 702 auich_detach(device_t self, int flags) 703 { 704 struct auich_softc *sc = device_private(self); 705 706 /* audio */ 707 if (sc->sc_audiodev != NULL) 708 config_detach(sc->sc_audiodev, flags); 709 710 /* sysctl */ 711 sysctl_teardown(&sc->sc_log); 712 713 mutex_enter(&sc->sc_lock); 714 715 /* ac97 */ 716 if (sc->codec_if != NULL) 717 sc->codec_if->vtbl->detach(sc->codec_if); 718 719 mutex_exit(&sc->sc_lock); 720 mutex_destroy(&sc->sc_lock); 721 mutex_destroy(&sc->sc_intr_lock); 722 723 /* PCI */ 724 if (sc->sc_ih != NULL) 725 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 726 if (sc->mix_size != 0) 727 bus_space_unmap(sc->iot, sc->mix_ioh, sc->mix_size); 728 if (sc->aud_size != 0) 729 bus_space_unmap(sc->iot, sc->aud_ioh, sc->aud_size); 730 return 0; 731 } 732 733 static int 734 auich_sysctl_verify(SYSCTLFN_ARGS) 735 { 736 int error, tmp; 737 struct sysctlnode node; 738 struct auich_softc *sc; 739 740 node = *rnode; 741 sc = rnode->sysctl_data; 742 if (node.sysctl_num == sc->sc_ac97_clock_mib) { 743 tmp = sc->sc_ac97_clock; 744 node.sysctl_data = &tmp; 745 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 746 if (error || newp == NULL) 747 return error; 748 749 if (tmp < 48000 || tmp > 96000) 750 return EINVAL; 751 mutex_enter(&sc->sc_lock); 752 sc->sc_ac97_clock = tmp; 753 mutex_exit(&sc->sc_lock); 754 } 755 756 return 0; 757 } 758 759 static void 760 auich_finish_attach(device_t self) 761 { 762 struct auich_softc *sc = device_private(self); 763 764 mutex_enter(&sc->sc_lock); 765 if (!AC97_IS_FIXED_RATE(sc->codec_if)) 766 auich_calibrate(sc); 767 mutex_exit(&sc->sc_lock); 768 769 sc->sc_audiodev = audio_attach_mi(&auich_hw_if, sc, sc->sc_dev); 770 771 return; 772 } 773 774 #define ICH_CODECIO_INTERVAL 10 775 static int 776 auich_read_codec(void *v, uint8_t reg, uint16_t *val) 777 { 778 struct auich_softc *sc; 779 int i; 780 uint32_t status; 781 782 sc = v; 783 /* wait for an access semaphore */ 784 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 785 bus_space_read_1(sc->iot, sc->aud_ioh, 786 ICH_CAS + sc->sc_modem_offset) & 1; 787 DELAY(ICH_CODECIO_INTERVAL)); 788 789 /* 790 * Be permissive in first attempt. If previous instances of 791 * this routine were interrupted precisely at this point (after 792 * access is granted by CAS but before a command is sent), 793 * they could have left hardware in an inconsistent state where 794 * a command is expected and therefore semaphore wait would hit 795 * the timeout. 796 */ 797 if (!sc->sc_cas_been_used && i <= 0) 798 i = 1; 799 sc->sc_cas_been_used = 1; 800 801 if (i > 0) { 802 *val = bus_space_read_2(sc->iot, sc->mix_ioh, 803 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET)); 804 DPRINTF(ICH_DEBUG_CODECIO, 805 (sc->sc_dev, "%s(%x, %x)\n", __func__, reg, *val)); 806 status = bus_space_read_4(sc->iot, sc->aud_ioh, 807 ICH_GSTS + sc->sc_modem_offset); 808 if (status & ICH_RCS) { 809 bus_space_write_4(sc->iot, sc->aud_ioh, 810 ICH_GSTS + sc->sc_modem_offset, 811 status & ~(ICH_SRI|ICH_PRI|ICH_GSCI)); 812 *val = 0xffff; 813 DPRINTF(ICH_DEBUG_CODECIO, 814 (sc->sc_dev, "%s: read_codec error\n", __func__)); 815 if (reg == AC97_REG_GPIO_STATUS) 816 auich_clear_cas(sc); 817 return -1; 818 } 819 if (reg == AC97_REG_GPIO_STATUS) 820 auich_clear_cas(sc); 821 return 0; 822 } else { 823 aprint_normal_dev(sc->sc_dev, "read_codec timeout\n"); 824 if (reg == AC97_REG_GPIO_STATUS) 825 auich_clear_cas(sc); 826 return -1; 827 } 828 } 829 830 static int 831 auich_write_codec(void *v, uint8_t reg, uint16_t val) 832 { 833 struct auich_softc *sc; 834 int i; 835 836 sc = v; 837 DPRINTF(ICH_DEBUG_CODECIO, (sc->sc_dev, "%s(%x, %x)\n", 838 __func__, reg, val)); 839 /* wait for an access semaphore */ 840 for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- && 841 bus_space_read_1(sc->iot, sc->aud_ioh, 842 ICH_CAS + sc->sc_modem_offset) & 1; 843 DELAY(ICH_CODECIO_INTERVAL)); 844 845 /* Be permissive in first attempt (see comments in auich_read_codec) */ 846 if (!sc->sc_cas_been_used && i <= 0) 847 i = 1; 848 sc->sc_cas_been_used = 1; 849 850 if (i > 0) { 851 bus_space_write_2(sc->iot, sc->mix_ioh, 852 reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val); 853 return 0; 854 } else { 855 aprint_normal_dev(sc->sc_dev, "write_codec timeout\n"); 856 return -1; 857 } 858 } 859 860 static int 861 auich_attach_codec(void *v, struct ac97_codec_if *cif) 862 { 863 struct auich_softc *sc; 864 865 sc = v; 866 sc->codec_if = cif; 867 868 return 0; 869 } 870 871 static int 872 auich_reset_codec(void *v) 873 { 874 struct auich_softc *sc; 875 int i; 876 uint32_t control, status; 877 878 sc = v; 879 control = bus_space_read_4(sc->iot, sc->aud_ioh, 880 ICH_GCTRL + sc->sc_modem_offset); 881 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 882 control &= ~(ICH_ACLSO | sc->sc_pcm246_mask); 883 } else { 884 control &= ~ICH_ACLSO; 885 control |= ICH_GIE; 886 } 887 control |= (control & ICH_CRESET) ? ICH_WRESET : ICH_CRESET; 888 bus_space_write_4(sc->iot, sc->aud_ioh, 889 ICH_GCTRL + sc->sc_modem_offset, control); 890 891 for (i = 500000; i >= 0; i--) { 892 status = bus_space_read_4(sc->iot, sc->aud_ioh, 893 ICH_GSTS + sc->sc_modem_offset); 894 if (status & (ICH_PCR | ICH_SCR | ICH_S2CR)) 895 break; 896 DELAY(1); 897 } 898 if (i <= 0) { 899 aprint_error_dev(sc->sc_dev, "auich_reset_codec: time out\n"); 900 return ETIMEDOUT; 901 } 902 #ifdef AUICH_DEBUG 903 if (status & ICH_SCR) 904 aprint_normal_dev(sc->sc_dev, "The 2nd codec is ready.\n"); 905 if (status & ICH_S2CR) 906 aprint_normal_dev(sc->sc_dev, "The 3rd codec is ready.\n"); 907 #endif 908 return 0; 909 } 910 911 static enum ac97_host_flags 912 auich_flags_codec(void *v) 913 { 914 struct auich_softc *sc = v; 915 return sc->sc_codecflags; 916 } 917 918 static void 919 auich_spdif_event(void *addr, bool flag) 920 { 921 struct auich_softc *sc; 922 923 sc = addr; 924 sc->sc_spdif = flag; 925 } 926 927 static int 928 auich_open(void *addr, int flags) 929 { 930 struct auich_softc *sc; 931 932 sc = (struct auich_softc *)addr; 933 mutex_spin_exit(&sc->sc_intr_lock); 934 sc->codec_if->vtbl->lock(sc->codec_if); 935 mutex_spin_enter(&sc->sc_intr_lock); 936 return 0; 937 } 938 939 static void 940 auich_close(void *addr) 941 { 942 struct auich_softc *sc; 943 944 sc = (struct auich_softc *)addr; 945 mutex_spin_exit(&sc->sc_intr_lock); 946 sc->codec_if->vtbl->unlock(sc->codec_if); 947 mutex_spin_enter(&sc->sc_intr_lock); 948 } 949 950 static int 951 auich_query_format(void *v, struct audio_format_query *afp) 952 { 953 struct auich_softc *sc; 954 955 sc = (struct auich_softc *)v; 956 if (sc->sc_spdif) { 957 return audio_query_format(auich_spdif_formats, 958 AUICH_SPDIF_NFORMATS, afp); 959 } else { 960 return audio_query_format(sc->sc_audio_formats, 961 AUICH_AUDIO_NFORMATS, afp); 962 } 963 } 964 965 static int 966 auich_set_rate(struct auich_softc *sc, int mode, u_long srate) 967 { 968 int ret; 969 u_int ratetmp; 970 971 sc->codec_if->vtbl->set_clock(sc->codec_if, sc->sc_ac97_clock); 972 ratetmp = srate; 973 if (mode == AUMODE_RECORD) 974 return sc->codec_if->vtbl->set_rate(sc->codec_if, 975 AC97_REG_PCM_LR_ADC_RATE, &ratetmp); 976 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 977 AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp); 978 if (ret) 979 return ret; 980 ratetmp = srate; 981 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 982 AC97_REG_PCM_SURR_DAC_RATE, &ratetmp); 983 if (ret) 984 return ret; 985 ratetmp = srate; 986 ret = sc->codec_if->vtbl->set_rate(sc->codec_if, 987 AC97_REG_PCM_LFE_DAC_RATE, &ratetmp); 988 return ret; 989 } 990 991 static int 992 auich_set_format(void *v, int setmode, 993 const audio_params_t *play, const audio_params_t *rec, 994 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 995 { 996 struct auich_softc *sc; 997 const audio_params_t *p; 998 int mode, index; 999 uint32_t control; 1000 1001 sc = v; 1002 for (mode = AUMODE_RECORD; mode != -1; 1003 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 1004 if ((setmode & mode) == 0) 1005 continue; 1006 1007 p = mode == AUMODE_PLAY ? play : rec; 1008 1009 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1010 if (!sc->sc_spdif) 1011 index = audio_indexof_format( 1012 sc->sc_audio_formats, AUICH_AUDIO_NFORMATS, 1013 mode, p); 1014 else 1015 index = audio_indexof_format( 1016 auich_spdif_formats, AUICH_SPDIF_NFORMATS, 1017 mode, p); 1018 } else { 1019 index = audio_indexof_format(sc->sc_modem_formats, 1020 AUICH_MODEM_NFORMATS, mode, p); 1021 } 1022 1023 /* p represents HW encoding */ 1024 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1025 if (sc->sc_audio_formats[index].frequency_type != 1 1026 && auich_set_rate(sc, mode, p->sample_rate)) 1027 return EINVAL; 1028 } else { 1029 if (sc->sc_modem_formats[index].frequency_type != 1 1030 && auich_set_rate(sc, mode, p->sample_rate)) 1031 return EINVAL; 1032 auich_write_codec(sc, AC97_REG_LINE1_RATE, 1033 p->sample_rate); 1034 auich_write_codec(sc, AC97_REG_LINE1_LEVEL, 0); 1035 } 1036 if (mode == AUMODE_PLAY && 1037 sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) { 1038 control = bus_space_read_4(sc->iot, sc->aud_ioh, 1039 ICH_GCTRL + sc->sc_modem_offset); 1040 control &= ~sc->sc_pcm246_mask; 1041 if (p->channels == 4) { 1042 control |= sc->sc_pcm4; 1043 } else if (p->channels == 6) { 1044 control |= sc->sc_pcm6; 1045 } 1046 bus_space_write_4(sc->iot, sc->aud_ioh, 1047 ICH_GCTRL + sc->sc_modem_offset, control); 1048 } 1049 } 1050 1051 return 0; 1052 } 1053 1054 static void 1055 auich_halt_pipe(struct auich_softc *sc, int pipe) 1056 { 1057 int i; 1058 uint32_t status; 1059 1060 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 0); 1061 for (i = 0; i < 100; i++) { 1062 status = bus_space_read_4(sc->iot, sc->aud_ioh, pipe + ICH_STS); 1063 if (status & ICH_DCH) 1064 break; 1065 DELAY(1); 1066 } 1067 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, ICH_RR); 1068 1069 #if AUICH_DEBUG 1070 if (i > 0) 1071 aprint_normal_dev(sc->sc_dev, "%s: halt took %d cycles\n", 1072 __func__, i); 1073 #endif 1074 } 1075 1076 static int 1077 auich_halt_output(void *v) 1078 { 1079 struct auich_softc *sc; 1080 1081 sc = v; 1082 DPRINTF(ICH_DEBUG_DMA, (sc->sc_dev, "%s\n", __func__)); 1083 1084 auich_halt_pipe(sc, ICH_PCMO); 1085 sc->pcmo.intr = NULL; 1086 1087 return 0; 1088 } 1089 1090 static int 1091 auich_halt_input(void *v) 1092 { 1093 struct auich_softc *sc; 1094 1095 sc = v; 1096 DPRINTF(ICH_DEBUG_DMA, (sc->sc_dev, "%s\n", __func__)); 1097 1098 auich_halt_pipe(sc, ICH_PCMI); 1099 sc->pcmi.intr = NULL; 1100 1101 return 0; 1102 } 1103 1104 static int 1105 auich_getdev(void *v, struct audio_device *adp) 1106 { 1107 struct auich_softc *sc; 1108 1109 sc = v; 1110 *adp = sc->sc_audev; 1111 return 0; 1112 } 1113 1114 static int 1115 auich_set_port(void *v, mixer_ctrl_t *cp) 1116 { 1117 struct auich_softc *sc; 1118 1119 sc = v; 1120 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1121 } 1122 1123 static int 1124 auich_get_port(void *v, mixer_ctrl_t *cp) 1125 { 1126 struct auich_softc *sc; 1127 1128 sc = v; 1129 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1130 } 1131 1132 static int 1133 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1134 { 1135 struct auich_softc *sc; 1136 1137 sc = v; 1138 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1139 } 1140 1141 static void * 1142 auich_allocm(void *v, int direction, size_t size) 1143 { 1144 struct auich_softc *sc; 1145 struct auich_dma *p; 1146 int error; 1147 1148 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1149 return NULL; 1150 1151 p = kmem_alloc(sizeof(*p), KM_SLEEP); 1152 1153 sc = v; 1154 error = auich_allocmem(sc, size, 0, p); 1155 if (error) { 1156 kmem_free(p, sizeof(*p)); 1157 return NULL; 1158 } 1159 1160 p->next = sc->sc_dmas; 1161 sc->sc_dmas = p; 1162 1163 return KERNADDR(p); 1164 } 1165 1166 static void 1167 auich_freem(void *v, void *ptr, size_t size) 1168 { 1169 struct auich_softc *sc; 1170 struct auich_dma *p, **pp; 1171 1172 sc = v; 1173 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1174 if (KERNADDR(p) == ptr) { 1175 auich_freemem(sc, p); 1176 *pp = p->next; 1177 kmem_free(p, sizeof(*p)); 1178 return; 1179 } 1180 } 1181 } 1182 1183 static size_t 1184 auich_round_buffersize(void *v, int direction, size_t size) 1185 { 1186 1187 if (size > (ICH_DMALIST_MAX * ICH_DMASEG_MAX)) 1188 size = ICH_DMALIST_MAX * ICH_DMASEG_MAX; 1189 1190 return size; 1191 } 1192 1193 static int 1194 auich_get_props(void *v) 1195 { 1196 1197 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 1198 AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1199 } 1200 1201 static int 1202 auich_intr(void *v) 1203 { 1204 struct auich_softc *sc; 1205 int ret, gsts; 1206 #ifdef DIAGNOSTIC 1207 int csts; 1208 #endif 1209 1210 sc = v; 1211 1212 if (!device_has_power(sc->sc_dev)) 1213 return (0); 1214 1215 mutex_spin_enter(&sc->sc_intr_lock); 1216 1217 ret = 0; 1218 #ifdef DIAGNOSTIC 1219 csts = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 1220 if (csts & PCI_STATUS_MASTER_ABORT) { 1221 aprint_error_dev(sc->sc_dev, "%s: PCI master abort\n", 1222 __func__); 1223 } 1224 #endif 1225 1226 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, 1227 ICH_GSTS + sc->sc_modem_offset); 1228 DPRINTF(ICH_DEBUG_INTR, (sc->sc_dev, "%s: gsts=0x%x\n", 1229 __func__, gsts)); 1230 1231 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_POINT) || 1232 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MOINT)) { 1233 int sts; 1234 1235 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1236 ICH_PCMO + sc->sc_sts_reg); 1237 DPRINTF(ICH_DEBUG_INTR, 1238 (sc->sc_dev, "%s: osts=0x%x\n", __func__, sts)); 1239 1240 if (sts & ICH_FIFOE) 1241 aprint_error_dev(sc->sc_dev, "%s: fifo underrun\n", 1242 __func__); 1243 1244 if (sts & ICH_BCIS) 1245 auich_intr_pipe(sc, ICH_PCMO, &sc->pcmo); 1246 1247 /* int ack */ 1248 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMO + 1249 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1250 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1251 bus_space_write_4(sc->iot, sc->aud_ioh, 1252 ICH_GSTS + sc->sc_modem_offset, ICH_POINT); 1253 else 1254 bus_space_write_4(sc->iot, sc->aud_ioh, 1255 ICH_GSTS + sc->sc_modem_offset, ICH_MOINT); 1256 ret++; 1257 } 1258 1259 if ((sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_PIINT) || 1260 (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_MIINT)) { 1261 int sts; 1262 1263 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1264 ICH_PCMI + sc->sc_sts_reg); 1265 DPRINTF(ICH_DEBUG_INTR, 1266 (sc->sc_dev, "%s: ists=0x%x\n", __func__, sts)); 1267 1268 if (sts & ICH_FIFOE) 1269 aprint_error_dev(sc->sc_dev, "%s: fifo overrun\n", 1270 __func__); 1271 1272 if (sts & ICH_BCIS) 1273 auich_intr_pipe(sc, ICH_PCMI, &sc->pcmi); 1274 1275 /* int ack */ 1276 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_PCMI + 1277 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1278 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO) 1279 bus_space_write_4(sc->iot, sc->aud_ioh, 1280 ICH_GSTS + sc->sc_modem_offset, ICH_PIINT); 1281 else 1282 bus_space_write_4(sc->iot, sc->aud_ioh, 1283 ICH_GSTS + sc->sc_modem_offset, ICH_MIINT); 1284 ret++; 1285 } 1286 1287 if (sc->sc_codectype == AC97_CODEC_TYPE_AUDIO && gsts & ICH_MINT) { 1288 int sts; 1289 1290 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1291 ICH_MICI + sc->sc_sts_reg); 1292 DPRINTF(ICH_DEBUG_INTR, 1293 (sc->sc_dev, "%s: ists=0x%x\n", __func__, sts)); 1294 1295 if (sts & ICH_FIFOE) 1296 aprint_error_dev(sc->sc_dev, "%s: fifo overrun\n", 1297 __func__); 1298 1299 if (sts & ICH_BCIS) 1300 auich_intr_pipe(sc, ICH_MICI, &sc->mici); 1301 1302 /* int ack */ 1303 bus_space_write_2(sc->iot, sc->aud_ioh, ICH_MICI + 1304 sc->sc_sts_reg, sts & (ICH_BCIS | ICH_FIFOE)); 1305 bus_space_write_4(sc->iot, sc->aud_ioh, 1306 ICH_GSTS + sc->sc_modem_offset, ICH_MINT); 1307 ret++; 1308 } 1309 1310 #ifdef AUICH_MODEM_DEBUG 1311 if (sc->sc_codectype == AC97_CODEC_TYPE_MODEM && gsts & ICH_GSCI) { 1312 aprint_normal_dev(sc->sc_dev, "gsts=0x%x\n", gsts); 1313 /* int ack */ 1314 bus_space_write_4(sc->iot, sc->aud_ioh, 1315 ICH_GSTS + sc->sc_modem_offset, ICH_GSCI); 1316 ret++; 1317 } 1318 #endif 1319 1320 mutex_spin_exit(&sc->sc_intr_lock); 1321 1322 return ret; 1323 } 1324 1325 static void 1326 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1327 { 1328 int blksize, qptr; 1329 struct auich_dmalist *q; 1330 1331 blksize = ring->blksize; 1332 1333 for (qptr = 0; qptr < ICH_DMALIST_MAX; qptr++) { 1334 q = &ring->dmalist[qptr]; 1335 q->base = ring->p; 1336 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1337 1338 ring->p += blksize; 1339 if (ring->p >= ring->end) 1340 ring->p = ring->start; 1341 } 1342 ring->qptr = 0; 1343 1344 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1345 (qptr - 1) & ICH_LVI_MASK); 1346 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_CTRL, 1347 ICH_IOCE | ICH_FEIE | ICH_RPBM); 1348 } 1349 1350 static void 1351 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1352 { 1353 int blksize, qptr, nqptr; 1354 struct auich_dmalist *q; 1355 1356 blksize = ring->blksize; 1357 qptr = ring->qptr; 1358 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + ICH_CIV); 1359 1360 while (qptr != nqptr) { 1361 q = &ring->dmalist[qptr]; 1362 q->base = ring->p; 1363 q->len = (blksize >> sc->sc_sample_shift) | ICH_DMAF_IOC; 1364 1365 DPRINTF(ICH_DEBUG_INTR, 1366 (sc->sc_dev, "%s: %p, %p = %x @ 0x%x\n", __func__, 1367 &ring->dmalist[qptr], q, q->len, q->base)); 1368 1369 ring->p += blksize; 1370 if (ring->p >= ring->end) 1371 ring->p = ring->start; 1372 1373 qptr = (qptr + 1) & ICH_LVI_MASK; 1374 if (ring->intr) 1375 ring->intr(ring->arg); 1376 } 1377 ring->qptr = qptr; 1378 1379 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + ICH_LVI, 1380 (qptr - 1) & ICH_LVI_MASK); 1381 } 1382 1383 static int 1384 auich_trigger_output(void *v, void *start, void *end, int blksize, 1385 void (*intr)(void *), void *arg, const audio_params_t *param) 1386 { 1387 struct auich_softc *sc; 1388 struct auich_dma *p; 1389 size_t size; 1390 1391 sc = v; 1392 DPRINTF(ICH_DEBUG_DMA, 1393 (sc->sc_dev, "%s(%p, %p, %d, %p, %p, %p)\n", __func__, 1394 start, end, blksize, intr, arg, param)); 1395 1396 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1397 continue; 1398 if (!p) { 1399 aprint_error_dev(sc->sc_dev, "%s: bad addr %p\n", __func__, 1400 start); 1401 return EINVAL; 1402 } 1403 1404 size = (size_t)((char *)end - (char *)start); 1405 1406 sc->pcmo.intr = intr; 1407 sc->pcmo.arg = arg; 1408 sc->pcmo.start = DMAADDR(p); 1409 sc->pcmo.p = sc->pcmo.start; 1410 sc->pcmo.end = sc->pcmo.start + size; 1411 sc->pcmo.blksize = blksize; 1412 1413 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMO + ICH_BDBAR, 1414 sc->sc_cddma + ICH_PCMO_OFF(0)); 1415 auich_trigger_pipe(sc, ICH_PCMO, &sc->pcmo); 1416 1417 return 0; 1418 } 1419 1420 static int 1421 auich_trigger_input(void *v, void *start, void *end, int blksize, 1422 void (*intr)(void *), void *arg, const audio_params_t *param) 1423 { 1424 struct auich_softc *sc; 1425 struct auich_dma *p; 1426 size_t size; 1427 1428 sc = v; 1429 DPRINTF(ICH_DEBUG_DMA, 1430 (sc->sc_dev, "%s(%p, %p, %d, %p, %p, %p)\n", __func__, 1431 start, end, blksize, intr, arg, param)); 1432 1433 for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next) 1434 continue; 1435 if (!p) { 1436 aprint_error_dev(sc->sc_dev, "%s: bad addr %p\n", __func__, 1437 start); 1438 return EINVAL; 1439 } 1440 1441 size = (size_t)((char *)end - (char *)start); 1442 1443 sc->pcmi.intr = intr; 1444 sc->pcmi.arg = arg; 1445 sc->pcmi.start = DMAADDR(p); 1446 sc->pcmi.p = sc->pcmi.start; 1447 sc->pcmi.end = sc->pcmi.start + size; 1448 sc->pcmi.blksize = blksize; 1449 1450 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1451 sc->sc_cddma + ICH_PCMI_OFF(0)); 1452 auich_trigger_pipe(sc, ICH_PCMI, &sc->pcmi); 1453 1454 return 0; 1455 } 1456 1457 static int 1458 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1459 struct auich_dma *p) 1460 { 1461 int error; 1462 1463 p->size = size; 1464 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1465 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1466 &p->nsegs, BUS_DMA_WAITOK); 1467 if (error) 1468 return error; 1469 1470 error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1471 &p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags); 1472 if (error) 1473 goto free; 1474 1475 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1476 0, BUS_DMA_WAITOK, &p->map); 1477 if (error) 1478 goto unmap; 1479 1480 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1481 BUS_DMA_WAITOK); 1482 if (error) 1483 goto destroy; 1484 return 0; 1485 1486 destroy: 1487 bus_dmamap_destroy(sc->dmat, p->map); 1488 unmap: 1489 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1490 free: 1491 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1492 return error; 1493 } 1494 1495 static int 1496 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1497 { 1498 1499 bus_dmamap_unload(sc->dmat, p->map); 1500 bus_dmamap_destroy(sc->dmat, p->map); 1501 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1502 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1503 return 0; 1504 } 1505 1506 static int 1507 auich_alloc_cdata(struct auich_softc *sc) 1508 { 1509 bus_dma_segment_t seg; 1510 int error, rseg; 1511 1512 /* 1513 * Allocate the control data structure, and create and load the 1514 * DMA map for it. 1515 */ 1516 if ((error = bus_dmamem_alloc(sc->dmat, 1517 sizeof(struct auich_cdata), 1518 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1519 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", error); 1520 goto fail_0; 1521 } 1522 1523 if ((error = bus_dmamem_map(sc->dmat, &seg, rseg, 1524 sizeof(struct auich_cdata), 1525 (void **) &sc->sc_cdata, 1526 sc->sc_dmamap_flags)) != 0) { 1527 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", error); 1528 goto fail_1; 1529 } 1530 1531 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1532 sizeof(struct auich_cdata), 0, 0, 1533 &sc->sc_cddmamap)) != 0) { 1534 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1535 "error = %d\n", error); 1536 goto fail_2; 1537 } 1538 1539 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, 1540 sc->sc_cdata, sizeof(struct auich_cdata), 1541 NULL, 0)) != 0) { 1542 aprint_error_dev(sc->sc_dev, "unable tp load control data DMA map, " 1543 "error = %d\n", error); 1544 goto fail_3; 1545 } 1546 1547 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1548 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1549 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1550 1551 return 0; 1552 1553 fail_3: 1554 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1555 fail_2: 1556 bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata, 1557 sizeof(struct auich_cdata)); 1558 fail_1: 1559 bus_dmamem_free(sc->dmat, &seg, rseg); 1560 fail_0: 1561 return error; 1562 } 1563 1564 static bool 1565 auich_resume(device_t dv, const pmf_qual_t *qual) 1566 { 1567 struct auich_softc *sc = device_private(dv); 1568 pcireg_t v; 1569 1570 mutex_enter(&sc->sc_lock); 1571 mutex_spin_enter(&sc->sc_intr_lock); 1572 1573 if (sc->sc_iose) { 1574 v = pci_conf_read(sc->sc_pc, sc->sc_pt, ICH_CFG); 1575 pci_conf_write(sc->sc_pc, sc->sc_pt, ICH_CFG, 1576 v | ICH_CFG_IOSE); 1577 } 1578 1579 auich_reset_codec(sc); 1580 mutex_spin_exit(&sc->sc_intr_lock); 1581 DELAY(1000); 1582 (sc->codec_if->vtbl->restore_ports)(sc->codec_if); 1583 mutex_exit(&sc->sc_lock); 1584 1585 return true; 1586 } 1587 1588 /* 1589 * Calibrate card (some boards are overclocked and need scaling) 1590 */ 1591 static void 1592 auich_calibrate(struct auich_softc *sc) 1593 { 1594 struct timeval t1, t2; 1595 uint8_t ociv, nciv; 1596 uint64_t wait_us; 1597 uint32_t actual_48k_rate, bytes, ac97rate; 1598 void *temp_buffer; 1599 struct auich_dma *p; 1600 u_int rate; 1601 1602 /* 1603 * Grab audio from input for fixed interval and compare how 1604 * much we actually get with what we expect. Interval needs 1605 * to be sufficiently short that no interrupts are 1606 * generated. 1607 */ 1608 1609 /* Force the codec to a known state first. */ 1610 sc->codec_if->vtbl->set_clock(sc->codec_if, 48000); 1611 rate = sc->sc_ac97_clock = 48000; 1612 sc->codec_if->vtbl->set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1613 &rate); 1614 1615 /* Setup a buffer */ 1616 bytes = 64000; 1617 temp_buffer = auich_allocm(sc, AUMODE_RECORD, bytes); 1618 1619 for (p = sc->sc_dmas; p && KERNADDR(p) != temp_buffer; p = p->next) 1620 continue; 1621 if (p == NULL) { 1622 aprint_error_dev(sc->sc_dev, "%s: bad address %p\n", 1623 __func__, temp_buffer); 1624 return; 1625 } 1626 sc->pcmi.dmalist[0].base = DMAADDR(p); 1627 sc->pcmi.dmalist[0].len = (bytes >> sc->sc_sample_shift); 1628 1629 /* 1630 * our data format is stereo, 16 bit so each sample is 4 bytes. 1631 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1632 * we're going to start recording with interrupts disabled and measure 1633 * the time taken for one block to complete. we know the block size, 1634 * we know the time in microseconds, we calculate the sample rate: 1635 * 1636 * actual_rate [bps] = bytes / (time [s] * 4) 1637 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1638 * actual_rate [Hz] = (bytes * 250000) / time [us] 1639 */ 1640 1641 /* prepare */ 1642 ociv = bus_space_read_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CIV); 1643 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_BDBAR, 1644 sc->sc_cddma + ICH_PCMI_OFF(0)); 1645 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_LVI, 1646 (0 - 1) & ICH_LVI_MASK); 1647 1648 /* start */ 1649 kpreempt_disable(); 1650 microtime(&t1); 1651 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RPBM); 1652 1653 /* wait */ 1654 nciv = ociv; 1655 do { 1656 microtime(&t2); 1657 if (t2.tv_sec - t1.tv_sec > 1) 1658 break; 1659 nciv = bus_space_read_1(sc->iot, sc->aud_ioh, 1660 ICH_PCMI + ICH_CIV); 1661 } while (nciv == ociv); 1662 microtime(&t2); 1663 1664 /* stop */ 1665 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, 0); 1666 kpreempt_enable(); 1667 1668 /* reset */ 1669 DELAY(100); 1670 bus_space_write_1(sc->iot, sc->aud_ioh, ICH_PCMI + ICH_CTRL, ICH_RR); 1671 1672 /* turn time delta into us */ 1673 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; 1674 1675 auich_freem(sc, temp_buffer, bytes); 1676 1677 if (nciv == ociv) { 1678 aprint_error_dev(sc->sc_dev, "ac97 link rate calibration " 1679 "timed out after %" PRIu64 " us\n", wait_us); 1680 return; 1681 } 1682 1683 if (wait_us == 0) { 1684 /* Can happen with emulated hardware */ 1685 aprint_error_dev(sc->sc_dev, "abnormal zero delay during " 1686 "calibration\n"); 1687 return; 1688 } 1689 1690 rnd_add_data(NULL, &wait_us, sizeof(wait_us), 1); 1691 1692 actual_48k_rate = (bytes * UINT64_C(250000)) / wait_us; 1693 1694 if (actual_48k_rate < 50000) 1695 ac97rate = 48000; 1696 else 1697 ac97rate = ((actual_48k_rate + 500) / 1000) * 1000; 1698 1699 aprint_verbose_dev(sc->sc_dev, "measured ac97 link rate at %d Hz", 1700 actual_48k_rate); 1701 if (ac97rate != actual_48k_rate) 1702 aprint_verbose(", will use %d Hz", ac97rate); 1703 aprint_verbose("\n"); 1704 1705 sc->sc_ac97_clock = ac97rate; 1706 } 1707 1708 static void 1709 auich_clear_cas(struct auich_softc *sc) 1710 { 1711 /* Clear the codec access semaphore */ 1712 (void)bus_space_read_2(sc->iot, sc->mix_ioh, 1713 AC97_REG_RESET * (sc->sc_codecnum * ICH_CODEC_OFFSET)); 1714 1715 return; 1716 } 1717 1718 static void 1719 auich_get_locks(void *addr, kmutex_t **intr, kmutex_t **thread) 1720 { 1721 struct auich_softc *sc; 1722 1723 sc = addr; 1724 *intr = &sc->sc_intr_lock; 1725 *thread = &sc->sc_lock; 1726 } 1727