1 /* $NetBSD: auacerreg.h,v 1.3 2005/12/11 12:22:48 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _DEV_PCI_AUACERREG_H_ 40 #define _DEV_PCI_AUACERREG_H_ 41 42 #define ALI_SCR 0x00 /* System Control Register */ 43 #define ALI_SCR_RESET (1<<31) /* master reset */ 44 #define ALI_SCR_AC97_DBL (1<<30) 45 #define ALI_SCR_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 46 #define ALI_SCR_IN_BITS (3<<18) 47 #define ALI_SCR_OUT_BITS (3<<16) 48 #define ALI_SCR_6CH_CFG (3<<14) 49 #define ALI_SCR_PCM_4 (1<<8) 50 #define ALI_SCR_PCM_6 (2<<8) 51 #define ALI_SCR_PCM_246_MASK (ALI_SCR_PCM_4 | ALI_SCR_PCM_6) 52 #define ALI_SSR 0x04 /* System Status Register */ 53 #define ALI_SSR_SEC_ID (3<<5) 54 #define ALI_SSR_PRI_ID (3<<3) 55 #define ALI_DMACR 0x08 /* DMA Control Register */ 56 #define ALI_DMACR_PAUSE 16 /* offset for pause bits */ 57 #define ALI_FIFOCR1 0x0c /* FIFO Control Register 1 */ 58 #define ALI_INTERFACECR 0x10 /* Interface Control Register */ 59 #define ALI_INTERRUPTCR 0x14 /* Interrupt Control Register */ 60 #define ALI_INTERRUPTSR 0x18 /* Interrupt Status Register */ 61 #define ALI_INT_MICIN2 (1<<26) 62 #define ALI_INT_PCMIN2 (1<<25) 63 #define ALI_INT_I2SIN (1<<24) 64 #define ALI_INT_SPDIFOUT (1<<23) 65 #define ALI_INT_SPDIFIN (1<<22) 66 #define ALI_INT_LFEOUT (1<<21) 67 #define ALI_INT_CENTEROUT (1<<20) 68 #define ALI_INT_CODECSPDIFOUT (1<<19) 69 #define ALI_INT_MICIN (1<<18) 70 #define ALI_INT_PCMOUT (1<<17) 71 #define ALI_INT_PCMIN (1<<16) 72 #define ALI_INT_CPRAIS (1<<7) 73 #define ALI_INT_SPRAIS (1<<5) 74 #define ALI_INT_GPIO (1<<1) 75 #define ALI_FIFOCR2 0x1c /* FIFO Control Register 2 */ 76 #define ALI_CPR 0x20 /* Command Port Register */ 77 #define ALI_CPR_ADDR_SECONDARY 0x100 78 #define ALI_CPR_ADDR_READ 0x80 79 #define ALI_CPR_ADDR 0x22 /* AC97 write addr */ 80 #define ALI_SPR 0x24 /* Status Port Register */ 81 #define ALI_SPR_ADDR 0x26 /* AC97 read addr */ 82 #define ALI_FIFOCR3 0x2c /* FIFO Control Register 3 */ 83 #define ALI_TTSR 0x30 /* Transmit Tag Slot Register */ 84 #define ALI_RTSR 0x34 /* Receive Tag Slot Register */ 85 #define ALI_CSPSR 0x38 /* Command/Status Port Status Register */ 86 #define ALI_CSPSR_CODEC_READY 0x08 87 #define ALI_CSPSR_READ_OK 0x02 88 #define ALI_CSPSR_WRITE_OK 0x01 89 #define ALI_CAS 0x3c /* Codec Write Semaphore Register */ 90 #define ALI_CAS_SEM_BUSY 0x80000000 91 #define ALI_HWVOL 0xf0 /* hardware volume control/status */ 92 #define ALI_I2SCR 0xf4 /* I2S control/status */ 93 #define ALI_SPDIFCSR 0xf8 /* SPDIF Channel Status Register */ 94 #define ALI_SPDIFICS 0xfc /* SPDIF Interface Control/Status */ 95 96 97 #define ALI_OFF_BDBAR 0x00 /* Buffer Descriptor list Base Address */ 98 #define ALI_OFF_CIV 0x04 /* Current Index Value */ 99 #define ALI_OFF_LVI 0x05 /* Last Valid Index */ 100 #define ALI_LVI_MASK 0x1f 101 #define ALI_OFF_SR 0x06 /* Status Register */ 102 #define ALI_SR_DMA_INT_FIFO (1<<4) /* fifo under/over flow */ 103 #define ALI_SR_DMA_INT_COMPLETE (1<<3) /* buffer read/write complete and ioc set */ 104 #define ALI_SR_DMA_INT_LVI (1<<2) /* last valid done */ 105 #define ALI_SR_DMA_INT_CELV (1<<1) /* last valid is current */ 106 #define ALI_SR_DMA_INT_DCH (1<<0) /* DMA Controller Halted (happens on LVI interrupts) */ 107 #define ALI_SR_W1TC (ALI_SR_DMA_INT_LVI | ALI_SR_DMA_INT_COMPLETE | ALI_SR_DMA_INT_FIFO | ALI_SR_DMA_INT_CELV) 108 #define ALI_OFF_PICB 0x08 /* Position In Current Buffer */ 109 #define ALI_PIV 0x0a /* 5 bits prefetched index value */ 110 #define ALI_OFF_CR 0x0b /* Control Register */ 111 #define ALI_CR_IOCE 0x10 /* Int On Completion Enable */ 112 #define ALI_CR_FEIE 0x08 /* Fifo Error Int Enable */ 113 #define ALI_CR_LVBIE 0x04 /* Last Valid Buf Int Enable */ 114 #define ALI_CR_RR 0x02 /* 1 - Reset Regs */ 115 #define ALI_CR_RPBM 0x01 /* 1 - Run, 0 - Pause */ 116 117 #define ALI_BASE_PI 0x40 /* PCM In */ 118 #define ALI_BASE_PO 0x50 /* PCM Out */ 119 #define ALI_BASE_MC 0x60 /* Mic In */ 120 #define ALI_BASE_CODEC_SPDIFO 0x70 /* Codec SPDIF Out */ 121 #define ALI_BASE_CENTER 0x80 /* Center out */ 122 #define ALI_BASE_LFE 0x90 /* ? */ 123 #define ALI_BASE_CTL_SPDIFI 0xa0 /* Controller SPDIF In */ 124 #define ALI_BASE_CTL_SPDIFO 0xb0 /* Controller SPDIF Out */ 125 126 #define ALI_PORT2SLOT(port) (((port) - 0x40) / 0x10) 127 #define ALI_PORT2INTR(port) (ALI_PORT2SLOT(port) + 16) 128 129 #define ALI_IF_AC97SP (1<<21) 130 #define ALI_IF_MC (1<<20) 131 #define ALI_IF_PI (1<<19) 132 #define ALI_IF_MC2 (1<<18) 133 #define ALI_IF_PI2 (1<<17) 134 #define ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 135 #define ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 136 #define ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 137 #define ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 138 #define ALI_IF_PO_SPDF (1<<3) 139 #define ALI_IF_PO (1<<1) 140 141 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 142 143 #define ALI_SAMPLE_SIZE 2 144 145 146 /* 147 * according to the dev/audiovar.h AU_RING_SIZE is 2^16, what fits 148 * in our limits perfectly, i.e. setting it to higher value 149 * in your kernel config would improve perfomance, still 2^21 is the max 150 */ 151 #define ALI_DMALIST_MAX 32 152 #define ALI_DMASEG_MAX (65536*2) /* 64k samples, 2x16 bit samples */ 153 struct auacer_dmalist { 154 uint32_t base; 155 uint32_t len; 156 #define ALI_DMAF_IOC 0x80000000 /* 1-int on complete */ 157 #define ALI_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */ 158 }; 159 160 #endif /* _DEV_PCI_AUACERREG_H_ */ 161