1 /* $NetBSD: amr.c,v 1.19 2003/11/05 16:03:27 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999,2000 Michael Smith 41 * Copyright (c) 2000 BSDi 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 66 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 67 */ 68 69 /* 70 * Driver for AMI RAID controllers. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.19 2003/11/05 16:03:27 fvdl Exp $"); 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 #include <sys/proc.h> 82 #include <sys/buf.h> 83 #include <sys/malloc.h> 84 #include <sys/kthread.h> 85 86 #include <uvm/uvm_extern.h> 87 88 #include <machine/endian.h> 89 #include <machine/bus.h> 90 91 #include <dev/pci/pcidevs.h> 92 #include <dev/pci/pcivar.h> 93 #include <dev/pci/amrreg.h> 94 #include <dev/pci/amrvar.h> 95 96 void amr_attach(struct device *, struct device *, void *); 97 void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 98 void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, void *); 99 int amr_init(struct amr_softc *, const char *, 100 struct pci_attach_args *pa); 101 int amr_intr(void *); 102 int amr_match(struct device *, struct cfdata *, void *); 103 int amr_print(void *, const char *); 104 void amr_shutdown(void *); 105 int amr_submatch(struct device *, struct cfdata *, void *); 106 void amr_teardown(struct amr_softc *); 107 void amr_thread(void *); 108 void amr_thread_create(void *); 109 110 int amr_mbox_wait(struct amr_softc *); 111 int amr_quartz_get_work(struct amr_softc *, struct amr_mailbox_resp *); 112 int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 113 int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 114 int amr_std_submit(struct amr_softc *, struct amr_ccb *); 115 116 static inline u_int8_t amr_inb(struct amr_softc *, int); 117 static inline u_int32_t amr_inl(struct amr_softc *, int); 118 static inline void amr_outb(struct amr_softc *, int, u_int8_t); 119 static inline void amr_outl(struct amr_softc *, int, u_int32_t); 120 121 CFATTACH_DECL(amr, sizeof(struct amr_softc), 122 amr_match, amr_attach, NULL, NULL); 123 124 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 125 #define AT_SIG 0x02 /* Check for signature */ 126 127 struct amr_pci_type { 128 u_short apt_vendor; 129 u_short apt_product; 130 u_short apt_flags; 131 } const amr_pci_type[] = { 132 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 133 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 134 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 136 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 137 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 138 }; 139 140 struct amr_typestr { 141 const char *at_str; 142 int at_sig; 143 } const amr_typestr[] = { 144 { "Series 431", AMR_SIG_431 }, 145 { "Series 438", AMR_SIG_438 }, 146 { "Series 466", AMR_SIG_466 }, 147 { "Series 467", AMR_SIG_467 }, 148 { "Series 490", AMR_SIG_490 }, 149 { "Series 762", AMR_SIG_762 }, 150 { "HP NetRAID (T5)", AMR_SIG_T5 }, 151 { "HP NetRAID (T7)", AMR_SIG_T7 }, 152 }; 153 154 struct { 155 const char *ds_descr; 156 int ds_happy; 157 } const amr_dstate[] = { 158 { "offline", 0 }, 159 { "degraded", 1 }, 160 { "optimal", 1 }, 161 { "online", 1 }, 162 { "failed", 0 }, 163 { "rebuilding", 1 }, 164 { "hotspare", 0 }, 165 }; 166 167 void *amr_sdh; 168 int amr_max_segs; 169 int amr_max_xfer; 170 171 static inline u_int8_t 172 amr_inb(struct amr_softc *amr, int off) 173 { 174 175 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 176 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 177 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 178 } 179 180 static inline u_int32_t 181 amr_inl(struct amr_softc *amr, int off) 182 { 183 184 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 185 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 186 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 187 } 188 189 static inline void 190 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 191 { 192 193 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 194 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 195 BUS_SPACE_BARRIER_WRITE); 196 } 197 198 static inline void 199 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 200 { 201 202 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 203 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 204 BUS_SPACE_BARRIER_WRITE); 205 } 206 207 /* 208 * Match a supported device. 209 */ 210 int 211 amr_match(struct device *parent, struct cfdata *match, void *aux) 212 { 213 struct pci_attach_args *pa; 214 pcireg_t s; 215 int i; 216 217 pa = (struct pci_attach_args *)aux; 218 219 /* 220 * Don't match the device if it's operating in I2O mode. In this 221 * case it should be handled by the `iop' driver. 222 */ 223 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 224 return (0); 225 226 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 227 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 228 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 229 break; 230 231 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 232 return (0); 233 234 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 235 return (1); 236 237 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 238 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 239 } 240 241 /* 242 * Attach a supported device. 243 */ 244 void 245 amr_attach(struct device *parent, struct device *self, void *aux) 246 { 247 struct pci_attach_args *pa; 248 struct amr_attach_args amra; 249 const struct amr_pci_type *apt; 250 struct amr_softc *amr; 251 pci_chipset_tag_t pc; 252 pci_intr_handle_t ih; 253 const char *intrstr; 254 pcireg_t reg; 255 int rseg, i, j, size, rv, memreg, ioreg; 256 struct amr_ccb *ac; 257 258 aprint_naive(": RAID controller\n"); 259 260 amr = (struct amr_softc *)self; 261 pa = (struct pci_attach_args *)aux; 262 pc = pa->pa_pc; 263 264 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 265 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 266 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 267 break; 268 apt = amr_pci_type + i; 269 270 memreg = ioreg = 0; 271 for (i = 0x10; i <= 0x14; i += 4) { 272 reg = pci_conf_read(pc, pa->pa_tag, i); 273 switch (PCI_MAPREG_TYPE(reg)) { 274 case PCI_MAPREG_TYPE_MEM: 275 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 276 memreg = i; 277 break; 278 case PCI_MAPREG_TYPE_IO: 279 if (PCI_MAPREG_IO_SIZE(reg) != 0) 280 ioreg = i; 281 break; 282 283 } 284 } 285 286 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 287 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 288 ; 289 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 290 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 291 ; 292 else { 293 aprint_error("can't map control registers\n"); 294 amr_teardown(amr); 295 return; 296 } 297 298 amr->amr_flags |= AMRF_PCI_REGS; 299 amr->amr_dmat = pa->pa_dmat; 300 amr->amr_pc = pa->pa_pc; 301 302 /* Enable the device. */ 303 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 304 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 305 reg | PCI_COMMAND_MASTER_ENABLE); 306 307 /* Map and establish the interrupt. */ 308 if (pci_intr_map(pa, &ih)) { 309 aprint_error("can't map interrupt\n"); 310 amr_teardown(amr); 311 return; 312 } 313 intrstr = pci_intr_string(pc, ih); 314 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr); 315 if (amr->amr_ih == NULL) { 316 aprint_error("can't establish interrupt"); 317 if (intrstr != NULL) 318 aprint_normal(" at %s", intrstr); 319 aprint_normal("\n"); 320 amr_teardown(amr); 321 return; 322 } 323 amr->amr_flags |= AMRF_PCI_INTR; 324 325 /* 326 * Allocate space for the mailbox and S/G lists. Some controllers 327 * don't like S/G lists to be located below 0x2000, so we allocate 328 * enough slop to enable us to compensate. 329 * 330 * The standard mailbox structure needs to be aligned on a 16-byte 331 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 332 * size, which preceeds the standard mailbox. 333 */ 334 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 335 amr->amr_dmasize = size; 336 337 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 338 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 339 aprint_error("%s: unable to allocate buffer, rv = %d\n", 340 amr->amr_dv.dv_xname, rv); 341 amr_teardown(amr); 342 return; 343 } 344 amr->amr_flags |= AMRF_DMA_ALLOC; 345 346 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 347 (caddr_t *)&amr->amr_mbox, 348 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 349 aprint_error("%s: unable to map buffer, rv = %d\n", 350 amr->amr_dv.dv_xname, rv); 351 amr_teardown(amr); 352 return; 353 } 354 amr->amr_flags |= AMRF_DMA_MAP; 355 356 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 357 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 358 aprint_error("%s: unable to create buffer DMA map, rv = %d\n", 359 amr->amr_dv.dv_xname, rv); 360 amr_teardown(amr); 361 return; 362 } 363 amr->amr_flags |= AMRF_DMA_CREATE; 364 365 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 366 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 367 aprint_error("%s: unable to load buffer DMA map, rv = %d\n", 368 amr->amr_dv.dv_xname, rv); 369 amr_teardown(amr); 370 return; 371 } 372 amr->amr_flags |= AMRF_DMA_LOAD; 373 374 memset(amr->amr_mbox, 0, size); 375 376 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 377 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 378 amr->amr_sgls = (struct amr_sgentry *)((caddr_t)amr->amr_mbox + 379 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 380 381 /* 382 * Allocate and initalise the command control blocks. 383 */ 384 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO); 385 amr->amr_ccbs = ac; 386 SLIST_INIT(&amr->amr_ccb_freelist); 387 TAILQ_INIT(&amr->amr_ccb_active); 388 amr->amr_flags |= AMRF_CCBS; 389 390 if (amr_max_xfer == 0) { 391 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 392 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 393 } 394 395 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 396 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 397 amr_max_segs, amr_max_xfer, 0, 398 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 399 if (rv != 0) 400 break; 401 402 ac->ac_ident = i; 403 amr_ccb_free(amr, ac); 404 } 405 if (i != AMR_MAX_CMDS) { 406 aprint_error("%s: memory exhausted\n", amr->amr_dv.dv_xname); 407 amr_teardown(amr); 408 return; 409 } 410 411 /* 412 * Take care of model-specific tasks. 413 */ 414 if ((apt->apt_flags & AT_QUARTZ) != 0) { 415 amr->amr_submit = amr_quartz_submit; 416 amr->amr_get_work = amr_quartz_get_work; 417 } else { 418 amr->amr_submit = amr_std_submit; 419 amr->amr_get_work = amr_std_get_work; 420 421 /* Notify the controller of the mailbox location. */ 422 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 423 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 424 425 /* Clear outstanding interrupts and enable interrupts. */ 426 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 427 amr_outb(amr, AMR_SREG_TOGL, 428 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 429 } 430 431 /* 432 * Retrieve parameters, and tell the world about us. 433 */ 434 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT); 435 amr->amr_flags |= AMRF_ENQBUF; 436 amr->amr_maxqueuecnt = i; 437 aprint_normal(": AMI RAID "); 438 if (amr_init(amr, intrstr, pa) != 0) { 439 amr_teardown(amr); 440 return; 441 } 442 443 /* 444 * Cap the maximum number of outstanding commands. AMI's Linux 445 * driver doesn't trust the controller's reported value, and lockups 446 * have been seen when we do. 447 */ 448 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 449 if (amr->amr_maxqueuecnt > i) 450 amr->amr_maxqueuecnt = i; 451 452 /* Set our `shutdownhook' before we start any device activity. */ 453 if (amr_sdh == NULL) 454 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 455 456 /* Attach sub-devices. */ 457 for (j = 0; j < amr->amr_numdrives; j++) { 458 if (amr->amr_drive[j].al_size == 0) 459 continue; 460 amra.amra_unit = j; 461 amr->amr_drive[j].al_dv = config_found_sm(&amr->amr_dv, &amra, 462 amr_print, amr_submatch); 463 } 464 465 SIMPLEQ_INIT(&amr->amr_ccb_queue); 466 467 /* XXX This doesn't work for newer boards yet. */ 468 if ((apt->apt_flags & AT_QUARTZ) == 0) 469 kthread_create(amr_thread_create, amr); 470 } 471 472 /* 473 * Free up resources. 474 */ 475 void 476 amr_teardown(struct amr_softc *amr) 477 { 478 struct amr_ccb *ac; 479 int fl; 480 481 fl = amr->amr_flags; 482 483 if ((fl & AMRF_THREAD) != 0) { 484 amr->amr_flags |= AMRF_THREAD_EXIT; 485 wakeup(amr_thread); 486 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) 487 tsleep(&amr->amr_flags, PWAIT, "amrexit", 0); 488 } 489 if ((fl & AMRF_CCBS) != 0) { 490 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 491 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 492 } 493 free(amr->amr_ccbs, M_DEVBUF); 494 } 495 if ((fl & AMRF_ENQBUF) != 0) 496 free(amr->amr_enqbuf, M_DEVBUF); 497 if ((fl & AMRF_DMA_LOAD) != 0) 498 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 499 if ((fl & AMRF_DMA_MAP) != 0) 500 bus_dmamem_unmap(amr->amr_dmat, (caddr_t)amr->amr_mbox, 501 amr->amr_dmasize); 502 if ((fl & AMRF_DMA_ALLOC) != 0) 503 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 504 if ((fl & AMRF_DMA_CREATE) != 0) 505 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 506 if ((fl & AMRF_PCI_INTR) != 0) 507 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 508 if ((fl & AMRF_PCI_REGS) != 0) 509 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 510 } 511 512 /* 513 * Print autoconfiguration message for a sub-device. 514 */ 515 int 516 amr_print(void *aux, const char *pnp) 517 { 518 struct amr_attach_args *amra; 519 520 amra = (struct amr_attach_args *)aux; 521 522 if (pnp != NULL) 523 aprint_normal("block device at %s", pnp); 524 aprint_normal(" unit %d", amra->amra_unit); 525 return (UNCONF); 526 } 527 528 /* 529 * Match a sub-device. 530 */ 531 int 532 amr_submatch(struct device *parent, struct cfdata *cf, void *aux) 533 { 534 struct amr_attach_args *amra; 535 536 amra = (struct amr_attach_args *)aux; 537 538 if (cf->amracf_unit != AMRCF_UNIT_DEFAULT && 539 cf->amracf_unit != amra->amra_unit) 540 return (0); 541 542 return (config_match(parent, cf, aux)); 543 } 544 545 /* 546 * Retrieve operational parameters and describe the controller. 547 */ 548 int 549 amr_init(struct amr_softc *amr, const char *intrstr, 550 struct pci_attach_args *pa) 551 { 552 struct amr_adapter_info *aa; 553 struct amr_prodinfo *ap; 554 struct amr_enquiry *ae; 555 struct amr_enquiry3 *aex; 556 const char *prodstr; 557 u_int i, sig, ishp; 558 char buf[64]; 559 560 /* 561 * Try to get 40LD product info, which tells us what the card is 562 * labelled as. 563 */ 564 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 565 amr->amr_enqbuf); 566 if (ap != NULL) { 567 aprint_normal("<%.80s>\n", ap->ap_product); 568 if (intrstr != NULL) 569 aprint_normal("%s: interrupting at %s\n", 570 amr->amr_dv.dv_xname, intrstr); 571 aprint_normal("%s: firmware %.16s, BIOS %.16s, %dMB RAM\n", 572 amr->amr_dv.dv_xname, ap->ap_firmware, ap->ap_bios, 573 le16toh(ap->ap_memsize)); 574 575 amr->amr_maxqueuecnt = ap->ap_maxio; 576 577 /* 578 * Fetch and record state of logical drives. 579 */ 580 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 581 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 582 if (aex == NULL) { 583 aprint_error("%s ENQUIRY3 failed\n", 584 amr->amr_dv.dv_xname); 585 return (-1); 586 } 587 588 if (aex->ae_numldrives > AMR_MAX_UNITS) { 589 aprint_error( 590 "%s: adjust AMR_MAX_UNITS to %d (currently %d)" 591 "\n", amr->amr_dv.dv_xname, AMR_MAX_UNITS, 592 amr->amr_numdrives); 593 amr->amr_numdrives = AMR_MAX_UNITS; 594 } else 595 amr->amr_numdrives = aex->ae_numldrives; 596 597 for (i = 0; i < amr->amr_numdrives; i++) { 598 amr->amr_drive[i].al_size = 599 le32toh(aex->ae_drivesize[i]); 600 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 601 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 602 } 603 604 return (0); 605 } 606 607 /* 608 * Try 8LD extended ENQUIRY to get the controller signature. Once 609 * found, search for a product description. 610 */ 611 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 612 if (ae != NULL) { 613 i = 0; 614 sig = le32toh(ae->ae_signature); 615 616 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 617 if (amr_typestr[i].at_sig == sig) 618 break; 619 i++; 620 } 621 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 622 sprintf(buf, "unknown ENQUIRY2 sig (0x%08x)", sig); 623 prodstr = buf; 624 } else 625 prodstr = amr_typestr[i].at_str; 626 } else { 627 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 628 if (ae == NULL) { 629 aprint_error("%s: unsupported controller\n", 630 amr->amr_dv.dv_xname); 631 return (-1); 632 } 633 634 switch (PCI_PRODUCT(pa->pa_id)) { 635 case PCI_PRODUCT_AMI_MEGARAID: 636 prodstr = "Series 428"; 637 break; 638 case PCI_PRODUCT_AMI_MEGARAID2: 639 prodstr = "Series 434"; 640 break; 641 default: 642 sprintf(buf, "unknown PCI dev (0x%04x)", 643 PCI_PRODUCT(pa->pa_id)); 644 prodstr = buf; 645 break; 646 } 647 } 648 649 /* 650 * HP NetRaid controllers have a special encoding of the firmware 651 * and BIOS versions. The AMI version seems to have it as strings 652 * whereas the HP version does it with a leading uppercase character 653 * and two binary numbers. 654 */ 655 aa = &ae->ae_adapter; 656 657 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 658 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 659 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 660 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 661 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 662 /* The AMI 438 is a NetRaid 3si in HP-land. */ 663 prodstr = "HP NetRaid 3si"; 664 } 665 ishp = 1; 666 } else 667 ishp = 0; 668 669 aprint_normal("<%s>\n", prodstr); 670 if (intrstr != NULL) 671 aprint_normal("%s: interrupting at %s\n", amr->amr_dv.dv_xname, 672 intrstr); 673 674 if (ishp) 675 aprint_normal("%s: firmware <%c.%02d.%02d>, BIOS <%c.%02d.%02d>" 676 ", %dMB RAM\n", amr->amr_dv.dv_xname, aa->aa_firmware[2], 677 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 678 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 679 else 680 aprint_normal("%s: firmware <%.4s>, BIOS <%.4s>, %dMB RAM\n", 681 amr->amr_dv.dv_xname, aa->aa_firmware, aa->aa_bios, 682 aa->aa_memorysize); 683 684 amr->amr_maxqueuecnt = aa->aa_maxio; 685 686 /* 687 * Record state of logical drives. 688 */ 689 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 690 aprint_error("%s: adjust AMR_MAX_UNITS to %d (currently %d)\n", 691 amr->amr_dv.dv_xname, ae->ae_ldrv.al_numdrives, 692 AMR_MAX_UNITS); 693 amr->amr_numdrives = AMR_MAX_UNITS; 694 } else 695 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 696 697 for (i = 0; i < AMR_MAX_UNITS; i++) { 698 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 699 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 700 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 701 } 702 703 return (0); 704 } 705 706 /* 707 * Flush the internal cache on each configured controller. Called at 708 * shutdown time. 709 */ 710 void 711 amr_shutdown(void *cookie) 712 { 713 extern struct cfdriver amr_cd; 714 struct amr_softc *amr; 715 struct amr_ccb *ac; 716 int i, rv, s; 717 718 for (i = 0; i < amr_cd.cd_ndevs; i++) { 719 if ((amr = device_lookup(&amr_cd, i)) == NULL) 720 continue; 721 722 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 723 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 724 s = splbio(); 725 rv = amr_ccb_poll(amr, ac, 30000); 726 splx(s); 727 amr_ccb_free(amr, ac); 728 } 729 if (rv != 0) 730 printf("%s: unable to flush cache (%d)\n", 731 amr->amr_dv.dv_xname, rv); 732 } 733 } 734 735 /* 736 * Interrupt service routine. 737 */ 738 int 739 amr_intr(void *cookie) 740 { 741 struct amr_softc *amr; 742 struct amr_ccb *ac; 743 struct amr_mailbox_resp mbox; 744 u_int i, forus, idx; 745 746 amr = cookie; 747 forus = 0; 748 749 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 750 /* Iterate over completed commands in this result. */ 751 for (i = 0; i < mbox.mb_nstatus; i++) { 752 idx = mbox.mb_completed[i] - 1; 753 ac = amr->amr_ccbs + idx; 754 755 if (idx >= amr->amr_maxqueuecnt) { 756 printf("%s: bad status (bogus ID: %u=%u)\n", 757 amr->amr_dv.dv_xname, i, idx); 758 continue; 759 } 760 761 if ((ac->ac_flags & AC_ACTIVE) == 0) { 762 printf("%s: bad status (not active; 0x04%x)\n", 763 amr->amr_dv.dv_xname, ac->ac_flags); 764 continue; 765 } 766 767 ac->ac_status = mbox.mb_status; 768 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 769 AC_COMPLETE; 770 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 771 772 if ((ac->ac_flags & AC_MOAN) != 0) 773 printf("%s: ccb %d completed\n", 774 amr->amr_dv.dv_xname, ac->ac_ident); 775 776 /* Pass notification to upper layers. */ 777 if (ac->ac_handler != NULL) 778 (*ac->ac_handler)(ac); 779 else 780 wakeup(ac); 781 } 782 forus = 1; 783 } 784 785 if (forus) 786 amr_ccb_enqueue(amr, NULL); 787 788 return (forus); 789 } 790 791 /* 792 * Create the watchdog thread. 793 */ 794 void 795 amr_thread_create(void *cookie) 796 { 797 struct amr_softc *amr; 798 int rv; 799 800 amr = cookie; 801 802 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 803 amr->amr_flags ^= AMRF_THREAD_EXIT; 804 wakeup(&amr->amr_flags); 805 return; 806 } 807 808 rv = kthread_create1(amr_thread, amr, &amr->amr_thread, "%s", 809 amr->amr_dv.dv_xname); 810 if (rv != 0) 811 aprint_error("%s: unable to create thread (%d)", 812 amr->amr_dv.dv_xname, rv); 813 else 814 amr->amr_flags |= AMRF_THREAD; 815 } 816 817 /* 818 * Watchdog thread. 819 */ 820 void 821 amr_thread(void *cookie) 822 { 823 struct amr_softc *amr; 824 struct amr_ccb *ac; 825 struct amr_logdrive *al; 826 struct amr_enquiry *ae; 827 time_t curtime; 828 int rv, i, s; 829 830 amr = cookie; 831 ae = amr->amr_enqbuf; 832 833 for (;;) { 834 tsleep(amr_thread, PWAIT, "amrwdog", AMR_WDOG_TICKS); 835 836 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 837 amr->amr_flags ^= AMRF_THREAD_EXIT; 838 wakeup(&amr->amr_flags); 839 kthread_exit(0); 840 } 841 842 s = splbio(); 843 amr_intr(cookie); 844 curtime = (time_t)mono_time.tv_sec; 845 ac = TAILQ_FIRST(&amr->amr_ccb_active); 846 while (ac != NULL) { 847 if (ac->ac_start_time + AMR_TIMEOUT > curtime) 848 break; 849 if ((ac->ac_flags & AC_MOAN) == 0) { 850 printf("%s: ccb %d timed out; mailbox:\n", 851 amr->amr_dv.dv_xname, ac->ac_ident); 852 amr_ccb_dump(amr, ac); 853 ac->ac_flags |= AC_MOAN; 854 } 855 ac = TAILQ_NEXT(ac, ac_chain.tailq); 856 } 857 splx(s); 858 859 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 860 printf("%s: ccb_alloc failed (%d)\n", 861 amr->amr_dv.dv_xname, rv); 862 continue; 863 } 864 865 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 866 867 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 868 AMR_ENQUIRY_BUFSIZE, 0); 869 if (rv != 0) { 870 printf("%s: ccb_map failed (%d)\n", 871 amr->amr_dv.dv_xname, rv); 872 amr_ccb_free(amr, ac); 873 continue; 874 } 875 876 rv = amr_ccb_wait(amr, ac); 877 amr_ccb_unmap(amr, ac); 878 if (rv != 0) { 879 printf("%s: enquiry failed (st=%d)\n", 880 amr->amr_dv.dv_xname, ac->ac_status); 881 continue; 882 } 883 amr_ccb_free(amr, ac); 884 885 al = amr->amr_drive; 886 for (i = 0; i < AMR_MAX_UNITS; i++, al++) { 887 if (al->al_dv == NULL) 888 continue; 889 if (al->al_state == ae->ae_ldrv.al_state[i]) 890 continue; 891 892 printf("%s: state changed: %s -> %s\n", 893 al->al_dv->dv_xname, 894 amr_drive_state(al->al_state, NULL), 895 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 896 897 al->al_state = ae->ae_ldrv.al_state[i]; 898 } 899 } 900 } 901 902 /* 903 * Return a text description of a logical drive's current state. 904 */ 905 const char * 906 amr_drive_state(int state, int *happy) 907 { 908 const char *str; 909 910 state = AMR_DRV_CURSTATE(state); 911 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 912 if (happy) 913 *happy = 1; 914 str = "status unknown"; 915 } else { 916 if (happy) 917 *happy = amr_dstate[state].ds_happy; 918 str = amr_dstate[state].ds_descr; 919 } 920 921 return (str); 922 } 923 924 /* 925 * Run a generic enquiry-style command. 926 */ 927 void * 928 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 929 u_int8_t cmdqual, void *buf) 930 { 931 struct amr_ccb *ac; 932 u_int8_t *mb; 933 int rv; 934 935 if (amr_ccb_alloc(amr, &ac) != 0) 936 return (NULL); 937 938 /* Build the command proper. */ 939 mb = (u_int8_t *)&ac->ac_cmd; 940 mb[0] = cmd; 941 mb[2] = cmdsub; 942 mb[3] = cmdqual; 943 944 rv = amr_ccb_map(amr, ac, buf, AMR_ENQUIRY_BUFSIZE, 0); 945 if (rv == 0) { 946 rv = amr_ccb_poll(amr, ac, 2000); 947 amr_ccb_unmap(amr, ac); 948 } 949 amr_ccb_free(amr, ac); 950 951 return (rv ? NULL : buf); 952 } 953 954 /* 955 * Allocate and initialise a CCB. 956 */ 957 int 958 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 959 { 960 int s; 961 962 s = splbio(); 963 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 964 splx(s); 965 return (EAGAIN); 966 } 967 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 968 splx(s); 969 970 return (0); 971 } 972 973 /* 974 * Free a CCB. 975 */ 976 void 977 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 978 { 979 int s; 980 981 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 982 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 983 ac->ac_cmd.mb_busy = 1; 984 ac->ac_handler = NULL; 985 ac->ac_flags = 0; 986 987 s = splbio(); 988 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 989 splx(s); 990 } 991 992 /* 993 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 994 * the order that they were enqueued and try to submit their command blocks 995 * to the controller for execution. 996 */ 997 void 998 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 999 { 1000 int s; 1001 1002 s = splbio(); 1003 1004 if (ac != NULL) 1005 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1006 1007 while ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1008 if ((*amr->amr_submit)(amr, ac) != 0) 1009 break; 1010 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, ac_chain.simpleq); 1011 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1012 } 1013 1014 splx(s); 1015 } 1016 1017 /* 1018 * Map the specified CCB's data buffer onto the bus, and fill the 1019 * scatter-gather list. 1020 */ 1021 int 1022 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1023 int out) 1024 { 1025 struct amr_sgentry *sge; 1026 struct amr_mailbox_cmd *mb; 1027 int nsegs, i, rv, sgloff; 1028 bus_dmamap_t xfer; 1029 1030 xfer = ac->ac_xfer_map; 1031 1032 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1033 BUS_DMA_NOWAIT); 1034 if (rv != 0) 1035 return (rv); 1036 1037 mb = &ac->ac_cmd; 1038 ac->ac_xfer_size = size; 1039 ac->ac_flags |= (out ? AC_XFER_OUT : AC_XFER_IN); 1040 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1041 1042 /* We don't need to use a scatter/gather list for just 1 segment. */ 1043 nsegs = xfer->dm_nsegs; 1044 if (nsegs == 1) { 1045 mb->mb_nsgelem = 0; 1046 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1047 ac->ac_flags |= AC_NOSGL; 1048 } else { 1049 mb->mb_nsgelem = nsegs; 1050 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1051 1052 sge = (struct amr_sgentry *)((caddr_t)amr->amr_sgls + sgloff); 1053 for (i = 0; i < nsegs; i++, sge++) { 1054 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1055 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1056 } 1057 } 1058 1059 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, 1060 out ? BUS_DMASYNC_PREWRITE : BUS_DMASYNC_PREREAD); 1061 1062 if ((ac->ac_flags & AC_NOSGL) == 0) 1063 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1064 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1065 1066 return (0); 1067 } 1068 1069 /* 1070 * Unmap the specified CCB's data buffer. 1071 */ 1072 void 1073 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1074 { 1075 1076 if ((ac->ac_flags & AC_NOSGL) == 0) 1077 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1078 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1079 BUS_DMASYNC_POSTWRITE); 1080 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1081 (ac->ac_flags & AC_XFER_IN) != 0 ? 1082 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1083 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1084 } 1085 1086 /* 1087 * Submit a command to the controller and poll on completion. Return 1088 * non-zero on timeout or error. Must be called with interrupts blocked. 1089 */ 1090 int 1091 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1092 { 1093 int rv; 1094 1095 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) 1096 return (rv); 1097 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1098 1099 for (timo *= 10; timo != 0; timo--) { 1100 amr_intr(amr); 1101 if ((ac->ac_flags & AC_COMPLETE) != 0) 1102 break; 1103 DELAY(100); 1104 } 1105 1106 return (timo == 0 || ac->ac_status != 0 ? EIO : 0); 1107 } 1108 1109 /* 1110 * Submit a command to the controller and sleep on completion. Return 1111 * non-zero on error. 1112 */ 1113 int 1114 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1115 { 1116 int s; 1117 1118 s = splbio(); 1119 amr_ccb_enqueue(amr, ac); 1120 tsleep(ac, PRIBIO, "amrcmd", 0); 1121 splx(s); 1122 1123 return (ac->ac_status != 0 ? EIO : 0); 1124 } 1125 1126 /* 1127 * Wait for the mailbox to become available. 1128 */ 1129 int 1130 amr_mbox_wait(struct amr_softc *amr) 1131 { 1132 int timo; 1133 1134 for (timo = 10000; timo != 0; timo--) { 1135 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1136 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1137 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1138 break; 1139 DELAY(100); 1140 } 1141 1142 if (timo == 0) 1143 printf("%s: controller wedged\n", amr->amr_dv.dv_xname); 1144 1145 return (timo != 0 ? 0 : EAGAIN); 1146 } 1147 1148 /* 1149 * Tell the controller that the mailbox contains a valid command. Must be 1150 * called with interrupts blocked. 1151 */ 1152 int 1153 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1154 { 1155 u_int32_t v; 1156 1157 amr->amr_mbox->mb_poll = 0; 1158 amr->amr_mbox->mb_ack = 0; 1159 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1160 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1161 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1162 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1163 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1164 return (EAGAIN); 1165 1166 v = amr_inl(amr, AMR_QREG_IDB); 1167 if ((v & AMR_QIDB_SUBMIT) != 0) { 1168 amr->amr_mbox->mb_cmd.mb_busy = 0; 1169 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1170 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1171 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1172 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1173 return (EAGAIN); 1174 } 1175 1176 amr->amr_mbox->mb_segment = 0; 1177 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1178 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1179 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1180 1181 ac->ac_start_time = (time_t)mono_time.tv_sec; 1182 ac->ac_flags |= AC_ACTIVE; 1183 amr_outl(amr, AMR_QREG_IDB, 1184 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1185 return (0); 1186 } 1187 1188 int 1189 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1190 { 1191 1192 amr->amr_mbox->mb_poll = 0; 1193 amr->amr_mbox->mb_ack = 0; 1194 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1195 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1196 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1197 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1198 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1199 return (EAGAIN); 1200 1201 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1202 amr->amr_mbox->mb_cmd.mb_busy = 0; 1203 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1204 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1205 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1206 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1207 return (EAGAIN); 1208 } 1209 1210 amr->amr_mbox->mb_segment = 0; 1211 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1212 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1213 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1214 1215 ac->ac_start_time = (time_t)mono_time.tv_sec; 1216 ac->ac_flags |= AC_ACTIVE; 1217 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1218 return (0); 1219 } 1220 1221 /* 1222 * Claim any work that the controller has completed; acknowledge completion, 1223 * save details of the completion in (mbsave). Must be called with 1224 * interrupts blocked. 1225 */ 1226 int 1227 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1228 { 1229 1230 /* Work waiting for us? */ 1231 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1232 return (-1); 1233 1234 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1235 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1236 1237 /* Save the mailbox, which contains a list of completed commands. */ 1238 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1239 1240 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1241 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1242 1243 /* Ack the interrupt and mailbox transfer. */ 1244 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1245 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1246 1247 /* 1248 * This waits for the controller to notice that we've taken the 1249 * command from it. It's very inefficient, and we shouldn't do it, 1250 * but if we remove this code, we stop completing commands under 1251 * load. 1252 * 1253 * Peter J says we shouldn't do this. The documentation says we 1254 * should. Who is right? 1255 */ 1256 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1257 DELAY(10); 1258 1259 return (0); 1260 } 1261 1262 int 1263 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1264 { 1265 u_int8_t istat; 1266 1267 /* Check for valid interrupt status. */ 1268 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1269 return (-1); 1270 1271 /* Ack the interrupt. */ 1272 amr_outb(amr, AMR_SREG_INTR, istat); 1273 1274 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1275 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1276 1277 /* Save mailbox, which contains a list of completed commands. */ 1278 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1279 1280 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1281 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1282 1283 /* Ack mailbox transfer. */ 1284 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1285 1286 return (0); 1287 } 1288 1289 void 1290 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1291 { 1292 int i; 1293 1294 printf("%s: ", amr->amr_dv.dv_xname); 1295 for (i = 0; i < 4; i++) 1296 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1297 printf("\n"); 1298 } 1299