1 /* $NetBSD: amr.c,v 1.66 2021/04/24 23:36:57 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999,2000 Michael Smith 34 * Copyright (c) 2000 BSDi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp 59 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp 60 */ 61 62 /* 63 * Driver for AMI RAID controllers. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.66 2021/04/24 23:36:57 thorpej Exp $"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/device.h> 73 #include <sys/queue.h> 74 #include <sys/proc.h> 75 #include <sys/buf.h> 76 #include <sys/malloc.h> 77 #include <sys/conf.h> 78 #include <sys/kthread.h> 79 #include <sys/kauth.h> 80 #include <sys/mutex.h> 81 #include <sys/condvar.h> 82 #include <sys/module.h> 83 84 #include <machine/endian.h> 85 #include <sys/bus.h> 86 87 #include <dev/pci/pcidevs.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/amrreg.h> 90 #include <dev/pci/amrvar.h> 91 #include <dev/pci/amrio.h> 92 93 #include "locators.h" 94 95 #include "ioconf.h" 96 97 static void amr_attach(device_t, device_t, void *); 98 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *); 99 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t, 100 void *); 101 static int amr_init(struct amr_softc *, const char *, 102 struct pci_attach_args *pa); 103 static int amr_intr(void *); 104 static int amr_match(device_t, cfdata_t, void *); 105 static int amr_rescan(device_t, const char *, const int *); 106 static int amr_print(void *, const char *); 107 static void amr_shutdown(void *); 108 static void amr_teardown(struct amr_softc *); 109 static void amr_quartz_thread(void *); 110 static void amr_std_thread(void *); 111 112 static int amr_quartz_get_work(struct amr_softc *, 113 struct amr_mailbox_resp *); 114 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *); 115 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *); 116 static int amr_std_submit(struct amr_softc *, struct amr_ccb *); 117 118 static dev_type_open(amropen); 119 static dev_type_close(amrclose); 120 static dev_type_ioctl(amrioctl); 121 122 CFATTACH_DECL3_NEW(amr, sizeof(struct amr_softc), 123 amr_match, amr_attach, NULL, NULL, amr_rescan, NULL, 0); 124 125 const struct cdevsw amr_cdevsw = { 126 .d_open = amropen, 127 .d_close = amrclose, 128 .d_read = noread, 129 .d_write = nowrite, 130 .d_ioctl = amrioctl, 131 .d_stop = nostop, 132 .d_tty = notty, 133 .d_poll = nopoll, 134 .d_mmap = nommap, 135 .d_kqfilter = nokqfilter, 136 .d_discard = nodiscard, 137 .d_flag = D_OTHER 138 }; 139 140 extern struct cfdriver amr_cd; 141 142 #define AT_QUARTZ 0x01 /* `Quartz' chipset */ 143 #define AT_SIG 0x02 /* Check for signature */ 144 145 static struct amr_pci_type { 146 u_short apt_vendor; 147 u_short apt_product; 148 u_short apt_flags; 149 } const amr_pci_type[] = { 150 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 }, 151 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 }, 152 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 153 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 157 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 158 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ }, 159 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ }, 160 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ }, 161 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ }, 162 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ }, 163 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ }, 164 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ }, 165 }; 166 167 static struct amr_typestr { 168 const char *at_str; 169 int at_sig; 170 } const amr_typestr[] = { 171 { "Series 431", AMR_SIG_431 }, 172 { "Series 438", AMR_SIG_438 }, 173 { "Series 466", AMR_SIG_466 }, 174 { "Series 467", AMR_SIG_467 }, 175 { "Series 490", AMR_SIG_490 }, 176 { "Series 762", AMR_SIG_762 }, 177 { "HP NetRAID (T5)", AMR_SIG_T5 }, 178 { "HP NetRAID (T7)", AMR_SIG_T7 }, 179 }; 180 181 static struct { 182 const char *ds_descr; 183 int ds_happy; 184 } const amr_dstate[] = { 185 { "offline", 0 }, 186 { "degraded", 1 }, 187 { "optimal", 1 }, 188 { "online", 1 }, 189 { "failed", 0 }, 190 { "rebuilding", 1 }, 191 { "hotspare", 0 }, 192 }; 193 194 static void *amr_sdh; 195 196 static kcondvar_t thread_cv; 197 static kmutex_t thread_mutex; 198 199 static int amr_max_segs; 200 int amr_max_xfer; 201 202 static inline u_int8_t 203 amr_inb(struct amr_softc *amr, int off) 204 { 205 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 206 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 207 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off)); 208 } 209 210 static inline u_int32_t 211 amr_inl(struct amr_softc *amr, int off) 212 { 213 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 214 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); 215 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off)); 216 } 217 218 static inline void 219 amr_outb(struct amr_softc *amr, int off, u_int8_t val) 220 { 221 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val); 222 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1, 223 BUS_SPACE_BARRIER_WRITE); 224 } 225 226 static inline void 227 amr_outl(struct amr_softc *amr, int off, u_int32_t val) 228 { 229 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val); 230 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4, 231 BUS_SPACE_BARRIER_WRITE); 232 } 233 234 /* 235 * Match a supported device. 236 */ 237 static int 238 amr_match(device_t parent, cfdata_t match, void *aux) 239 { 240 struct pci_attach_args *pa; 241 pcireg_t s; 242 int i; 243 244 pa = (struct pci_attach_args *)aux; 245 246 /* 247 * Don't match the device if it's operating in I2O mode. In this 248 * case it should be handled by the `iop' driver. 249 */ 250 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O) 251 return (0); 252 253 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 254 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 255 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 256 break; 257 258 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0])) 259 return (0); 260 261 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0) 262 return (1); 263 264 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff; 265 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1); 266 } 267 268 /* 269 * Attach a supported device. 270 */ 271 static void 272 amr_attach(device_t parent, device_t self, void *aux) 273 { 274 struct pci_attach_args *pa; 275 const struct amr_pci_type *apt; 276 struct amr_softc *amr; 277 pci_chipset_tag_t pc; 278 pci_intr_handle_t ih; 279 const char *intrstr; 280 pcireg_t reg; 281 int rseg, i, size, rv, memreg, ioreg; 282 struct amr_ccb *ac; 283 char intrbuf[PCI_INTRSTR_LEN]; 284 285 aprint_naive(": RAID controller\n"); 286 287 amr = device_private(self); 288 amr->amr_dv = self; 289 290 mutex_init(&amr->amr_mutex, MUTEX_DEFAULT, IPL_BIO); 291 292 pa = (struct pci_attach_args *)aux; 293 pc = pa->pa_pc; 294 295 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++) 296 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor && 297 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product) 298 break; 299 apt = amr_pci_type + i; 300 301 memreg = ioreg = 0; 302 for (i = 0x10; i <= 0x14; i += 4) { 303 reg = pci_conf_read(pc, pa->pa_tag, i); 304 switch (PCI_MAPREG_TYPE(reg)) { 305 case PCI_MAPREG_TYPE_MEM: 306 if (PCI_MAPREG_MEM_SIZE(reg) != 0) 307 memreg = i; 308 break; 309 case PCI_MAPREG_TYPE_IO: 310 if (PCI_MAPREG_IO_SIZE(reg) != 0) 311 ioreg = i; 312 break; 313 } 314 } 315 316 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0, 317 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 318 ; 319 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0, 320 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0) 321 ; 322 else { 323 aprint_error("can't map control registers\n"); 324 amr_teardown(amr); 325 return; 326 } 327 328 amr->amr_flags |= AMRF_PCI_REGS; 329 amr->amr_dmat = pa->pa_dmat; 330 amr->amr_pc = pa->pa_pc; 331 332 /* Enable the device. */ 333 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 334 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 335 reg | PCI_COMMAND_MASTER_ENABLE); 336 337 /* Map and establish the interrupt. */ 338 if (pci_intr_map(pa, &ih)) { 339 aprint_error("can't map interrupt\n"); 340 amr_teardown(amr); 341 return; 342 } 343 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 344 amr->amr_ih = pci_intr_establish_xname(pc, ih, IPL_BIO, amr_intr, amr, 345 device_xname(self)); 346 if (amr->amr_ih == NULL) { 347 aprint_error("can't establish interrupt"); 348 if (intrstr != NULL) 349 aprint_error(" at %s", intrstr); 350 aprint_error("\n"); 351 amr_teardown(amr); 352 return; 353 } 354 amr->amr_flags |= AMRF_PCI_INTR; 355 356 /* 357 * Allocate space for the mailbox and S/G lists. Some controllers 358 * don't like S/G lists to be located below 0x2000, so we allocate 359 * enough slop to enable us to compensate. 360 * 361 * The standard mailbox structure needs to be aligned on a 16-byte 362 * boundary. The 64-bit mailbox has one extra field, 4 bytes in 363 * size, which precedes the standard mailbox. 364 */ 365 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000; 366 amr->amr_dmasize = size; 367 368 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0, 369 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 370 aprint_error_dev(amr->amr_dv, 371 "unable to allocate buffer, rv = %d\n", rv); 372 amr_teardown(amr); 373 return; 374 } 375 amr->amr_flags |= AMRF_DMA_ALLOC; 376 377 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size, 378 (void **)&amr->amr_mbox, 379 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 380 aprint_error_dev(amr->amr_dv, "unable to map buffer, rv = %d\n", 381 rv); 382 amr_teardown(amr); 383 return; 384 } 385 amr->amr_flags |= AMRF_DMA_MAP; 386 387 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0, 388 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) { 389 aprint_error_dev(amr->amr_dv, 390 "unable to create buffer DMA map, rv = %d\n", rv); 391 amr_teardown(amr); 392 return; 393 } 394 amr->amr_flags |= AMRF_DMA_CREATE; 395 396 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap, 397 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) { 398 aprint_error_dev(amr->amr_dv, 399 "unable to load buffer DMA map, rv = %d\n", rv); 400 amr_teardown(amr); 401 return; 402 } 403 amr->amr_flags |= AMRF_DMA_LOAD; 404 405 memset(amr->amr_mbox, 0, size); 406 407 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr; 408 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff; 409 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox + 410 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr); 411 412 /* 413 * Allocate and initalise the command control blocks. 414 */ 415 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_WAITOK | M_ZERO); 416 amr->amr_ccbs = ac; 417 SLIST_INIT(&amr->amr_ccb_freelist); 418 TAILQ_INIT(&amr->amr_ccb_active); 419 amr->amr_flags |= AMRF_CCBS; 420 421 if (amr_max_xfer == 0) { 422 amr_max_xfer = uimin(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS); 423 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE; 424 } 425 426 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) { 427 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer, 428 amr_max_segs, amr_max_xfer, 0, 429 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map); 430 if (rv != 0) 431 break; 432 433 ac->ac_ident = i; 434 cv_init(&ac->ac_cv, "amr1ccb"); 435 mutex_init(&ac->ac_mutex, MUTEX_DEFAULT, IPL_NONE); 436 amr_ccb_free(amr, ac); 437 } 438 if (i != AMR_MAX_CMDS) { 439 aprint_error_dev(amr->amr_dv, "memory exhausted\n"); 440 amr_teardown(amr); 441 return; 442 } 443 444 /* 445 * Take care of model-specific tasks. 446 */ 447 if ((apt->apt_flags & AT_QUARTZ) != 0) { 448 amr->amr_submit = amr_quartz_submit; 449 amr->amr_get_work = amr_quartz_get_work; 450 } else { 451 amr->amr_submit = amr_std_submit; 452 amr->amr_get_work = amr_std_get_work; 453 454 /* Notify the controller of the mailbox location. */ 455 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16); 456 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR); 457 458 /* Clear outstanding interrupts and enable interrupts. */ 459 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 460 amr_outb(amr, AMR_SREG_TOGL, 461 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE); 462 } 463 464 /* 465 * Retrieve parameters, and tell the world about us. 466 */ 467 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_WAITOK); 468 amr->amr_flags |= AMRF_ENQBUF; 469 amr->amr_maxqueuecnt = i; 470 aprint_normal(": AMI RAID "); 471 if (amr_init(amr, intrstr, pa) != 0) { 472 amr_teardown(amr); 473 return; 474 } 475 476 /* 477 * Cap the maximum number of outstanding commands. AMI's Linux 478 * driver doesn't trust the controller's reported value, and lockups 479 * have been seen when we do. 480 */ 481 amr->amr_maxqueuecnt = uimin(amr->amr_maxqueuecnt, AMR_MAX_CMDS); 482 if (amr->amr_maxqueuecnt > i) 483 amr->amr_maxqueuecnt = i; 484 485 /* Set our `shutdownhook' before we start any device activity. */ 486 if (amr_sdh == NULL) 487 amr_sdh = shutdownhook_establish(amr_shutdown, NULL); 488 489 /* Attach sub-devices. */ 490 amr_rescan(self, NULL, NULL); 491 492 SIMPLEQ_INIT(&amr->amr_ccb_queue); 493 494 cv_init(&thread_cv, "amrwdog"); 495 mutex_init(&thread_mutex, MUTEX_DEFAULT, IPL_NONE); 496 497 if ((apt->apt_flags & AT_QUARTZ) == 0) { 498 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, 499 amr_std_thread, amr, &amr->amr_thread, 500 "%s", device_xname(amr->amr_dv)); 501 } else { 502 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, 503 amr_quartz_thread, amr, &amr->amr_thread, 504 "%s", device_xname(amr->amr_dv)); 505 } 506 if (rv != 0) 507 aprint_error_dev(amr->amr_dv, "unable to create thread (%d)", 508 rv); 509 else 510 amr->amr_flags |= AMRF_THREAD; 511 } 512 513 static int 514 amr_rescan(device_t self, const char *ifattr, const int *ulocs) 515 { 516 int j; 517 int locs[AMRCF_NLOCS]; 518 struct amr_attach_args amra; 519 struct amr_softc *amr; 520 521 amr = device_private(self); 522 for (j = 0; j < amr->amr_numdrives; j++) { 523 if (amr->amr_drive[j].al_dv) 524 continue; 525 if (amr->amr_drive[j].al_size == 0) 526 continue; 527 amra.amra_unit = j; 528 529 locs[AMRCF_UNIT] = j; 530 531 amr->amr_drive[j].al_dv = 532 config_found(amr->amr_dv, &amra, amr_print, 533 CFARG_SUBMATCH, config_stdsubmatch, 534 CFARG_IATTR, ifattr, 535 CFARG_LOCATORS, locs, 536 CFARG_EOL); 537 } 538 return 0; 539 } 540 541 /* 542 * Free up resources. 543 */ 544 static void 545 amr_teardown(struct amr_softc *amr) 546 { 547 struct amr_ccb *ac; 548 int fl; 549 550 fl = amr->amr_flags; 551 552 if ((fl & AMRF_THREAD) != 0) { 553 amr->amr_flags |= AMRF_THREAD_EXIT; 554 mutex_enter(&thread_mutex); 555 cv_broadcast(&thread_cv); 556 mutex_exit(&thread_mutex); 557 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 558 mutex_enter(&thread_mutex); 559 cv_wait(&thread_cv, &thread_mutex); 560 mutex_exit(&thread_mutex); 561 } 562 } 563 if ((fl & AMRF_CCBS) != 0) { 564 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) { 565 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map); 566 } 567 free(amr->amr_ccbs, M_DEVBUF); 568 } 569 if ((fl & AMRF_ENQBUF) != 0) 570 free(amr->amr_enqbuf, M_DEVBUF); 571 if ((fl & AMRF_DMA_LOAD) != 0) 572 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap); 573 if ((fl & AMRF_DMA_MAP) != 0) 574 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox, 575 amr->amr_dmasize); 576 if ((fl & AMRF_DMA_ALLOC) != 0) 577 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1); 578 if ((fl & AMRF_DMA_CREATE) != 0) 579 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap); 580 if ((fl & AMRF_PCI_INTR) != 0) 581 pci_intr_disestablish(amr->amr_pc, amr->amr_ih); 582 if ((fl & AMRF_PCI_REGS) != 0) 583 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios); 584 } 585 586 /* 587 * Print autoconfiguration message for a sub-device. 588 */ 589 static int 590 amr_print(void *aux, const char *pnp) 591 { 592 struct amr_attach_args *amra; 593 594 amra = (struct amr_attach_args *)aux; 595 596 if (pnp != NULL) 597 aprint_normal("block device at %s", pnp); 598 aprint_normal(" unit %d", amra->amra_unit); 599 return (UNCONF); 600 } 601 602 /* 603 * Retrieve operational parameters and describe the controller. 604 */ 605 static int 606 amr_init(struct amr_softc *amr, const char *intrstr, 607 struct pci_attach_args *pa) 608 { 609 struct amr_adapter_info *aa; 610 struct amr_prodinfo *ap; 611 struct amr_enquiry *ae; 612 struct amr_enquiry3 *aex; 613 const char *prodstr; 614 u_int i, sig, ishp; 615 char sbuf[64]; 616 617 /* 618 * Try to get 40LD product info, which tells us what the card is 619 * labelled as. 620 */ 621 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0, 622 amr->amr_enqbuf); 623 if (ap != NULL) { 624 aprint_normal("<%.80s>\n", ap->ap_product); 625 if (intrstr != NULL) 626 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n", 627 intrstr); 628 aprint_normal_dev(amr->amr_dv, 629 "firmware %.16s, BIOS %.16s, %dMB RAM\n", 630 ap->ap_firmware, ap->ap_bios, le16toh(ap->ap_memsize)); 631 632 amr->amr_maxqueuecnt = ap->ap_maxio; 633 634 /* 635 * Fetch and record state of logical drives. 636 */ 637 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3, 638 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf); 639 if (aex == NULL) { 640 aprint_error_dev(amr->amr_dv, "ENQUIRY3 failed\n"); 641 return (-1); 642 } 643 644 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) { 645 aprint_error_dev(amr->amr_dv, "Inquiry returned more " 646 "drives (%d) than the array can handle (%zu)\n", 647 aex->ae_numldrives, 648 __arraycount(aex->ae_drivestate)); 649 aex->ae_numldrives = __arraycount(aex->ae_drivestate); 650 } 651 if (aex->ae_numldrives > AMR_MAX_UNITS) { 652 aprint_error_dev(amr->amr_dv, 653 "adjust AMR_MAX_UNITS to %d (currently %d)\n", 654 AMR_MAX_UNITS, amr->amr_numdrives); 655 amr->amr_numdrives = AMR_MAX_UNITS; 656 } else 657 amr->amr_numdrives = aex->ae_numldrives; 658 659 for (i = 0; i < amr->amr_numdrives; i++) { 660 amr->amr_drive[i].al_size = 661 le32toh(aex->ae_drivesize[i]); 662 amr->amr_drive[i].al_state = aex->ae_drivestate[i]; 663 amr->amr_drive[i].al_properties = aex->ae_driveprop[i]; 664 } 665 666 return (0); 667 } 668 669 /* 670 * Try 8LD extended ENQUIRY to get the controller signature. Once 671 * found, search for a product description. 672 */ 673 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf); 674 if (ae != NULL) { 675 i = 0; 676 sig = le32toh(ae->ae_signature); 677 678 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 679 if (amr_typestr[i].at_sig == sig) 680 break; 681 i++; 682 } 683 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) { 684 snprintf(sbuf, sizeof(sbuf), 685 "unknown ENQUIRY2 sig (0x%08x)", sig); 686 prodstr = sbuf; 687 } else 688 prodstr = amr_typestr[i].at_str; 689 } else { 690 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf); 691 if (ae == NULL) { 692 aprint_error_dev(amr->amr_dv, 693 "unsupported controller\n"); 694 return (-1); 695 } 696 697 switch (PCI_PRODUCT(pa->pa_id)) { 698 case PCI_PRODUCT_AMI_MEGARAID: 699 prodstr = "Series 428"; 700 break; 701 case PCI_PRODUCT_AMI_MEGARAID2: 702 prodstr = "Series 434"; 703 break; 704 default: 705 snprintf(sbuf, sizeof(sbuf), 706 "unknown PCI dev (0x%04x)", 707 PCI_PRODUCT(pa->pa_id)); 708 prodstr = sbuf; 709 break; 710 } 711 } 712 713 /* 714 * HP NetRaid controllers have a special encoding of the firmware 715 * and BIOS versions. The AMI version seems to have it as strings 716 * whereas the HP version does it with a leading uppercase character 717 * and two binary numbers. 718 */ 719 aa = &ae->ae_adapter; 720 721 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' && 722 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' && 723 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' && 724 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') { 725 if (le32toh(ae->ae_signature) == AMR_SIG_438) { 726 /* The AMI 438 is a NetRaid 3si in HP-land. */ 727 prodstr = "HP NetRaid 3si"; 728 } 729 ishp = 1; 730 } else 731 ishp = 0; 732 733 aprint_normal("<%s>\n", prodstr); 734 if (intrstr != NULL) 735 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n", 736 intrstr); 737 738 if (ishp) 739 aprint_normal_dev(amr->amr_dv, "firmware <%c.%02d.%02d>, " 740 "BIOS <%c.%02d.%02d>, %dMB RAM\n", aa->aa_firmware[2], 741 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2], 742 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize); 743 else 744 aprint_normal_dev(amr->amr_dv, "firmware <%.4s>, BIOS <%.4s>, " 745 "%dMB RAM\n", aa->aa_firmware, aa->aa_bios, 746 aa->aa_memorysize); 747 748 amr->amr_maxqueuecnt = aa->aa_maxio; 749 750 /* 751 * Record state of logical drives. 752 */ 753 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) { 754 aprint_error_dev(amr->amr_dv, "Inquiry returned more drives " 755 "(%d) than the array can handle (%zu)\n", 756 ae->ae_ldrv.al_numdrives, 757 __arraycount(ae->ae_ldrv.al_size)); 758 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size); 759 } 760 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) { 761 aprint_error_dev(amr->amr_dv, 762 "adjust AMR_MAX_UNITS to %d (currently %d)\n", 763 ae->ae_ldrv.al_numdrives, AMR_MAX_UNITS); 764 amr->amr_numdrives = AMR_MAX_UNITS; 765 } else 766 amr->amr_numdrives = ae->ae_ldrv.al_numdrives; 767 768 for (i = 0; i < amr->amr_numdrives; i++) { 769 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]); 770 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i]; 771 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i]; 772 } 773 774 return (0); 775 } 776 777 /* 778 * Flush the internal cache on each configured controller. Called at 779 * shutdown time. 780 */ 781 static void 782 amr_shutdown(void *cookie) 783 { 784 extern struct cfdriver amr_cd; 785 struct amr_softc *amr; 786 struct amr_ccb *ac; 787 int i, rv; 788 789 for (i = 0; i < amr_cd.cd_ndevs; i++) { 790 if ((amr = device_lookup_private(&amr_cd, i)) == NULL) 791 continue; 792 793 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) { 794 ac->ac_cmd.mb_command = AMR_CMD_FLUSH; 795 rv = amr_ccb_poll(amr, ac, 30000); 796 amr_ccb_free(amr, ac); 797 } 798 if (rv != 0) 799 aprint_error_dev(amr->amr_dv, 800 "unable to flush cache (%d)\n", rv); 801 } 802 } 803 804 /* 805 * Interrupt service routine. 806 */ 807 static int 808 amr_intr(void *cookie) 809 { 810 struct amr_softc *amr; 811 struct amr_ccb *ac; 812 struct amr_mailbox_resp mbox; 813 u_int i, forus, idx; 814 815 amr = cookie; 816 forus = 0; 817 818 mutex_spin_enter(&amr->amr_mutex); 819 820 while ((*amr->amr_get_work)(amr, &mbox) == 0) { 821 /* Iterate over completed commands in this result. */ 822 for (i = 0; i < mbox.mb_nstatus; i++) { 823 idx = mbox.mb_completed[i] - 1; 824 ac = amr->amr_ccbs + idx; 825 826 if (idx >= amr->amr_maxqueuecnt) { 827 printf("%s: bad status (bogus ID: %u=%u)\n", 828 device_xname(amr->amr_dv), i, idx); 829 continue; 830 } 831 832 if ((ac->ac_flags & AC_ACTIVE) == 0) { 833 printf("%s: bad status (not active; 0x04%x)\n", 834 device_xname(amr->amr_dv), ac->ac_flags); 835 continue; 836 } 837 838 ac->ac_status = mbox.mb_status; 839 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) | 840 AC_COMPLETE; 841 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq); 842 843 if ((ac->ac_flags & AC_MOAN) != 0) 844 printf("%s: ccb %d completed\n", 845 device_xname(amr->amr_dv), ac->ac_ident); 846 847 /* Pass notification to upper layers. */ 848 mutex_spin_exit(&amr->amr_mutex); 849 if (ac->ac_handler != NULL) { 850 (*ac->ac_handler)(ac); 851 } else { 852 mutex_enter(&ac->ac_mutex); 853 cv_signal(&ac->ac_cv); 854 mutex_exit(&ac->ac_mutex); 855 } 856 mutex_spin_enter(&amr->amr_mutex); 857 } 858 forus = 1; 859 } 860 861 mutex_spin_exit(&amr->amr_mutex); 862 863 if (forus) 864 amr_ccb_enqueue(amr, NULL); 865 866 return (forus); 867 } 868 869 /* 870 * Watchdog thread. 871 */ 872 static void 873 amr_quartz_thread(void *cookie) 874 { 875 struct amr_softc *amr; 876 struct amr_ccb *ac; 877 878 amr = cookie; 879 880 for (;;) { 881 mutex_enter(&thread_mutex); 882 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS); 883 mutex_exit(&thread_mutex); 884 885 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 886 amr->amr_flags ^= AMRF_THREAD_EXIT; 887 mutex_enter(&thread_mutex); 888 cv_signal(&thread_cv); 889 mutex_exit(&thread_mutex); 890 kthread_exit(0); 891 } 892 893 if (amr_intr(amr) == 0) 894 amr_ccb_enqueue(amr, NULL); 895 896 mutex_spin_enter(&amr->amr_mutex); 897 ac = TAILQ_FIRST(&amr->amr_ccb_active); 898 while (ac != NULL) { 899 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 900 break; 901 if ((ac->ac_flags & AC_MOAN) == 0) { 902 printf("%s: ccb %d timed out; mailbox:\n", 903 device_xname(amr->amr_dv), ac->ac_ident); 904 amr_ccb_dump(amr, ac); 905 ac->ac_flags |= AC_MOAN; 906 } 907 ac = TAILQ_NEXT(ac, ac_chain.tailq); 908 } 909 mutex_spin_exit(&amr->amr_mutex); 910 } 911 } 912 913 static void 914 amr_std_thread(void *cookie) 915 { 916 struct amr_softc *amr; 917 struct amr_ccb *ac; 918 struct amr_logdrive *al; 919 struct amr_enquiry *ae; 920 int rv, i; 921 922 amr = cookie; 923 ae = amr->amr_enqbuf; 924 925 for (;;) { 926 mutex_enter(&thread_mutex); 927 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS); 928 mutex_exit(&thread_mutex); 929 930 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) { 931 amr->amr_flags ^= AMRF_THREAD_EXIT; 932 mutex_enter(&thread_mutex); 933 cv_signal(&thread_cv); 934 mutex_exit(&thread_mutex); 935 kthread_exit(0); 936 } 937 938 if (amr_intr(amr) == 0) 939 amr_ccb_enqueue(amr, NULL); 940 941 mutex_spin_enter(&amr->amr_mutex); 942 ac = TAILQ_FIRST(&amr->amr_ccb_active); 943 while (ac != NULL) { 944 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime) 945 break; 946 if ((ac->ac_flags & AC_MOAN) == 0) { 947 printf("%s: ccb %d timed out; mailbox:\n", 948 device_xname(amr->amr_dv), ac->ac_ident); 949 amr_ccb_dump(amr, ac); 950 ac->ac_flags |= AC_MOAN; 951 } 952 ac = TAILQ_NEXT(ac, ac_chain.tailq); 953 } 954 mutex_spin_exit(&amr->amr_mutex); 955 956 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) { 957 printf("%s: ccb_alloc failed (%d)\n", 958 device_xname(amr->amr_dv), rv); 959 continue; 960 } 961 962 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY; 963 964 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf, 965 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 966 if (rv != 0) { 967 aprint_error_dev(amr->amr_dv, "ccb_map failed (%d)\n", 968 rv); 969 amr_ccb_free(amr, ac); 970 continue; 971 } 972 973 rv = amr_ccb_wait(amr, ac); 974 amr_ccb_unmap(amr, ac); 975 if (rv != 0) { 976 aprint_error_dev(amr->amr_dv, 977 "enquiry failed (st=%d)\n", ac->ac_status); 978 continue; 979 } 980 amr_ccb_free(amr, ac); 981 982 al = amr->amr_drive; 983 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) { 984 if (al->al_dv == NULL) 985 continue; 986 if (al->al_state == ae->ae_ldrv.al_state[i]) 987 continue; 988 989 printf("%s: state changed: %s -> %s\n", 990 device_xname(al->al_dv), 991 amr_drive_state(al->al_state, NULL), 992 amr_drive_state(ae->ae_ldrv.al_state[i], NULL)); 993 994 al->al_state = ae->ae_ldrv.al_state[i]; 995 } 996 } 997 } 998 999 /* 1000 * Return a text description of a logical drive's current state. 1001 */ 1002 const char * 1003 amr_drive_state(int state, int *happy) 1004 { 1005 const char *str; 1006 1007 state = AMR_DRV_CURSTATE(state); 1008 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) { 1009 if (happy) 1010 *happy = 1; 1011 str = "status unknown"; 1012 } else { 1013 if (happy) 1014 *happy = amr_dstate[state].ds_happy; 1015 str = amr_dstate[state].ds_descr; 1016 } 1017 1018 return (str); 1019 } 1020 1021 /* 1022 * Run a generic enquiry-style command. 1023 */ 1024 static void * 1025 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub, 1026 u_int8_t cmdqual, void *sbuf) 1027 { 1028 struct amr_ccb *ac; 1029 u_int8_t *mb; 1030 int rv; 1031 1032 if (amr_ccb_alloc(amr, &ac) != 0) 1033 return (NULL); 1034 1035 /* Build the command proper. */ 1036 mb = (u_int8_t *)&ac->ac_cmd; 1037 mb[0] = cmd; 1038 mb[2] = cmdsub; 1039 mb[3] = cmdqual; 1040 1041 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN); 1042 if (rv == 0) { 1043 rv = amr_ccb_poll(amr, ac, 2000); 1044 amr_ccb_unmap(amr, ac); 1045 } 1046 amr_ccb_free(amr, ac); 1047 1048 return (rv ? NULL : sbuf); 1049 } 1050 1051 /* 1052 * Allocate and initialise a CCB. 1053 */ 1054 int 1055 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp) 1056 { 1057 mutex_spin_enter(&amr->amr_mutex); 1058 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) { 1059 mutex_spin_exit(&amr->amr_mutex); 1060 return (EAGAIN); 1061 } 1062 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist); 1063 mutex_spin_exit(&amr->amr_mutex); 1064 1065 return (0); 1066 } 1067 1068 /* 1069 * Free a CCB. 1070 */ 1071 void 1072 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac) 1073 { 1074 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd)); 1075 ac->ac_cmd.mb_ident = ac->ac_ident + 1; 1076 ac->ac_cmd.mb_busy = 1; 1077 ac->ac_handler = NULL; 1078 ac->ac_flags = 0; 1079 1080 mutex_spin_enter(&amr->amr_mutex); 1081 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist); 1082 mutex_spin_exit(&amr->amr_mutex); 1083 } 1084 1085 /* 1086 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in 1087 * the order that they were enqueued and try to submit their command blocks 1088 * to the controller for execution. 1089 */ 1090 void 1091 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac) 1092 { 1093 if (ac != NULL) { 1094 mutex_spin_enter(&amr->amr_mutex); 1095 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq); 1096 mutex_spin_exit(&amr->amr_mutex); 1097 } 1098 1099 while (SIMPLEQ_FIRST(&amr->amr_ccb_queue) != NULL) { 1100 mutex_spin_enter(&amr->amr_mutex); 1101 if ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) { 1102 if ((*amr->amr_submit)(amr, ac) != 0) { 1103 mutex_spin_exit(&amr->amr_mutex); 1104 break; 1105 } 1106 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue, 1107 ac_chain.simpleq); 1108 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, 1109 ac_chain.tailq); 1110 } 1111 mutex_spin_exit(&amr->amr_mutex); 1112 } 1113 } 1114 1115 /* 1116 * Map the specified CCB's data buffer onto the bus, and fill the 1117 * scatter-gather list. 1118 */ 1119 int 1120 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size, 1121 int tflag) 1122 { 1123 struct amr_sgentry *sge; 1124 struct amr_mailbox_cmd *mb; 1125 int nsegs, i, rv, sgloff; 1126 bus_dmamap_t xfer; 1127 int dmaflag = 0; 1128 1129 xfer = ac->ac_xfer_map; 1130 1131 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL, 1132 BUS_DMA_NOWAIT); 1133 if (rv != 0) 1134 return (rv); 1135 1136 mb = &ac->ac_cmd; 1137 ac->ac_xfer_size = size; 1138 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN)); 1139 sgloff = AMR_SGL_SIZE * ac->ac_ident; 1140 1141 if (tflag & AC_XFER_OUT) 1142 dmaflag |= BUS_DMASYNC_PREWRITE; 1143 if (tflag & AC_XFER_IN) 1144 dmaflag |= BUS_DMASYNC_PREREAD; 1145 1146 /* We don't need to use a scatter/gather list for just 1 segment. */ 1147 nsegs = xfer->dm_nsegs; 1148 if (nsegs == 1) { 1149 mb->mb_nsgelem = 0; 1150 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr); 1151 ac->ac_flags |= AC_NOSGL; 1152 } else { 1153 mb->mb_nsgelem = nsegs; 1154 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff); 1155 1156 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff); 1157 for (i = 0; i < nsegs; i++, sge++) { 1158 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr); 1159 sge->sge_count = htole32(xfer->dm_segs[i].ds_len); 1160 } 1161 } 1162 1163 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag); 1164 1165 if ((ac->ac_flags & AC_NOSGL) == 0) 1166 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff, 1167 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE); 1168 1169 return (0); 1170 } 1171 1172 /* 1173 * Unmap the specified CCB's data buffer. 1174 */ 1175 void 1176 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac) 1177 { 1178 int dmaflag = 0; 1179 1180 if (ac->ac_flags & AC_XFER_IN) 1181 dmaflag |= BUS_DMASYNC_POSTREAD; 1182 if (ac->ac_flags & AC_XFER_OUT) 1183 dmaflag |= BUS_DMASYNC_POSTWRITE; 1184 1185 if ((ac->ac_flags & AC_NOSGL) == 0) 1186 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 1187 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE, 1188 BUS_DMASYNC_POSTWRITE); 1189 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size, 1190 dmaflag); 1191 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map); 1192 } 1193 1194 /* 1195 * Submit a command to the controller and poll on completion. Return 1196 * non-zero on timeout or error. 1197 */ 1198 int 1199 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo) 1200 { 1201 int rv, i; 1202 1203 mutex_spin_enter(&amr->amr_mutex); 1204 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) { 1205 mutex_spin_exit(&amr->amr_mutex); 1206 return (rv); 1207 } 1208 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq); 1209 mutex_spin_exit(&amr->amr_mutex); 1210 1211 for (i = timo * 10; i > 0; i--) { 1212 amr_intr(amr); 1213 if ((ac->ac_flags & AC_COMPLETE) != 0) 1214 break; 1215 DELAY(100); 1216 } 1217 1218 if (i == 0) 1219 printf("%s: polled operation timed out after %d ms\n", 1220 device_xname(amr->amr_dv), timo); 1221 1222 return ((i == 0 || ac->ac_status != 0) ? EIO : 0); 1223 } 1224 1225 /* 1226 * Submit a command to the controller and sleep on completion. Return 1227 * non-zero on error. 1228 */ 1229 int 1230 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac) 1231 { 1232 amr_ccb_enqueue(amr, ac); 1233 mutex_enter(&ac->ac_mutex); 1234 cv_wait(&ac->ac_cv, &ac->ac_mutex); 1235 mutex_exit(&ac->ac_mutex); 1236 1237 return (ac->ac_status != 0 ? EIO : 0); 1238 } 1239 1240 #if 0 1241 /* 1242 * Wait for the mailbox to become available. 1243 */ 1244 static int 1245 amr_mbox_wait(struct amr_softc *amr) 1246 { 1247 int timo; 1248 1249 for (timo = 10000; timo != 0; timo--) { 1250 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1251 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1252 if (amr->amr_mbox->mb_cmd.mb_busy == 0) 1253 break; 1254 DELAY(100); 1255 } 1256 1257 if (timo == 0) 1258 printf("%s: controller wedged\n", device_xname(amr->amr_dv)); 1259 1260 return (timo != 0 ? 0 : EAGAIN); 1261 } 1262 #endif 1263 1264 /* 1265 * Tell the controller that the mailbox contains a valid command. Must be 1266 * called with interrupts blocked. 1267 */ 1268 static int 1269 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac) 1270 { 1271 int i = 0; 1272 u_int32_t v; 1273 1274 amr->amr_mbox->mb_poll = 0; 1275 amr->amr_mbox->mb_ack = 0; 1276 1277 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1278 sizeof(struct amr_mailbox), 1279 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1280 1281 v = amr_inl(amr, AMR_QREG_ODB); 1282 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1283 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1284 while ((amr->amr_mbox->mb_cmd.mb_busy != 0) && (i++ < 10)) { 1285 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1286 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1287 /* This is a no-op read that flushes pending mailbox updates */ 1288 v = amr_inl(amr, AMR_QREG_ODB); 1289 DELAY(1); 1290 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1291 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1292 } 1293 1294 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1295 return (EAGAIN); 1296 1297 v = amr_inl(amr, AMR_QREG_IDB); 1298 if ((v & AMR_QIDB_SUBMIT) != 0) { 1299 amr->amr_mbox->mb_cmd.mb_busy = 0; 1300 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1301 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1302 printf("%s: submit failed\n", device_xname(amr->amr_dv)); 1303 return (EAGAIN); 1304 } 1305 1306 amr->amr_mbox->mb_segment = 0; 1307 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1308 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1309 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1310 1311 ac->ac_start_time = time_uptime; 1312 ac->ac_flags |= AC_ACTIVE; 1313 1314 amr_outl(amr, AMR_QREG_IDB, 1315 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT); 1316 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1317 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE); 1318 1319 return (0); 1320 } 1321 1322 static int 1323 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac) 1324 { 1325 1326 amr->amr_mbox->mb_poll = 0; 1327 amr->amr_mbox->mb_ack = 0; 1328 1329 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1330 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1331 1332 if (amr->amr_mbox->mb_cmd.mb_busy != 0) 1333 return (EAGAIN); 1334 1335 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) { 1336 amr->amr_mbox->mb_cmd.mb_busy = 0; 1337 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1338 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1339 return (EAGAIN); 1340 } 1341 1342 amr->amr_mbox->mb_segment = 0; 1343 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd)); 1344 1345 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1346 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE); 1347 1348 ac->ac_start_time = time_uptime; 1349 ac->ac_flags |= AC_ACTIVE; 1350 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST); 1351 1352 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1353 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE); 1354 1355 return (0); 1356 } 1357 1358 /* 1359 * Claim any work that the controller has completed; acknowledge completion, 1360 * save details of the completion in (mbsave). Must be called with 1361 * interrupts blocked. 1362 */ 1363 static int 1364 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1365 { 1366 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1367 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1368 1369 /* Work waiting for us? */ 1370 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY) 1371 return (-1); 1372 1373 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1374 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1375 1376 /* Save the mailbox, which contains a list of completed commands. */ 1377 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1378 1379 /* Ack the interrupt and mailbox transfer. */ 1380 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY); 1381 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK); 1382 1383 /* 1384 * This waits for the controller to notice that we've taken the 1385 * command from it. It's very inefficient, and we shouldn't do it, 1386 * but if we remove this code, we stop completing commands under 1387 * load. 1388 * 1389 * Peter J says we shouldn't do this. The documentation says we 1390 * should. Who is right? 1391 */ 1392 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0) 1393 DELAY(10); 1394 1395 return (0); 1396 } 1397 1398 static int 1399 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave) 1400 { 1401 u_int8_t istat; 1402 1403 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1404 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD); 1405 1406 /* Check for valid interrupt status. */ 1407 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0) 1408 return (-1); 1409 1410 /* Ack the interrupt. */ 1411 amr_outb(amr, AMR_SREG_INTR, istat); 1412 1413 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0, 1414 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD); 1415 1416 /* Save mailbox, which contains a list of completed commands. */ 1417 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave)); 1418 1419 /* Ack mailbox transfer. */ 1420 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR); 1421 1422 return (0); 1423 } 1424 1425 static void 1426 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac) 1427 { 1428 int i; 1429 1430 printf("%s: ", device_xname(amr->amr_dv)); 1431 for (i = 0; i < 4; i++) 1432 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]); 1433 printf("\n"); 1434 } 1435 1436 static int 1437 amropen(dev_t dev, int flag, int mode, struct lwp *l) 1438 { 1439 struct amr_softc *amr; 1440 1441 if ((amr = device_lookup_private(&amr_cd, minor(dev))) == NULL) 1442 return (ENXIO); 1443 if ((amr->amr_flags & AMRF_OPEN) != 0) 1444 return (EBUSY); 1445 1446 amr->amr_flags |= AMRF_OPEN; 1447 return (0); 1448 } 1449 1450 static int 1451 amrclose(dev_t dev, int flag, int mode, struct lwp *l) 1452 { 1453 struct amr_softc *amr; 1454 1455 amr = device_lookup_private(&amr_cd, minor(dev)); 1456 amr->amr_flags &= ~AMRF_OPEN; 1457 return (0); 1458 } 1459 1460 /* used below to correct for a firmware bug */ 1461 static unsigned long 1462 amrioctl_buflen(unsigned long len) 1463 { 1464 if (len <= 4 * 1024) 1465 return (4 * 1024); 1466 if (len <= 8 * 1024) 1467 return (8 * 1024); 1468 if (len <= 32 * 1024) 1469 return (32 * 1024); 1470 if (len <= 64 * 1024) 1471 return (64 * 1024); 1472 return (len); 1473 } 1474 1475 static int 1476 amrioctl(dev_t dev, u_long cmd, void *data, int flag, 1477 struct lwp *l) 1478 { 1479 struct amr_softc *amr; 1480 struct amr_user_ioctl *au; 1481 struct amr_ccb *ac; 1482 struct amr_mailbox_ioctl *mbi; 1483 unsigned long au_length; 1484 uint8_t *au_cmd; 1485 int error; 1486 void *dp = NULL, *au_buffer; 1487 1488 amr = device_lookup_private(&amr_cd, minor(dev)); 1489 1490 /* This should be compatible with the FreeBSD interface */ 1491 1492 switch (cmd) { 1493 case AMR_IO_VERSION: 1494 *(int *)data = AMR_IO_VERSION_NUMBER; 1495 return 0; 1496 case AMR_IO_COMMAND: 1497 error = kauth_authorize_device_passthru(l->l_cred, dev, 1498 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data); 1499 if (error) 1500 return (error); 1501 1502 au = (struct amr_user_ioctl *)data; 1503 au_cmd = au->au_cmd; 1504 au_buffer = au->au_buffer; 1505 au_length = au->au_length; 1506 break; 1507 default: 1508 return ENOTTY; 1509 } 1510 1511 if (au_cmd[0] == AMR_CMD_PASS) { 1512 /* not yet */ 1513 return EOPNOTSUPP; 1514 } 1515 1516 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06) 1517 return (EINVAL); 1518 1519 /* 1520 * allocate kernel memory for data, doing I/O directly to user 1521 * buffer isn't that easy. Correct allocation size for a bug 1522 * in at least some versions of the device firmware, by using 1523 * the amrioctl_buflen() function, defined above. 1524 */ 1525 dp = malloc(amrioctl_buflen(au_length), M_DEVBUF, M_WAITOK|M_ZERO); 1526 if (dp == NULL) 1527 return ENOMEM; 1528 if ((error = copyin(au_buffer, dp, au_length)) != 0) 1529 goto out; 1530 1531 /* direct command to controller */ 1532 while (amr_ccb_alloc(amr, &ac) != 0) { 1533 mutex_enter(&thread_mutex); 1534 error = cv_timedwait_sig(&thread_cv, &thread_mutex, hz); 1535 mutex_exit(&thread_mutex); 1536 if (error == EINTR) 1537 goto out; 1538 } 1539 1540 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd; 1541 mbi->mb_command = au_cmd[0]; 1542 mbi->mb_channel = au_cmd[1]; 1543 mbi->mb_param = au_cmd[2]; 1544 mbi->mb_pad[0] = au_cmd[3]; 1545 mbi->mb_drive = au_cmd[4]; 1546 error = amr_ccb_map(amr, ac, dp, (int)au_length, 1547 AC_XFER_IN | AC_XFER_OUT); 1548 if (error == 0) { 1549 error = amr_ccb_wait(amr, ac); 1550 amr_ccb_unmap(amr, ac); 1551 if (error == 0) 1552 error = copyout(dp, au_buffer, au_length); 1553 1554 } 1555 amr_ccb_free(amr, ac); 1556 out: 1557 free(dp, M_DEVBUF); 1558 return (error); 1559 } 1560 1561 MODULE(MODULE_CLASS_DRIVER, amr, "pci"); 1562 1563 #ifdef _MODULE 1564 #include "ioconf.c" 1565 #endif 1566 1567 static int 1568 amr_modcmd(modcmd_t cmd, void *opaque) 1569 { 1570 int error = 0; 1571 1572 #ifdef _MODULE 1573 switch (cmd) { 1574 case MODULE_CMD_INIT: 1575 error = config_init_component(cfdriver_ioconf_amr, 1576 cfattach_ioconf_amr, cfdata_ioconf_amr); 1577 break; 1578 case MODULE_CMD_FINI: 1579 error = config_fini_component(cfdriver_ioconf_amr, 1580 cfattach_ioconf_amr, cfdata_ioconf_amr); 1581 break; 1582 default: 1583 error = ENOTTY; 1584 break; 1585 } 1586 #endif 1587 1588 return error; 1589 } 1590