1 /* $NetBSD: ahd_pci.c,v 1.2 2003/05/14 12:57:46 wiz Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * //depot/aic7xxx/aic7xxx/aic79xx_pci.c#67 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.9 2003/03/06 23:58:34 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 49 */ 50 51 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 52 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 53 54 #include <dev/ic/aic79xx_osm.h> 55 #include <dev/ic/aic79xx_inline.h> 56 57 static __inline uint64_t 58 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 59 { 60 uint64_t id; 61 62 id = subvendor 63 | (subdevice << 16) 64 | ((uint64_t)vendor << 32) 65 | ((uint64_t)device << 48); 66 67 return (id); 68 } 69 70 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 71 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 72 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 73 74 #define ID_AIC7901 0x800F9005FFFF9005ull 75 #define ID_AIC7901A 0x801E9005FFFF9005ull 76 #define ID_AIC7901A_IROC 0x809E9005FFFF9005ull 77 #define ID_AHA_29320A 0x8000900500609005ull 78 #define ID_AHA_29320LP 0x8014900500449005ull 79 #define ID_AHA_29320LP_IROC 0x8094900500449005ull 80 81 #define ID_AIC7902 0x801F9005FFFF9005ull 82 #define ID_AIC7902_IROC 0x809F9005FFFF9005ull 83 #define ID_AIC7902_B 0x801D9005FFFF9005ull 84 #define ID_AIC7902_B_IROC 0x809D9005FFFF9005ull 85 #define ID_AHA_39320 0x8010900500409005ull 86 #define ID_AHA_39320A 0x8016900500409005ull 87 #define ID_AHA_39320D 0x8011900500419005ull 88 #define ID_AHA_39320D_B 0x801C900500419005ull 89 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 90 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 91 #define ID_AHA_29320 0x8012900500429005ull 92 #define ID_AHA_29320B 0x8013900500439005ull 93 #define ID_AIC7902_PCI_REV_A4 0x3 94 #define ID_AIC7902_PCI_REV_B0 0x10 95 #define SUBID_HP 0x0E11 96 97 #define DEVID_9005_TYPE(id) ((id) & 0xF) 98 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 99 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 100 #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */ 101 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 102 103 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 104 105 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 106 107 #define SUBID_9005_TYPE(id) ((id) & 0xF) 108 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 109 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 110 111 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 112 113 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 114 115 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 116 #define SUBID_9005_SEEPTYPE_NONE 0x0 117 #define SUBID_9005_SEEPTYPE_4K 0x1 118 119 static ahd_device_setup_t ahd_aic7901A_setup; 120 static ahd_device_setup_t ahd_aic7902_setup; 121 122 struct ahd_pci_identity ahd_pci_ident_table [] = 123 { 124 /* aic7901A based controllers */ 125 { 126 ID_AHA_29320LP, 127 ID_ALL_MASK, 128 "Adaptec 29320LP Ultra320 SCSI adapter", 129 ahd_aic7901A_setup 130 }, 131 { 132 ID_AHA_29320A, 133 ID_ALL_MASK, 134 "Adaptec 29320A Ultra320 SCSI adapter", 135 ahd_aic7901A_setup 136 }, 137 /* aic7902 based controllers */ 138 { 139 ID_AHA_39320, 140 ID_ALL_MASK, 141 "Adaptec 39320 Ultra320 SCSI adapter", 142 ahd_aic7902_setup 143 }, 144 { 145 ID_AHA_39320A, 146 ID_ALL_MASK, 147 "Adaptec 39320A Ultra320 SCSI adapter", 148 ahd_aic7902_setup 149 }, 150 { 151 ID_AHA_39320D, 152 ID_ALL_MASK, 153 "Adaptec 39320D Ultra320 SCSI adapter", 154 ahd_aic7902_setup 155 }, 156 { 157 ID_AHA_39320D_HP, 158 ID_ALL_MASK, 159 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 160 ahd_aic7902_setup 161 }, 162 { 163 ID_AHA_39320D_B, 164 ID_ALL_MASK, 165 "Adaptec 39320D Ultra320 SCSI adapter", 166 ahd_aic7902_setup 167 }, 168 { 169 ID_AHA_39320D_B_HP, 170 ID_ALL_MASK, 171 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 172 ahd_aic7902_setup 173 }, 174 { 175 ID_AHA_29320, 176 ID_ALL_MASK, 177 "Adaptec 29320 Ultra320 SCSI adapter", 178 ahd_aic7902_setup 179 }, 180 { 181 ID_AHA_29320B, 182 ID_ALL_MASK, 183 "Adaptec 29320B Ultra320 SCSI adapter", 184 ahd_aic7902_setup 185 }, 186 /* Generic chip probes for devices we don't know 'exactly' */ 187 { 188 ID_AIC7901A & ID_DEV_VENDOR_MASK, 189 ID_DEV_VENDOR_MASK, 190 "Adaptec AIC7901A Ultra320 SCSI adapter", 191 ahd_aic7901A_setup 192 }, 193 { 194 ID_AIC7902 & ID_9005_GENERIC_MASK, 195 ID_9005_GENERIC_MASK, 196 "Adaptec AIC7902 Ultra320 SCSI adapter", 197 ahd_aic7902_setup 198 } 199 }; 200 201 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 202 203 #define DEVCONFIG 0x40 204 #define PCIXINITPAT 0x0000E000ul 205 #define PCIXINIT_PCI33_66 0x0000E000ul 206 #define PCIXINIT_PCIX50_66 0x0000C000ul 207 #define PCIXINIT_PCIX66_100 0x0000A000ul 208 #define PCIXINIT_PCIX100_133 0x00008000ul 209 #define PCI_BUS_MODES_INDEX(devconfig) \ 210 (((devconfig) & PCIXINITPAT) >> 13) 211 212 static const char *pci_bus_modes[] = 213 { 214 "PCI bus mode unknown", 215 "PCI bus mode unknown", 216 "PCI bus mode unknown", 217 "PCI bus mode unknown", 218 "PCI-X 101-133Mhz", 219 "PCI-X 67-100Mhz", 220 "PCI-X 50-66Mhz", 221 "PCI 33 or 66Mhz" 222 }; 223 224 #define TESTMODE 0x00000800ul 225 #define IRDY_RST 0x00000200ul 226 #define FRAME_RST 0x00000100ul 227 #define PCI64BIT 0x00000080ul 228 #define MRDCEN 0x00000040ul 229 #define ENDIANSEL 0x00000020ul 230 #define MIXQWENDIANEN 0x00000008ul 231 #define DACEN 0x00000004ul 232 #define STPWLEVEL 0x00000002ul 233 #define QWENDIANSEL 0x00000001ul 234 235 #define DEVCONFIG1 0x44 236 #define PREQDIS 0x01 237 238 #define LATTIME 0x0000ff00ul 239 240 int ahd_pci_probe __P((struct device *, struct cfdata *, void *)); 241 void ahd_pci_attach __P((struct device *, struct device *, void *)); 242 243 CFATTACH_DECL(ahd_pci, sizeof(struct ahd_softc), 244 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 245 246 static int ahd_check_extport(struct ahd_softc *ahd); 247 static void ahd_configure_termination(struct ahd_softc *ahd, 248 u_int adapter_control); 249 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 250 251 const struct ahd_pci_identity * 252 ahd_find_pci_device(id, subid) 253 pcireg_t id, subid; 254 { 255 u_int64_t full_id; 256 const struct ahd_pci_identity *entry; 257 u_int i; 258 259 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 260 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 261 262 for (i = 0; i < ahd_num_pci_devs; i++) { 263 entry = &ahd_pci_ident_table[i]; 264 if (entry->full_id == (full_id & entry->id_mask)) 265 return (entry); 266 } 267 return (NULL); 268 } 269 270 int 271 ahd_pci_probe(parent, match, aux) 272 struct device *parent; 273 struct cfdata *match; 274 void *aux; 275 { 276 struct pci_attach_args *pa = aux; 277 const struct ahd_pci_identity *entry; 278 pcireg_t subid; 279 280 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 281 entry = ahd_find_pci_device(pa->pa_id, subid); 282 return entry != NULL ? 1 : 0; 283 } 284 285 void 286 ahd_pci_attach(parent, self, aux) 287 struct device *parent, *self; 288 void *aux; 289 { 290 struct pci_attach_args *pa = aux; 291 struct ahd_softc *ahd = (void *)self; 292 293 const struct ahd_pci_identity *entry; 294 295 uint32_t devconfig; 296 pcireg_t command; 297 int error; 298 pcireg_t subid; 299 uint16_t subvendor; 300 int pci_pwrmgmt_cap_reg; 301 int pci_pwrmgmt_csr_reg; 302 pcireg_t reg; 303 int ioh_valid, ioh2_valid, memh_valid; 304 pcireg_t memtype; 305 pci_intr_handle_t ih; 306 const char *intrstr; 307 struct ahd_pci_busdata *bd; 308 309 ahd_set_name(ahd, ahd->sc_dev.dv_xname); 310 ahd->parent_dmat = pa->pa_dmat; 311 312 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 313 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 314 entry = ahd_find_pci_device(pa->pa_id, subid); 315 if (entry == NULL) 316 return; 317 318 /* Keep information about the PCI bus */ 319 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 320 if (bd == NULL) { 321 printf("%s: unable to allocate bus-specific data\n", ahd_name(ahd)); 322 return; 323 } 324 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 325 326 bd->pc = pa->pa_pc; 327 bd->tag = pa->pa_tag; 328 bd->func = pa->pa_function; 329 bd->dev = pa->pa_device; 330 331 ahd->bus_data = bd; 332 333 ahd->description = entry->name; 334 335 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 336 M_DEVBUF, M_NOWAIT); 337 if (ahd->seep_config == NULL) { 338 printf("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 339 return; 340 } 341 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 342 343 LIST_INIT(&ahd->pending_scbs); 344 ahd_timer_init(&ahd->reset_timer); 345 ahd_timer_init(&ahd->stat_timer); 346 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 347 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 348 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 349 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 350 ahd->int_coalescing_stop_threshold = AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 351 352 if (ahd_platform_alloc(ahd, NULL) != 0) { 353 ahd_free(ahd); 354 return; 355 } 356 357 /* 358 * Record if this is an HP board. 359 */ 360 subvendor = PCI_VENDOR(subid); 361 if (subvendor == SUBID_HP) 362 ahd->flags |= AHD_HP_BOARD; 363 364 error = entry->setup(ahd, pa); 365 if (error != 0) 366 return; 367 368 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 369 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66 || 370 (devconfig & PCIXINITPAT) == PCIXINIT_PCIX66_100) { 371 ahd->chip |= AHD_PCI; 372 /* Disable PCIX workarounds when running in PCI mode. */ 373 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 374 } else { 375 ahd->chip |= AHD_PCIX; 376 } 377 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 378 379 memh_valid = ioh_valid = ioh2_valid = 0; 380 381 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 382 &bd->pcix_off, NULL)) { 383 if (ahd->chip & AHD_PCIX) 384 printf("%s: warning: can't find PCI-X capability\n", 385 ahd->sc_dev.dv_xname); 386 ahd->chip &= ~AHD_PCIX; 387 ahd->chip |= AHD_PCI; 388 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 389 } 390 391 /* 392 * Map PCI Registers 393 */ 394 if ((command & (PCI_COMMAND_MEM_ENABLE)) != 0) { 395 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHD_PCI_MEMADDR); 396 switch (memtype) { 397 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 398 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 399 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 400 memtype, 0, &ahd->tags[0], 401 &ahd->bshs[0], NULL, NULL) == 0); 402 403 ahd->tags[1] = ahd->tags[0]; 404 405 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 406 /*offset*/0x100, 407 /*size*/0x100, 408 &ahd->bshs[1]); 409 break; 410 default: 411 printf("%s: unable to map memory registers\n", ahd_name(ahd)); 412 return; 413 } 414 415 if (memh_valid) { 416 command &= ~PCI_COMMAND_IO_ENABLE; 417 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 418 } 419 #ifdef AHD_DEBUG 420 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, shs0 0x%lx, shs1 0x%lx\n", 421 ahd_name(ahd), ahd->tags[0], ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 422 #endif 423 } 424 425 if ((command & (PCI_COMMAND_IO_ENABLE)) != 0 && 426 !(ahd->bugs & AHD_PCIX_MMAPIO_BUG)) { 427 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHD_PCI_IOADDR); 428 429 /* First BAR */ 430 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 431 memtype, 0, &ahd->tags[0], 432 &ahd->bshs[0], NULL, NULL) == 0); 433 434 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHD_PCI_IOADDR1); 435 436 /* 2nd BAR */ 437 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 438 memtype, 0, &ahd->tags[1], 439 &ahd->bshs[1], NULL, NULL) == 0); 440 441 if (ioh_valid && ioh2_valid) { 442 command &= ~PCI_COMMAND_MEM_ENABLE; 443 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 444 } 445 #ifdef AHD_DEBUG 446 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, shs0 0x%lx, shs1 0x%lx\n", 447 ahd_name(ahd), ahd->tags[0], ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 448 #endif 449 450 } 451 452 if ((memh_valid == 0) && ((ioh_valid == 0) || (ioh2_valid == 0))) { 453 printf("%s: unable to map memory registers\n", ahd_name(ahd)); 454 return; 455 } 456 457 printf("\n"); 458 459 /* 460 * Set Power State D0. 461 */ 462 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 463 &pci_pwrmgmt_cap_reg, 0)) { 464 465 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 466 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 467 pci_pwrmgmt_csr_reg); 468 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 469 pci_conf_write(pa->pa_pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 470 (reg & ~PCI_PMCSR_STATE_MASK) | 471 PCI_PMCSR_STATE_D0); 472 } 473 } 474 475 /* 476 * Should we bother disabling 39Bit addressing 477 * based on installed memory? 478 */ 479 if (sizeof(bus_addr_t) > 4) 480 ahd->flags |= AHD_39BIT_ADDRESSING; 481 482 /* 483 * If we need to support high memory, enable dual 484 * address cycles. This bit must be set to enable 485 * high address bit generation even if we are on a 486 * 64bit bus (PCI64BIT set in devconfig). 487 */ 488 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 489 uint32_t devconfig; 490 491 printf("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 492 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 493 devconfig |= DACEN; 494 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 495 } 496 497 /* Ensure busmastering is enabled */ 498 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 499 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 500 reg | PCI_COMMAND_MASTER_ENABLE); 501 502 ahd_softc_init(ahd); 503 504 /* 505 * Map the interrupt routines 506 */ 507 ahd->bus_intr = ahd_pci_intr; 508 509 if (pci_intr_map(pa, &ih)) { 510 printf("%s: couldn't map interrupt\n", ahd_name(ahd)); 511 ahd_free(ahd); 512 return; 513 } 514 intrstr = pci_intr_string(pa->pa_pc, ih); 515 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 516 if (ahd->ih == NULL) { 517 printf("%s: couldn't establish interrupt", 518 ahd_name(ahd)); 519 if (intrstr != NULL) 520 printf(" at %s", intrstr); 521 printf("\n"); 522 ahd_free(ahd); 523 return; 524 } 525 if (intrstr != NULL) 526 printf("%s: interrupting at %s\n", ahd_name(ahd), 527 intrstr); 528 529 /* Get the size of the cache */ 530 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 531 ahd->pci_cachesize *= 4; 532 533 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 534 /* See if we have a SEEPROM and perform auto-term */ 535 error = ahd_check_extport(ahd); 536 if (error != 0) 537 return; 538 539 /* Core initialization */ 540 error = ahd_init(ahd); 541 if (error != 0) 542 return; 543 544 /* 545 * Link this softc in with all other ahd instances. 546 */ 547 ahd_attach(ahd); 548 549 return; 550 } 551 552 553 /* 554 * Check the external port logic for a serial eeprom 555 * and termination/cable detection contrls. 556 */ 557 static int 558 ahd_check_extport(struct ahd_softc *ahd) 559 { 560 struct seeprom_config *sc; 561 u_int adapter_control; 562 int have_seeprom; 563 int error; 564 565 sc = ahd->seep_config; 566 have_seeprom = ahd_acquire_seeprom(ahd); 567 if (have_seeprom) { 568 u_int start_addr; 569 #ifdef AHD_DEBUG 570 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 571 #endif 572 573 /* Address is always in units of 16bit words */ 574 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 575 576 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 577 start_addr, sizeof(*sc)/2); 578 579 if (error != 0) { 580 #ifdef AHD_DEBUG 581 printf("Unable to read SEEPROM\n"); 582 #endif 583 have_seeprom = 0; 584 } else { 585 have_seeprom = ahd_verify_cksum(sc); 586 #ifdef AHD_DEBUG 587 if (have_seeprom == 0) 588 printf ("checksum error\n"); 589 else 590 printf ("done.\n"); 591 #endif 592 } 593 ahd_release_seeprom(ahd); 594 } 595 596 if (!have_seeprom) { 597 u_int nvram_scb; 598 599 /* 600 * Pull scratch ram settings and treat them as 601 * if they are the contents of an seeprom if 602 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 603 * in SCB 0xFF. We manually compose the data as 16bit 604 * values to avoid endian issues. 605 */ 606 ahd_set_scbptr(ahd, 0xFF); 607 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 608 if (nvram_scb != 0xFF 609 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 610 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 611 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 612 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 613 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 614 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 615 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 616 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 617 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 618 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 619 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 620 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 621 uint16_t *sc_data; 622 int i; 623 624 ahd_set_scbptr(ahd, nvram_scb); 625 sc_data = (uint16_t *)sc; 626 for (i = 0; i < 64; i += 2) 627 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 628 have_seeprom = ahd_verify_cksum(sc); 629 if (have_seeprom) 630 ahd->flags |= AHD_SCB_CONFIG_USED; 631 } 632 } 633 634 #ifdef AHD_DEBUG 635 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 636 uint8_t *sc_data; 637 int i; 638 639 printf("%s: Seeprom Contents:", ahd_name(ahd)); 640 sc_data = (uint8_t *)sc; 641 for (i = 0; i < (sizeof(*sc)); i += 2) 642 printf("\n\t0x%.4x", 643 sc_data[i] | (sc_data[i+1] << 8)); 644 printf("\n"); 645 } 646 #endif 647 648 if (!have_seeprom) { 649 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 650 ahd->flags |= AHD_USEDEFAULTS; 651 error = ahd_default_config(ahd); 652 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 653 free(ahd->seep_config, M_DEVBUF); 654 ahd->seep_config = NULL; 655 } else { 656 error = ahd_parse_cfgdata(ahd, sc); 657 adapter_control = sc->adapter_control; 658 } 659 if (error != 0) 660 return (error); 661 662 ahd_configure_termination(ahd, adapter_control); 663 664 return (0); 665 } 666 667 static void 668 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 669 { 670 int error; 671 u_int sxfrctl1; 672 uint8_t termctl; 673 uint32_t devconfig; 674 struct ahd_pci_busdata *bd = ahd->bus_data; 675 676 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 677 devconfig &= ~STPWLEVEL; 678 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 679 devconfig |= STPWLEVEL; 680 #ifdef AHD_DEBUG 681 printf("%s: STPWLEVEL is %s\n", 682 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 683 #endif 684 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 685 686 /* Make sure current sensing is off. */ 687 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 688 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 689 } 690 691 /* 692 * Read to sense. Write to set. 693 */ 694 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 695 if ((adapter_control & CFAUTOTERM) == 0) { 696 printf("%s: Manual Primary Termination\n", 697 ahd_name(ahd)); 698 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 699 if ((adapter_control & CFSTERM) != 0) 700 termctl |= FLX_TERMCTL_ENPRILOW; 701 if ((adapter_control & CFWSTERM) != 0) 702 termctl |= FLX_TERMCTL_ENPRIHIGH; 703 } else if (error != 0) { 704 printf("%s: Primary Auto-Term Sensing failed! " 705 "Using Defaults.\n", ahd_name(ahd)); 706 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 707 } 708 709 if ((adapter_control & CFSEAUTOTERM) == 0) { 710 printf("%s: Manual Secondary Termination\n", 711 ahd_name(ahd)); 712 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 713 if ((adapter_control & CFSELOWTERM) != 0) 714 termctl |= FLX_TERMCTL_ENSECLOW; 715 if ((adapter_control & CFSEHIGHTERM) != 0) 716 termctl |= FLX_TERMCTL_ENSECHIGH; 717 } else if (error != 0) { 718 printf("%s: Secondary Auto-Term Sensing failed! " 719 "Using Defaults.\n", ahd_name(ahd)); 720 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 721 } 722 723 /* 724 * Now set the termination based on what we found. 725 */ 726 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 727 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 728 ahd->flags |= AHD_TERM_ENB_A; 729 sxfrctl1 |= STPWEN; 730 } 731 /* Must set the latch once in order to be effective. */ 732 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 733 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 734 735 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 736 if (error != 0) { 737 printf("%s: Unable to set termination settings!\n", 738 ahd_name(ahd)); 739 } else { 740 printf("%s: Primary High byte termination %sabled\n", 741 ahd_name(ahd), 742 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 743 744 printf("%s: Primary Low byte termination %sabled\n", 745 ahd_name(ahd), 746 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 747 748 printf("%s: Secondary High byte termination %sabled\n", 749 ahd_name(ahd), 750 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 751 752 printf("%s: Secondary Low byte termination %sabled\n", 753 ahd_name(ahd), 754 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 755 } 756 return; 757 } 758 759 #define DPE 0x80 760 #define SSE 0x40 761 #define RMA 0x20 762 #define RTA 0x10 763 #define STA 0x08 764 #define DPR 0x01 765 766 static const char *split_status_source[] = 767 { 768 "DFF0", 769 "DFF1", 770 "OVLY", 771 "CMC", 772 }; 773 774 static const char *pci_status_source[] = 775 { 776 "DFF0", 777 "DFF1", 778 "SG", 779 "CMC", 780 "OVLY", 781 "NONE", 782 "MSI", 783 "TARG" 784 }; 785 786 static const char *split_status_strings[] = 787 { 788 "%s: Received split response in %s.\n", 789 "%s: Received split completion error message in %s\n", 790 "%s: Receive overrun in %s\n", 791 "%s: Count not complete in %s\n", 792 "%s: Split completion data bucket in %s\n", 793 "%s: Split completion address error in %s\n", 794 "%s: Split completion byte count error in %s\n", 795 "%s: Signaled Target-abort to early terminate a split in %s\n" 796 }; 797 798 static const char *pci_status_strings[] = 799 { 800 "%s: Data Parity Error has been reported via PERR# in %s\n", 801 "%s: Target initial wait state error in %s\n", 802 "%s: Split completion read data parity error in %s\n", 803 "%s: Split completion address attribute parity error in %s\n", 804 "%s: Received a Target Abort in %s\n", 805 "%s: Received a Master Abort in %s\n", 806 "%s: Signal System Error Detected in %s\n", 807 "%s: Address or Write Phase Parity Error Detected in %s.\n" 808 }; 809 810 int 811 ahd_pci_intr(struct ahd_softc *ahd) 812 { 813 uint8_t pci_status[8]; 814 ahd_mode_state saved_modes; 815 u_int pci_status1; 816 u_int intstat; 817 u_int i; 818 u_int reg; 819 struct ahd_pci_busdata *bd = ahd->bus_data; 820 821 intstat = ahd_inb(ahd, INTSTAT); 822 823 if ((intstat & SPLTINT) != 0) 824 ahd_pci_split_intr(ahd, intstat); 825 826 if ((intstat & PCIINT) == 0) 827 return 0; 828 829 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 830 saved_modes = ahd_save_modes(ahd); 831 ahd_dump_card_state(ahd); 832 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 833 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 834 835 if (i == 5) 836 continue; 837 pci_status[i] = ahd_inb(ahd, reg); 838 /* Clear latched errors. So our interrupt deasserts. */ 839 ahd_outb(ahd, reg, pci_status[i]); 840 } 841 842 for (i = 0; i < 8; i++) { 843 u_int bit; 844 845 if (i == 5) 846 continue; 847 848 for (bit = 0; bit < 8; bit++) { 849 850 if ((pci_status[i] & (0x1 << bit)) != 0) { 851 static const char *s; 852 853 s = pci_status_strings[bit]; 854 if (i == 7/*TARG*/ && bit == 3) 855 s = "%s: Signaled Target Abort\n"; 856 printf(s, ahd_name(ahd), pci_status_source[i]); 857 } 858 } 859 } 860 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 861 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 862 863 ahd_restore_modes(ahd, saved_modes); 864 ahd_outb(ahd, CLRINT, CLRPCIINT); 865 ahd_unpause(ahd); 866 867 return 1; 868 } 869 870 static void 871 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 872 { 873 uint8_t split_status[4]; 874 uint8_t split_status1[4]; 875 uint8_t sg_split_status[2]; 876 uint8_t sg_split_status1[2]; 877 ahd_mode_state saved_modes; 878 u_int i; 879 pcireg_t pcix_status; 880 struct ahd_pci_busdata *bd = ahd->bus_data; 881 882 /* 883 * Check for splits in all modes. Modes 0 and 1 884 * additionally have SG engine splits to look at. 885 */ 886 pcix_status = pci_conf_read(bd->pc, bd->tag, 887 bd->pcix_off + PCI_PCIX_STATUS); 888 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 889 ahd_name(ahd), pcix_status); 890 891 saved_modes = ahd_save_modes(ahd); 892 for (i = 0; i < 4; i++) { 893 ahd_set_modes(ahd, i, i); 894 895 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 896 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 897 /* Clear latched errors. So our interrupt deasserts. */ 898 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 899 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 900 if (i != 0) 901 continue; 902 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 903 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 904 /* Clear latched errors. So our interrupt deasserts. */ 905 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 906 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 907 } 908 909 for (i = 0; i < 4; i++) { 910 u_int bit; 911 912 for (bit = 0; bit < 8; bit++) { 913 914 if ((split_status[i] & (0x1 << bit)) != 0) { 915 static const char *s; 916 917 s = split_status_strings[bit]; 918 printf(s, ahd_name(ahd), 919 split_status_source[i]); 920 } 921 922 if (i != 0) 923 continue; 924 925 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 926 static const char *s; 927 928 s = split_status_strings[bit]; 929 printf(s, ahd_name(ahd), "SG"); 930 } 931 } 932 } 933 /* 934 * Clear PCI-X status bits. 935 */ 936 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 937 pcix_status); 938 ahd_outb(ahd, CLRINT, CLRSPLTINT); 939 ahd_restore_modes(ahd, saved_modes); 940 } 941 942 static int 943 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 944 { 945 int error; 946 947 error = ahd_aic7902_setup(ahd, pa); 948 if (error != 0) 949 return (error); 950 ahd->chip = AHD_AIC7901A; 951 return (0); 952 } 953 954 static int 955 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 956 { 957 u_int rev; 958 959 rev = PCI_REVISION(pa->pa_class); 960 #ifdef AHD_DEBUG 961 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 962 #endif 963 if (rev < ID_AIC7902_PCI_REV_A4) { 964 printf("%s: Unable to attach to unsupported chip revision %d\n", 965 ahd_name(ahd), rev); 966 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 967 return (ENXIO); 968 } 969 970 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 971 ahd->chip = AHD_AIC7902; 972 ahd->features = AHD_AIC7902_FE; 973 if (rev < ID_AIC7902_PCI_REV_B0) { 974 /* 975 * Enable A series workarounds. 976 */ 977 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 978 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 979 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 980 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 981 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 982 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 983 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 984 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 985 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 986 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG; 987 988 989 /* 990 * IO Cell paramter setup. 991 */ 992 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 993 994 if ((ahd->flags & AHD_HP_BOARD) == 0) 995 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 996 } else { 997 u_int devconfig1; 998 999 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1000 | AHD_NEW_DFCNTRL_OPTS; 1001 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_ABORT_LQI_BUG 1002 | AHD_INTCOLLISION_BUG|AHD_EARLY_REQ_BUG; 1003 1004 /* 1005 * IO Cell paramter setup. 1006 */ 1007 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1008 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1009 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1010 1011 /* 1012 * Set the PREQDIS bit for H2B which disables some workaround 1013 * that doesn't work on regular PCI busses. 1014 * XXX - Find out exactly what this does from the hardware 1015 * folks! 1016 */ 1017 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1018 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1019 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1020 } 1021 1022 return (0); 1023 } 1024 1025