1 /* $NetBSD: ahd_pci.c,v 1.32 2010/04/21 21:38:47 dyoung Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. 49 * - April 2003 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.32 2010/04/21 21:38:47 dyoung Exp $"); 54 55 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 56 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 57 58 #include <dev/ic/aic79xx_osm.h> 59 #include <dev/ic/aic79xx_inline.h> 60 61 static inline uint64_t 62 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 63 { 64 uint64_t id; 65 66 id = subvendor 67 | (subdevice << 16) 68 | ((uint64_t)vendor << 32) 69 | ((uint64_t)device << 48); 70 71 return (id); 72 } 73 74 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 75 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 76 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 77 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 78 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 79 80 #define ID_AIC7901 0x800F9005FFFF9005ull 81 #define ID_AHA_29320A 0x8000900500609005ull 82 #define ID_AHA_29320ALP 0x8017900500449005ull 83 84 #define ID_AIC7901A 0x801E9005FFFF9005ull 85 #define ID_AHA_29320LP 0x8014900500449005ull 86 87 #define ID_AIC7902 0x801F9005FFFF9005ull 88 #define ID_AIC7902_B 0x801D9005FFFF9005ull 89 #define ID_AHA_39320 0x8010900500409005ull 90 #define ID_AHA_29320 0x8012900500429005ull 91 #define ID_AHA_29320B 0x8013900500439005ull 92 #define ID_AHA_39320_B 0x8015900500409005ull 93 #define ID_AHA_39320A 0x8016900500409005ull 94 #define ID_AHA_39320D 0x8011900500419005ull 95 #define ID_AHA_39320D_B 0x801C900500419005ull 96 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 97 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 98 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 99 #define ID_AIC7902_PCI_REV_A4 0x3 100 #define ID_AIC7902_PCI_REV_B0 0x10 101 #define SUBID_HP 0x0E11 102 103 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 104 105 #define DEVID_9005_TYPE(id) ((id) & 0xF) 106 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 107 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 108 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 109 110 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 111 112 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 113 114 #define SUBID_9005_TYPE(id) ((id) & 0xF) 115 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 116 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 117 118 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 119 120 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 121 122 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 123 #define SUBID_9005_SEEPTYPE_NONE 0x0 124 #define SUBID_9005_SEEPTYPE_4K 0x1 125 126 static ahd_device_setup_t ahd_aic7901_setup; 127 static ahd_device_setup_t ahd_aic7901A_setup; 128 static ahd_device_setup_t ahd_aic7902_setup; 129 static ahd_device_setup_t ahd_aic790X_setup; 130 131 static struct ahd_pci_identity ahd_pci_ident_table [] = 132 { 133 /* aic7901 based controllers */ 134 { 135 ID_AHA_29320A, 136 ID_ALL_MASK, 137 "Adaptec 29320A Ultra320 SCSI adapter", 138 ahd_aic7901_setup 139 }, 140 { 141 ID_AHA_29320ALP, 142 ID_ALL_MASK, 143 "Adaptec 29320ALP Ultra320 SCSI adapter", 144 ahd_aic7901_setup 145 }, 146 /* aic7901A based controllers */ 147 { 148 ID_AHA_29320LP, 149 ID_ALL_MASK, 150 "Adaptec 29320LP Ultra320 SCSI adapter", 151 ahd_aic7901A_setup 152 }, 153 /* aic7902 based controllers */ 154 { 155 ID_AHA_39320, 156 ID_ALL_MASK, 157 "Adaptec 39320 Ultra320 SCSI adapter", 158 ahd_aic7902_setup 159 }, 160 { 161 ID_AHA_39320_B, 162 ID_ALL_MASK, 163 "Adaptec 39320 Ultra320 SCSI adapter", 164 ahd_aic7902_setup 165 }, 166 { 167 ID_AHA_39320_B_DELL, 168 ID_ALL_IROC_MASK, 169 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 170 ahd_aic7902_setup 171 }, 172 { 173 ID_AHA_39320A, 174 ID_ALL_MASK, 175 "Adaptec 39320A Ultra320 SCSI adapter", 176 ahd_aic7902_setup 177 }, 178 { 179 ID_AHA_39320D, 180 ID_ALL_MASK, 181 "Adaptec 39320D Ultra320 SCSI adapter", 182 ahd_aic7902_setup 183 }, 184 { 185 ID_AHA_39320D_HP, 186 ID_ALL_MASK, 187 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 188 ahd_aic7902_setup 189 }, 190 { 191 ID_AHA_39320D_B, 192 ID_ALL_MASK, 193 "Adaptec 39320D Ultra320 SCSI adapter", 194 ahd_aic7902_setup 195 }, 196 { 197 ID_AHA_39320D_B_HP, 198 ID_ALL_MASK, 199 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 200 ahd_aic7902_setup 201 }, 202 /* Generic chip probes for devices we don't know 'exactly' */ 203 { 204 ID_AIC7901 & ID_9005_GENERIC_MASK, 205 ID_9005_GENERIC_MASK, 206 "Adaptec AIC7901 Ultra320 SCSI adapter", 207 ahd_aic7901_setup 208 }, 209 { 210 ID_AIC7901A & ID_DEV_VENDOR_MASK, 211 ID_DEV_VENDOR_MASK, 212 "Adaptec AIC7901A Ultra320 SCSI adapter", 213 ahd_aic7901A_setup 214 }, 215 { 216 ID_AIC7902 & ID_9005_GENERIC_MASK, 217 ID_9005_GENERIC_MASK, 218 "Adaptec AIC7902 Ultra320 SCSI adapter", 219 ahd_aic7902_setup 220 } 221 }; 222 223 static const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 224 225 #define DEVCONFIG 0x40 226 #define PCIXINITPAT 0x0000E000ul 227 #define PCIXINIT_PCI33_66 0x0000E000ul 228 #define PCIXINIT_PCIX50_66 0x0000C000ul 229 #define PCIXINIT_PCIX66_100 0x0000A000ul 230 #define PCIXINIT_PCIX100_133 0x00008000ul 231 #define PCI_BUS_MODES_INDEX(devconfig) \ 232 (((devconfig) & PCIXINITPAT) >> 13) 233 234 static const char *pci_bus_modes[] = 235 { 236 "PCI bus mode unknown", 237 "PCI bus mode unknown", 238 "PCI bus mode unknown", 239 "PCI bus mode unknown", 240 "PCI-X 101-133 MHz", 241 "PCI-X 67-100 MHz", 242 "PCI-X 50-66 MHz", 243 "PCI 33 or 66 MHz" 244 }; 245 246 #define TESTMODE 0x00000800ul 247 #define IRDY_RST 0x00000200ul 248 #define FRAME_RST 0x00000100ul 249 #define PCI64BIT 0x00000080ul 250 #define MRDCEN 0x00000040ul 251 #define ENDIANSEL 0x00000020ul 252 #define MIXQWENDIANEN 0x00000008ul 253 #define DACEN 0x00000004ul 254 #define STPWLEVEL 0x00000002ul 255 #define QWENDIANSEL 0x00000001ul 256 257 #define DEVCONFIG1 0x44 258 #define PREQDIS 0x01 259 260 #define LATTIME 0x0000ff00ul 261 262 static int ahd_check_extport(struct ahd_softc *ahd); 263 static void ahd_configure_termination(struct ahd_softc *ahd, 264 u_int adapter_control); 265 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 266 267 static int ahd_pci_test_register_access(struct ahd_softc *); 268 269 static int ahd_pci_intr(struct ahd_softc *); 270 271 static const struct ahd_pci_identity * 272 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 273 { 274 u_int64_t full_id; 275 const struct ahd_pci_identity *entry; 276 u_int i; 277 278 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 279 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 280 281 for (i = 0; i < ahd_num_pci_devs; i++) { 282 entry = &ahd_pci_ident_table[i]; 283 if (entry->full_id == (full_id & entry->id_mask)) 284 return (entry); 285 } 286 return (NULL); 287 } 288 289 static int 290 ahd_pci_probe(device_t parent, cfdata_t match, void *aux) 291 { 292 struct pci_attach_args *pa = aux; 293 const struct ahd_pci_identity *entry; 294 pcireg_t subid; 295 296 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 297 entry = ahd_find_pci_device(pa->pa_id, subid); 298 return entry != NULL ? 1 : 0; 299 } 300 301 static void 302 ahd_pci_attach(device_t parent, device_t self, void *aux) 303 { 304 struct pci_attach_args *pa = aux; 305 struct ahd_softc *ahd = device_private(self); 306 307 const struct ahd_pci_identity *entry; 308 309 uint32_t devconfig; 310 pcireg_t command; 311 int error; 312 pcireg_t subid; 313 uint16_t subvendor; 314 pcireg_t reg; 315 int ioh_valid, ioh2_valid, memh_valid; 316 pcireg_t memtype; 317 pci_intr_handle_t ih; 318 const char *intrstr; 319 struct ahd_pci_busdata *bd; 320 321 ahd->sc_dev = self; 322 ahd_set_name(ahd, device_xname(self)); 323 ahd->parent_dmat = pa->pa_dmat; 324 325 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 326 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 327 entry = ahd_find_pci_device(pa->pa_id, subid); 328 if (entry == NULL) 329 return; 330 331 /* Keep information about the PCI bus */ 332 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 333 if (bd == NULL) { 334 aprint_error("%s: unable to allocate bus-specific data\n", 335 ahd_name(ahd)); 336 return; 337 } 338 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 339 340 bd->pc = pa->pa_pc; 341 bd->tag = pa->pa_tag; 342 bd->func = pa->pa_function; 343 bd->dev = pa->pa_device; 344 345 ahd->bus_data = bd; 346 347 ahd->description = entry->name; 348 349 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 350 M_DEVBUF, M_NOWAIT); 351 if (ahd->seep_config == NULL) { 352 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 353 return; 354 } 355 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 356 357 LIST_INIT(&ahd->pending_scbs); 358 ahd_timer_init(&ahd->reset_timer); 359 ahd_timer_init(&ahd->stat_timer); 360 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 361 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 362 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 363 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 364 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 365 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 366 ahd->int_coalescing_stop_threshold = 367 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 368 369 if (ahd_platform_alloc(ahd, NULL) != 0) { 370 ahd_free(ahd); 371 return; 372 } 373 374 /* 375 * Record if this is an HP board. 376 */ 377 subvendor = PCI_VENDOR(subid); 378 if (subvendor == SUBID_HP) 379 ahd->flags |= AHD_HP_BOARD; 380 381 error = entry->setup(ahd, pa); 382 if (error != 0) 383 return; 384 385 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 386 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 387 ahd->chip |= AHD_PCI; 388 /* Disable PCIX workarounds when running in PCI mode. */ 389 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 390 } else { 391 ahd->chip |= AHD_PCIX; 392 } 393 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 394 395 memh_valid = ioh_valid = ioh2_valid = 0; 396 397 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 398 &bd->pcix_off, NULL)) { 399 if (ahd->chip & AHD_PCIX) 400 aprint_error_dev(self, 401 "warning: can't find PCI-X capability\n"); 402 ahd->chip &= ~AHD_PCIX; 403 ahd->chip |= AHD_PCI; 404 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 405 } 406 407 /* 408 * Map PCI Registers 409 */ 410 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 411 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 412 AHD_PCI_MEMADDR); 413 switch (memtype) { 414 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 415 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 416 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 417 memtype, 0, &ahd->tags[0], 418 &ahd->bshs[0], 419 NULL, NULL) == 0); 420 if (memh_valid) { 421 ahd->tags[1] = ahd->tags[0]; 422 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 423 /*offset*/0x100, 424 /*size*/0x100, 425 &ahd->bshs[1]); 426 if (ahd_pci_test_register_access(ahd) != 0) 427 memh_valid = 0; 428 } 429 break; 430 default: 431 memh_valid = 0; 432 aprint_error("%s: unknown memory type: 0x%x\n", 433 ahd_name(ahd), memtype); 434 break; 435 } 436 437 if (memh_valid) { 438 command &= ~PCI_COMMAND_IO_ENABLE; 439 pci_conf_write(pa->pa_pc, pa->pa_tag, 440 PCI_COMMAND_STATUS_REG, command); 441 } 442 #ifdef AHD_DEBUG 443 printf("%s: doing memory mapping shs0 0x%lx, shs1 0x%lx\n", 444 ahd_name(ahd), ahd->bshs[0], ahd->bshs[1]); 445 #endif 446 } 447 448 if (command & PCI_COMMAND_IO_ENABLE) { 449 /* First BAR */ 450 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 451 PCI_MAPREG_TYPE_IO, 0, 452 &ahd->tags[0], &ahd->bshs[0], 453 NULL, NULL) == 0); 454 455 /* 2nd BAR */ 456 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 457 PCI_MAPREG_TYPE_IO, 0, 458 &ahd->tags[1], &ahd->bshs[1], 459 NULL, NULL) == 0); 460 461 if (ioh_valid && ioh2_valid) { 462 KASSERT(memh_valid == 0); 463 command &= ~PCI_COMMAND_MEM_ENABLE; 464 pci_conf_write(pa->pa_pc, pa->pa_tag, 465 PCI_COMMAND_STATUS_REG, command); 466 } 467 #ifdef AHD_DEBUG 468 printf("%s: doing io mapping shs0 0x%lx, shs1 0x%lx\n", 469 ahd_name(ahd), ahd->bshs[0], ahd->bshs[1]); 470 #endif 471 472 } 473 474 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 475 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 476 return; 477 } 478 479 aprint_normal("\n"); 480 aprint_naive("\n"); 481 482 /* power up chip */ 483 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 484 pci_activate_null)) && error != EOPNOTSUPP) { 485 aprint_error_dev(self, "cannot activate %d\n", error); 486 return; 487 } 488 /* 489 * Should we bother disabling 39Bit addressing 490 * based on installed memory? 491 */ 492 if (sizeof(bus_addr_t) > 4) 493 ahd->flags |= AHD_39BIT_ADDRESSING; 494 495 /* 496 * If we need to support high memory, enable dual 497 * address cycles. This bit must be set to enable 498 * high address bit generation even if we are on a 499 * 64bit bus (PCI64BIT set in devconfig). 500 */ 501 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 502 uint32_t dvconfig; 503 504 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 505 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 506 dvconfig |= DACEN; 507 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, dvconfig); 508 } 509 510 /* Ensure busmastering is enabled */ 511 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 512 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 513 reg | PCI_COMMAND_MASTER_ENABLE); 514 515 ahd_softc_init(ahd); 516 517 /* 518 * Map the interrupt routines 519 */ 520 ahd->bus_intr = ahd_pci_intr; 521 522 error = ahd_reset(ahd, /*reinit*/FALSE); 523 if (error != 0) { 524 ahd_free(ahd); 525 return; 526 } 527 528 if (pci_intr_map(pa, &ih)) { 529 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 530 ahd_free(ahd); 531 return; 532 } 533 intrstr = pci_intr_string(pa->pa_pc, ih); 534 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 535 if (ahd->ih == NULL) { 536 aprint_error("%s: couldn't establish interrupt", 537 ahd_name(ahd)); 538 if (intrstr != NULL) 539 aprint_error(" at %s", intrstr); 540 aprint_error("\n"); 541 ahd_free(ahd); 542 return; 543 } 544 if (intrstr != NULL) 545 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 546 intrstr); 547 548 /* Get the size of the cache */ 549 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 550 ahd->pci_cachesize *= 4; 551 552 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 553 /* See if we have a SEEPROM and perform auto-term */ 554 error = ahd_check_extport(ahd); 555 if (error != 0) 556 return; 557 558 /* Core initialization */ 559 error = ahd_init(ahd); 560 if (error != 0) 561 return; 562 563 /* 564 * Link this softc in with all other ahd instances. 565 */ 566 ahd_attach(ahd); 567 } 568 569 CFATTACH_DECL_NEW(ahd_pci, sizeof(struct ahd_softc), 570 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 571 572 /* 573 * Perform some simple tests that should catch situations where 574 * our registers are invalidly mapped. 575 */ 576 static int 577 ahd_pci_test_register_access(struct ahd_softc *ahd) 578 { 579 uint32_t cmd; 580 struct ahd_pci_busdata *bd = ahd->bus_data; 581 u_int targpcistat; 582 uint32_t pci_status1; 583 int error; 584 uint8_t hcntrl; 585 586 error = EIO; 587 588 /* 589 * Enable PCI error interrupt status, but suppress NMIs 590 * generated by SERR raised due to target aborts. 591 */ 592 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 593 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 594 cmd & ~PCI_COMMAND_SERR_ENABLE); 595 596 /* 597 * First a simple test to see if any 598 * registers can be read. Reading 599 * HCNTRL has no side effects and has 600 * at least one bit that is guaranteed to 601 * be zero so it is a good register to 602 * use for this test. 603 */ 604 hcntrl = ahd_inb(ahd, HCNTRL); 605 if (hcntrl == 0xFF) 606 goto fail; 607 608 /* 609 * Next create a situation where write combining 610 * or read prefetching could be initiated by the 611 * CPU or host bridge. Our device does not support 612 * either, so look for data corruption and/or flaged 613 * PCI errors. First pause without causing another 614 * chip reset. 615 */ 616 hcntrl &= ~CHIPRST; 617 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 618 while (ahd_is_paused(ahd) == 0) 619 ; 620 621 /* Clear any PCI errors that occurred before our driver attached. */ 622 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 623 targpcistat = ahd_inb(ahd, TARGPCISTAT); 624 ahd_outb(ahd, TARGPCISTAT, targpcistat); 625 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 626 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 627 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 628 ahd_outb(ahd, CLRINT, CLRPCIINT); 629 630 ahd_outb(ahd, SEQCTL0, PERRORDIS); 631 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 632 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 633 goto fail; 634 635 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 636 u_int trgpcistat; 637 638 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 639 trgpcistat = ahd_inb(ahd, TARGPCISTAT); 640 if ((trgpcistat & STA) != 0) 641 goto fail; 642 } 643 644 error = 0; 645 646 fail: 647 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 648 649 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 650 targpcistat = ahd_inb(ahd, TARGPCISTAT); 651 652 /* Silently clear any latched errors. */ 653 ahd_outb(ahd, TARGPCISTAT, targpcistat); 654 pci_status1 = pci_conf_read(bd->pc, bd->tag, 655 PCI_COMMAND_STATUS_REG); 656 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 657 pci_status1); 658 ahd_outb(ahd, CLRINT, CLRPCIINT); 659 } 660 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 661 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 662 return (error); 663 } 664 665 /* 666 * Check the external port logic for a serial eeprom 667 * and termination/cable detection contrls. 668 */ 669 static int 670 ahd_check_extport(struct ahd_softc *ahd) 671 { 672 struct vpd_config vpd; 673 struct seeprom_config *sc; 674 u_int adapter_control; 675 int have_seeprom; 676 int error; 677 678 sc = ahd->seep_config; 679 have_seeprom = ahd_acquire_seeprom(ahd); 680 if (have_seeprom) { 681 u_int start_addr; 682 683 /* 684 * Fetch VPD for this function and parse it. 685 */ 686 #ifdef AHD_DEBUG 687 printf("%s: Reading VPD from SEEPROM...", 688 ahd_name(ahd)); 689 #endif 690 /* Address is always in units of 16bit words */ 691 start_addr = ((2 * sizeof(*sc)) 692 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 693 694 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 695 start_addr, sizeof(vpd)/2, 696 /*bytestream*/TRUE); 697 if (error == 0) 698 error = ahd_parse_vpddata(ahd, &vpd); 699 #ifdef AHD_DEBUG 700 printf("%s: VPD parsing %s\n", 701 ahd_name(ahd), 702 error == 0 ? "successful" : "failed"); 703 #endif 704 705 #ifdef AHD_DEBUG 706 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 707 #endif 708 709 /* Address is always in units of 16bit words */ 710 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 711 712 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 713 start_addr, sizeof(*sc)/2, 714 /*bytestream*/FALSE); 715 716 if (error != 0) { 717 #ifdef AHD_DEBUG 718 printf("Unable to read SEEPROM\n"); 719 #endif 720 have_seeprom = 0; 721 } else { 722 have_seeprom = ahd_verify_cksum(sc); 723 #ifdef AHD_DEBUG 724 if (have_seeprom == 0) 725 printf ("checksum error\n"); 726 else 727 printf ("done.\n"); 728 #endif 729 } 730 ahd_release_seeprom(ahd); 731 } 732 733 if (!have_seeprom) { 734 u_int nvram_scb; 735 736 /* 737 * Pull scratch ram settings and treat them as 738 * if they are the contents of an seeprom if 739 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 740 * in SCB 0xFF. We manually compose the data as 16bit 741 * values to avoid endian issues. 742 */ 743 ahd_set_scbptr(ahd, 0xFF); 744 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 745 if (nvram_scb != 0xFF 746 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 747 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 748 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 749 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 750 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 751 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 752 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 753 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 754 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 755 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 756 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 757 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 758 uint16_t *sc_data; 759 int i; 760 761 ahd_set_scbptr(ahd, nvram_scb); 762 sc_data = (uint16_t *)sc; 763 for (i = 0; i < 64; i += 2) 764 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 765 have_seeprom = ahd_verify_cksum(sc); 766 if (have_seeprom) 767 ahd->flags |= AHD_SCB_CONFIG_USED; 768 } 769 } 770 771 #ifdef AHD_DEBUG 772 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 773 uint16_t *sc_data; 774 int i; 775 776 printf("%s: Seeprom Contents:", ahd_name(ahd)); 777 sc_data = (uint16_t *)sc; 778 for (i = 0; i < (sizeof(*sc)); i += 2) 779 printf("\n\t0x%.4x", sc_data[i]); 780 printf("\n"); 781 } 782 #endif 783 784 if (!have_seeprom) { 785 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 786 ahd->flags |= AHD_USEDEFAULTS; 787 error = ahd_default_config(ahd); 788 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 789 free(ahd->seep_config, M_DEVBUF); 790 ahd->seep_config = NULL; 791 } else { 792 error = ahd_parse_cfgdata(ahd, sc); 793 adapter_control = sc->adapter_control; 794 } 795 if (error != 0) 796 return (error); 797 798 ahd_configure_termination(ahd, adapter_control); 799 800 return (0); 801 } 802 803 static void 804 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 805 { 806 int error; 807 u_int sxfrctl1; 808 uint8_t termctl; 809 uint32_t devconfig; 810 struct ahd_pci_busdata *bd = ahd->bus_data; 811 812 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 813 devconfig &= ~STPWLEVEL; 814 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 815 devconfig |= STPWLEVEL; 816 #ifdef AHD_DEBUG 817 printf("%s: STPWLEVEL is %s\n", 818 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 819 #endif 820 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 821 822 /* Make sure current sensing is off. */ 823 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 824 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 825 } 826 827 /* 828 * Read to sense. Write to set. 829 */ 830 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 831 if ((adapter_control & CFAUTOTERM) == 0) { 832 if (bootverbose) 833 printf("%s: Manual Primary Termination\n", 834 ahd_name(ahd)); 835 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 836 if ((adapter_control & CFSTERM) != 0) 837 termctl |= FLX_TERMCTL_ENPRILOW; 838 if ((adapter_control & CFWSTERM) != 0) 839 termctl |= FLX_TERMCTL_ENPRIHIGH; 840 } else if (error != 0) { 841 if (bootverbose) 842 printf("%s: Primary Auto-Term Sensing failed! " 843 "Using Defaults.\n", ahd_name(ahd)); 844 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 845 } 846 847 if ((adapter_control & CFSEAUTOTERM) == 0) { 848 if (bootverbose) 849 printf("%s: Manual Secondary Termination\n", 850 ahd_name(ahd)); 851 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 852 if ((adapter_control & CFSELOWTERM) != 0) 853 termctl |= FLX_TERMCTL_ENSECLOW; 854 if ((adapter_control & CFSEHIGHTERM) != 0) 855 termctl |= FLX_TERMCTL_ENSECHIGH; 856 } else if (error != 0) { 857 if (bootverbose) 858 printf("%s: Secondary Auto-Term Sensing failed! " 859 "Using Defaults.\n", ahd_name(ahd)); 860 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 861 } 862 863 /* 864 * Now set the termination based on what we found. 865 */ 866 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 867 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 868 ahd->flags |= AHD_TERM_ENB_A; 869 sxfrctl1 |= STPWEN; 870 } 871 /* Must set the latch once in order to be effective. */ 872 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 873 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 874 875 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 876 if (error != 0) { 877 aprint_error("%s: Unable to set termination settings!\n", 878 ahd_name(ahd)); 879 } else { 880 if (bootverbose) { 881 printf("%s: Primary High byte termination %sabled\n", 882 ahd_name(ahd), 883 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 884 885 printf("%s: Primary Low byte termination %sabled\n", 886 ahd_name(ahd), 887 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 888 889 printf("%s: Secondary High byte termination %sabled\n", 890 ahd_name(ahd), 891 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 892 893 printf("%s: Secondary Low byte termination %sabled\n", 894 ahd_name(ahd), 895 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 896 } 897 } 898 return; 899 } 900 901 #define DPE 0x80 902 #define SSE 0x40 903 #define RMA 0x20 904 #define RTA 0x10 905 #define STA 0x08 906 #define DPR 0x01 907 908 static const char *split_status_source[] = 909 { 910 "DFF0", 911 "DFF1", 912 "OVLY", 913 "CMC", 914 }; 915 916 static const char *pci_status_source[] = 917 { 918 "DFF0", 919 "DFF1", 920 "SG", 921 "CMC", 922 "OVLY", 923 "NONE", 924 "MSI", 925 "TARG" 926 }; 927 928 static const char *split_status_strings[] = 929 { 930 "%s: Received split response in %s.\n", 931 "%s: Received split completion error message in %s\n", 932 "%s: Receive overrun in %s\n", 933 "%s: Count not complete in %s\n", 934 "%s: Split completion data bucket in %s\n", 935 "%s: Split completion address error in %s\n", 936 "%s: Split completion byte count error in %s\n", 937 "%s: Signaled Target-abort to early terminate a split in %s\n" 938 }; 939 940 static const char *pci_status_strings[] = 941 { 942 "%s: Data Parity Error has been reported via PERR# in %s\n", 943 "%s: Target initial wait state error in %s\n", 944 "%s: Split completion read data parity error in %s\n", 945 "%s: Split completion address attribute parity error in %s\n", 946 "%s: Received a Target Abort in %s\n", 947 "%s: Received a Master Abort in %s\n", 948 "%s: Signal System Error Detected in %s\n", 949 "%s: Address or Write Phase Parity Error Detected in %s.\n" 950 }; 951 952 static int 953 ahd_pci_intr(struct ahd_softc *ahd) 954 { 955 uint8_t pci_status[8]; 956 ahd_mode_state saved_modes; 957 u_int pci_status1; 958 u_int intstat; 959 u_int i; 960 u_int reg; 961 struct ahd_pci_busdata *bd = ahd->bus_data; 962 963 intstat = ahd_inb(ahd, INTSTAT); 964 965 if ((intstat & SPLTINT) != 0) 966 ahd_pci_split_intr(ahd, intstat); 967 968 if ((intstat & PCIINT) == 0) 969 return 0; 970 971 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 972 saved_modes = ahd_save_modes(ahd); 973 ahd_dump_card_state(ahd); 974 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 975 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 976 977 if (i == 5) 978 continue; 979 pci_status[i] = ahd_inb(ahd, reg); 980 /* Clear latched errors. So our interrupt deasserts. */ 981 ahd_outb(ahd, reg, pci_status[i]); 982 } 983 984 for (i = 0; i < 8; i++) { 985 u_int bit; 986 987 if (i == 5) 988 continue; 989 990 for (bit = 0; bit < 8; bit++) { 991 992 if ((pci_status[i] & (0x1 << bit)) != 0) { 993 static const char *s; 994 995 s = pci_status_strings[bit]; 996 if (i == 7/*TARG*/ && bit == 3) 997 s = "%s: Signaled Target Abort\n"; 998 printf(s, ahd_name(ahd), pci_status_source[i]); 999 } 1000 } 1001 } 1002 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1003 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1004 1005 ahd_restore_modes(ahd, saved_modes); 1006 ahd_outb(ahd, CLRINT, CLRPCIINT); 1007 ahd_unpause(ahd); 1008 1009 return 1; 1010 } 1011 1012 static void 1013 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1014 { 1015 uint8_t split_status[4]; 1016 uint8_t split_status1[4]; 1017 uint8_t sg_split_status[2]; 1018 uint8_t sg_split_status1[2]; 1019 ahd_mode_state saved_modes; 1020 u_int i; 1021 pcireg_t pcix_status; 1022 struct ahd_pci_busdata *bd = ahd->bus_data; 1023 1024 /* 1025 * Check for splits in all modes. Modes 0 and 1 1026 * additionally have SG engine splits to look at. 1027 */ 1028 pcix_status = pci_conf_read(bd->pc, bd->tag, 1029 bd->pcix_off + PCI_PCIX_STATUS); 1030 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1031 ahd_name(ahd), pcix_status); 1032 1033 saved_modes = ahd_save_modes(ahd); 1034 for (i = 0; i < 4; i++) { 1035 ahd_set_modes(ahd, i, i); 1036 1037 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1038 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1039 /* Clear latched errors. So our interrupt deasserts. */ 1040 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1041 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1042 if (i > 1) 1043 continue; 1044 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1045 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1046 /* Clear latched errors. So our interrupt deasserts. */ 1047 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1048 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1049 } 1050 1051 for (i = 0; i < 4; i++) { 1052 u_int bit; 1053 1054 for (bit = 0; bit < 8; bit++) { 1055 1056 if ((split_status[i] & (0x1 << bit)) != 0) { 1057 static const char *s; 1058 1059 s = split_status_strings[bit]; 1060 printf(s, ahd_name(ahd), 1061 split_status_source[i]); 1062 } 1063 1064 if (i > 0) 1065 continue; 1066 1067 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1068 static const char *s; 1069 1070 s = split_status_strings[bit]; 1071 printf(s, ahd_name(ahd), "SG"); 1072 } 1073 } 1074 } 1075 /* 1076 * Clear PCI-X status bits. 1077 */ 1078 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1079 pcix_status); 1080 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1081 ahd_restore_modes(ahd, saved_modes); 1082 } 1083 1084 static int 1085 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1086 { 1087 1088 ahd->chip = AHD_AIC7901; 1089 ahd->features = AHD_AIC7901_FE; 1090 return (ahd_aic790X_setup(ahd, pa)); 1091 } 1092 1093 static int 1094 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1095 { 1096 1097 ahd->chip = AHD_AIC7901A; 1098 ahd->features = AHD_AIC7901A_FE; 1099 return (ahd_aic790X_setup(ahd, pa)); 1100 } 1101 1102 static int 1103 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1104 { 1105 1106 ahd->chip = AHD_AIC7902; 1107 ahd->features = AHD_AIC7902_FE; 1108 return (ahd_aic790X_setup(ahd, pa)); 1109 } 1110 1111 static int 1112 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1113 { 1114 u_int rev; 1115 1116 rev = PCI_REVISION(pa->pa_class); 1117 #ifdef AHD_DEBUG 1118 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1119 #endif 1120 if (rev < ID_AIC7902_PCI_REV_A4) { 1121 aprint_error("%s: Unable to attach to " 1122 "unsupported chip revision %d\n", ahd_name(ahd), rev); 1123 pci_conf_write(pa->pa_pc, pa->pa_tag, 1124 PCI_COMMAND_STATUS_REG, 0); 1125 return (ENXIO); 1126 } 1127 1128 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1129 if (rev < ID_AIC7902_PCI_REV_B0) { 1130 /* 1131 * Enable A series workarounds. 1132 */ 1133 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1134 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1135 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1136 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1137 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1138 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1139 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1140 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1141 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1142 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1143 | AHD_FAINT_LED_BUG; 1144 1145 1146 /* 1147 * IO Cell parameter setup. 1148 */ 1149 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1150 1151 if ((ahd->flags & AHD_HP_BOARD) == 0) 1152 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1153 } else { 1154 u_int devconfig1; 1155 1156 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1157 | AHD_NEW_DFCNTRL_OPTS; 1158 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1159 1160 /* 1161 * Some issues have been resolved in the 7901B. 1162 */ 1163 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1164 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1165 1166 /* 1167 * IO Cell parameter setup. 1168 */ 1169 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1170 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1171 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1172 1173 /* 1174 * Set the PREQDIS bit for H2B which disables some workaround 1175 * that doesn't work on regular PCI busses. 1176 * XXX - Find out exactly what this does from the hardware 1177 * folks! 1178 */ 1179 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1180 pci_conf_write(pa->pa_pc, pa->pa_tag, 1181 DEVCONFIG1, devconfig1|PREQDIS); 1182 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1183 } 1184 1185 return (0); 1186 } 1187