1 /* $NetBSD: ahd_pci.c,v 1.3 2003/07/14 15:47:23 lukem Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * //depot/aic7xxx/aic7xxx/aic79xx_pci.c#67 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.9 2003/03/06 23:58:34 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.3 2003/07/14 15:47:23 lukem Exp $"); 53 54 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 55 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 56 57 #include <dev/ic/aic79xx_osm.h> 58 #include <dev/ic/aic79xx_inline.h> 59 60 static __inline uint64_t 61 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 75 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 76 77 #define ID_AIC7901 0x800F9005FFFF9005ull 78 #define ID_AIC7901A 0x801E9005FFFF9005ull 79 #define ID_AIC7901A_IROC 0x809E9005FFFF9005ull 80 #define ID_AHA_29320A 0x8000900500609005ull 81 #define ID_AHA_29320LP 0x8014900500449005ull 82 #define ID_AHA_29320LP_IROC 0x8094900500449005ull 83 84 #define ID_AIC7902 0x801F9005FFFF9005ull 85 #define ID_AIC7902_IROC 0x809F9005FFFF9005ull 86 #define ID_AIC7902_B 0x801D9005FFFF9005ull 87 #define ID_AIC7902_B_IROC 0x809D9005FFFF9005ull 88 #define ID_AHA_39320 0x8010900500409005ull 89 #define ID_AHA_39320A 0x8016900500409005ull 90 #define ID_AHA_39320D 0x8011900500419005ull 91 #define ID_AHA_39320D_B 0x801C900500419005ull 92 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 93 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 94 #define ID_AHA_29320 0x8012900500429005ull 95 #define ID_AHA_29320B 0x8013900500439005ull 96 #define ID_AIC7902_PCI_REV_A4 0x3 97 #define ID_AIC7902_PCI_REV_B0 0x10 98 #define SUBID_HP 0x0E11 99 100 #define DEVID_9005_TYPE(id) ((id) & 0xF) 101 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 102 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 103 #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */ 104 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 105 106 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 107 108 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 109 110 #define SUBID_9005_TYPE(id) ((id) & 0xF) 111 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 112 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 113 114 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 115 116 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 117 118 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 119 #define SUBID_9005_SEEPTYPE_NONE 0x0 120 #define SUBID_9005_SEEPTYPE_4K 0x1 121 122 static ahd_device_setup_t ahd_aic7901A_setup; 123 static ahd_device_setup_t ahd_aic7902_setup; 124 125 struct ahd_pci_identity ahd_pci_ident_table [] = 126 { 127 /* aic7901A based controllers */ 128 { 129 ID_AHA_29320LP, 130 ID_ALL_MASK, 131 "Adaptec 29320LP Ultra320 SCSI adapter", 132 ahd_aic7901A_setup 133 }, 134 { 135 ID_AHA_29320A, 136 ID_ALL_MASK, 137 "Adaptec 29320A Ultra320 SCSI adapter", 138 ahd_aic7901A_setup 139 }, 140 /* aic7902 based controllers */ 141 { 142 ID_AHA_39320, 143 ID_ALL_MASK, 144 "Adaptec 39320 Ultra320 SCSI adapter", 145 ahd_aic7902_setup 146 }, 147 { 148 ID_AHA_39320A, 149 ID_ALL_MASK, 150 "Adaptec 39320A Ultra320 SCSI adapter", 151 ahd_aic7902_setup 152 }, 153 { 154 ID_AHA_39320D, 155 ID_ALL_MASK, 156 "Adaptec 39320D Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_39320D_HP, 161 ID_ALL_MASK, 162 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320D_B, 167 ID_ALL_MASK, 168 "Adaptec 39320D Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_39320D_B_HP, 173 ID_ALL_MASK, 174 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_29320, 179 ID_ALL_MASK, 180 "Adaptec 29320 Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 { 184 ID_AHA_29320B, 185 ID_ALL_MASK, 186 "Adaptec 29320B Ultra320 SCSI adapter", 187 ahd_aic7902_setup 188 }, 189 /* Generic chip probes for devices we don't know 'exactly' */ 190 { 191 ID_AIC7901A & ID_DEV_VENDOR_MASK, 192 ID_DEV_VENDOR_MASK, 193 "Adaptec AIC7901A Ultra320 SCSI adapter", 194 ahd_aic7901A_setup 195 }, 196 { 197 ID_AIC7902 & ID_9005_GENERIC_MASK, 198 ID_9005_GENERIC_MASK, 199 "Adaptec AIC7902 Ultra320 SCSI adapter", 200 ahd_aic7902_setup 201 } 202 }; 203 204 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 205 206 #define DEVCONFIG 0x40 207 #define PCIXINITPAT 0x0000E000ul 208 #define PCIXINIT_PCI33_66 0x0000E000ul 209 #define PCIXINIT_PCIX50_66 0x0000C000ul 210 #define PCIXINIT_PCIX66_100 0x0000A000ul 211 #define PCIXINIT_PCIX100_133 0x00008000ul 212 #define PCI_BUS_MODES_INDEX(devconfig) \ 213 (((devconfig) & PCIXINITPAT) >> 13) 214 215 static const char *pci_bus_modes[] = 216 { 217 "PCI bus mode unknown", 218 "PCI bus mode unknown", 219 "PCI bus mode unknown", 220 "PCI bus mode unknown", 221 "PCI-X 101-133Mhz", 222 "PCI-X 67-100Mhz", 223 "PCI-X 50-66Mhz", 224 "PCI 33 or 66Mhz" 225 }; 226 227 #define TESTMODE 0x00000800ul 228 #define IRDY_RST 0x00000200ul 229 #define FRAME_RST 0x00000100ul 230 #define PCI64BIT 0x00000080ul 231 #define MRDCEN 0x00000040ul 232 #define ENDIANSEL 0x00000020ul 233 #define MIXQWENDIANEN 0x00000008ul 234 #define DACEN 0x00000004ul 235 #define STPWLEVEL 0x00000002ul 236 #define QWENDIANSEL 0x00000001ul 237 238 #define DEVCONFIG1 0x44 239 #define PREQDIS 0x01 240 241 #define LATTIME 0x0000ff00ul 242 243 int ahd_pci_probe __P((struct device *, struct cfdata *, void *)); 244 void ahd_pci_attach __P((struct device *, struct device *, void *)); 245 246 CFATTACH_DECL(ahd_pci, sizeof(struct ahd_softc), 247 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 248 249 static int ahd_check_extport(struct ahd_softc *ahd); 250 static void ahd_configure_termination(struct ahd_softc *ahd, 251 u_int adapter_control); 252 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 253 254 const struct ahd_pci_identity * 255 ahd_find_pci_device(id, subid) 256 pcireg_t id, subid; 257 { 258 u_int64_t full_id; 259 const struct ahd_pci_identity *entry; 260 u_int i; 261 262 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 263 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 264 265 for (i = 0; i < ahd_num_pci_devs; i++) { 266 entry = &ahd_pci_ident_table[i]; 267 if (entry->full_id == (full_id & entry->id_mask)) 268 return (entry); 269 } 270 return (NULL); 271 } 272 273 int 274 ahd_pci_probe(parent, match, aux) 275 struct device *parent; 276 struct cfdata *match; 277 void *aux; 278 { 279 struct pci_attach_args *pa = aux; 280 const struct ahd_pci_identity *entry; 281 pcireg_t subid; 282 283 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 284 entry = ahd_find_pci_device(pa->pa_id, subid); 285 return entry != NULL ? 1 : 0; 286 } 287 288 void 289 ahd_pci_attach(parent, self, aux) 290 struct device *parent, *self; 291 void *aux; 292 { 293 struct pci_attach_args *pa = aux; 294 struct ahd_softc *ahd = (void *)self; 295 296 const struct ahd_pci_identity *entry; 297 298 uint32_t devconfig; 299 pcireg_t command; 300 int error; 301 pcireg_t subid; 302 uint16_t subvendor; 303 int pci_pwrmgmt_cap_reg; 304 int pci_pwrmgmt_csr_reg; 305 pcireg_t reg; 306 int ioh_valid, ioh2_valid, memh_valid; 307 pcireg_t memtype; 308 pci_intr_handle_t ih; 309 const char *intrstr; 310 struct ahd_pci_busdata *bd; 311 312 ahd_set_name(ahd, ahd->sc_dev.dv_xname); 313 ahd->parent_dmat = pa->pa_dmat; 314 315 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 316 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 317 entry = ahd_find_pci_device(pa->pa_id, subid); 318 if (entry == NULL) 319 return; 320 321 /* Keep information about the PCI bus */ 322 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 323 if (bd == NULL) { 324 printf("%s: unable to allocate bus-specific data\n", ahd_name(ahd)); 325 return; 326 } 327 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 328 329 bd->pc = pa->pa_pc; 330 bd->tag = pa->pa_tag; 331 bd->func = pa->pa_function; 332 bd->dev = pa->pa_device; 333 334 ahd->bus_data = bd; 335 336 ahd->description = entry->name; 337 338 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 339 M_DEVBUF, M_NOWAIT); 340 if (ahd->seep_config == NULL) { 341 printf("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 342 return; 343 } 344 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 345 346 LIST_INIT(&ahd->pending_scbs); 347 ahd_timer_init(&ahd->reset_timer); 348 ahd_timer_init(&ahd->stat_timer); 349 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 350 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 351 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 352 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 353 ahd->int_coalescing_stop_threshold = AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 354 355 if (ahd_platform_alloc(ahd, NULL) != 0) { 356 ahd_free(ahd); 357 return; 358 } 359 360 /* 361 * Record if this is an HP board. 362 */ 363 subvendor = PCI_VENDOR(subid); 364 if (subvendor == SUBID_HP) 365 ahd->flags |= AHD_HP_BOARD; 366 367 error = entry->setup(ahd, pa); 368 if (error != 0) 369 return; 370 371 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 372 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66 || 373 (devconfig & PCIXINITPAT) == PCIXINIT_PCIX66_100) { 374 ahd->chip |= AHD_PCI; 375 /* Disable PCIX workarounds when running in PCI mode. */ 376 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 377 } else { 378 ahd->chip |= AHD_PCIX; 379 } 380 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 381 382 memh_valid = ioh_valid = ioh2_valid = 0; 383 384 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 385 &bd->pcix_off, NULL)) { 386 if (ahd->chip & AHD_PCIX) 387 printf("%s: warning: can't find PCI-X capability\n", 388 ahd->sc_dev.dv_xname); 389 ahd->chip &= ~AHD_PCIX; 390 ahd->chip |= AHD_PCI; 391 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 392 } 393 394 /* 395 * Map PCI Registers 396 */ 397 if ((command & (PCI_COMMAND_MEM_ENABLE)) != 0) { 398 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHD_PCI_MEMADDR); 399 switch (memtype) { 400 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 401 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 402 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 403 memtype, 0, &ahd->tags[0], 404 &ahd->bshs[0], NULL, NULL) == 0); 405 406 ahd->tags[1] = ahd->tags[0]; 407 408 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 409 /*offset*/0x100, 410 /*size*/0x100, 411 &ahd->bshs[1]); 412 break; 413 default: 414 printf("%s: unable to map memory registers\n", ahd_name(ahd)); 415 return; 416 } 417 418 if (memh_valid) { 419 command &= ~PCI_COMMAND_IO_ENABLE; 420 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 421 } 422 #ifdef AHD_DEBUG 423 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, shs0 0x%lx, shs1 0x%lx\n", 424 ahd_name(ahd), ahd->tags[0], ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 425 #endif 426 } 427 428 if ((command & (PCI_COMMAND_IO_ENABLE)) != 0 && 429 !(ahd->bugs & AHD_PCIX_MMAPIO_BUG)) { 430 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHD_PCI_IOADDR); 431 432 /* First BAR */ 433 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 434 memtype, 0, &ahd->tags[0], 435 &ahd->bshs[0], NULL, NULL) == 0); 436 437 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHD_PCI_IOADDR1); 438 439 /* 2nd BAR */ 440 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 441 memtype, 0, &ahd->tags[1], 442 &ahd->bshs[1], NULL, NULL) == 0); 443 444 if (ioh_valid && ioh2_valid) { 445 command &= ~PCI_COMMAND_MEM_ENABLE; 446 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 447 } 448 #ifdef AHD_DEBUG 449 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, shs0 0x%lx, shs1 0x%lx\n", 450 ahd_name(ahd), ahd->tags[0], ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 451 #endif 452 453 } 454 455 if ((memh_valid == 0) && ((ioh_valid == 0) || (ioh2_valid == 0))) { 456 printf("%s: unable to map memory registers\n", ahd_name(ahd)); 457 return; 458 } 459 460 printf("\n"); 461 462 /* 463 * Set Power State D0. 464 */ 465 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 466 &pci_pwrmgmt_cap_reg, 0)) { 467 468 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 469 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 470 pci_pwrmgmt_csr_reg); 471 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 472 pci_conf_write(pa->pa_pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 473 (reg & ~PCI_PMCSR_STATE_MASK) | 474 PCI_PMCSR_STATE_D0); 475 } 476 } 477 478 /* 479 * Should we bother disabling 39Bit addressing 480 * based on installed memory? 481 */ 482 if (sizeof(bus_addr_t) > 4) 483 ahd->flags |= AHD_39BIT_ADDRESSING; 484 485 /* 486 * If we need to support high memory, enable dual 487 * address cycles. This bit must be set to enable 488 * high address bit generation even if we are on a 489 * 64bit bus (PCI64BIT set in devconfig). 490 */ 491 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 492 uint32_t devconfig; 493 494 printf("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 495 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 496 devconfig |= DACEN; 497 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 498 } 499 500 /* Ensure busmastering is enabled */ 501 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 502 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 503 reg | PCI_COMMAND_MASTER_ENABLE); 504 505 ahd_softc_init(ahd); 506 507 /* 508 * Map the interrupt routines 509 */ 510 ahd->bus_intr = ahd_pci_intr; 511 512 if (pci_intr_map(pa, &ih)) { 513 printf("%s: couldn't map interrupt\n", ahd_name(ahd)); 514 ahd_free(ahd); 515 return; 516 } 517 intrstr = pci_intr_string(pa->pa_pc, ih); 518 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 519 if (ahd->ih == NULL) { 520 printf("%s: couldn't establish interrupt", 521 ahd_name(ahd)); 522 if (intrstr != NULL) 523 printf(" at %s", intrstr); 524 printf("\n"); 525 ahd_free(ahd); 526 return; 527 } 528 if (intrstr != NULL) 529 printf("%s: interrupting at %s\n", ahd_name(ahd), 530 intrstr); 531 532 /* Get the size of the cache */ 533 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 534 ahd->pci_cachesize *= 4; 535 536 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 537 /* See if we have a SEEPROM and perform auto-term */ 538 error = ahd_check_extport(ahd); 539 if (error != 0) 540 return; 541 542 /* Core initialization */ 543 error = ahd_init(ahd); 544 if (error != 0) 545 return; 546 547 /* 548 * Link this softc in with all other ahd instances. 549 */ 550 ahd_attach(ahd); 551 552 return; 553 } 554 555 556 /* 557 * Check the external port logic for a serial eeprom 558 * and termination/cable detection contrls. 559 */ 560 static int 561 ahd_check_extport(struct ahd_softc *ahd) 562 { 563 struct seeprom_config *sc; 564 u_int adapter_control; 565 int have_seeprom; 566 int error; 567 568 sc = ahd->seep_config; 569 have_seeprom = ahd_acquire_seeprom(ahd); 570 if (have_seeprom) { 571 u_int start_addr; 572 #ifdef AHD_DEBUG 573 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 574 #endif 575 576 /* Address is always in units of 16bit words */ 577 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 578 579 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 580 start_addr, sizeof(*sc)/2); 581 582 if (error != 0) { 583 #ifdef AHD_DEBUG 584 printf("Unable to read SEEPROM\n"); 585 #endif 586 have_seeprom = 0; 587 } else { 588 have_seeprom = ahd_verify_cksum(sc); 589 #ifdef AHD_DEBUG 590 if (have_seeprom == 0) 591 printf ("checksum error\n"); 592 else 593 printf ("done.\n"); 594 #endif 595 } 596 ahd_release_seeprom(ahd); 597 } 598 599 if (!have_seeprom) { 600 u_int nvram_scb; 601 602 /* 603 * Pull scratch ram settings and treat them as 604 * if they are the contents of an seeprom if 605 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 606 * in SCB 0xFF. We manually compose the data as 16bit 607 * values to avoid endian issues. 608 */ 609 ahd_set_scbptr(ahd, 0xFF); 610 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 611 if (nvram_scb != 0xFF 612 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 613 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 614 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 615 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 616 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 617 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 618 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 619 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 620 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 621 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 622 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 623 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 624 uint16_t *sc_data; 625 int i; 626 627 ahd_set_scbptr(ahd, nvram_scb); 628 sc_data = (uint16_t *)sc; 629 for (i = 0; i < 64; i += 2) 630 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 631 have_seeprom = ahd_verify_cksum(sc); 632 if (have_seeprom) 633 ahd->flags |= AHD_SCB_CONFIG_USED; 634 } 635 } 636 637 #ifdef AHD_DEBUG 638 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 639 uint8_t *sc_data; 640 int i; 641 642 printf("%s: Seeprom Contents:", ahd_name(ahd)); 643 sc_data = (uint8_t *)sc; 644 for (i = 0; i < (sizeof(*sc)); i += 2) 645 printf("\n\t0x%.4x", 646 sc_data[i] | (sc_data[i+1] << 8)); 647 printf("\n"); 648 } 649 #endif 650 651 if (!have_seeprom) { 652 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 653 ahd->flags |= AHD_USEDEFAULTS; 654 error = ahd_default_config(ahd); 655 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 656 free(ahd->seep_config, M_DEVBUF); 657 ahd->seep_config = NULL; 658 } else { 659 error = ahd_parse_cfgdata(ahd, sc); 660 adapter_control = sc->adapter_control; 661 } 662 if (error != 0) 663 return (error); 664 665 ahd_configure_termination(ahd, adapter_control); 666 667 return (0); 668 } 669 670 static void 671 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 672 { 673 int error; 674 u_int sxfrctl1; 675 uint8_t termctl; 676 uint32_t devconfig; 677 struct ahd_pci_busdata *bd = ahd->bus_data; 678 679 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 680 devconfig &= ~STPWLEVEL; 681 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 682 devconfig |= STPWLEVEL; 683 #ifdef AHD_DEBUG 684 printf("%s: STPWLEVEL is %s\n", 685 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 686 #endif 687 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 688 689 /* Make sure current sensing is off. */ 690 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 691 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 692 } 693 694 /* 695 * Read to sense. Write to set. 696 */ 697 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 698 if ((adapter_control & CFAUTOTERM) == 0) { 699 printf("%s: Manual Primary Termination\n", 700 ahd_name(ahd)); 701 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 702 if ((adapter_control & CFSTERM) != 0) 703 termctl |= FLX_TERMCTL_ENPRILOW; 704 if ((adapter_control & CFWSTERM) != 0) 705 termctl |= FLX_TERMCTL_ENPRIHIGH; 706 } else if (error != 0) { 707 printf("%s: Primary Auto-Term Sensing failed! " 708 "Using Defaults.\n", ahd_name(ahd)); 709 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 710 } 711 712 if ((adapter_control & CFSEAUTOTERM) == 0) { 713 printf("%s: Manual Secondary Termination\n", 714 ahd_name(ahd)); 715 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 716 if ((adapter_control & CFSELOWTERM) != 0) 717 termctl |= FLX_TERMCTL_ENSECLOW; 718 if ((adapter_control & CFSEHIGHTERM) != 0) 719 termctl |= FLX_TERMCTL_ENSECHIGH; 720 } else if (error != 0) { 721 printf("%s: Secondary Auto-Term Sensing failed! " 722 "Using Defaults.\n", ahd_name(ahd)); 723 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 724 } 725 726 /* 727 * Now set the termination based on what we found. 728 */ 729 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 730 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 731 ahd->flags |= AHD_TERM_ENB_A; 732 sxfrctl1 |= STPWEN; 733 } 734 /* Must set the latch once in order to be effective. */ 735 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 736 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 737 738 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 739 if (error != 0) { 740 printf("%s: Unable to set termination settings!\n", 741 ahd_name(ahd)); 742 } else { 743 printf("%s: Primary High byte termination %sabled\n", 744 ahd_name(ahd), 745 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 746 747 printf("%s: Primary Low byte termination %sabled\n", 748 ahd_name(ahd), 749 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 750 751 printf("%s: Secondary High byte termination %sabled\n", 752 ahd_name(ahd), 753 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 754 755 printf("%s: Secondary Low byte termination %sabled\n", 756 ahd_name(ahd), 757 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 758 } 759 return; 760 } 761 762 #define DPE 0x80 763 #define SSE 0x40 764 #define RMA 0x20 765 #define RTA 0x10 766 #define STA 0x08 767 #define DPR 0x01 768 769 static const char *split_status_source[] = 770 { 771 "DFF0", 772 "DFF1", 773 "OVLY", 774 "CMC", 775 }; 776 777 static const char *pci_status_source[] = 778 { 779 "DFF0", 780 "DFF1", 781 "SG", 782 "CMC", 783 "OVLY", 784 "NONE", 785 "MSI", 786 "TARG" 787 }; 788 789 static const char *split_status_strings[] = 790 { 791 "%s: Received split response in %s.\n", 792 "%s: Received split completion error message in %s\n", 793 "%s: Receive overrun in %s\n", 794 "%s: Count not complete in %s\n", 795 "%s: Split completion data bucket in %s\n", 796 "%s: Split completion address error in %s\n", 797 "%s: Split completion byte count error in %s\n", 798 "%s: Signaled Target-abort to early terminate a split in %s\n" 799 }; 800 801 static const char *pci_status_strings[] = 802 { 803 "%s: Data Parity Error has been reported via PERR# in %s\n", 804 "%s: Target initial wait state error in %s\n", 805 "%s: Split completion read data parity error in %s\n", 806 "%s: Split completion address attribute parity error in %s\n", 807 "%s: Received a Target Abort in %s\n", 808 "%s: Received a Master Abort in %s\n", 809 "%s: Signal System Error Detected in %s\n", 810 "%s: Address or Write Phase Parity Error Detected in %s.\n" 811 }; 812 813 int 814 ahd_pci_intr(struct ahd_softc *ahd) 815 { 816 uint8_t pci_status[8]; 817 ahd_mode_state saved_modes; 818 u_int pci_status1; 819 u_int intstat; 820 u_int i; 821 u_int reg; 822 struct ahd_pci_busdata *bd = ahd->bus_data; 823 824 intstat = ahd_inb(ahd, INTSTAT); 825 826 if ((intstat & SPLTINT) != 0) 827 ahd_pci_split_intr(ahd, intstat); 828 829 if ((intstat & PCIINT) == 0) 830 return 0; 831 832 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 833 saved_modes = ahd_save_modes(ahd); 834 ahd_dump_card_state(ahd); 835 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 836 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 837 838 if (i == 5) 839 continue; 840 pci_status[i] = ahd_inb(ahd, reg); 841 /* Clear latched errors. So our interrupt deasserts. */ 842 ahd_outb(ahd, reg, pci_status[i]); 843 } 844 845 for (i = 0; i < 8; i++) { 846 u_int bit; 847 848 if (i == 5) 849 continue; 850 851 for (bit = 0; bit < 8; bit++) { 852 853 if ((pci_status[i] & (0x1 << bit)) != 0) { 854 static const char *s; 855 856 s = pci_status_strings[bit]; 857 if (i == 7/*TARG*/ && bit == 3) 858 s = "%s: Signaled Target Abort\n"; 859 printf(s, ahd_name(ahd), pci_status_source[i]); 860 } 861 } 862 } 863 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 864 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 865 866 ahd_restore_modes(ahd, saved_modes); 867 ahd_outb(ahd, CLRINT, CLRPCIINT); 868 ahd_unpause(ahd); 869 870 return 1; 871 } 872 873 static void 874 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 875 { 876 uint8_t split_status[4]; 877 uint8_t split_status1[4]; 878 uint8_t sg_split_status[2]; 879 uint8_t sg_split_status1[2]; 880 ahd_mode_state saved_modes; 881 u_int i; 882 pcireg_t pcix_status; 883 struct ahd_pci_busdata *bd = ahd->bus_data; 884 885 /* 886 * Check for splits in all modes. Modes 0 and 1 887 * additionally have SG engine splits to look at. 888 */ 889 pcix_status = pci_conf_read(bd->pc, bd->tag, 890 bd->pcix_off + PCI_PCIX_STATUS); 891 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 892 ahd_name(ahd), pcix_status); 893 894 saved_modes = ahd_save_modes(ahd); 895 for (i = 0; i < 4; i++) { 896 ahd_set_modes(ahd, i, i); 897 898 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 899 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 900 /* Clear latched errors. So our interrupt deasserts. */ 901 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 902 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 903 if (i != 0) 904 continue; 905 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 906 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 907 /* Clear latched errors. So our interrupt deasserts. */ 908 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 909 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 910 } 911 912 for (i = 0; i < 4; i++) { 913 u_int bit; 914 915 for (bit = 0; bit < 8; bit++) { 916 917 if ((split_status[i] & (0x1 << bit)) != 0) { 918 static const char *s; 919 920 s = split_status_strings[bit]; 921 printf(s, ahd_name(ahd), 922 split_status_source[i]); 923 } 924 925 if (i != 0) 926 continue; 927 928 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 929 static const char *s; 930 931 s = split_status_strings[bit]; 932 printf(s, ahd_name(ahd), "SG"); 933 } 934 } 935 } 936 /* 937 * Clear PCI-X status bits. 938 */ 939 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 940 pcix_status); 941 ahd_outb(ahd, CLRINT, CLRSPLTINT); 942 ahd_restore_modes(ahd, saved_modes); 943 } 944 945 static int 946 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 947 { 948 int error; 949 950 error = ahd_aic7902_setup(ahd, pa); 951 if (error != 0) 952 return (error); 953 ahd->chip = AHD_AIC7901A; 954 return (0); 955 } 956 957 static int 958 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 959 { 960 u_int rev; 961 962 rev = PCI_REVISION(pa->pa_class); 963 #ifdef AHD_DEBUG 964 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 965 #endif 966 if (rev < ID_AIC7902_PCI_REV_A4) { 967 printf("%s: Unable to attach to unsupported chip revision %d\n", 968 ahd_name(ahd), rev); 969 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 970 return (ENXIO); 971 } 972 973 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 974 ahd->chip = AHD_AIC7902; 975 ahd->features = AHD_AIC7902_FE; 976 if (rev < ID_AIC7902_PCI_REV_B0) { 977 /* 978 * Enable A series workarounds. 979 */ 980 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 981 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 982 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 983 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 984 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 985 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 986 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 987 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 988 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 989 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG; 990 991 992 /* 993 * IO Cell paramter setup. 994 */ 995 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 996 997 if ((ahd->flags & AHD_HP_BOARD) == 0) 998 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 999 } else { 1000 u_int devconfig1; 1001 1002 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1003 | AHD_NEW_DFCNTRL_OPTS; 1004 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_ABORT_LQI_BUG 1005 | AHD_INTCOLLISION_BUG|AHD_EARLY_REQ_BUG; 1006 1007 /* 1008 * IO Cell paramter setup. 1009 */ 1010 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1011 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1012 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1013 1014 /* 1015 * Set the PREQDIS bit for H2B which disables some workaround 1016 * that doesn't work on regular PCI busses. 1017 * XXX - Find out exactly what this does from the hardware 1018 * folks! 1019 */ 1020 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1021 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1022 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1023 } 1024 1025 return (0); 1026 } 1027 1028