1 /* $NetBSD: ahd_pci.c,v 1.28 2009/05/06 09:25:14 cegger Exp $ */ 2 3 /* 4 * Product specific probe and attach routines for: 5 * aic7901 and aic7902 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $ 44 * 45 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.16 2003/06/28 04:39:49 gibbs Exp $ 46 */ 47 /* 48 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: ahd_pci.c,v 1.28 2009/05/06 09:25:14 cegger Exp $"); 53 54 #define AHD_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 55 #define AHD_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 56 57 #include <dev/ic/aic79xx_osm.h> 58 #include <dev/ic/aic79xx_inline.h> 59 60 static inline uint64_t 61 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 62 { 63 uint64_t id; 64 65 id = subvendor 66 | (subdevice << 16) 67 | ((uint64_t)vendor << 32) 68 | ((uint64_t)device << 48); 69 70 return (id); 71 } 72 73 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 74 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 75 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 76 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 77 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 78 79 #define ID_AIC7901 0x800F9005FFFF9005ull 80 #define ID_AHA_29320A 0x8000900500609005ull 81 #define ID_AHA_29320ALP 0x8017900500449005ull 82 83 #define ID_AIC7901A 0x801E9005FFFF9005ull 84 #define ID_AHA_29320LP 0x8014900500449005ull 85 86 #define ID_AIC7902 0x801F9005FFFF9005ull 87 #define ID_AIC7902_B 0x801D9005FFFF9005ull 88 #define ID_AHA_39320 0x8010900500409005ull 89 #define ID_AHA_29320 0x8012900500429005ull 90 #define ID_AHA_29320B 0x8013900500439005ull 91 #define ID_AHA_39320_B 0x8015900500409005ull 92 #define ID_AHA_39320A 0x8016900500409005ull 93 #define ID_AHA_39320D 0x8011900500419005ull 94 #define ID_AHA_39320D_B 0x801C900500419005ull 95 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 96 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 97 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 98 #define ID_AIC7902_PCI_REV_A4 0x3 99 #define ID_AIC7902_PCI_REV_B0 0x10 100 #define SUBID_HP 0x0E11 101 102 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 103 104 #define DEVID_9005_TYPE(id) ((id) & 0xF) 105 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 106 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 107 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 108 109 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 110 111 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 112 113 #define SUBID_9005_TYPE(id) ((id) & 0xF) 114 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 115 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 116 117 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 118 119 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 120 121 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 122 #define SUBID_9005_SEEPTYPE_NONE 0x0 123 #define SUBID_9005_SEEPTYPE_4K 0x1 124 125 static ahd_device_setup_t ahd_aic7901_setup; 126 static ahd_device_setup_t ahd_aic7901A_setup; 127 static ahd_device_setup_t ahd_aic7902_setup; 128 static ahd_device_setup_t ahd_aic790X_setup; 129 130 static struct ahd_pci_identity ahd_pci_ident_table [] = 131 { 132 /* aic7901 based controllers */ 133 { 134 ID_AHA_29320A, 135 ID_ALL_MASK, 136 "Adaptec 29320A Ultra320 SCSI adapter", 137 ahd_aic7901_setup 138 }, 139 { 140 ID_AHA_29320ALP, 141 ID_ALL_MASK, 142 "Adaptec 29320ALP Ultra320 SCSI adapter", 143 ahd_aic7901_setup 144 }, 145 /* aic7901A based controllers */ 146 { 147 ID_AHA_29320LP, 148 ID_ALL_MASK, 149 "Adaptec 29320LP Ultra320 SCSI adapter", 150 ahd_aic7901A_setup 151 }, 152 /* aic7902 based controllers */ 153 { 154 ID_AHA_39320, 155 ID_ALL_MASK, 156 "Adaptec 39320 Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_39320_B, 161 ID_ALL_MASK, 162 "Adaptec 39320 Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320_B_DELL, 167 ID_ALL_IROC_MASK, 168 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_39320A, 173 ID_ALL_MASK, 174 "Adaptec 39320A Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_39320D, 179 ID_ALL_MASK, 180 "Adaptec 39320D Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 { 184 ID_AHA_39320D_HP, 185 ID_ALL_MASK, 186 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 187 ahd_aic7902_setup 188 }, 189 { 190 ID_AHA_39320D_B, 191 ID_ALL_MASK, 192 "Adaptec 39320D Ultra320 SCSI adapter", 193 ahd_aic7902_setup 194 }, 195 { 196 ID_AHA_39320D_B_HP, 197 ID_ALL_MASK, 198 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 199 ahd_aic7902_setup 200 }, 201 /* Generic chip probes for devices we don't know 'exactly' */ 202 { 203 ID_AIC7901 & ID_9005_GENERIC_MASK, 204 ID_9005_GENERIC_MASK, 205 "Adaptec AIC7901 Ultra320 SCSI adapter", 206 ahd_aic7901_setup 207 }, 208 { 209 ID_AIC7901A & ID_DEV_VENDOR_MASK, 210 ID_DEV_VENDOR_MASK, 211 "Adaptec AIC7901A Ultra320 SCSI adapter", 212 ahd_aic7901A_setup 213 }, 214 { 215 ID_AIC7902 & ID_9005_GENERIC_MASK, 216 ID_9005_GENERIC_MASK, 217 "Adaptec AIC7902 Ultra320 SCSI adapter", 218 ahd_aic7902_setup 219 } 220 }; 221 222 static const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 223 224 #define DEVCONFIG 0x40 225 #define PCIXINITPAT 0x0000E000ul 226 #define PCIXINIT_PCI33_66 0x0000E000ul 227 #define PCIXINIT_PCIX50_66 0x0000C000ul 228 #define PCIXINIT_PCIX66_100 0x0000A000ul 229 #define PCIXINIT_PCIX100_133 0x00008000ul 230 #define PCI_BUS_MODES_INDEX(devconfig) \ 231 (((devconfig) & PCIXINITPAT) >> 13) 232 233 static const char *pci_bus_modes[] = 234 { 235 "PCI bus mode unknown", 236 "PCI bus mode unknown", 237 "PCI bus mode unknown", 238 "PCI bus mode unknown", 239 "PCI-X 101-133 MHz", 240 "PCI-X 67-100 MHz", 241 "PCI-X 50-66 MHz", 242 "PCI 33 or 66 MHz" 243 }; 244 245 #define TESTMODE 0x00000800ul 246 #define IRDY_RST 0x00000200ul 247 #define FRAME_RST 0x00000100ul 248 #define PCI64BIT 0x00000080ul 249 #define MRDCEN 0x00000040ul 250 #define ENDIANSEL 0x00000020ul 251 #define MIXQWENDIANEN 0x00000008ul 252 #define DACEN 0x00000004ul 253 #define STPWLEVEL 0x00000002ul 254 #define QWENDIANSEL 0x00000001ul 255 256 #define DEVCONFIG1 0x44 257 #define PREQDIS 0x01 258 259 #define LATTIME 0x0000ff00ul 260 261 static int ahd_check_extport(struct ahd_softc *ahd); 262 static void ahd_configure_termination(struct ahd_softc *ahd, 263 u_int adapter_control); 264 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 265 266 static int ahd_pci_test_register_access(struct ahd_softc *); 267 268 static int ahd_pci_intr(struct ahd_softc *); 269 270 static const struct ahd_pci_identity * 271 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 272 { 273 u_int64_t full_id; 274 const struct ahd_pci_identity *entry; 275 u_int i; 276 277 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 278 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 279 280 for (i = 0; i < ahd_num_pci_devs; i++) { 281 entry = &ahd_pci_ident_table[i]; 282 if (entry->full_id == (full_id & entry->id_mask)) 283 return (entry); 284 } 285 return (NULL); 286 } 287 288 static int 289 ahd_pci_probe(device_t parent, cfdata_t match, void *aux) 290 { 291 struct pci_attach_args *pa = aux; 292 const struct ahd_pci_identity *entry; 293 pcireg_t subid; 294 295 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 296 entry = ahd_find_pci_device(pa->pa_id, subid); 297 return entry != NULL ? 1 : 0; 298 } 299 300 static void 301 ahd_pci_attach(device_t parent, device_t self, void *aux) 302 { 303 struct pci_attach_args *pa = aux; 304 struct ahd_softc *ahd = device_private(self); 305 306 const struct ahd_pci_identity *entry; 307 308 uint32_t devconfig; 309 pcireg_t command; 310 int error; 311 pcireg_t subid; 312 uint16_t subvendor; 313 pcireg_t reg; 314 int ioh_valid, ioh2_valid, memh_valid; 315 pcireg_t memtype; 316 pci_intr_handle_t ih; 317 const char *intrstr; 318 struct ahd_pci_busdata *bd; 319 320 ahd_set_name(ahd, device_xname(&ahd->sc_dev)); 321 ahd->parent_dmat = pa->pa_dmat; 322 323 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 324 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 325 entry = ahd_find_pci_device(pa->pa_id, subid); 326 if (entry == NULL) 327 return; 328 329 /* Keep information about the PCI bus */ 330 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 331 if (bd == NULL) { 332 aprint_error("%s: unable to allocate bus-specific data\n", ahd_name(ahd)); 333 return; 334 } 335 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 336 337 bd->pc = pa->pa_pc; 338 bd->tag = pa->pa_tag; 339 bd->func = pa->pa_function; 340 bd->dev = pa->pa_device; 341 342 ahd->bus_data = bd; 343 344 ahd->description = entry->name; 345 346 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 347 M_DEVBUF, M_NOWAIT); 348 if (ahd->seep_config == NULL) { 349 aprint_error("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 350 return; 351 } 352 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 353 354 LIST_INIT(&ahd->pending_scbs); 355 ahd_timer_init(&ahd->reset_timer); 356 ahd_timer_init(&ahd->stat_timer); 357 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 358 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 359 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 360 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 361 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 362 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 363 ahd->int_coalescing_stop_threshold = AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 364 365 if (ahd_platform_alloc(ahd, NULL) != 0) { 366 ahd_free(ahd); 367 return; 368 } 369 370 /* 371 * Record if this is an HP board. 372 */ 373 subvendor = PCI_VENDOR(subid); 374 if (subvendor == SUBID_HP) 375 ahd->flags |= AHD_HP_BOARD; 376 377 error = entry->setup(ahd, pa); 378 if (error != 0) 379 return; 380 381 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 382 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 383 ahd->chip |= AHD_PCI; 384 /* Disable PCIX workarounds when running in PCI mode. */ 385 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 386 } else { 387 ahd->chip |= AHD_PCIX; 388 } 389 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 390 391 memh_valid = ioh_valid = ioh2_valid = 0; 392 393 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 394 &bd->pcix_off, NULL)) { 395 if (ahd->chip & AHD_PCIX) 396 aprint_error_dev(&ahd->sc_dev, 397 "warning: can't find PCI-X capability\n"); 398 ahd->chip &= ~AHD_PCIX; 399 ahd->chip |= AHD_PCI; 400 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 401 } 402 403 /* 404 * Map PCI Registers 405 */ 406 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 407 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 408 AHD_PCI_MEMADDR); 409 switch (memtype) { 410 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 411 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 412 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 413 memtype, 0, &ahd->tags[0], 414 &ahd->bshs[0], 415 NULL, NULL) == 0); 416 if (memh_valid) { 417 ahd->tags[1] = ahd->tags[0]; 418 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 419 /*offset*/0x100, 420 /*size*/0x100, 421 &ahd->bshs[1]); 422 if (ahd_pci_test_register_access(ahd) != 0) 423 memh_valid = 0; 424 } 425 break; 426 default: 427 memh_valid = 0; 428 aprint_error("%s: unknown memory type: 0x%x\n", 429 ahd_name(ahd), memtype); 430 break; 431 } 432 433 if (memh_valid) { 434 command &= ~PCI_COMMAND_IO_ENABLE; 435 pci_conf_write(pa->pa_pc, pa->pa_tag, 436 PCI_COMMAND_STATUS_REG, command); 437 } 438 #ifdef AHD_DEBUG 439 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, " 440 "shs0 0x%lx, shs1 0x%lx\n", 441 ahd_name(ahd), ahd->tags[0], ahd->tags[1], 442 ahd->bshs[0], ahd->bshs[1]); 443 #endif 444 } 445 446 if (command & PCI_COMMAND_IO_ENABLE) { 447 /* First BAR */ 448 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 449 PCI_MAPREG_TYPE_IO, 0, 450 &ahd->tags[0], &ahd->bshs[0], 451 NULL, NULL) == 0); 452 453 /* 2nd BAR */ 454 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 455 PCI_MAPREG_TYPE_IO, 0, 456 &ahd->tags[1], &ahd->bshs[1], 457 NULL, NULL) == 0); 458 459 if (ioh_valid && ioh2_valid) { 460 KASSERT(memh_valid == 0); 461 command &= ~PCI_COMMAND_MEM_ENABLE; 462 pci_conf_write(pa->pa_pc, pa->pa_tag, 463 PCI_COMMAND_STATUS_REG, command); 464 } 465 #ifdef AHD_DEBUG 466 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, " 467 "shs0 0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 468 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 469 #endif 470 471 } 472 473 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 474 aprint_error("%s: unable to map registers\n", ahd_name(ahd)); 475 return; 476 } 477 478 aprint_normal("\n"); 479 aprint_naive("\n"); 480 481 /* power up chip */ 482 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 483 pci_activate_null)) && error != EOPNOTSUPP) { 484 aprint_error_dev(&ahd->sc_dev, "cannot activate %d\n", error); 485 return; 486 } 487 /* 488 * Should we bother disabling 39Bit addressing 489 * based on installed memory? 490 */ 491 if (sizeof(bus_addr_t) > 4) 492 ahd->flags |= AHD_39BIT_ADDRESSING; 493 494 /* 495 * If we need to support high memory, enable dual 496 * address cycles. This bit must be set to enable 497 * high address bit generation even if we are on a 498 * 64bit bus (PCI64BIT set in devconfig). 499 */ 500 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 501 uint32_t dvconfig; 502 503 aprint_normal("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); 504 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 505 dvconfig |= DACEN; 506 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, dvconfig); 507 } 508 509 /* Ensure busmastering is enabled */ 510 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 511 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 512 reg | PCI_COMMAND_MASTER_ENABLE); 513 514 ahd_softc_init(ahd); 515 516 /* 517 * Map the interrupt routines 518 */ 519 ahd->bus_intr = ahd_pci_intr; 520 521 error = ahd_reset(ahd, /*reinit*/FALSE); 522 if (error != 0) { 523 ahd_free(ahd); 524 return; 525 } 526 527 if (pci_intr_map(pa, &ih)) { 528 aprint_error("%s: couldn't map interrupt\n", ahd_name(ahd)); 529 ahd_free(ahd); 530 return; 531 } 532 intrstr = pci_intr_string(pa->pa_pc, ih); 533 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahd_intr, ahd); 534 if (ahd->ih == NULL) { 535 aprint_error("%s: couldn't establish interrupt", 536 ahd_name(ahd)); 537 if (intrstr != NULL) 538 aprint_error(" at %s", intrstr); 539 aprint_error("\n"); 540 ahd_free(ahd); 541 return; 542 } 543 if (intrstr != NULL) 544 aprint_normal("%s: interrupting at %s\n", ahd_name(ahd), 545 intrstr); 546 547 /* Get the size of the cache */ 548 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 549 ahd->pci_cachesize *= 4; 550 551 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 552 /* See if we have a SEEPROM and perform auto-term */ 553 error = ahd_check_extport(ahd); 554 if (error != 0) 555 return; 556 557 /* Core initialization */ 558 error = ahd_init(ahd); 559 if (error != 0) 560 return; 561 562 /* 563 * Link this softc in with all other ahd instances. 564 */ 565 ahd_attach(ahd); 566 } 567 568 CFATTACH_DECL(ahd_pci, sizeof(struct ahd_softc), 569 ahd_pci_probe, ahd_pci_attach, NULL, NULL); 570 571 /* 572 * Perform some simple tests that should catch situations where 573 * our registers are invalidly mapped. 574 */ 575 static int 576 ahd_pci_test_register_access(struct ahd_softc *ahd) 577 { 578 uint32_t cmd; 579 struct ahd_pci_busdata *bd = ahd->bus_data; 580 u_int targpcistat; 581 uint32_t pci_status1; 582 int error; 583 uint8_t hcntrl; 584 585 error = EIO; 586 587 /* 588 * Enable PCI error interrupt status, but suppress NMIs 589 * generated by SERR raised due to target aborts. 590 */ 591 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 592 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 593 cmd & ~PCI_COMMAND_SERR_ENABLE); 594 595 /* 596 * First a simple test to see if any 597 * registers can be read. Reading 598 * HCNTRL has no side effects and has 599 * at least one bit that is guaranteed to 600 * be zero so it is a good register to 601 * use for this test. 602 */ 603 hcntrl = ahd_inb(ahd, HCNTRL); 604 if (hcntrl == 0xFF) 605 goto fail; 606 607 /* 608 * Next create a situation where write combining 609 * or read prefetching could be initiated by the 610 * CPU or host bridge. Our device does not support 611 * either, so look for data corruption and/or flaged 612 * PCI errors. First pause without causing another 613 * chip reset. 614 */ 615 hcntrl &= ~CHIPRST; 616 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 617 while (ahd_is_paused(ahd) == 0) 618 ; 619 620 /* Clear any PCI errors that occurred before our driver attached. */ 621 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 622 targpcistat = ahd_inb(ahd, TARGPCISTAT); 623 ahd_outb(ahd, TARGPCISTAT, targpcistat); 624 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 625 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 626 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 627 ahd_outb(ahd, CLRINT, CLRPCIINT); 628 629 ahd_outb(ahd, SEQCTL0, PERRORDIS); 630 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 631 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 632 goto fail; 633 634 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 635 u_int trgpcistat; 636 637 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 638 trgpcistat = ahd_inb(ahd, TARGPCISTAT); 639 if ((trgpcistat & STA) != 0) 640 goto fail; 641 } 642 643 error = 0; 644 645 fail: 646 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 647 648 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 649 targpcistat = ahd_inb(ahd, TARGPCISTAT); 650 651 /* Silently clear any latched errors. */ 652 ahd_outb(ahd, TARGPCISTAT, targpcistat); 653 pci_status1 = pci_conf_read(bd->pc, bd->tag, 654 PCI_COMMAND_STATUS_REG); 655 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 656 pci_status1); 657 ahd_outb(ahd, CLRINT, CLRPCIINT); 658 } 659 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 660 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 661 return (error); 662 } 663 664 /* 665 * Check the external port logic for a serial eeprom 666 * and termination/cable detection contrls. 667 */ 668 static int 669 ahd_check_extport(struct ahd_softc *ahd) 670 { 671 struct vpd_config vpd; 672 struct seeprom_config *sc; 673 u_int adapter_control; 674 int have_seeprom; 675 int error; 676 677 sc = ahd->seep_config; 678 have_seeprom = ahd_acquire_seeprom(ahd); 679 if (have_seeprom) { 680 u_int start_addr; 681 682 /* 683 * Fetch VPD for this function and parse it. 684 */ 685 #ifdef AHD_DEBUG 686 printf("%s: Reading VPD from SEEPROM...", 687 ahd_name(ahd)); 688 #endif 689 /* Address is always in units of 16bit words */ 690 start_addr = ((2 * sizeof(*sc)) 691 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 692 693 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 694 start_addr, sizeof(vpd)/2, 695 /*bytestream*/TRUE); 696 if (error == 0) 697 error = ahd_parse_vpddata(ahd, &vpd); 698 #ifdef AHD_DEBUG 699 printf("%s: VPD parsing %s\n", 700 ahd_name(ahd), 701 error == 0 ? "successful" : "failed"); 702 #endif 703 704 #ifdef AHD_DEBUG 705 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 706 #endif 707 708 /* Address is always in units of 16bit words */ 709 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 710 711 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 712 start_addr, sizeof(*sc)/2, 713 /*bytestream*/FALSE); 714 715 if (error != 0) { 716 #ifdef AHD_DEBUG 717 printf("Unable to read SEEPROM\n"); 718 #endif 719 have_seeprom = 0; 720 } else { 721 have_seeprom = ahd_verify_cksum(sc); 722 #ifdef AHD_DEBUG 723 if (have_seeprom == 0) 724 printf ("checksum error\n"); 725 else 726 printf ("done.\n"); 727 #endif 728 } 729 ahd_release_seeprom(ahd); 730 } 731 732 if (!have_seeprom) { 733 u_int nvram_scb; 734 735 /* 736 * Pull scratch ram settings and treat them as 737 * if they are the contents of an seeprom if 738 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 739 * in SCB 0xFF. We manually compose the data as 16bit 740 * values to avoid endian issues. 741 */ 742 ahd_set_scbptr(ahd, 0xFF); 743 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 744 if (nvram_scb != 0xFF 745 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 746 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 747 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 748 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 749 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 750 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 751 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 752 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 753 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 754 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 755 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 756 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 757 uint16_t *sc_data; 758 int i; 759 760 ahd_set_scbptr(ahd, nvram_scb); 761 sc_data = (uint16_t *)sc; 762 for (i = 0; i < 64; i += 2) 763 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 764 have_seeprom = ahd_verify_cksum(sc); 765 if (have_seeprom) 766 ahd->flags |= AHD_SCB_CONFIG_USED; 767 } 768 } 769 770 #ifdef AHD_DEBUG 771 if ((have_seeprom != 0) && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 772 uint16_t *sc_data; 773 int i; 774 775 printf("%s: Seeprom Contents:", ahd_name(ahd)); 776 sc_data = (uint16_t *)sc; 777 for (i = 0; i < (sizeof(*sc)); i += 2) 778 printf("\n\t0x%.4x", sc_data[i]); 779 printf("\n"); 780 } 781 #endif 782 783 if (!have_seeprom) { 784 aprint_error("%s: No SEEPROM available.\n", ahd_name(ahd)); 785 ahd->flags |= AHD_USEDEFAULTS; 786 error = ahd_default_config(ahd); 787 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 788 free(ahd->seep_config, M_DEVBUF); 789 ahd->seep_config = NULL; 790 } else { 791 error = ahd_parse_cfgdata(ahd, sc); 792 adapter_control = sc->adapter_control; 793 } 794 if (error != 0) 795 return (error); 796 797 ahd_configure_termination(ahd, adapter_control); 798 799 return (0); 800 } 801 802 static void 803 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 804 { 805 int error; 806 u_int sxfrctl1; 807 uint8_t termctl; 808 uint32_t devconfig; 809 struct ahd_pci_busdata *bd = ahd->bus_data; 810 811 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 812 devconfig &= ~STPWLEVEL; 813 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 814 devconfig |= STPWLEVEL; 815 #ifdef AHD_DEBUG 816 printf("%s: STPWLEVEL is %s\n", 817 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 818 #endif 819 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 820 821 /* Make sure current sensing is off. */ 822 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 823 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 824 } 825 826 /* 827 * Read to sense. Write to set. 828 */ 829 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 830 if ((adapter_control & CFAUTOTERM) == 0) { 831 if (bootverbose) 832 printf("%s: Manual Primary Termination\n", 833 ahd_name(ahd)); 834 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 835 if ((adapter_control & CFSTERM) != 0) 836 termctl |= FLX_TERMCTL_ENPRILOW; 837 if ((adapter_control & CFWSTERM) != 0) 838 termctl |= FLX_TERMCTL_ENPRIHIGH; 839 } else if (error != 0) { 840 if (bootverbose) 841 printf("%s: Primary Auto-Term Sensing failed! " 842 "Using Defaults.\n", ahd_name(ahd)); 843 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 844 } 845 846 if ((adapter_control & CFSEAUTOTERM) == 0) { 847 if (bootverbose) 848 printf("%s: Manual Secondary Termination\n", 849 ahd_name(ahd)); 850 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 851 if ((adapter_control & CFSELOWTERM) != 0) 852 termctl |= FLX_TERMCTL_ENSECLOW; 853 if ((adapter_control & CFSEHIGHTERM) != 0) 854 termctl |= FLX_TERMCTL_ENSECHIGH; 855 } else if (error != 0) { 856 if (bootverbose) 857 printf("%s: Secondary Auto-Term Sensing failed! " 858 "Using Defaults.\n", ahd_name(ahd)); 859 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 860 } 861 862 /* 863 * Now set the termination based on what we found. 864 */ 865 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 866 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 867 ahd->flags |= AHD_TERM_ENB_A; 868 sxfrctl1 |= STPWEN; 869 } 870 /* Must set the latch once in order to be effective. */ 871 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 872 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 873 874 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 875 if (error != 0) { 876 aprint_error("%s: Unable to set termination settings!\n", 877 ahd_name(ahd)); 878 } else { 879 if (bootverbose) { 880 printf("%s: Primary High byte termination %sabled\n", 881 ahd_name(ahd), 882 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 883 884 printf("%s: Primary Low byte termination %sabled\n", 885 ahd_name(ahd), 886 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 887 888 printf("%s: Secondary High byte termination %sabled\n", 889 ahd_name(ahd), 890 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 891 892 printf("%s: Secondary Low byte termination %sabled\n", 893 ahd_name(ahd), 894 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 895 } 896 } 897 return; 898 } 899 900 #define DPE 0x80 901 #define SSE 0x40 902 #define RMA 0x20 903 #define RTA 0x10 904 #define STA 0x08 905 #define DPR 0x01 906 907 static const char *split_status_source[] = 908 { 909 "DFF0", 910 "DFF1", 911 "OVLY", 912 "CMC", 913 }; 914 915 static const char *pci_status_source[] = 916 { 917 "DFF0", 918 "DFF1", 919 "SG", 920 "CMC", 921 "OVLY", 922 "NONE", 923 "MSI", 924 "TARG" 925 }; 926 927 static const char *split_status_strings[] = 928 { 929 "%s: Received split response in %s.\n", 930 "%s: Received split completion error message in %s\n", 931 "%s: Receive overrun in %s\n", 932 "%s: Count not complete in %s\n", 933 "%s: Split completion data bucket in %s\n", 934 "%s: Split completion address error in %s\n", 935 "%s: Split completion byte count error in %s\n", 936 "%s: Signaled Target-abort to early terminate a split in %s\n" 937 }; 938 939 static const char *pci_status_strings[] = 940 { 941 "%s: Data Parity Error has been reported via PERR# in %s\n", 942 "%s: Target initial wait state error in %s\n", 943 "%s: Split completion read data parity error in %s\n", 944 "%s: Split completion address attribute parity error in %s\n", 945 "%s: Received a Target Abort in %s\n", 946 "%s: Received a Master Abort in %s\n", 947 "%s: Signal System Error Detected in %s\n", 948 "%s: Address or Write Phase Parity Error Detected in %s.\n" 949 }; 950 951 static int 952 ahd_pci_intr(struct ahd_softc *ahd) 953 { 954 uint8_t pci_status[8]; 955 ahd_mode_state saved_modes; 956 u_int pci_status1; 957 u_int intstat; 958 u_int i; 959 u_int reg; 960 struct ahd_pci_busdata *bd = ahd->bus_data; 961 962 intstat = ahd_inb(ahd, INTSTAT); 963 964 if ((intstat & SPLTINT) != 0) 965 ahd_pci_split_intr(ahd, intstat); 966 967 if ((intstat & PCIINT) == 0) 968 return 0; 969 970 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 971 saved_modes = ahd_save_modes(ahd); 972 ahd_dump_card_state(ahd); 973 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 974 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 975 976 if (i == 5) 977 continue; 978 pci_status[i] = ahd_inb(ahd, reg); 979 /* Clear latched errors. So our interrupt deasserts. */ 980 ahd_outb(ahd, reg, pci_status[i]); 981 } 982 983 for (i = 0; i < 8; i++) { 984 u_int bit; 985 986 if (i == 5) 987 continue; 988 989 for (bit = 0; bit < 8; bit++) { 990 991 if ((pci_status[i] & (0x1 << bit)) != 0) { 992 static const char *s; 993 994 s = pci_status_strings[bit]; 995 if (i == 7/*TARG*/ && bit == 3) 996 s = "%s: Signaled Target Abort\n"; 997 printf(s, ahd_name(ahd), pci_status_source[i]); 998 } 999 } 1000 } 1001 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1002 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1003 1004 ahd_restore_modes(ahd, saved_modes); 1005 ahd_outb(ahd, CLRINT, CLRPCIINT); 1006 ahd_unpause(ahd); 1007 1008 return 1; 1009 } 1010 1011 static void 1012 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1013 { 1014 uint8_t split_status[4]; 1015 uint8_t split_status1[4]; 1016 uint8_t sg_split_status[2]; 1017 uint8_t sg_split_status1[2]; 1018 ahd_mode_state saved_modes; 1019 u_int i; 1020 pcireg_t pcix_status; 1021 struct ahd_pci_busdata *bd = ahd->bus_data; 1022 1023 /* 1024 * Check for splits in all modes. Modes 0 and 1 1025 * additionally have SG engine splits to look at. 1026 */ 1027 pcix_status = pci_conf_read(bd->pc, bd->tag, 1028 bd->pcix_off + PCI_PCIX_STATUS); 1029 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1030 ahd_name(ahd), pcix_status); 1031 1032 saved_modes = ahd_save_modes(ahd); 1033 for (i = 0; i < 4; i++) { 1034 ahd_set_modes(ahd, i, i); 1035 1036 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1037 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1038 /* Clear latched errors. So our interrupt deasserts. */ 1039 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1040 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1041 if (i > 1) 1042 continue; 1043 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1044 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1045 /* Clear latched errors. So our interrupt deasserts. */ 1046 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1047 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1048 } 1049 1050 for (i = 0; i < 4; i++) { 1051 u_int bit; 1052 1053 for (bit = 0; bit < 8; bit++) { 1054 1055 if ((split_status[i] & (0x1 << bit)) != 0) { 1056 static const char *s; 1057 1058 s = split_status_strings[bit]; 1059 printf(s, ahd_name(ahd), 1060 split_status_source[i]); 1061 } 1062 1063 if (i > 0) 1064 continue; 1065 1066 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1067 static const char *s; 1068 1069 s = split_status_strings[bit]; 1070 printf(s, ahd_name(ahd), "SG"); 1071 } 1072 } 1073 } 1074 /* 1075 * Clear PCI-X status bits. 1076 */ 1077 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + PCI_PCIX_STATUS, 1078 pcix_status); 1079 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1080 ahd_restore_modes(ahd, saved_modes); 1081 } 1082 1083 static int 1084 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1085 { 1086 1087 ahd->chip = AHD_AIC7901; 1088 ahd->features = AHD_AIC7901_FE; 1089 return (ahd_aic790X_setup(ahd, pa)); 1090 } 1091 1092 static int 1093 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1094 { 1095 1096 ahd->chip = AHD_AIC7901A; 1097 ahd->features = AHD_AIC7901A_FE; 1098 return (ahd_aic790X_setup(ahd, pa)); 1099 } 1100 1101 static int 1102 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1103 { 1104 1105 ahd->chip = AHD_AIC7902; 1106 ahd->features = AHD_AIC7902_FE; 1107 return (ahd_aic790X_setup(ahd, pa)); 1108 } 1109 1110 static int 1111 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1112 { 1113 u_int rev; 1114 1115 rev = PCI_REVISION(pa->pa_class); 1116 #ifdef AHD_DEBUG 1117 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1118 #endif 1119 if (rev < ID_AIC7902_PCI_REV_A4) { 1120 aprint_error("%s: Unable to attach to unsupported chip revision %d\n", 1121 ahd_name(ahd), rev); 1122 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1123 return (ENXIO); 1124 } 1125 1126 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1127 if (rev < ID_AIC7902_PCI_REV_B0) { 1128 /* 1129 * Enable A series workarounds. 1130 */ 1131 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1132 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1133 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1134 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1135 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1136 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1137 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1138 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1139 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1140 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1141 | AHD_FAINT_LED_BUG; 1142 1143 1144 /* 1145 * IO Cell parameter setup. 1146 */ 1147 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1148 1149 if ((ahd->flags & AHD_HP_BOARD) == 0) 1150 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1151 } else { 1152 u_int devconfig1; 1153 1154 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1155 | AHD_NEW_DFCNTRL_OPTS; 1156 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1157 1158 /* 1159 * Some issues have been resolved in the 7901B. 1160 */ 1161 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1162 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1163 1164 /* 1165 * IO Cell parameter setup. 1166 */ 1167 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1168 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1169 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1170 1171 /* 1172 * Set the PREQDIS bit for H2B which disables some workaround 1173 * that doesn't work on regular PCI busses. 1174 * XXX - Find out exactly what this does from the hardware 1175 * folks! 1176 */ 1177 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1178 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1179 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1180 } 1181 1182 return (0); 1183 } 1184